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49 * interface to the low latency DRAM
51 * <hr>$Revision: 70030 $<hr>
55 #ifndef __CVMX_LLM_H__
56 #define __CVMX_LLM_H__
62 #define ENABLE_DEPRECATED /* Set to enable the old 18/36 bit names */
66 CVMX_LLM_REPLICATION_NONE = 0,
67 CVMX_LLM_REPLICATION_2X = 1, // on both interfaces, or 2x if only one interface
68 CVMX_LLM_REPLICATION_4X = 2, // both interfaces, 2x, or 4x if only one interface
69 CVMX_LLM_REPLICATION_8X = 3, // both interfaces, 4x, or 8x if only one interface
70 } cvmx_llm_replication_t;
73 * This structure defines the address used to the low-latency memory.
74 * This address format is used for both loads and stores.
82 cvmx_llm_replication_t repl : 2;
83 uint64_t address :32; // address<1:0> mbz, address<31:30> mbz
88 * This structure defines the data format in the low-latency memory
95 * this format defines the format returned on a load
96 * a load returns the 32/36-bits in memory, plus xxor = even_parity(dat<35:0>)
97 * typically, dat<35> = parity(dat<34:0>), so the xor bit directly indicates parity error
98 * Note that the data field size is 36 bits on the 36XX/38XX, and 32 bits on the 31XX
116 * This format defines what should be used if parity is desired. Hardware returns
117 * the XOR of all the bits in the 36/32 bit data word, so for parity software must use
118 * one of the data field bits as a parity bit.
120 struct cn31xx_par_struct
126 struct cn38xx_par_struct
132 #if !OCTEON_IS_COMMON_BINARY()
133 #if CVMX_COMPILED_FOR(OCTEON_CN31XX)
134 struct cn31xx_par_struct spar;
136 struct cn38xx_par_struct spar;
141 #define CVMX_LLM_NARROW_DATA_WIDTH ((CVMX_COMPILED_FOR(OCTEON_CN31XX)) ? 32 : 36)
144 * Calculate the parity value of a number
147 * @return parity value
149 static inline uint64_t cvmx_llm_parity(uint64_t value)
152 CVMX_DPOP(result, value);
158 * Calculate the ECC needed for 36b LLM mode
163 static inline int cvmx_llm_ecc(uint64_t value)
165 /* FIXME: This needs a re-write */
166 static const uint32_t ecc_code_29[7] = {
174 uint64_t pop0, pop1, pop2, pop3, pop4, pop5, pop6;
176 pop0 = ecc_code_29[0];
177 pop1 = ecc_code_29[1];
178 pop2 = ecc_code_29[2];
180 pop3 = ecc_code_29[3];
181 CVMX_DPOP(pop0, pop0);
182 pop4 = ecc_code_29[4];
184 CVMX_DPOP(pop1, pop1);
186 pop5 = ecc_code_29[5];
187 CVMX_DPOP(pop2, pop2);
188 pop6 = ecc_code_29[6];
190 CVMX_DPOP(pop3, pop3);
192 CVMX_DPOP(pop4, pop4);
194 CVMX_DPOP(pop5, pop5);
196 CVMX_DPOP(pop6, pop6);
198 return((pop6&1)<<6) | ((pop5&1)<<5) | ((pop4&1)<<4) | ((pop3&1)<<3) | ((pop2&1)<<2) | ((pop1&1)<<1) | (pop0&1);
202 #ifdef ENABLE_DEPRECATED
203 /* These macros are provided to provide compatibility with code that uses
204 ** the old names for the llm access functions. The names were changed
205 ** when support for the 31XX llm was added, as the widths differ between Octeon Models.
206 ** The wide/narrow names are preferred, and should be used in all new code */
207 #define cvmx_llm_write36 cvmx_llm_write_narrow
208 #define cvmx_llm_read36 cvmx_llm_read_narrow
209 #define cvmx_llm_write64 cvmx_llm_write_wide
210 #define cvmx_llm_read64 cvmx_llm_read_wide
213 * Write to LLM memory - 36 bit
215 * @param address Address in LLM to write. Consecutive writes increment the
216 * address by 4. The replication mode is also encoded in this
218 * @param value Value to write to LLM. Only the low 36 bits will be used.
219 * @param set Which of the two coprocessor 2 register sets to use for the
220 * write. May be used to get two outstanding LLM access at once
221 * per core. Range: 0-1
223 static inline void cvmx_llm_write_narrow(cvmx_llm_address_t address, uint64_t value, int set)
225 cvmx_llm_data_t data;
234 CVMX_MT_LLM_DATA(1, data.u64);
235 CVMX_MT_LLM_WRITE_ADDR_INTERNAL(1, address.u64);
239 CVMX_MT_LLM_DATA(0, data.u64);
240 CVMX_MT_LLM_WRITE_ADDR_INTERNAL(0, address.u64);
246 * Write to LLM memory - 64 bit
248 * @param address Address in LLM to write. Consecutive writes increment the
249 * address by 8. The replication mode is also encoded in this
251 * @param value Value to write to LLM.
252 * @param set Which of the two coprocessor 2 register sets to use for the
253 * write. May be used to get two outstanding LLM access at once
254 * per core. Range: 0-1
256 static inline void cvmx_llm_write_wide(cvmx_llm_address_t address, uint64_t value, int set)
260 CVMX_MT_LLM_DATA(1, value);
261 CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(1, address.u64);
265 CVMX_MT_LLM_DATA(0, value);
266 CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(0, address.u64);
272 * Read from LLM memory - 36 bit
274 * @param address Address in LLM to read. Consecutive reads increment the
275 * address by 4. The replication mode is also encoded in this
277 * @param set Which of the two coprocessor 2 register sets to use for the
278 * write. May be used to get two outstanding LLM access at once
279 * per core. Range: 0-1
280 * @return The lower 36 bits contain the result of the read
282 static inline cvmx_llm_data_t cvmx_llm_read_narrow(cvmx_llm_address_t address, int set)
284 cvmx_llm_data_t value;
287 CVMX_MT_LLM_READ_ADDR(1, address.u64);
288 CVMX_MF_LLM_DATA(1, value.u64);
292 CVMX_MT_LLM_READ_ADDR(0, address.u64);
293 CVMX_MF_LLM_DATA(0, value.u64);
300 * Read from LLM memory - 64 bit
302 * @param address Address in LLM to read. Consecutive reads increment the
303 * address by 8. The replication mode is also encoded in this
305 * @param set Which of the two coprocessor 2 register sets to use for the
306 * write. May be used to get two outstanding LLM access at once
307 * per core. Range: 0-1
308 * @return The result of the read
310 static inline uint64_t cvmx_llm_read_wide(cvmx_llm_address_t address, int set)
315 CVMX_MT_LLM_READ64_ADDR(1, address);
316 CVMX_MF_LLM_DATA(1, value);
320 CVMX_MT_LLM_READ64_ADDR(0, address);
321 CVMX_MF_LLM_DATA(0, value);
327 #define RLD_INIT_DELAY (1<<18)
331 /* This structure describes the RLDRAM configuration for a board. This structure
332 ** must be populated with the correct values and passed to the initialization function.
336 uint32_t cpu_hz; /* CPU frequency in Hz */
337 char addr_rld0_fb_str [100]; /* String describing RLDRAM connections on rld 0 front (0) bunk*/
338 char addr_rld0_bb_str [100]; /* String describing RLDRAM connections on rld 0 back (1) bunk*/
339 char addr_rld1_fb_str [100]; /* String describing RLDRAM connections on rld 1 front (0) bunk*/
340 char addr_rld1_bb_str [100]; /* String describing RLDRAM connections on rld 1 back (1) bunk*/
341 uint8_t rld0_bunks; /* Number of bunks on rld 0 (0 is disabled) */
342 uint8_t rld1_bunks; /* Number of bunks on rld 1 (0 is disabled) */
343 uint16_t rld0_mbytes; /* mbytes on rld 0 */
344 uint16_t rld1_mbytes; /* mbytes on rld 1 */
345 uint16_t max_rld_clock_mhz; /* Maximum RLD clock in MHz, only used for CN58XX */
349 * Initialize LLM memory controller. This must be done
350 * before the low latency memory can be used.
351 * This is simply a wrapper around cvmx_llm_initialize_desc(),
354 * @return -1 on error
357 int cvmx_llm_initialize(void);
361 * Initialize LLM memory controller. This must be done
362 * before the low latency memory can be used.
364 * @param llm_desc_ptr
365 * Pointer to descriptor structure. If NULL
366 * is passed, a default setting is used if available.
368 * @return -1 on error
369 * Size of llm in bytes on success
371 int cvmx_llm_initialize_desc(llm_descriptor_t *llm_desc_ptr);
376 * Gets the default llm descriptor for the board code is being run on.
378 * @param llm_desc_ptr
379 * Pointer to descriptor structure to be filled in. Contents are only
380 * valid after successful completion. Must not be NULL.
382 * @return -1 on error
385 int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr);
391 #endif /* __CVM_LLM_H__ */