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47 * interface to the low latency DRAM
49 * <hr>$Revision: 41586 $<hr>
53 #ifndef __CVMX_LLM_H__
54 #define __CVMX_LLM_H__
60 #define ENABLE_DEPRECATED /* Set to enable the old 18/36 bit names */
64 CVMX_LLM_REPLICATION_NONE = 0,
65 CVMX_LLM_REPLICATION_2X = 1, // on both interfaces, or 2x if only one interface
66 CVMX_LLM_REPLICATION_4X = 2, // both interfaces, 2x, or 4x if only one interface
67 CVMX_LLM_REPLICATION_8X = 3, // both interfaces, 4x, or 8x if only one interface
68 } cvmx_llm_replication_t;
71 * This structure defines the address used to the low-latency memory.
72 * This address format is used for both loads and stores.
80 cvmx_llm_replication_t repl : 2;
81 uint64_t address :32; // address<1:0> mbz, address<31:30> mbz
86 * This structure defines the data format in the low-latency memory
93 * this format defines the format returned on a load
94 * a load returns the 32/36-bits in memory, plus xxor = even_parity(dat<35:0>)
95 * typically, dat<35> = parity(dat<34:0>), so the xor bit directly indicates parity error
96 * Note that the data field size is 36 bits on the 36XX/38XX, and 32 bits on the 31XX
114 * This format defines what should be used if parity is desired. Hardware returns
115 * the XOR of all the bits in the 36/32 bit data word, so for parity software must use
116 * one of the data field bits as a parity bit.
118 struct cn31xx_par_struct
124 struct cn38xx_par_struct
130 #if !OCTEON_IS_COMMON_BINARY()
131 #if CVMX_COMPILED_FOR(OCTEON_CN31XX)
132 struct cn31xx_par_struct spar;
134 struct cn38xx_par_struct spar;
139 #define CVMX_LLM_NARROW_DATA_WIDTH ((CVMX_COMPILED_FOR(OCTEON_CN31XX)) ? 32 : 36)
142 * Calculate the parity value of a number
145 * @return parity value
147 static inline uint64_t cvmx_llm_parity(uint64_t value)
150 CVMX_DPOP(result, value);
156 * Calculate the ECC needed for 36b LLM mode
161 static inline int cvmx_llm_ecc(uint64_t value)
163 /* FIXME: This needs a re-write */
164 static const uint32_t ecc_code_29[7] = {
172 uint64_t pop0, pop1, pop2, pop3, pop4, pop5, pop6;
174 pop0 = ecc_code_29[0];
175 pop1 = ecc_code_29[1];
176 pop2 = ecc_code_29[2];
178 pop3 = ecc_code_29[3];
179 CVMX_DPOP(pop0, pop0);
180 pop4 = ecc_code_29[4];
182 CVMX_DPOP(pop1, pop1);
184 pop5 = ecc_code_29[5];
185 CVMX_DPOP(pop2, pop2);
186 pop6 = ecc_code_29[6];
188 CVMX_DPOP(pop3, pop3);
190 CVMX_DPOP(pop4, pop4);
192 CVMX_DPOP(pop5, pop5);
194 CVMX_DPOP(pop6, pop6);
196 return((pop6&1)<<6) | ((pop5&1)<<5) | ((pop4&1)<<4) | ((pop3&1)<<3) | ((pop2&1)<<2) | ((pop1&1)<<1) | (pop0&1);
200 #ifdef ENABLE_DEPRECATED
201 /* These macros are provided to provide compatibility with code that uses
202 ** the old names for the llm access functions. The names were changed
203 ** when support for the 31XX llm was added, as the widths differ between Octeon Models.
204 ** The wide/narrow names are preferred, and should be used in all new code */
205 #define cvmx_llm_write36 cvmx_llm_write_narrow
206 #define cvmx_llm_read36 cvmx_llm_read_narrow
207 #define cvmx_llm_write64 cvmx_llm_write_wide
208 #define cvmx_llm_read64 cvmx_llm_read_wide
211 * Write to LLM memory - 36 bit
213 * @param address Address in LLM to write. Consecutive writes increment the
214 * address by 4. The replication mode is also encoded in this
216 * @param value Value to write to LLM. Only the low 36 bits will be used.
217 * @param set Which of the two coprocessor 2 register sets to use for the
218 * write. May be used to get two outstanding LLM access at once
219 * per core. Range: 0-1
221 static inline void cvmx_llm_write_narrow(cvmx_llm_address_t address, uint64_t value, int set)
223 cvmx_llm_data_t data;
226 if (cvmx_octeon_is_pass1())
227 data.s.dat = ((value & 0x3ffff) << 18) | ((value >> 18) & 0x3ffff);
235 CVMX_MT_LLM_DATA(1, data.u64);
236 CVMX_MT_LLM_WRITE_ADDR_INTERNAL(1, address.u64);
240 CVMX_MT_LLM_DATA(0, data.u64);
241 CVMX_MT_LLM_WRITE_ADDR_INTERNAL(0, address.u64);
247 * Write to LLM memory - 64 bit
249 * @param address Address in LLM to write. Consecutive writes increment the
250 * address by 8. The replication mode is also encoded in this
252 * @param value Value to write to LLM.
253 * @param set Which of the two coprocessor 2 register sets to use for the
254 * write. May be used to get two outstanding LLM access at once
255 * per core. Range: 0-1
257 static inline void cvmx_llm_write_wide(cvmx_llm_address_t address, uint64_t value, int set)
259 if (cvmx_octeon_is_pass1())
261 cvmx_llm_write36(address, value & 0xfffffffffull, set);
262 address.s.address+=4;
263 cvmx_llm_write36(address, ((value>>36) & 0xfffffff) | (cvmx_llm_ecc(value) << 28), set);
269 CVMX_MT_LLM_DATA(1, value);
270 CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(1, address.u64);
274 CVMX_MT_LLM_DATA(0, value);
275 CVMX_MT_LLM_WRITE64_ADDR_INTERNAL(0, address.u64);
282 * Read from LLM memory - 36 bit
284 * @param address Address in LLM to read. Consecutive reads increment the
285 * address by 4. The replication mode is also encoded in this
287 * @param set Which of the two coprocessor 2 register sets to use for the
288 * write. May be used to get two outstanding LLM access at once
289 * per core. Range: 0-1
290 * @return The lower 36 bits contain the result of the read
292 static inline cvmx_llm_data_t cvmx_llm_read_narrow(cvmx_llm_address_t address, int set)
294 cvmx_llm_data_t value;
297 CVMX_MT_LLM_READ_ADDR(1, address.u64);
298 CVMX_MF_LLM_DATA(1, value.u64);
302 CVMX_MT_LLM_READ_ADDR(0, address.u64);
303 CVMX_MF_LLM_DATA(0, value.u64);
310 * Read from LLM memory - 64 bit
312 * @param address Address in LLM to read. Consecutive reads increment the
313 * address by 8. The replication mode is also encoded in this
315 * @param set Which of the two coprocessor 2 register sets to use for the
316 * write. May be used to get two outstanding LLM access at once
317 * per core. Range: 0-1
318 * @return The result of the read
320 static inline uint64_t cvmx_llm_read_wide(cvmx_llm_address_t address, int set)
325 CVMX_MT_LLM_READ64_ADDR(1, address);
326 CVMX_MF_LLM_DATA(1, value);
330 CVMX_MT_LLM_READ64_ADDR(0, address);
331 CVMX_MF_LLM_DATA(0, value);
337 #define RLD_INIT_DELAY (1<<18)
341 /* This structure describes the RLDRAM configuration for a board. This structure
342 ** must be populated with the correct values and passed to the initialization function.
346 uint32_t cpu_hz; /* CPU frequency in Hz */
347 char addr_rld0_fb_str [100]; /* String describing RLDRAM connections on rld 0 front (0) bunk*/
348 char addr_rld0_bb_str [100]; /* String describing RLDRAM connections on rld 0 back (1) bunk*/
349 char addr_rld1_fb_str [100]; /* String describing RLDRAM connections on rld 1 front (0) bunk*/
350 char addr_rld1_bb_str [100]; /* String describing RLDRAM connections on rld 1 back (1) bunk*/
351 uint8_t rld0_bunks; /* Number of bunks on rld 0 (0 is disabled) */
352 uint8_t rld1_bunks; /* Number of bunks on rld 1 (0 is disabled) */
353 uint16_t rld0_mbytes; /* mbytes on rld 0 */
354 uint16_t rld1_mbytes; /* mbytes on rld 1 */
355 uint16_t max_rld_clock_mhz; /* Maximum RLD clock in MHz, only used for CN58XX */
359 * Initialize LLM memory controller. This must be done
360 * before the low latency memory can be used.
361 * This is simply a wrapper around cvmx_llm_initialize_desc(),
364 * @return -1 on error
367 int cvmx_llm_initialize(void);
371 * Initialize LLM memory controller. This must be done
372 * before the low latency memory can be used.
374 * @param llm_desc_ptr
375 * Pointer to descriptor structure. If NULL
376 * is passed, a default setting is used if available.
378 * @return -1 on error
379 * Size of llm in bytes on success
381 int cvmx_llm_initialize_desc(llm_descriptor_t *llm_desc_ptr);
386 * Gets the default llm descriptor for the board code is being run on.
388 * @param llm_desc_ptr
389 * Pointer to descriptor structure to be filled in. Contents are only
390 * valid after successful completion. Must not be NULL.
392 * @return -1 on error
395 int cvmx_llm_get_default_descriptor(llm_descriptor_t *llm_desc_ptr);
401 #endif /* __CVM_LLM_H__ */