1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_MPI_DEFS_H__
53 #define __CVMX_MPI_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_MPI_CFG CVMX_MPI_CFG_FUNC()
57 static inline uint64_t CVMX_MPI_CFG_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
60 cvmx_warn("CVMX_MPI_CFG not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001070000001000ull);
64 #define CVMX_MPI_CFG (CVMX_ADD_IO_SEG(0x0001070000001000ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 static inline uint64_t CVMX_MPI_DATX(unsigned long offset)
70 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 8))) ||
71 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 8))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 8))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 8))) ||
74 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 8))) ||
75 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 8)))))
76 cvmx_warn("CVMX_MPI_DATX(%lu) is invalid on this chip\n", offset);
77 return CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8;
80 #define CVMX_MPI_DATX(offset) (CVMX_ADD_IO_SEG(0x0001070000001080ull) + ((offset) & 15) * 8)
82 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
83 #define CVMX_MPI_STS CVMX_MPI_STS_FUNC()
84 static inline uint64_t CVMX_MPI_STS_FUNC(void)
86 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
87 cvmx_warn("CVMX_MPI_STS not supported on this chip\n");
88 return CVMX_ADD_IO_SEG(0x0001070000001008ull);
91 #define CVMX_MPI_STS (CVMX_ADD_IO_SEG(0x0001070000001008ull))
93 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
94 #define CVMX_MPI_TX CVMX_MPI_TX_FUNC()
95 static inline uint64_t CVMX_MPI_TX_FUNC(void)
97 if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
98 cvmx_warn("CVMX_MPI_TX not supported on this chip\n");
99 return CVMX_ADD_IO_SEG(0x0001070000001010ull);
102 #define CVMX_MPI_TX (CVMX_ADD_IO_SEG(0x0001070000001010ull))
112 * Some of the SPI/MPI pins are muxed with UART pins.
113 * SPI_CLK : spi clock, dedicated pin
114 * SPI_DI : spi input, shared with UART0_DCD_N/SPI_DI, enabled when MPI_CFG[ENABLE]=1
115 * SPI_DO : spi output, mux to UART0_DTR_N/SPI_DO, enabled when MPI_CFG[ENABLE]=1
116 * SPI_CS0_L : chips select 0, mux to BOOT_CE_N<6>/SPI_CS0_L pin, enabled when MPI_CFG[CSENA0]=1 and MPI_CFG[ENABLE]=1
117 * SPI_CS1_L : chips select 1, mux to BOOT_CE_N<7>/SPI_CS1_L pin, enabled when MPI_CFG[CSENA1]=1 and MPI_CFG[ENABLE]=1
121 struct cvmx_mpi_cfg_s {
122 #ifdef __BIG_ENDIAN_BITFIELD
123 uint64_t reserved_29_63 : 35;
124 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
125 CLKDIV = Fsclk / (2 * Fspi_clk) */
126 uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS
127 1, UART1_RTS_L/SPI_CS3_L pin is SPI pin
128 SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */
129 uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS
130 1, UART0_RTS_L/SPI_CS2_L pin is SPI pin
131 SPI_CS2_L drives UART0_RTS_L/SPI_CS2_L */
132 uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS
133 1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin
134 SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */
135 uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS
136 1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin
137 SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */
138 uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
139 1, SPI_CS assert coincident with transaction
140 NOTE: This control apply for 2 CSs */
141 uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
142 expected to be driving
143 1, SPI_DO pin is tristated when not transmitting
144 NOTE: only used when WIREOR==1 */
145 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
147 uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
148 1, CS is high asserted */
149 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
150 1, CS is driven per MPI_TX intruction */
151 uint64_t int_ena : 1; /**< If 0, polling is required | NS
152 1, MPI engine interrupts X end of transaction */
153 uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
154 1, shift LSB first */
155 uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
156 SPI_DO pin is always driven
157 1, SPI_DO/DI is all from SPI_DO pin (MPI)
158 SPI_DO pin is tristated when not transmitting
159 NOTE: if WIREOR==1, SPI_DI pin is not used by the
161 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
162 completion of MPI transaction
163 1, clock never idles, requires CS deassertion
164 assertion between commands */
165 uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
166 1, SPI_CLK idles low, 1st transition is lo->hi */
167 uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
168 BOOT_CE_N<7:6>/SPI_CSx_L
169 pins are UART/BOOT pins
170 1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
171 pins are SPI/MPI pins.
172 BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1
173 BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */
177 uint64_t clk_cont : 1;
179 uint64_t lsbfirst : 1;
180 uint64_t int_ena : 1;
183 uint64_t idleclks : 2;
190 uint64_t clkdiv : 13;
191 uint64_t reserved_29_63 : 35;
194 struct cvmx_mpi_cfg_cn30xx {
195 #ifdef __BIG_ENDIAN_BITFIELD
196 uint64_t reserved_29_63 : 35;
197 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
198 CLKDIV = Feclk / (2 * Fsclk) */
199 uint64_t reserved_12_15 : 4;
200 uint64_t cslate : 1; /**< If 0, MPI_CS asserts 1/2 SCLK before transaction
201 1, MPI_CS assert coincident with transaction
202 NOTE: only used if CSENA == 1 */
203 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
204 expected to be driving
205 1, MPI_TX pin is tristated when not transmitting
206 NOTE: only used when WIREOR==1 */
207 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
209 uint64_t cshi : 1; /**< If 0, CS is low asserted
210 1, CS is high asserted */
211 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
212 1, CS is driven per MPI_TX intruction */
213 uint64_t int_ena : 1; /**< If 0, polling is required
214 1, MPI engine interrupts X end of transaction */
215 uint64_t lsbfirst : 1; /**< If 0, shift MSB first
216 1, shift LSB first */
217 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
218 MPI_TX pin is always driven
219 1, MPI_TX/RX is all from MPI_TX pin (MPI)
220 MPI_TX pin is tristated when not transmitting
221 NOTE: if WIREOR==1, MPI_RX pin is not used by the
223 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
224 completion of MPI transaction
225 1, clock never idles, requires CS deassertion
226 assertion between commands */
227 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
228 1, MPI_CLK idles low, 1st transition is lo->hi */
229 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
230 1, MPI_CLK, MPI_CS, and MPI_TX are driven */
234 uint64_t clk_cont : 1;
236 uint64_t lsbfirst : 1;
237 uint64_t int_ena : 1;
240 uint64_t idleclks : 2;
243 uint64_t reserved_12_15 : 4;
244 uint64_t clkdiv : 13;
245 uint64_t reserved_29_63 : 35;
248 struct cvmx_mpi_cfg_cn31xx {
249 #ifdef __BIG_ENDIAN_BITFIELD
250 uint64_t reserved_29_63 : 35;
251 uint64_t clkdiv : 13; /**< Fsclk = Feclk / (2 * CLKDIV)
252 CLKDIV = Feclk / (2 * Fsclk) */
253 uint64_t reserved_11_15 : 5;
254 uint64_t tritx : 1; /**< If 0, MPI_TX pin is driven when slave is not
255 expected to be driving
256 1, MPI_TX pin is tristated when not transmitting
257 NOTE: only used when WIREOR==1 */
258 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between
260 uint64_t cshi : 1; /**< If 0, CS is low asserted
261 1, CS is high asserted */
262 uint64_t csena : 1; /**< If 0, the MPI_CS is a GPIO, not used by MPI_TX
263 1, CS is driven per MPI_TX intruction */
264 uint64_t int_ena : 1; /**< If 0, polling is required
265 1, MPI engine interrupts X end of transaction */
266 uint64_t lsbfirst : 1; /**< If 0, shift MSB first
267 1, shift LSB first */
268 uint64_t wireor : 1; /**< If 0, MPI_TX and MPI_RX are separate wires (SPI)
269 MPI_TX pin is always driven
270 1, MPI_TX/RX is all from MPI_TX pin (MPI)
271 MPI_TX pin is tristated when not transmitting
272 NOTE: if WIREOR==1, MPI_RX pin is not used by the
274 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after
275 completion of MPI transaction
276 1, clock never idles, requires CS deassertion
277 assertion between commands */
278 uint64_t idlelo : 1; /**< If 0, MPI_CLK idles high, 1st transition is hi->lo
279 1, MPI_CLK idles low, 1st transition is lo->hi */
280 uint64_t enable : 1; /**< If 0, all MPI pins are GPIOs
281 1, MPI_CLK, MPI_CS, and MPI_TX are driven */
285 uint64_t clk_cont : 1;
287 uint64_t lsbfirst : 1;
288 uint64_t int_ena : 1;
291 uint64_t idleclks : 2;
293 uint64_t reserved_11_15 : 5;
294 uint64_t clkdiv : 13;
295 uint64_t reserved_29_63 : 35;
298 struct cvmx_mpi_cfg_cn30xx cn50xx;
299 struct cvmx_mpi_cfg_cn61xx {
300 #ifdef __BIG_ENDIAN_BITFIELD
301 uint64_t reserved_29_63 : 35;
302 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
303 CLKDIV = Fsclk / (2 * Fspi_clk) */
304 uint64_t reserved_14_15 : 2;
305 uint64_t csena1 : 1; /**< If 0, BOOT_CE_N<7>/SPI_CS1_L pin is BOOT pin | NS
306 1, BOOT_CE_N<7>/SPI_CS1_L pin is SPI pin
307 SPI_CS1_L drives BOOT_CE_N<7>/SPI_CS1_L */
308 uint64_t csena0 : 1; /**< If 0, BOOT_CE_N<6>/SPI_CS0_L pin is BOOT pin | NS
309 1, BOOT_CE_N<6>/SPI_CS0_L pin is SPI pin
310 SPI_CS0_L drives BOOT_CE_N<6>/SPI_CS0_L */
311 uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
312 1, SPI_CS assert coincident with transaction
313 NOTE: This control apply for 2 CSs */
314 uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
315 expected to be driving
316 1, SPI_DO pin is tristated when not transmitting
317 NOTE: only used when WIREOR==1 */
318 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
320 uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
321 1, CS is high asserted */
322 uint64_t reserved_6_6 : 1;
323 uint64_t int_ena : 1; /**< If 0, polling is required | NS
324 1, MPI engine interrupts X end of transaction */
325 uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
326 1, shift LSB first */
327 uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
328 SPI_DO pin is always driven
329 1, SPI_DO/DI is all from SPI_DO pin (MPI)
330 SPI_DO pin is tristated when not transmitting
331 NOTE: if WIREOR==1, SPI_DI pin is not used by the
333 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
334 completion of MPI transaction
335 1, clock never idles, requires CS deassertion
336 assertion between commands */
337 uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
338 1, SPI_CLK idles low, 1st transition is lo->hi */
339 uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
340 BOOT_CE_N<7:6>/SPI_CSx_L
341 pins are UART/BOOT pins
342 1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
343 pins are SPI/MPI pins.
344 BOOT_CE_N<6>/SPI_CS0_L is SPI pin if CSENA0=1
345 BOOT_CE_N<7>/SPI_CS1_L is SPI pin if CSENA1=1 */
349 uint64_t clk_cont : 1;
351 uint64_t lsbfirst : 1;
352 uint64_t int_ena : 1;
353 uint64_t reserved_6_6 : 1;
355 uint64_t idleclks : 2;
360 uint64_t reserved_14_15 : 2;
361 uint64_t clkdiv : 13;
362 uint64_t reserved_29_63 : 35;
365 struct cvmx_mpi_cfg_cn66xx {
366 #ifdef __BIG_ENDIAN_BITFIELD
367 uint64_t reserved_29_63 : 35;
368 uint64_t clkdiv : 13; /**< Fspi_clk = Fsclk / (2 * CLKDIV) | NS
369 CLKDIV = Fsclk / (2 * Fspi_clk) */
370 uint64_t csena3 : 1; /**< If 0, UART1_RTS_L/SPI_CS3_L pin is UART pin | NS
371 1, UART1_RTS_L/SPI_CS3_L pin is SPI pin
372 SPI_CS3_L drives UART1_RTS_L/SPI_CS3_L */
373 uint64_t csena2 : 1; /**< If 0, UART0_RTS_L/SPI_CS2_L pin is UART pin | NS
374 1, UART0_RTS_L/SPI_CS2_L pin is SPI pin
375 SPI_CS2_L drives UART0_RTS_L/SPI_CS2_L */
376 uint64_t reserved_12_13 : 2;
377 uint64_t cslate : 1; /**< If 0, SPI_CS asserts 1/2 SCLK before transaction | NS
378 1, SPI_CS assert coincident with transaction
379 NOTE: This control apply for 4 CSs */
380 uint64_t tritx : 1; /**< If 0, SPI_DO pin is driven when slave is not | NS
381 expected to be driving
382 1, SPI_DO pin is tristated when not transmitting
383 NOTE: only used when WIREOR==1 */
384 uint64_t idleclks : 2; /**< Guarantee IDLECLKS idle sclk cycles between | NS
386 uint64_t cshi : 1; /**< If 0, CS is low asserted | NS
387 1, CS is high asserted */
388 uint64_t reserved_6_6 : 1;
389 uint64_t int_ena : 1; /**< If 0, polling is required | NS
390 1, MPI engine interrupts X end of transaction */
391 uint64_t lsbfirst : 1; /**< If 0, shift MSB first | NS
392 1, shift LSB first */
393 uint64_t wireor : 1; /**< If 0, SPI_DO and SPI_DI are separate wires (SPI) | NS
394 SPI_DO pin is always driven
395 1, SPI_DO/DI is all from SPI_DO pin (MPI)
396 SPI_DO pin is tristated when not transmitting
397 NOTE: if WIREOR==1, SPI_DI pin is not used by the
399 uint64_t clk_cont : 1; /**< If 0, clock idles to value given by IDLELO after | NS
400 completion of MPI transaction
401 1, clock never idles, requires CS deassertion
402 assertion between commands */
403 uint64_t idlelo : 1; /**< If 0, SPI_CLK idles high, 1st transition is hi->lo | NS
404 1, SPI_CLK idles low, 1st transition is lo->hi */
405 uint64_t enable : 1; /**< If 0, UART0_DTR_L/SPI_DO, UART0_DCD_L/SPI_DI | NS
406 UART0_RTS_L/SPI_CS2_L, UART1_RTS_L/SPI_CS3_L
408 1, UART0_DTR_L/SPI_DO and UART0_DCD_L/SPI_DI
409 pins are SPI/MPI pins.
410 UART0_RTS_L/SPI_CS2_L is SPI pin if CSENA2=1
411 UART1_RTS_L/SPI_CS3_L is SPI pin if CSENA3=1 */
415 uint64_t clk_cont : 1;
417 uint64_t lsbfirst : 1;
418 uint64_t int_ena : 1;
419 uint64_t reserved_6_6 : 1;
421 uint64_t idleclks : 2;
424 uint64_t reserved_12_13 : 2;
427 uint64_t clkdiv : 13;
428 uint64_t reserved_29_63 : 35;
431 struct cvmx_mpi_cfg_cn61xx cnf71xx;
433 typedef union cvmx_mpi_cfg cvmx_mpi_cfg_t;
438 union cvmx_mpi_datx {
440 struct cvmx_mpi_datx_s {
441 #ifdef __BIG_ENDIAN_BITFIELD
442 uint64_t reserved_8_63 : 56;
443 uint64_t data : 8; /**< Data to transmit/received | NS */
446 uint64_t reserved_8_63 : 56;
449 struct cvmx_mpi_datx_s cn30xx;
450 struct cvmx_mpi_datx_s cn31xx;
451 struct cvmx_mpi_datx_s cn50xx;
452 struct cvmx_mpi_datx_s cn61xx;
453 struct cvmx_mpi_datx_s cn66xx;
454 struct cvmx_mpi_datx_s cnf71xx;
456 typedef union cvmx_mpi_datx cvmx_mpi_datx_t;
463 struct cvmx_mpi_sts_s {
464 #ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t reserved_13_63 : 51;
466 uint64_t rxnum : 5; /**< Number of bytes written for transaction | NS */
467 uint64_t reserved_1_7 : 7;
468 uint64_t busy : 1; /**< If 0, no MPI transaction in progress | NS
469 1, MPI engine is processing a transaction */
472 uint64_t reserved_1_7 : 7;
474 uint64_t reserved_13_63 : 51;
477 struct cvmx_mpi_sts_s cn30xx;
478 struct cvmx_mpi_sts_s cn31xx;
479 struct cvmx_mpi_sts_s cn50xx;
480 struct cvmx_mpi_sts_s cn61xx;
481 struct cvmx_mpi_sts_s cn66xx;
482 struct cvmx_mpi_sts_s cnf71xx;
484 typedef union cvmx_mpi_sts cvmx_mpi_sts_t;
491 struct cvmx_mpi_tx_s {
492 #ifdef __BIG_ENDIAN_BITFIELD
493 uint64_t reserved_22_63 : 42;
494 uint64_t csid : 2; /**< Which CS to assert for this transaction | NS */
495 uint64_t reserved_17_19 : 3;
496 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS
497 1, leave CS asserted after transactrion is done */
498 uint64_t reserved_13_15 : 3;
499 uint64_t txnum : 5; /**< Number of bytes to transmit | NS */
500 uint64_t reserved_5_7 : 3;
501 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */
504 uint64_t reserved_5_7 : 3;
506 uint64_t reserved_13_15 : 3;
507 uint64_t leavecs : 1;
508 uint64_t reserved_17_19 : 3;
510 uint64_t reserved_22_63 : 42;
513 struct cvmx_mpi_tx_cn30xx {
514 #ifdef __BIG_ENDIAN_BITFIELD
515 uint64_t reserved_17_63 : 47;
516 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done
517 1, leave CS asserted after transactrion is done */
518 uint64_t reserved_13_15 : 3;
519 uint64_t txnum : 5; /**< Number of bytes to transmit */
520 uint64_t reserved_5_7 : 3;
521 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) */
524 uint64_t reserved_5_7 : 3;
526 uint64_t reserved_13_15 : 3;
527 uint64_t leavecs : 1;
528 uint64_t reserved_17_63 : 47;
531 struct cvmx_mpi_tx_cn30xx cn31xx;
532 struct cvmx_mpi_tx_cn30xx cn50xx;
533 struct cvmx_mpi_tx_cn61xx {
534 #ifdef __BIG_ENDIAN_BITFIELD
535 uint64_t reserved_21_63 : 43;
536 uint64_t csid : 1; /**< Which CS to assert for this transaction | NS */
537 uint64_t reserved_17_19 : 3;
538 uint64_t leavecs : 1; /**< If 0, deassert CS after transaction is done | NS
539 1, leave CS asserted after transactrion is done */
540 uint64_t reserved_13_15 : 3;
541 uint64_t txnum : 5; /**< Number of bytes to transmit | NS */
542 uint64_t reserved_5_7 : 3;
543 uint64_t totnum : 5; /**< Number of bytes to shift (transmit + receive) | NS */
546 uint64_t reserved_5_7 : 3;
548 uint64_t reserved_13_15 : 3;
549 uint64_t leavecs : 1;
550 uint64_t reserved_17_19 : 3;
552 uint64_t reserved_21_63 : 43;
555 struct cvmx_mpi_tx_s cn66xx;
556 struct cvmx_mpi_tx_cn61xx cnf71xx;
558 typedef union cvmx_mpi_tx cvmx_mpi_tx_t;