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49 * This header defines the CVMX interface to the NAND flash controller. The
50 * basic operations common to all NAND devices are supported by this API, but
51 * many more advanced functions are not support. The low level hardware supports
52 * all types of transactions, but this API only implements the must commonly
53 * used operations. This API performs no locking, so it is the responsibility of
54 * the caller to make sure only one thread of execution is accessing the NAND
55 * controller at a time. Most applications should not use this API directly but
56 * instead use a flash logical layer supplied through a secondary system. For
57 * example, the Linux MTD layer provides a driver for running JFFS2 on top of
60 * <h2>Selecting the NAND Chip</h2>
62 * Octeon's NAND controller assumes a single NAND chip is connected to a boot
63 * bus chip select. Throughout this API, NAND chips are referred to by the chip
64 * select they are connected to (0-7). Chip select 0 will only be a NAND chip
65 * when you are booting from NAND flash.
67 * <h2>NAND Addressing</h2>
69 * Various functions in cvmx-nand use addresses to index into NAND flash. All
70 * functions us a uniform address translation scheme to map the passed address
71 * into a NAND block, page, and column. In NAND flash a page represents the
72 * basic unit of reads and writes. Each page contains a power of two number of
73 * bytes and some number of extra out of band (OOB) bytes. A fixed number of
74 * pages fit into each NAND block. Here is the mapping of bits in the cvmx-nand
75 * address to the NAND hardware:
77 * 63 56 48 40 32 24 16 8 0
78 * +-------+-------+-------+-------+-------+-------+-------+------+
79 * | 64 bit cvmx-nand nand_address|
80 * +------------------------------------------------+----+--------+
81 * | block |page| column |
82 * +-------+-------+-------+-------+-------+--------+----+--------+
83 * 63 56 48 40 32 24 16 8 0
85 * Basically the block, page, and column addresses are packet together. Before
86 * being sent out the NAND pins for addressing the column is padded out to an
87 * even number of bytes. This means that column address are 2 bytes, or 2
88 * address cycles, for page sizes between 512 and 65536 bytes. Page sizes
89 * between 128KB and 16MB would use 3 column address cycles. NAND device
90 * normally either have 32 or 64 pages per block, needing either 5 or 6 address
91 * bits respectively. This means you have 10 bits for block address using 4
92 * address cycles, or 18 for 5 address cycles. Using the cvmx-nand addressing
93 * scheme, it is not possible to directly index the OOB data. Instead you can
94 * access it by reading or writing more data than the normal page size would
95 * allow. Logically the OOB data is appended onto the the page data. For
96 * example, this means that a read of 65 bytes from a column address of 0x7ff
97 * would yield byte 2047 of the page and then 64 bytes of OOB data.
99 * <hr>$Revision: 35726 $<hr>
102 #ifndef __CVMX_NAND_H__
103 #define __CVMX_NAND_H__
109 /* Maxium PAGE + OOB size supported. This is used to size
110 ** buffers, some that must be statically allocated. */
111 #define CVMX_NAND_MAX_PAGE_AND_OOB_SIZE (4096 + 256)
114 /* Block size for boot ECC */
115 #define CVMX_NAND_BOOT_ECC_BLOCK_SIZE (256)
116 /* ECC bytes for each block */
117 #define CVMX_NAND_BOOT_ECC_ECC_SIZE (8)
120 * Flags to be passed to the initialize function
124 CVMX_NAND_INITIALIZE_FLAGS_16BIT = 1<<0,
125 CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE = 1<<1,
126 CVMX_NAND_INITIALIZE_FLAGS_DEBUG = 1<<15,
127 } cvmx_nand_initialize_flags_t;
130 * Return codes from NAND functions
134 CVMX_NAND_SUCCESS = 0,
135 CVMX_NAND_NO_MEMORY = -1,
137 CVMX_NAND_INVALID_PARAM = -3,
138 CVMX_NAND_TIMEOUT = -4,
139 CVMX_NAND_ERROR = -5,
140 } cvmx_nand_status_t;
143 * NAND NOP command definition
147 uint64_t reserved_64_127 : 64;
148 uint64_t reserved_4_63 : 60;
150 } cvmx_nand_cmd_nop_t;
153 * NAND SET_TM_PAR command definition
157 uint64_t reserved_64_127 : 64;
158 uint64_t tim_par7 : 8;
159 uint64_t tim_par6 : 8;
160 uint64_t tim_par5 : 8;
161 uint64_t tim_par4 : 8;
162 uint64_t tim_par3 : 8;
163 uint64_t tim_par2 : 8;
164 uint64_t tim_par1 : 8;
165 uint64_t tim_mult : 4;
167 } cvmx_nand_cmd_set_tm_par_t;
170 * NAND WAIT command definition
174 uint64_t reserved_64_127 : 64;
175 uint64_t reserved_11_63 : 53;
177 uint64_t reserved_5_7 : 3;
180 } cvmx_nand_cmd_wait_t;
183 * NAND CHIP_EN command definition
187 uint64_t reserved_64_127 : 64;
188 uint64_t reserved_10_63 : 54;
193 } cvmx_nand_cmd_chip_en_t;
196 * NAND CHIP_DIS command definition
200 uint64_t reserved_64_127 : 64;
201 uint64_t reserved_4_63 : 60;
203 } cvmx_nand_cmd_chip_dis_t;
206 * NAND CLE command definition
210 uint64_t reserved_64_127 : 64;
211 uint64_t reserved_25_63 : 39;
215 uint64_t cmd_data : 8;
216 uint64_t reserved_4_7 : 4;
218 } cvmx_nand_cmd_cle_t;
221 * NAND ALE command definition
225 uint64_t reserved_96_127 : 32;
226 uint64_t adr_bytes_h : 32;
227 uint64_t adr_bytes_l : 32;
228 uint64_t reserved_28_31 : 4;
233 uint64_t reserved_12_15 : 4;
234 uint64_t adr_byte_num : 4;
235 uint64_t reserved_4_7 : 4;
237 } cvmx_nand_cmd_ale_t;
240 * NAND WR command definition
244 uint64_t reserved_64_127 : 64;
245 uint64_t reserved_31_63 : 34;
248 uint64_t reserved_20_24 : 4;
249 uint64_t data_bytes : 16;
251 } cvmx_nand_cmd_wr_t;
254 * NAND RD command definition
258 uint64_t reserved_64_127 : 64;
259 uint64_t reserved_32_63 : 32;
264 uint64_t data_bytes : 16;
266 } cvmx_nand_cmd_rd_t;
269 * NAND RD_EDO command definition
273 uint64_t reserved_64_127 : 64;
274 uint64_t reserved_32_63 : 32;
279 uint64_t data_bytes : 16;
281 } cvmx_nand_cmd_rd_edo_t;
284 * NAND WAIT_STATUS command definition
292 uint64_t comp_byte : 8;
293 uint64_t and_mask : 8;
295 uint64_t reserved_28_95 : 64;
301 uint64_t reserved_4_7 : 4;
303 } cvmx_nand_cmd_wait_status_t;
306 * NAND WAIT_STATUS_ALE command definition
314 uint64_t comp_byte : 8;
315 uint64_t and_mask : 8;
317 uint64_t adr_bytes : 32;
318 uint64_t reserved_60_63 : 4;
323 uint64_t reserved_44_47 : 4;
324 uint64_t adr_byte_num : 4;
326 uint64_t reserved_25_31 : 7;
331 uint64_t reserved_4_7 : 4;
333 } cvmx_nand_cmd_wait_status_ale_t;
336 * NAND BUS_ACQ command definition
340 uint64_t reserved_64_127 : 64;
341 uint64_t reserved_8_63 : 56;
343 uint64_t fifteen : 4;
344 } cvmx_nand_cmd_bus_acq_t;
347 * NAND BUS_REL command definition
351 uint64_t reserved_64_127 : 64;
352 uint64_t reserved_8_63 : 56;
354 uint64_t fifteen : 4;
355 } cvmx_nand_cmd_bus_rel_t;
358 * NAND command union of all possible commands
363 cvmx_nand_cmd_nop_t nop;
364 cvmx_nand_cmd_set_tm_par_t set_tm_par;
365 cvmx_nand_cmd_wait_t wait;
366 cvmx_nand_cmd_chip_en_t chip_en;
367 cvmx_nand_cmd_chip_dis_t chip_dis;
368 cvmx_nand_cmd_cle_t cle;
369 cvmx_nand_cmd_ale_t ale;
370 cvmx_nand_cmd_rd_t rd;
371 cvmx_nand_cmd_rd_edo_t rd_edo;
372 cvmx_nand_cmd_wr_t wr;
373 cvmx_nand_cmd_wait_status_t wait_status;
374 cvmx_nand_cmd_wait_status_ale_t wait_status_ale;
375 cvmx_nand_cmd_bus_acq_t bus_acq;
376 cvmx_nand_cmd_bus_rel_t bus_rel;
379 uint64_t reserved_64_127: 64;
380 uint64_t reserved_4_63 : 60;
381 uint64_t op_code : 4;
386 typedef struct __attribute__ ((packed))
388 char onfi[4]; /**< Bytes 0-3: The ASCII characters 'O', 'N', 'F', 'I' */
389 uint16_t revision_number; /**< Bytes 4-5: ONFI revision number
391 - 1 1 = supports ONFI version 1.0
393 uint16_t features; /**< Bytes 6-7: Features supported
395 - 4 1 = supports odd to even page Copyback
396 - 3 1 = supports interleaved operations
397 - 2 1 = supports non-sequential page programming
398 - 1 1 = supports multiple LUN operations
399 - 0 1 = supports 16-bit data bus width */
400 uint16_t optional_commands; /**< Bytes 8-9: Optional commands supported
402 - 5 1 = supports Read Unique ID
403 - 4 1 = supports Copyback
404 - 3 1 = supports Read Status Enhanced
405 - 2 1 = supports Get Features and Set Features
406 - 1 1 = supports Read Cache commands
407 - 0 1 = supports Page Cache Program command */
408 uint8_t reserved_10_31[22]; /**< Bytes 10-31: Reserved */
410 char manufacturer[12]; /**< Bytes 32-43: Device manufacturer (12 ASCII characters) */
411 char model[20]; /**< Bytes 40-63: Device model (20 ASCII characters) */
412 uint8_t jedec_id; /**< Byte 64: JEDEC manufacturer ID */
413 uint16_t date_code; /**< Byte 65-66: Date code */
414 uint8_t reserved_67_79[13]; /**< Bytes 67-79: Reserved */
416 uint32_t page_data_bytes; /**< Bytes 80-83: Number of data bytes per page */
417 uint16_t page_spare_bytes; /**< Bytes 84-85: Number of spare bytes per page */
418 uint32_t partial_page_data_bytes; /**< Bytes 86-89: Number of data bytes per partial page */
419 uint16_t partial_page_spare_bytes; /**< Bytes 90-91: Number of spare bytes per partial page */
420 uint32_t pages_per_block; /**< Bytes 92-95: Number of pages per block */
421 uint32_t blocks_per_lun; /**< Bytes 96-99: Number of blocks per logical unit (LUN) */
422 uint8_t number_lun; /**< Byte 100: Number of logical units (LUNs) */
423 uint8_t address_cycles; /**< Byte 101: Number of address cycles
424 - 4-7 Column address cycles
425 - 0-3 Row address cycles */
426 uint8_t bits_per_cell; /**< Byte 102: Number of bits per cell */
427 uint16_t bad_block_per_lun; /**< Bytes 103-104: Bad blocks maximum per LUN */
428 uint16_t block_endurance; /**< Bytes 105-106: Block endurance */
429 uint8_t good_blocks; /**< Byte 107: Guaranteed valid blocks at beginning of target */
430 uint16_t good_block_endurance; /**< Bytes 108-109: Block endurance for guaranteed valid blocks */
431 uint8_t programs_per_page; /**< Byte 110: Number of programs per page */
432 uint8_t partial_program_attrib; /**< Byte 111: Partial programming attributes
434 - 4 1 = partial page layout is partial page data followed by partial page spare
436 - 0 1 = partial page programming has constraints */
437 uint8_t bits_ecc; /**< Byte 112: Number of bits ECC correctability */
438 uint8_t interleaved_address_bits; /**< Byte 113: Number of interleaved address bits
440 - 0-3 Number of interleaved address bits */
441 uint8_t interleaved_attrib; /**< Byte 114: Interleaved operation attributes
443 - 3 Address restrictions for program cache
444 - 2 1 = program cache supported
445 - 1 1 = no block address restrictions
446 - 0 Overlapped / concurrent interleaving support */
447 uint8_t reserved_115_127[13]; /**< Bytes 115-127: Reserved (0) */
449 uint8_t pin_capacitance; /**< Byte 128: I/O pin capacitance */
450 uint16_t timing_mode; /**< Byte 129-130: Timing mode support
452 - 5 1 = supports timing mode 5
453 - 4 1 = supports timing mode 4
454 - 3 1 = supports timing mode 3
455 - 2 1 = supports timing mode 2
456 - 1 1 = supports timing mode 1
457 - 0 1 = supports timing mode 0, shall be 1 */
458 uint16_t cache_timing_mode; /**< Byte 131-132: Program cache timing mode support
460 - 5 1 = supports timing mode 5
461 - 4 1 = supports timing mode 4
462 - 3 1 = supports timing mode 3
463 - 2 1 = supports timing mode 2
464 - 1 1 = supports timing mode 1
465 - 0 1 = supports timing mode 0 */
466 uint16_t t_prog; /**< Byte 133-134: Maximum page program time (us) */
467 uint16_t t_bers; /**< Byte 135-136: Maximum block erase time (us) */
468 uint16_t t_r; /**< Byte 137-148: Maximum page read time (us) */
469 uint16_t t_ccs; /**< Byte 139-140: Minimum change column setup time (ns) */
470 uint8_t reserved_141_163[23]; /**< Byte 141-163: Reserved (0) */
472 uint16_t vendor_revision; /**< Byte 164-165: Vendor specific Revision number */
473 uint8_t vendor_specific[88]; /**< Byte 166-253: Vendor specific */
474 uint16_t crc; /**< Byte 254-255: Integrity CRC */
475 } cvmx_nand_onfi_param_page_t;
479 * Called to initialize the NAND controller for use. Note that
480 * you must be running out of L2 or memory and not NAND before
481 * calling this function.
482 * When probing for NAND chips, this function attempts to autoconfigure based on the NAND parts detected.
483 * It currently supports autodetection for ONFI parts (with valid parameter pages), and some Samsung NAND
484 * parts (decoding ID bits.) If autoconfiguration fails, the defaults set with __set_chip_defaults()
485 * prior to calling cvmx_nand_initialize() are used.
486 * If defaults are set and the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is provided, the defaults are used
487 * for all chips in the active_chips mask.
489 * @param flags Optional initialization flags
490 * If the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is passed, chips are not probed,
491 * and the default parameters (if set with cvmx_nand_set_defaults) are used for all chips
492 * in the active_chips mask.
493 * @param active_chips
494 * Each bit in this parameter represents a chip select that might
495 * contain NAND flash. Any chip select present in this bitmask may
496 * be connected to NAND. It is normally safe to pass 0xff here and
497 * let the API probe all 8 chip selects.
499 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
501 extern cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips);
506 * This function may be called before cvmx_nand_initialize to set default values that will be used
507 * for NAND chips that do not identify themselves in a way that allows autoconfiguration. (ONFI chip with
508 * missing parameter page, for example.)
509 * The parameters set by this function will be used by _all_ non-autoconfigured NAND chips.
512 * NOTE: This function signature is _NOT_ stable, and will change in the future as required to support
513 * various NAND chips.
515 * @param page_size page size in bytes
516 * @param oob_size Out of band size in bytes (per page)
517 * @param pages_per_block
518 * number of pages per block
519 * @param blocks Total number of blocks in device
520 * @param onfi_timing_mode
523 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
525 extern cvmx_nand_status_t cvmx_nand_set_defaults(int page_size, int oob_size, int pages_per_block, int blocks, int onfi_timing_mode);
529 * Call to shutdown the NAND controller after all transactions
530 * are done. In most setups this will never be called.
532 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
534 extern cvmx_nand_status_t cvmx_nand_shutdown(void);
538 * Returns a bitmask representing the chip selects that are
539 * connected to NAND chips. This can be called after the
540 * initialize to determine the actual number of NAND chips
541 * found. Each bit in the response coresponds to a chip select.
543 * @return Zero if no NAND chips were found. Otherwise a bit is set for
544 * each chip select (1<<chip).
546 extern int cvmx_nand_get_active_chips(void);
550 * Override the timing parameters for a NAND chip
552 * @param chip Chip select to override
560 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
562 extern cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[7], int clen[4], int alen[4], int rdn[4], int wrn[2]);
566 * Submit a command to the NAND command queue. Generally this
567 * will not be used directly. Instead most programs will use the other
568 * higher level NAND functions.
570 * @param cmd Command to submit
572 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
574 extern cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd);
577 * Read a page from NAND. If the buffer has room, the out of band
578 * data will be included.
580 * @param chip Chip select for NAND flash
581 * @param nand_address
582 * Location in NAND to read. See description in file comment
583 * @param buffer_address
584 * Physical address to store the result at
585 * @param buffer_length
586 * Number of bytes to read
588 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
590 extern int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length);
593 * Write a page to NAND. The buffer must contain the entire page
594 * including the out of band data.
596 * @param chip Chip select for NAND flash
597 * @param nand_address
598 * Location in NAND to write. See description in file comment
599 * @param buffer_address
600 * Physical address to read the data from
602 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
604 extern cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address);
607 * Erase a NAND block. A single block contains multiple pages.
609 * @param chip Chip select for NAND flash
610 * @param nand_address
611 * Location in NAND to erase. See description in file comment
613 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
615 extern cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address);
618 * Read the NAND ID information
620 * @param chip Chip select for NAND flash
621 * @param nand_address
622 * NAND address to read ID from. Usually this is either 0x0 or 0x20.
623 * @param buffer_address
624 * Physical address to store data in
625 * @param buffer_length
626 * Length of the buffer. Usually this is 4 bytes
628 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
630 extern int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length);
633 * Read the NAND parameter page
635 * @param chip Chip select for NAND flash
636 * @param buffer_address
637 * Physical address to store data in
638 * @param buffer_length
639 * Length of the buffer. Usually this is 4 bytes
641 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
643 extern int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length);
646 * Get the status of the NAND flash
648 * @param chip Chip select for NAND flash
650 * @return NAND status or a negative cvmx_nand_status_t error code on failure
652 extern int cvmx_nand_get_status(int chip);
655 * Get the page size, excluding out of band data. This function
656 * will return zero for chip selects not connected to NAND.
658 * @param chip Chip select for NAND flash
660 * @return Page size in bytes or a negative cvmx_nand_status_t error code on failure
662 extern int cvmx_nand_get_page_size(int chip);
667 * @param chip Chip select for NAND flash
669 * @return OOB in bytes or a negative cvmx_nand_status_t error code on failure
671 extern int cvmx_nand_get_oob_size(int chip);
674 * Get the number of pages per NAND block
676 * @param chip Chip select for NAND flash
678 * @return Numboer of pages in each block or a negative cvmx_nand_status_t error code on failure
680 extern int cvmx_nand_get_pages_per_block(int chip);
683 * Get the number of blocks in the NAND flash
685 * @param chip Chip select for NAND flash
687 * @return Number of blocks or a negative cvmx_nand_status_t error code on failure
689 extern int cvmx_nand_get_blocks(int chip);
692 * Reset the NAND flash
694 * @param chip Chip select for NAND flash
696 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
698 extern cvmx_nand_status_t cvmx_nand_reset(int chip);
701 * This function computes the Octeon specific ECC data used by the NAND boot
704 * @param block pointer to 256 bytes of data
705 * @param eccp pointer to where 8 bytes of ECC data will be stored
707 extern void cvmx_nand_compute_boot_ecc(unsigned char *block, unsigned char *eccp);
710 extern int cvmx_nand_correct_boot_ecc(uint8_t *block);
715 #endif /* __CVMX_NAND_H__ */