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49 * This header defines the CVMX interface to the NAND flash controller. The
50 * basic operations common to all NAND devices are supported by this API, but
51 * many more advanced functions are not support. The low level hardware supports
52 * all types of transactions, but this API only implements the must commonly
53 * used operations. This API performs no locking, so it is the responsibility of
54 * the caller to make sure only one thread of execution is accessing the NAND
55 * controller at a time. Most applications should not use this API directly but
56 * instead use a flash logical layer supplied through a secondary system. For
57 * example, the Linux MTD layer provides a driver for running JFFS2 on top of
60 * <h2>Selecting the NAND Chip</h2>
62 * Octeon's NAND controller assumes a single NAND chip is connected to a boot
63 * bus chip select. Throughout this API, NAND chips are referred to by the chip
64 * select they are connected to (0-7). Chip select 0 will only be a NAND chip
65 * when you are booting from NAND flash.
67 * <h2>NAND Addressing</h2>
69 * Various functions in cvmx-nand use addresses to index into NAND flash. All
70 * functions us a uniform address translation scheme to map the passed address
71 * into a NAND block, page, and column. In NAND flash a page represents the
72 * basic unit of reads and writes. Each page contains a power of two number of
73 * bytes and some number of extra out of band (OOB) bytes. A fixed number of
74 * pages fit into each NAND block. Here is the mapping of bits in the cvmx-nand
75 * address to the NAND hardware:
77 * 63 56 48 40 32 24 16 8 0
78 * +-------+-------+-------+-------+-------+-------+-------+------+
79 * | 64 bit cvmx-nand nand_address|
80 * +------------------------------------------------+----+--------+
81 * | block |page| column |
82 * +-------+-------+-------+-------+-------+--------+----+--------+
83 * 63 56 48 40 32 24 16 8 0
85 * Basically the block, page, and column addresses are packet together. Before
86 * being sent out the NAND pins for addressing the column is padded out to an
87 * even number of bytes. This means that column address are 2 bytes, or 2
88 * address cycles, for page sizes between 512 and 65536 bytes. Page sizes
89 * between 128KB and 16MB would use 3 column address cycles. NAND device
90 * normally either have 32 or 64 pages per block, needing either 5 or 6 address
91 * bits respectively. This means you have 10 bits for block address using 4
92 * address cycles, or 18 for 5 address cycles. Using the cvmx-nand addressing
93 * scheme, it is not possible to directly index the OOB data. Instead you can
94 * access it by reading or writing more data than the normal page size would
95 * allow. Logically the OOB data is appended onto the the page data. For
96 * example, this means that a read of 65 bytes from a column address of 0x7ff
97 * would yield byte 2047 of the page and then 64 bytes of OOB data.
99 * <hr>$Revision: 35726 $<hr>
102 #ifndef __CVMX_NAND_H__
103 #define __CVMX_NAND_H__
109 /* Maxium PAGE + OOB size supported. This is used to size
110 ** buffers, some that must be statically allocated. */
111 #define CVMX_NAND_MAX_PAGE_AND_OOB_SIZE (4096 + 256)
114 /* Block size for boot ECC */
115 #define CVMX_NAND_BOOT_ECC_BLOCK_SIZE (256)
116 /* ECC bytes for each block */
117 #define CVMX_NAND_BOOT_ECC_ECC_SIZE (8)
120 * Flags to be passed to the initialize function
124 CVMX_NAND_INITIALIZE_FLAGS_16BIT = 1<<0,
125 CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE = 1<<1,
126 CVMX_NAND_INITIALIZE_FLAGS_DEBUG = 1<<15,
127 } cvmx_nand_initialize_flags_t;
130 * Return codes from NAND functions
134 CVMX_NAND_SUCCESS = 0,
135 CVMX_NAND_NO_MEMORY = -1,
137 CVMX_NAND_INVALID_PARAM = -3,
138 CVMX_NAND_TIMEOUT = -4,
139 CVMX_NAND_ERROR = -5,
140 CVMX_NAND_NO_DEVICE = -6,
141 } cvmx_nand_status_t;
144 * NAND NOP command definition
148 uint64_t reserved_64_127 : 64;
149 uint64_t reserved_4_63 : 60;
151 } cvmx_nand_cmd_nop_t;
154 * NAND SET_TM_PAR command definition
158 uint64_t reserved_64_127 : 64;
159 uint64_t tim_par7 : 8;
160 uint64_t tim_par6 : 8;
161 uint64_t tim_par5 : 8;
162 uint64_t tim_par4 : 8;
163 uint64_t tim_par3 : 8;
164 uint64_t tim_par2 : 8;
165 uint64_t tim_par1 : 8;
166 uint64_t tim_mult : 4;
168 } cvmx_nand_cmd_set_tm_par_t;
171 * NAND WAIT command definition
175 uint64_t reserved_64_127 : 64;
176 uint64_t reserved_11_63 : 53;
178 uint64_t reserved_5_7 : 3;
181 } cvmx_nand_cmd_wait_t;
184 * NAND CHIP_EN command definition
188 uint64_t reserved_64_127 : 64;
189 uint64_t reserved_10_63 : 54;
194 } cvmx_nand_cmd_chip_en_t;
197 * NAND CHIP_DIS command definition
201 uint64_t reserved_64_127 : 64;
202 uint64_t reserved_4_63 : 60;
204 } cvmx_nand_cmd_chip_dis_t;
207 * NAND CLE command definition
211 uint64_t reserved_64_127 : 64;
212 uint64_t reserved_25_63 : 39;
216 uint64_t cmd_data : 8;
217 uint64_t reserved_4_7 : 4;
219 } cvmx_nand_cmd_cle_t;
222 * NAND ALE command definition
226 uint64_t reserved_96_127 : 32;
227 uint64_t adr_bytes_h : 32;
228 uint64_t adr_bytes_l : 32;
229 uint64_t reserved_28_31 : 4;
234 uint64_t reserved_12_15 : 4;
235 uint64_t adr_byte_num : 4;
236 uint64_t reserved_4_7 : 4;
238 } cvmx_nand_cmd_ale_t;
241 * NAND WR command definition
245 uint64_t reserved_64_127 : 64;
246 uint64_t reserved_31_63 : 34;
249 uint64_t reserved_20_24 : 4;
250 uint64_t data_bytes : 16;
252 } cvmx_nand_cmd_wr_t;
255 * NAND RD command definition
259 uint64_t reserved_64_127 : 64;
260 uint64_t reserved_32_63 : 32;
265 uint64_t data_bytes : 16;
267 } cvmx_nand_cmd_rd_t;
270 * NAND RD_EDO command definition
274 uint64_t reserved_64_127 : 64;
275 uint64_t reserved_32_63 : 32;
280 uint64_t data_bytes : 16;
282 } cvmx_nand_cmd_rd_edo_t;
285 * NAND WAIT_STATUS command definition
293 uint64_t comp_byte : 8;
294 uint64_t and_mask : 8;
296 uint64_t reserved_28_95 : 64;
302 uint64_t reserved_4_7 : 4;
304 } cvmx_nand_cmd_wait_status_t;
307 * NAND WAIT_STATUS_ALE command definition
315 uint64_t comp_byte : 8;
316 uint64_t and_mask : 8;
318 uint64_t adr_bytes : 32;
319 uint64_t reserved_60_63 : 4;
324 uint64_t reserved_44_47 : 4;
325 uint64_t adr_byte_num : 4;
327 uint64_t reserved_25_31 : 7;
332 uint64_t reserved_4_7 : 4;
334 } cvmx_nand_cmd_wait_status_ale_t;
337 * NAND BUS_ACQ command definition
341 uint64_t reserved_64_127 : 64;
342 uint64_t reserved_8_63 : 56;
344 uint64_t fifteen : 4;
345 } cvmx_nand_cmd_bus_acq_t;
348 * NAND BUS_REL command definition
352 uint64_t reserved_64_127 : 64;
353 uint64_t reserved_8_63 : 56;
355 uint64_t fifteen : 4;
356 } cvmx_nand_cmd_bus_rel_t;
359 * NAND command union of all possible commands
364 cvmx_nand_cmd_nop_t nop;
365 cvmx_nand_cmd_set_tm_par_t set_tm_par;
366 cvmx_nand_cmd_wait_t wait;
367 cvmx_nand_cmd_chip_en_t chip_en;
368 cvmx_nand_cmd_chip_dis_t chip_dis;
369 cvmx_nand_cmd_cle_t cle;
370 cvmx_nand_cmd_ale_t ale;
371 cvmx_nand_cmd_rd_t rd;
372 cvmx_nand_cmd_rd_edo_t rd_edo;
373 cvmx_nand_cmd_wr_t wr;
374 cvmx_nand_cmd_wait_status_t wait_status;
375 cvmx_nand_cmd_wait_status_ale_t wait_status_ale;
376 cvmx_nand_cmd_bus_acq_t bus_acq;
377 cvmx_nand_cmd_bus_rel_t bus_rel;
380 uint64_t reserved_64_127: 64;
381 uint64_t reserved_4_63 : 60;
382 uint64_t op_code : 4;
387 typedef struct __attribute__ ((packed))
389 char onfi[4]; /**< Bytes 0-3: The ASCII characters 'O', 'N', 'F', 'I' */
390 uint16_t revision_number; /**< Bytes 4-5: ONFI revision number
392 - 1 1 = supports ONFI version 1.0
394 uint16_t features; /**< Bytes 6-7: Features supported
396 - 4 1 = supports odd to even page Copyback
397 - 3 1 = supports interleaved operations
398 - 2 1 = supports non-sequential page programming
399 - 1 1 = supports multiple LUN operations
400 - 0 1 = supports 16-bit data bus width */
401 uint16_t optional_commands; /**< Bytes 8-9: Optional commands supported
403 - 5 1 = supports Read Unique ID
404 - 4 1 = supports Copyback
405 - 3 1 = supports Read Status Enhanced
406 - 2 1 = supports Get Features and Set Features
407 - 1 1 = supports Read Cache commands
408 - 0 1 = supports Page Cache Program command */
409 uint8_t reserved_10_31[22]; /**< Bytes 10-31: Reserved */
411 char manufacturer[12]; /**< Bytes 32-43: Device manufacturer (12 ASCII characters) */
412 char model[20]; /**< Bytes 40-63: Device model (20 ASCII characters) */
413 uint8_t jedec_id; /**< Byte 64: JEDEC manufacturer ID */
414 uint16_t date_code; /**< Byte 65-66: Date code */
415 uint8_t reserved_67_79[13]; /**< Bytes 67-79: Reserved */
417 uint32_t page_data_bytes; /**< Bytes 80-83: Number of data bytes per page */
418 uint16_t page_spare_bytes; /**< Bytes 84-85: Number of spare bytes per page */
419 uint32_t partial_page_data_bytes; /**< Bytes 86-89: Number of data bytes per partial page */
420 uint16_t partial_page_spare_bytes; /**< Bytes 90-91: Number of spare bytes per partial page */
421 uint32_t pages_per_block; /**< Bytes 92-95: Number of pages per block */
422 uint32_t blocks_per_lun; /**< Bytes 96-99: Number of blocks per logical unit (LUN) */
423 uint8_t number_lun; /**< Byte 100: Number of logical units (LUNs) */
424 uint8_t address_cycles; /**< Byte 101: Number of address cycles
425 - 4-7 Column address cycles
426 - 0-3 Row address cycles */
427 uint8_t bits_per_cell; /**< Byte 102: Number of bits per cell */
428 uint16_t bad_block_per_lun; /**< Bytes 103-104: Bad blocks maximum per LUN */
429 uint16_t block_endurance; /**< Bytes 105-106: Block endurance */
430 uint8_t good_blocks; /**< Byte 107: Guaranteed valid blocks at beginning of target */
431 uint16_t good_block_endurance; /**< Bytes 108-109: Block endurance for guaranteed valid blocks */
432 uint8_t programs_per_page; /**< Byte 110: Number of programs per page */
433 uint8_t partial_program_attrib; /**< Byte 111: Partial programming attributes
435 - 4 1 = partial page layout is partial page data followed by partial page spare
437 - 0 1 = partial page programming has constraints */
438 uint8_t bits_ecc; /**< Byte 112: Number of bits ECC correctability */
439 uint8_t interleaved_address_bits; /**< Byte 113: Number of interleaved address bits
441 - 0-3 Number of interleaved address bits */
442 uint8_t interleaved_attrib; /**< Byte 114: Interleaved operation attributes
444 - 3 Address restrictions for program cache
445 - 2 1 = program cache supported
446 - 1 1 = no block address restrictions
447 - 0 Overlapped / concurrent interleaving support */
448 uint8_t reserved_115_127[13]; /**< Bytes 115-127: Reserved (0) */
450 uint8_t pin_capacitance; /**< Byte 128: I/O pin capacitance */
451 uint16_t timing_mode; /**< Byte 129-130: Timing mode support
453 - 5 1 = supports timing mode 5
454 - 4 1 = supports timing mode 4
455 - 3 1 = supports timing mode 3
456 - 2 1 = supports timing mode 2
457 - 1 1 = supports timing mode 1
458 - 0 1 = supports timing mode 0, shall be 1 */
459 uint16_t cache_timing_mode; /**< Byte 131-132: Program cache timing mode support
461 - 5 1 = supports timing mode 5
462 - 4 1 = supports timing mode 4
463 - 3 1 = supports timing mode 3
464 - 2 1 = supports timing mode 2
465 - 1 1 = supports timing mode 1
466 - 0 1 = supports timing mode 0 */
467 uint16_t t_prog; /**< Byte 133-134: Maximum page program time (us) */
468 uint16_t t_bers; /**< Byte 135-136: Maximum block erase time (us) */
469 uint16_t t_r; /**< Byte 137-148: Maximum page read time (us) */
470 uint16_t t_ccs; /**< Byte 139-140: Minimum change column setup time (ns) */
471 uint8_t reserved_141_163[23]; /**< Byte 141-163: Reserved (0) */
473 uint16_t vendor_revision; /**< Byte 164-165: Vendor specific Revision number */
474 uint8_t vendor_specific[88]; /**< Byte 166-253: Vendor specific */
475 uint16_t crc; /**< Byte 254-255: Integrity CRC */
476 } cvmx_nand_onfi_param_page_t;
480 * Called to initialize the NAND controller for use. Note that
481 * you must be running out of L2 or memory and not NAND before
482 * calling this function.
483 * When probing for NAND chips, this function attempts to autoconfigure based on the NAND parts detected.
484 * It currently supports autodetection for ONFI parts (with valid parameter pages), and some Samsung NAND
485 * parts (decoding ID bits.) If autoconfiguration fails, the defaults set with __set_chip_defaults()
486 * prior to calling cvmx_nand_initialize() are used.
487 * If defaults are set and the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is provided, the defaults are used
488 * for all chips in the active_chips mask.
490 * @param flags Optional initialization flags
491 * If the CVMX_NAND_INITIALIZE_FLAGS_DONT_PROBE flag is passed, chips are not probed,
492 * and the default parameters (if set with cvmx_nand_set_defaults) are used for all chips
493 * in the active_chips mask.
494 * @param active_chips
495 * Each bit in this parameter represents a chip select that might
496 * contain NAND flash. Any chip select present in this bitmask may
497 * be connected to NAND. It is normally safe to pass 0xff here and
498 * let the API probe all 8 chip selects.
500 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
502 extern cvmx_nand_status_t cvmx_nand_initialize(cvmx_nand_initialize_flags_t flags, int active_chips);
507 * This function may be called before cvmx_nand_initialize to set default values that will be used
508 * for NAND chips that do not identify themselves in a way that allows autoconfiguration. (ONFI chip with
509 * missing parameter page, for example.)
510 * The parameters set by this function will be used by _all_ non-autoconfigured NAND chips.
513 * NOTE: This function signature is _NOT_ stable, and will change in the future as required to support
514 * various NAND chips.
516 * @param page_size page size in bytes
517 * @param oob_size Out of band size in bytes (per page)
518 * @param pages_per_block
519 * number of pages per block
520 * @param blocks Total number of blocks in device
521 * @param onfi_timing_mode
524 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
526 extern cvmx_nand_status_t cvmx_nand_set_defaults(int page_size, int oob_size, int pages_per_block, int blocks, int onfi_timing_mode);
530 * Call to shutdown the NAND controller after all transactions
531 * are done. In most setups this will never be called.
533 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
535 extern cvmx_nand_status_t cvmx_nand_shutdown(void);
539 * Returns a bitmask representing the chip selects that are
540 * connected to NAND chips. This can be called after the
541 * initialize to determine the actual number of NAND chips
542 * found. Each bit in the response coresponds to a chip select.
544 * @return Zero if no NAND chips were found. Otherwise a bit is set for
545 * each chip select (1<<chip).
547 extern int cvmx_nand_get_active_chips(void);
551 * Override the timing parameters for a NAND chip
553 * @param chip Chip select to override
561 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
563 extern cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[7], int clen[4], int alen[4], int rdn[4], int wrn[2]);
567 * Submit a command to the NAND command queue. Generally this
568 * will not be used directly. Instead most programs will use the other
569 * higher level NAND functions.
571 * @param cmd Command to submit
573 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
575 extern cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd);
578 * Read a page from NAND. If the buffer has room, the out of band
579 * data will be included.
581 * @param chip Chip select for NAND flash
582 * @param nand_address
583 * Location in NAND to read. See description in file comment
584 * @param buffer_address
585 * Physical address to store the result at
586 * @param buffer_length
587 * Number of bytes to read
589 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
591 extern int cvmx_nand_page_read(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length);
594 * Write a page to NAND. The buffer must contain the entire page
595 * including the out of band data.
597 * @param chip Chip select for NAND flash
598 * @param nand_address
599 * Location in NAND to write. See description in file comment
600 * @param buffer_address
601 * Physical address to read the data from
603 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
605 extern cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_address);
608 * Erase a NAND block. A single block contains multiple pages.
610 * @param chip Chip select for NAND flash
611 * @param nand_address
612 * Location in NAND to erase. See description in file comment
614 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
616 extern cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address);
619 * Read the NAND ID information
621 * @param chip Chip select for NAND flash
622 * @param nand_address
623 * NAND address to read ID from. Usually this is either 0x0 or 0x20.
624 * @param buffer_address
625 * Physical address to store data in
626 * @param buffer_length
627 * Length of the buffer. Usually this is 4 bytes
629 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
631 extern int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_length);
634 * Read the NAND parameter page
636 * @param chip Chip select for NAND flash
637 * @param buffer_address
638 * Physical address to store data in
639 * @param buffer_length
640 * Length of the buffer. Usually this is 4 bytes
642 * @return Bytes read on success, a negative cvmx_nand_status_t error code on failure
644 extern int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length);
647 * Get the status of the NAND flash
649 * @param chip Chip select for NAND flash
651 * @return NAND status or a negative cvmx_nand_status_t error code on failure
653 extern int cvmx_nand_get_status(int chip);
656 * Get the page size, excluding out of band data. This function
657 * will return zero for chip selects not connected to NAND.
659 * @param chip Chip select for NAND flash
661 * @return Page size in bytes or a negative cvmx_nand_status_t error code on failure
663 extern int cvmx_nand_get_page_size(int chip);
668 * @param chip Chip select for NAND flash
670 * @return OOB in bytes or a negative cvmx_nand_status_t error code on failure
672 extern int cvmx_nand_get_oob_size(int chip);
675 * Get the number of pages per NAND block
677 * @param chip Chip select for NAND flash
679 * @return Numboer of pages in each block or a negative cvmx_nand_status_t error code on failure
681 extern int cvmx_nand_get_pages_per_block(int chip);
684 * Get the number of blocks in the NAND flash
686 * @param chip Chip select for NAND flash
688 * @return Number of blocks or a negative cvmx_nand_status_t error code on failure
690 extern int cvmx_nand_get_blocks(int chip);
693 * Reset the NAND flash
695 * @param chip Chip select for NAND flash
697 * @return Zero on success, a negative cvmx_nand_status_t error code on failure
699 extern cvmx_nand_status_t cvmx_nand_reset(int chip);
702 * This function computes the Octeon specific ECC data used by the NAND boot
705 * @param block pointer to 256 bytes of data
706 * @param eccp pointer to where 8 bytes of ECC data will be stored
708 extern void cvmx_nand_compute_boot_ecc(unsigned char *block, unsigned char *eccp);
711 extern int cvmx_nand_correct_boot_ecc(uint8_t *block);
716 #endif /* __CVMX_NAND_H__ */