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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_NDF_DEFS_H__
53 #define __CVMX_NDF_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
57 static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
60 cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001070001000018ull);
64 #define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
68 static inline uint64_t CVMX_NDF_CMD_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
71 cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001070001000000ull);
75 #define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull))
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
79 static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
81 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
82 cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001070001000030ull);
86 #define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull))
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
90 static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
92 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
93 cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001070001000010ull);
97 #define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull))
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 #define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
101 static inline uint64_t CVMX_NDF_INT_FUNC(void)
103 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
104 cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
105 return CVMX_ADD_IO_SEG(0x0001070001000020ull);
108 #define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull))
110 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
111 #define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
112 static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
114 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
115 cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
116 return CVMX_ADD_IO_SEG(0x0001070001000028ull);
119 #define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull))
121 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
122 #define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
123 static inline uint64_t CVMX_NDF_MISC_FUNC(void)
125 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
126 cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
127 return CVMX_ADD_IO_SEG(0x0001070001000008ull);
130 #define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull))
132 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
133 #define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
134 static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
136 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
137 cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
138 return CVMX_ADD_IO_SEG(0x0001070001000038ull);
141 #define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull))
145 * cvmx_ndf_bt_pg_info
148 * NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR
149 * during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is
150 * used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is
151 * otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value.
153 * Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes.
154 * 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values
156 * Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this
157 * field, and a SW CSR write with a value greater than 8, will write an 8 to this field.
159 * Like all NDF_... registers, 64-bit operations must be used to access this register
161 union cvmx_ndf_bt_pg_info {
163 struct cvmx_ndf_bt_pg_info_s {
164 #ifdef __BIG_ENDIAN_BITFIELD
165 uint64_t reserved_11_63 : 53;
166 uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
168 uint64_t adr_cyc : 4; /**< # of column address cycles */
169 uint64_t size : 3; /**< bytes per page in the nand device */
172 uint64_t adr_cyc : 4;
174 uint64_t reserved_11_63 : 53;
177 struct cvmx_ndf_bt_pg_info_s cn52xx;
178 struct cvmx_ndf_bt_pg_info_s cn63xx;
179 struct cvmx_ndf_bt_pg_info_s cn63xxp1;
180 struct cvmx_ndf_bt_pg_info_s cn66xx;
181 struct cvmx_ndf_bt_pg_info_s cn68xx;
182 struct cvmx_ndf_bt_pg_info_s cn68xxp1;
184 typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t;
190 * When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes
191 * this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it
192 * must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these
193 * 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr.
195 * Like all NDF_... registers, 64-bit operations must be used to access this register
199 struct cvmx_ndf_cmd_s {
200 #ifdef __BIG_ENDIAN_BITFIELD
201 uint64_t nf_cmd : 64; /**< 8 Command Bytes */
203 uint64_t nf_cmd : 64;
206 struct cvmx_ndf_cmd_s cn52xx;
207 struct cvmx_ndf_cmd_s cn63xx;
208 struct cvmx_ndf_cmd_s cn63xxp1;
209 struct cvmx_ndf_cmd_s cn66xx;
210 struct cvmx_ndf_cmd_s cn68xx;
211 struct cvmx_ndf_cmd_s cn68xxp1;
213 typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t;
219 * SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value.
220 * HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the
221 * flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will
222 * stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a
223 * non-zero data value, can the execution unit come out of the stalled condition, and resume execution.
225 * The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit
226 * has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by
227 * asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of
228 * commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and
229 * the last command in the sequence will be a bus release command. The execution unit will start execution of
230 * the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first
231 * command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command
232 * and ending with a chip disable command, and then write a non-zero data value to this csr to increment the
233 * CNT field by the number of the command sequences, loaded to the command fifo.
235 * Like all NDF_... registers, 64-bit operations must be used to access this register
237 union cvmx_ndf_drbell {
239 struct cvmx_ndf_drbell_s {
240 #ifdef __BIG_ENDIAN_BITFIELD
241 uint64_t reserved_8_63 : 56;
242 uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */
245 uint64_t reserved_8_63 : 56;
248 struct cvmx_ndf_drbell_s cn52xx;
249 struct cvmx_ndf_drbell_s cn63xx;
250 struct cvmx_ndf_drbell_s cn63xxp1;
251 struct cvmx_ndf_drbell_s cn66xx;
252 struct cvmx_ndf_drbell_s cn68xx;
253 struct cvmx_ndf_drbell_s cn68xxp1;
255 typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t;
261 * XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256]
262 * ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot
263 * ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash
265 * Like all NDF_... registers, 64-bit operations must be used to access this register
267 union cvmx_ndf_ecc_cnt {
269 struct cvmx_ndf_ecc_cnt_s {
270 #ifdef __BIG_ENDIAN_BITFIELD
271 uint64_t reserved_32_63 : 32;
272 uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated
273 bytes. The value pertains to the last 1 bit ecc err */
274 uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot
275 This count saturates instead of wrapping around. */
277 uint64_t ecc_err : 8;
278 uint64_t xor_ecc : 24;
279 uint64_t reserved_32_63 : 32;
282 struct cvmx_ndf_ecc_cnt_s cn52xx;
283 struct cvmx_ndf_ecc_cnt_s cn63xx;
284 struct cvmx_ndf_ecc_cnt_s cn63xxp1;
285 struct cvmx_ndf_ecc_cnt_s cn66xx;
286 struct cvmx_ndf_ecc_cnt_s cn68xx;
287 struct cvmx_ndf_ecc_cnt_s cn68xxp1;
289 typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t;
295 * FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it.
297 * EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the
298 * last instruction out of the command fifo.
300 * Like all NDF_... registers, 64-bit operations must be used to access this register
304 struct cvmx_ndf_int_s {
305 #ifdef __BIG_ENDIAN_BITFIELD
306 uint64_t reserved_7_63 : 57;
307 uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a
309 uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */
310 uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */
311 uint64_t sm_bad : 1; /**< One of the state machines in a bad state */
312 uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */
313 uint64_t full : 1; /**< Command fifo is full */
314 uint64_t empty : 1; /**< Command fifo is empty */
320 uint64_t ecc_1bit : 1;
321 uint64_t ecc_mult : 1;
323 uint64_t reserved_7_63 : 57;
326 struct cvmx_ndf_int_s cn52xx;
327 struct cvmx_ndf_int_s cn63xx;
328 struct cvmx_ndf_int_s cn63xxp1;
329 struct cvmx_ndf_int_s cn66xx;
330 struct cvmx_ndf_int_s cn68xx;
331 struct cvmx_ndf_int_s cn68xxp1;
333 typedef union cvmx_ndf_int cvmx_ndf_int_t;
339 * Like all NDF_... registers, 64-bit operations must be used to access this register
342 union cvmx_ndf_int_en {
344 struct cvmx_ndf_int_en_s {
345 #ifdef __BIG_ENDIAN_BITFIELD
346 uint64_t reserved_7_63 : 57;
347 uint64_t ovrf : 1; /**< Wrote to a full command fifo */
348 uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */
349 uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */
350 uint64_t sm_bad : 1; /**< One of the state machines in a bad state */
351 uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */
352 uint64_t full : 1; /**< Command fifo is full */
353 uint64_t empty : 1; /**< Command fifo is empty */
359 uint64_t ecc_1bit : 1;
360 uint64_t ecc_mult : 1;
362 uint64_t reserved_7_63 : 57;
365 struct cvmx_ndf_int_en_s cn52xx;
366 struct cvmx_ndf_int_en_s cn63xx;
367 struct cvmx_ndf_int_en_s cn63xxp1;
368 struct cvmx_ndf_int_en_s cn66xx;
369 struct cvmx_ndf_int_en_s cn68xx;
370 struct cvmx_ndf_int_en_s cn68xxp1;
372 typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t;
378 * NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo.
379 * the fifo size is 16 entries.
381 * WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count
382 * represents number of eclk cycles.
384 * FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands
385 * complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1)
387 * RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo,
388 * in response to RD_CMD bit being set to 1 by SW.
390 * RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response
391 * to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0.
393 * RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the
394 * RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the
395 * NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the
396 * middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD
397 * bit will be cleared on any NDF_CMD csr write by SW.
399 * BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin.
400 * SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0
401 * when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is
402 * permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0.
404 * BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended.
405 * whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must
406 * never be set when booting from nand flash and region zero is enabled.
408 * EX_DIS When 1, command execution stops after completing execution of all commands currently in the command
409 * fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution
410 * will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo
411 * is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0.
413 * RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting
414 * the fifo. The fifo comes up empty at the end of power on reset.
416 * Like all NDF_... registers, 64-bit operations must be used to access this register
418 union cvmx_ndf_misc {
420 struct cvmx_ndf_misc_s {
421 #ifdef __BIG_ENDIAN_BITFIELD
422 uint64_t reserved_28_63 : 36;
423 uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads
424 or boot dma's proceed as if no multi bit errors
425 occured. HW will fix single bit errors as usual */
426 uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */
427 uint64_t wait_cnt : 6; /**< WAIT input filter count */
428 uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */
429 uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes
430 command fifo read out, in response to RD_CMD */
431 uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8
432 bytes from Command fifo into the NDF_CMD csr
433 SW reads NDF_CMD csr, HW clears this bit to 0 */
434 uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8
435 bytes at a time into the NDF_CMD csr */
436 uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */
437 uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1
438 causes boot state mchines to sleep */
439 uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at
440 next command in the fifo. */
441 uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty,
442 0=normal operation */
450 uint64_t rd_done : 1;
451 uint64_t fr_byt : 11;
452 uint64_t wait_cnt : 6;
453 uint64_t nbr_hwm : 3;
455 uint64_t reserved_28_63 : 36;
458 struct cvmx_ndf_misc_cn52xx {
459 #ifdef __BIG_ENDIAN_BITFIELD
460 uint64_t reserved_27_63 : 37;
461 uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */
462 uint64_t wait_cnt : 6; /**< WAIT input filter count */
463 uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */
464 uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes
465 command fifo read out, in response to RD_CMD */
466 uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8
467 bytes from Command fifo into the NDF_CMD csr
468 SW reads NDF_CMD csr, HW clears this bit to 0 */
469 uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8
470 bytes at a time into the NDF_CMD csr */
471 uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */
472 uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1
473 causes boot state mchines to sleep */
474 uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at
475 next command in the fifo. */
476 uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty,
477 0=normal operation */
485 uint64_t rd_done : 1;
486 uint64_t fr_byt : 11;
487 uint64_t wait_cnt : 6;
488 uint64_t nbr_hwm : 3;
489 uint64_t reserved_27_63 : 37;
492 struct cvmx_ndf_misc_s cn63xx;
493 struct cvmx_ndf_misc_s cn63xxp1;
494 struct cvmx_ndf_misc_s cn66xx;
495 struct cvmx_ndf_misc_s cn68xx;
496 struct cvmx_ndf_misc_s cn68xxp1;
498 typedef union cvmx_ndf_misc cvmx_ndf_misc_t;
504 * This CSR aggregates all state machines used in nand flash controller for debug.
505 * Like all NDF_... registers, 64-bit operations must be used to access this register
507 union cvmx_ndf_st_reg {
509 struct cvmx_ndf_st_reg_s {
510 #ifdef __BIG_ENDIAN_BITFIELD
511 uint64_t reserved_16_63 : 48;
512 uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy
513 1 means execution of command sequence is complete
514 and command fifo is empty */
515 uint64_t exe_sm : 4; /**< Command Execution State machine states */
516 uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */
517 uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */
518 uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */
519 uint64_t main_bad : 1; /**< Main State machine in bad state */
520 uint64_t main_sm : 3; /**< Main State machine states */
522 uint64_t main_sm : 3;
523 uint64_t main_bad : 1;
525 uint64_t rd_ff_bad : 1;
528 uint64_t exe_idle : 1;
529 uint64_t reserved_16_63 : 48;
532 struct cvmx_ndf_st_reg_s cn52xx;
533 struct cvmx_ndf_st_reg_s cn63xx;
534 struct cvmx_ndf_st_reg_s cn63xxp1;
535 struct cvmx_ndf_st_reg_s cn66xx;
536 struct cvmx_ndf_st_reg_s cn68xx;
537 struct cvmx_ndf_st_reg_s cn68xxp1;
539 typedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t;