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38 ***********************license end**************************************/
49 * PCI / PCIe packet engine related structures.
51 * <hr>$Revision: 70030 $<hr>
54 #ifndef __CVMX_NPI_H__
55 #define __CVMX_NPI_H__
62 * PCI / PCIe packet instruction header format
69 #ifdef __BIG_ENDIAN_BITFIELD
70 uint64_t r : 1; /**< Packet is RAW */
71 uint64_t g : 1; /**< Gather list is used */
72 uint64_t dlengsz : 14; /**< Data length / Gather list size */
73 uint64_t fsz : 6; /**< Front data size */
74 uint64_t qos : 3; /**< POW QoS queue */
75 uint64_t grp : 4; /**< POW Group */
76 uint64_t rs : 1; /**< Real short */
77 cvmx_pow_tag_type_t tt : 2; /**< POW Tag type */
78 uint64_t tag : 32; /**< POW 32 bit tag */
81 cvmx_pow_tag_type_t tt : 2;
86 uint64_t dlengsz : 14;
91 } cvmx_npi_inst_hdr_t;
94 * PCI / PCIe packet data pointer formats 0-3
101 #ifdef __BIG_ENDIAN_BITFIELD
102 uint64_t es : 2; /**< Endian swap mode */
103 uint64_t ns : 1; /**< No snoop */
104 uint64_t ro : 1; /**< Relaxed ordering */
105 uint64_t addr : 60; /**< PCI/PCIe address */
115 #ifdef __BIG_ENDIAN_BITFIELD
116 uint64_t pm : 2; /**< Parse mode */
117 uint64_t sl : 7; /**< Skip length */
118 uint64_t addr : 55; /**< PCI/PCIe address */
127 #ifdef __BIG_ENDIAN_BITFIELD
128 uint64_t es : 2; /**< Endian swap mode */
129 uint64_t ns : 1; /**< No snoop */
130 uint64_t ro : 1; /**< Relaxed ordering */
131 uint64_t pm : 2; /**< Parse mode */
132 uint64_t sl : 7; /**< Skip length */
133 uint64_t addr : 51; /**< PCI/PCIe address */
149 #endif /* __CVMX_NPI_H__ */