1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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7 * modification, are permitted provided that the following conditions are
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PCSX_DEFS_H__
53 #define __CVMX_PCSX_DEFS_H__
55 static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
57 switch(cvmx_get_octeon_family()) {
58 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
59 if (((offset <= 1)) && ((block_id == 0)))
60 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
62 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
63 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
64 if (((offset <= 3)) && ((block_id == 0)))
65 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
67 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
68 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
69 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
70 if (((offset <= 3)) && ((block_id <= 1)))
71 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
73 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
74 if (((offset <= 3)) && ((block_id <= 4)))
75 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
78 cvmx_warn("CVMX_PCSX_ANX_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
79 return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
81 static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
83 switch(cvmx_get_octeon_family()) {
84 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
85 if (((offset <= 1)) && ((block_id == 0)))
86 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
88 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
89 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
90 if (((offset <= 3)) && ((block_id == 0)))
91 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
93 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
94 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
95 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
96 if (((offset <= 3)) && ((block_id <= 1)))
97 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
99 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
100 if (((offset <= 3)) && ((block_id <= 4)))
101 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
104 cvmx_warn("CVMX_PCSX_ANX_EXT_ST_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
105 return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
107 static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
109 switch(cvmx_get_octeon_family()) {
110 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
111 if (((offset <= 1)) && ((block_id == 0)))
112 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
114 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
115 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
116 if (((offset <= 3)) && ((block_id == 0)))
117 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
119 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
120 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
121 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
122 if (((offset <= 3)) && ((block_id <= 1)))
123 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
125 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
126 if (((offset <= 3)) && ((block_id <= 4)))
127 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
130 cvmx_warn("CVMX_PCSX_ANX_LP_ABIL_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
131 return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
133 static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
135 switch(cvmx_get_octeon_family()) {
136 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
137 if (((offset <= 1)) && ((block_id == 0)))
138 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
140 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
141 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
142 if (((offset <= 3)) && ((block_id == 0)))
143 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
145 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
146 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
147 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
148 if (((offset <= 3)) && ((block_id <= 1)))
149 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
151 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
152 if (((offset <= 3)) && ((block_id <= 4)))
153 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
156 cvmx_warn("CVMX_PCSX_ANX_RESULTS_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
157 return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
159 static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
161 switch(cvmx_get_octeon_family()) {
162 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
163 if (((offset <= 1)) && ((block_id == 0)))
164 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
166 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
167 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
168 if (((offset <= 3)) && ((block_id == 0)))
169 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
171 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
172 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
173 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
174 if (((offset <= 3)) && ((block_id <= 1)))
175 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
177 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
178 if (((offset <= 3)) && ((block_id <= 4)))
179 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
182 cvmx_warn("CVMX_PCSX_INTX_EN_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
183 return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
185 static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
187 switch(cvmx_get_octeon_family()) {
188 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
189 if (((offset <= 1)) && ((block_id == 0)))
190 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
192 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
193 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
194 if (((offset <= 3)) && ((block_id == 0)))
195 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
197 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
198 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
199 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
200 if (((offset <= 3)) && ((block_id <= 1)))
201 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
203 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
204 if (((offset <= 3)) && ((block_id <= 4)))
205 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
208 cvmx_warn("CVMX_PCSX_INTX_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
209 return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
211 static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
213 switch(cvmx_get_octeon_family()) {
214 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
215 if (((offset <= 1)) && ((block_id == 0)))
216 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
218 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
219 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
220 if (((offset <= 3)) && ((block_id == 0)))
221 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
223 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
224 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
225 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
226 if (((offset <= 3)) && ((block_id <= 1)))
227 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
229 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
230 if (((offset <= 3)) && ((block_id <= 4)))
231 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
234 cvmx_warn("CVMX_PCSX_LINKX_TIMER_COUNT_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
235 return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
237 static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
239 switch(cvmx_get_octeon_family()) {
240 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
241 if (((offset <= 1)) && ((block_id == 0)))
242 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
244 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
245 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
246 if (((offset <= 3)) && ((block_id == 0)))
247 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
249 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
250 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
251 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
252 if (((offset <= 3)) && ((block_id <= 1)))
253 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
255 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
256 if (((offset <= 3)) && ((block_id <= 4)))
257 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
260 cvmx_warn("CVMX_PCSX_LOG_ANLX_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
261 return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
263 static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
265 switch(cvmx_get_octeon_family()) {
266 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
267 if (((offset <= 1)) && ((block_id == 0)))
268 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
270 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
271 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
272 if (((offset <= 3)) && ((block_id == 0)))
273 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
275 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
276 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
277 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
278 if (((offset <= 3)) && ((block_id <= 1)))
279 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
281 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
282 if (((offset <= 3)) && ((block_id <= 4)))
283 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
286 cvmx_warn("CVMX_PCSX_MISCX_CTL_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
287 return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
289 static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
291 switch(cvmx_get_octeon_family()) {
292 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
293 if (((offset <= 1)) && ((block_id == 0)))
294 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
296 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
297 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
298 if (((offset <= 3)) && ((block_id == 0)))
299 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
301 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
302 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
303 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
304 if (((offset <= 3)) && ((block_id <= 1)))
305 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
307 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
308 if (((offset <= 3)) && ((block_id <= 4)))
309 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
312 cvmx_warn("CVMX_PCSX_MRX_CONTROL_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
313 return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
315 static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
317 switch(cvmx_get_octeon_family()) {
318 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
319 if (((offset <= 1)) && ((block_id == 0)))
320 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
322 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
323 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
324 if (((offset <= 3)) && ((block_id == 0)))
325 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
327 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
328 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
329 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
330 if (((offset <= 3)) && ((block_id <= 1)))
331 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
333 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
334 if (((offset <= 3)) && ((block_id <= 4)))
335 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
338 cvmx_warn("CVMX_PCSX_MRX_STATUS_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
339 return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
341 static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
343 switch(cvmx_get_octeon_family()) {
344 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
345 if (((offset <= 1)) && ((block_id == 0)))
346 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
348 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
349 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
350 if (((offset <= 3)) && ((block_id == 0)))
351 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
353 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
354 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
355 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
356 if (((offset <= 3)) && ((block_id <= 1)))
357 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
359 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
360 if (((offset <= 3)) && ((block_id <= 4)))
361 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
364 cvmx_warn("CVMX_PCSX_RXX_STATES_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
365 return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
367 static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
369 switch(cvmx_get_octeon_family()) {
370 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
371 if (((offset <= 1)) && ((block_id == 0)))
372 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
374 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
375 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
376 if (((offset <= 3)) && ((block_id == 0)))
377 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
379 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
380 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
381 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
382 if (((offset <= 3)) && ((block_id <= 1)))
383 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
385 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
386 if (((offset <= 3)) && ((block_id <= 4)))
387 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
390 cvmx_warn("CVMX_PCSX_RXX_SYNC_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
391 return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
393 static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
395 switch(cvmx_get_octeon_family()) {
396 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
397 if (((offset <= 1)) && ((block_id == 0)))
398 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
400 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
401 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
402 if (((offset <= 3)) && ((block_id == 0)))
403 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
405 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
406 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
407 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
408 if (((offset <= 3)) && ((block_id <= 1)))
409 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
411 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
412 if (((offset <= 3)) && ((block_id <= 4)))
413 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
416 cvmx_warn("CVMX_PCSX_SGMX_AN_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
417 return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
419 static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
421 switch(cvmx_get_octeon_family()) {
422 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
423 if (((offset <= 1)) && ((block_id == 0)))
424 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
426 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
427 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
428 if (((offset <= 3)) && ((block_id == 0)))
429 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
431 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
432 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
433 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
434 if (((offset <= 3)) && ((block_id <= 1)))
435 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
437 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
438 if (((offset <= 3)) && ((block_id <= 4)))
439 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
442 cvmx_warn("CVMX_PCSX_SGMX_LP_ADV_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
443 return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
445 static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
447 switch(cvmx_get_octeon_family()) {
448 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
449 if (((offset <= 1)) && ((block_id == 0)))
450 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
452 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
453 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
454 if (((offset <= 3)) && ((block_id == 0)))
455 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
457 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
458 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
459 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
460 if (((offset <= 3)) && ((block_id <= 1)))
461 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
463 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
464 if (((offset <= 3)) && ((block_id <= 4)))
465 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
468 cvmx_warn("CVMX_PCSX_TXX_STATES_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
469 return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
471 static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
473 switch(cvmx_get_octeon_family()) {
474 case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
475 if (((offset <= 1)) && ((block_id == 0)))
476 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
478 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
479 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
480 if (((offset <= 3)) && ((block_id == 0)))
481 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 0) * 0x20000ull) * 1024;
483 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
484 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
485 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
486 if (((offset <= 3)) && ((block_id <= 1)))
487 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 1) * 0x20000ull) * 1024;
489 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
490 if (((offset <= 3)) && ((block_id <= 4)))
491 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 3) + ((block_id) & 7) * 0x4000ull) * 1024;
494 cvmx_warn("CVMX_PCSX_TX_RXX_POLARITY_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
495 return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + (((offset) & 1) + ((block_id) & 0) * 0x20000ull) * 1024;
499 * cvmx_pcs#_an#_adv_reg
501 * Bits [15:9] in the Status Register indicate ability to operate as per those signalling specification,
502 * when misc ctl reg MAC_PHY bit is set to MAC mode. Bits [15:9] will all, always read 1'b0, indicating
503 * that the chip cannot operate in the corresponding modes.
505 * Bit [4] RM_FLT is a don't care when the selected mode is SGMII.
509 * PCS_AN_ADV_REG = AN Advertisement Register4
511 union cvmx_pcsx_anx_adv_reg {
513 struct cvmx_pcsx_anx_adv_reg_s {
514 #ifdef __BIG_ENDIAN_BITFIELD
515 uint64_t reserved_16_63 : 48;
516 uint64_t np : 1; /**< Always 0, no next page capability supported */
517 uint64_t reserved_14_14 : 1;
518 uint64_t rem_flt : 2; /**< [<13>,<12>]
519 0 0 Link OK XMIT=DATA
520 0 1 Link failure (loss of sync, XMIT!= DATA)
521 1 0 local device Offline
522 1 1 AN Error failure to complete AN
523 AN Error is set if resolution function
524 precludes operation with link partner */
525 uint64_t reserved_9_11 : 3;
526 uint64_t pause : 2; /**< [<8>, <7>] Pause frame flow capability across link
527 Exchanged during Auto Negotiation
531 1 1 Both symm and asymm pause to local device */
532 uint64_t hfd : 1; /**< 1 means local device Half Duplex capable */
533 uint64_t fd : 1; /**< 1 means local device Full Duplex capable */
534 uint64_t reserved_0_4 : 5;
536 uint64_t reserved_0_4 : 5;
540 uint64_t reserved_9_11 : 3;
541 uint64_t rem_flt : 2;
542 uint64_t reserved_14_14 : 1;
544 uint64_t reserved_16_63 : 48;
547 struct cvmx_pcsx_anx_adv_reg_s cn52xx;
548 struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
549 struct cvmx_pcsx_anx_adv_reg_s cn56xx;
550 struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
551 struct cvmx_pcsx_anx_adv_reg_s cn61xx;
552 struct cvmx_pcsx_anx_adv_reg_s cn63xx;
553 struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
554 struct cvmx_pcsx_anx_adv_reg_s cn66xx;
555 struct cvmx_pcsx_anx_adv_reg_s cn68xx;
556 struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
557 struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
559 typedef union cvmx_pcsx_anx_adv_reg cvmx_pcsx_anx_adv_reg_t;
562 * cvmx_pcs#_an#_ext_st_reg
565 * an_results_reg is don't care when AN_OVRD is set to 1. If AN_OVRD=0 and AN_CPT=1
566 * the an_results_reg is valid.
569 * PCS_AN_EXT_ST_REG = AN Extended Status Register15
570 * as per IEEE802.3 Clause 22
572 union cvmx_pcsx_anx_ext_st_reg {
574 struct cvmx_pcsx_anx_ext_st_reg_s {
575 #ifdef __BIG_ENDIAN_BITFIELD
576 uint64_t reserved_16_63 : 48;
577 uint64_t thou_xfd : 1; /**< 1 means PHY is 1000BASE-X Full Dup capable */
578 uint64_t thou_xhd : 1; /**< 1 means PHY is 1000BASE-X Half Dup capable */
579 uint64_t thou_tfd : 1; /**< 1 means PHY is 1000BASE-T Full Dup capable */
580 uint64_t thou_thd : 1; /**< 1 means PHY is 1000BASE-T Half Dup capable */
581 uint64_t reserved_0_11 : 12;
583 uint64_t reserved_0_11 : 12;
584 uint64_t thou_thd : 1;
585 uint64_t thou_tfd : 1;
586 uint64_t thou_xhd : 1;
587 uint64_t thou_xfd : 1;
588 uint64_t reserved_16_63 : 48;
591 struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
592 struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
593 struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
594 struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
595 struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
596 struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
597 struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
598 struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
599 struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
600 struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
601 struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
603 typedef union cvmx_pcsx_anx_ext_st_reg cvmx_pcsx_anx_ext_st_reg_t;
606 * cvmx_pcs#_an#_lp_abil_reg
608 * PCS_AN_LP_ABIL_REG = AN link Partner Ability Register5
609 * as per IEEE802.3 Clause 37
611 union cvmx_pcsx_anx_lp_abil_reg {
613 struct cvmx_pcsx_anx_lp_abil_reg_s {
614 #ifdef __BIG_ENDIAN_BITFIELD
615 uint64_t reserved_16_63 : 48;
616 uint64_t np : 1; /**< 1=lp next page capable, 0=lp not next page capable */
617 uint64_t ack : 1; /**< 1=Acknowledgement received */
618 uint64_t rem_flt : 2; /**< [<13>,<12>] Link Partner's link status
623 uint64_t reserved_9_11 : 3;
624 uint64_t pause : 2; /**< [<8>, <7>] Link Partner Pause setting
628 1 1 Both symm and asymm pause to local device */
629 uint64_t hfd : 1; /**< 1 means link partner Half Duplex capable */
630 uint64_t fd : 1; /**< 1 means link partner Full Duplex capable */
631 uint64_t reserved_0_4 : 5;
633 uint64_t reserved_0_4 : 5;
637 uint64_t reserved_9_11 : 3;
638 uint64_t rem_flt : 2;
641 uint64_t reserved_16_63 : 48;
644 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
645 struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
646 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
647 struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
648 struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
649 struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
650 struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
651 struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
652 struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
653 struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
654 struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
656 typedef union cvmx_pcsx_anx_lp_abil_reg cvmx_pcsx_anx_lp_abil_reg_t;
659 * cvmx_pcs#_an#_results_reg
661 * PCS_AN_RESULTS_REG = AN Results Register
664 union cvmx_pcsx_anx_results_reg {
666 struct cvmx_pcsx_anx_results_reg_s {
667 #ifdef __BIG_ENDIAN_BITFIELD
668 uint64_t reserved_7_63 : 57;
669 uint64_t pause : 2; /**< [<6>, <5>] PAUSE Selection (Don't care for SGMII)
670 0 0 Disable Pause, TX and RX
671 0 1 Enable pause frames RX only
672 1 0 Enable Pause frames TX only
673 1 1 Enable pause frames TX and RX */
674 uint64_t spd : 2; /**< [<4>, <3>] Link Speed Selection
679 uint64_t an_cpt : 1; /**< 1=AN Completed, 0=AN not completed or failed */
680 uint64_t dup : 1; /**< 1=Full Duplex, 0=Half Duplex */
681 uint64_t link_ok : 1; /**< 1=Link up(OK), 0=Link down */
683 uint64_t link_ok : 1;
688 uint64_t reserved_7_63 : 57;
691 struct cvmx_pcsx_anx_results_reg_s cn52xx;
692 struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
693 struct cvmx_pcsx_anx_results_reg_s cn56xx;
694 struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
695 struct cvmx_pcsx_anx_results_reg_s cn61xx;
696 struct cvmx_pcsx_anx_results_reg_s cn63xx;
697 struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
698 struct cvmx_pcsx_anx_results_reg_s cn66xx;
699 struct cvmx_pcsx_anx_results_reg_s cn68xx;
700 struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
701 struct cvmx_pcsx_anx_results_reg_s cnf71xx;
703 typedef union cvmx_pcsx_anx_results_reg cvmx_pcsx_anx_results_reg_t;
706 * cvmx_pcs#_int#_en_reg
708 * NOTE: RXERR and TXERR conditions to be discussed with Dan before finalising
709 * DBG_SYNC interrupt fires when code group synchronization state machine makes a transition from
710 * SYNC_ACQUIRED_1 state to SYNC_ACQUIRED_2 state(See IEEE 802.3-2005 figure 37-9). It is an indication that a bad code group
711 * was received after code group synchronizaton was achieved. This interrupt should be disabled during normal link operation.
712 * Use it as a debug help feature only.
715 * PCS Interrupt Enable Register
717 union cvmx_pcsx_intx_en_reg {
719 struct cvmx_pcsx_intx_en_reg_s {
720 #ifdef __BIG_ENDIAN_BITFIELD
721 uint64_t reserved_13_63 : 51;
722 uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */
723 uint64_t dup : 1; /**< Enable duplex mode changed interrupt */
724 uint64_t sync_bad_en : 1; /**< Enable rx sync st machine in bad state interrupt */
725 uint64_t an_bad_en : 1; /**< Enable AN state machine bad state interrupt */
726 uint64_t rxlock_en : 1; /**< Enable rx code group sync/bit lock failure interrupt */
727 uint64_t rxbad_en : 1; /**< Enable rx state machine in bad state interrupt */
728 uint64_t rxerr_en : 1; /**< Enable RX error condition interrupt */
729 uint64_t txbad_en : 1; /**< Enable tx state machine in bad state interrupt */
730 uint64_t txfifo_en : 1; /**< Enable tx fifo overflow condition interrupt */
731 uint64_t txfifu_en : 1; /**< Enable tx fifo underflow condition intrrupt */
732 uint64_t an_err_en : 1; /**< Enable AN Error condition interrupt */
733 uint64_t xmit_en : 1; /**< Enable XMIT variable state change interrupt */
734 uint64_t lnkspd_en : 1; /**< Enable Link Speed has changed interrupt */
736 uint64_t lnkspd_en : 1;
737 uint64_t xmit_en : 1;
738 uint64_t an_err_en : 1;
739 uint64_t txfifu_en : 1;
740 uint64_t txfifo_en : 1;
741 uint64_t txbad_en : 1;
742 uint64_t rxerr_en : 1;
743 uint64_t rxbad_en : 1;
744 uint64_t rxlock_en : 1;
745 uint64_t an_bad_en : 1;
746 uint64_t sync_bad_en : 1;
748 uint64_t dbg_sync_en : 1;
749 uint64_t reserved_13_63 : 51;
752 struct cvmx_pcsx_intx_en_reg_cn52xx {
753 #ifdef __BIG_ENDIAN_BITFIELD
754 uint64_t reserved_12_63 : 52;
755 uint64_t dup : 1; /**< Enable duplex mode changed interrupt */
756 uint64_t sync_bad_en : 1; /**< Enable rx sync st machine in bad state interrupt */
757 uint64_t an_bad_en : 1; /**< Enable AN state machine bad state interrupt */
758 uint64_t rxlock_en : 1; /**< Enable rx code group sync/bit lock failure interrupt */
759 uint64_t rxbad_en : 1; /**< Enable rx state machine in bad state interrupt */
760 uint64_t rxerr_en : 1; /**< Enable RX error condition interrupt */
761 uint64_t txbad_en : 1; /**< Enable tx state machine in bad state interrupt */
762 uint64_t txfifo_en : 1; /**< Enable tx fifo overflow condition interrupt */
763 uint64_t txfifu_en : 1; /**< Enable tx fifo underflow condition intrrupt */
764 uint64_t an_err_en : 1; /**< Enable AN Error condition interrupt */
765 uint64_t xmit_en : 1; /**< Enable XMIT variable state change interrupt */
766 uint64_t lnkspd_en : 1; /**< Enable Link Speed has changed interrupt */
768 uint64_t lnkspd_en : 1;
769 uint64_t xmit_en : 1;
770 uint64_t an_err_en : 1;
771 uint64_t txfifu_en : 1;
772 uint64_t txfifo_en : 1;
773 uint64_t txbad_en : 1;
774 uint64_t rxerr_en : 1;
775 uint64_t rxbad_en : 1;
776 uint64_t rxlock_en : 1;
777 uint64_t an_bad_en : 1;
778 uint64_t sync_bad_en : 1;
780 uint64_t reserved_12_63 : 52;
783 struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
784 struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
785 struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
786 struct cvmx_pcsx_intx_en_reg_s cn61xx;
787 struct cvmx_pcsx_intx_en_reg_s cn63xx;
788 struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
789 struct cvmx_pcsx_intx_en_reg_s cn66xx;
790 struct cvmx_pcsx_intx_en_reg_s cn68xx;
791 struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
792 struct cvmx_pcsx_intx_en_reg_s cnf71xx;
794 typedef union cvmx_pcsx_intx_en_reg cvmx_pcsx_intx_en_reg_t;
799 * SGMII bit [12] is really a misnomer, it is a decode of pi_qlm_cfg pins to indicate SGMII or 1000Base-X modes.
802 * When MODE=1, 1000Base-X mode is selected. Auto negotiation will follow IEEE 802.3 clause 37.
803 * When MODE=0, SGMII mode is selected and the following note will apply.
804 * Repeat note from SGM_AN_ADV register
805 * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
806 * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
807 * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
809 * PCS Interrupt Register
811 union cvmx_pcsx_intx_reg {
813 struct cvmx_pcsx_intx_reg_s {
814 #ifdef __BIG_ENDIAN_BITFIELD
815 uint64_t reserved_13_63 : 51;
816 uint64_t dbg_sync : 1; /**< Code Group sync failure debug help */
817 uint64_t dup : 1; /**< Set whenever Duplex mode changes on the link */
818 uint64_t sync_bad : 1; /**< Set by HW whenever rx sync st machine reaches a bad
819 state. Should never be set during normal operation */
820 uint64_t an_bad : 1; /**< Set by HW whenever AN st machine reaches a bad
821 state. Should never be set during normal operation */
822 uint64_t rxlock : 1; /**< Set by HW whenever code group Sync or bit lock
824 Cannot fire in loopback1 mode */
825 uint64_t rxbad : 1; /**< Set by HW whenever rx st machine reaches a bad
826 state. Should never be set during normal operation */
827 uint64_t rxerr : 1; /**< Set whenever RX receives a code group error in
828 10 bit to 8 bit decode logic
829 Cannot fire in loopback1 mode */
830 uint64_t txbad : 1; /**< Set by HW whenever tx st machine reaches a bad
831 state. Should never be set during normal operation */
832 uint64_t txfifo : 1; /**< Set whenever HW detects a TX fifo overflow
834 uint64_t txfifu : 1; /**< Set whenever HW detects a TX fifo underflowflow
836 uint64_t an_err : 1; /**< AN Error, AN resolution function failed */
837 uint64_t xmit : 1; /**< Set whenever HW detects a change in the XMIT
838 variable. XMIT variable states are IDLE, CONFIG and
840 uint64_t lnkspd : 1; /**< Set by HW whenever Link Speed has changed */
852 uint64_t sync_bad : 1;
854 uint64_t dbg_sync : 1;
855 uint64_t reserved_13_63 : 51;
858 struct cvmx_pcsx_intx_reg_cn52xx {
859 #ifdef __BIG_ENDIAN_BITFIELD
860 uint64_t reserved_12_63 : 52;
861 uint64_t dup : 1; /**< Set whenever Duplex mode changes on the link */
862 uint64_t sync_bad : 1; /**< Set by HW whenever rx sync st machine reaches a bad
863 state. Should never be set during normal operation */
864 uint64_t an_bad : 1; /**< Set by HW whenever AN st machine reaches a bad
865 state. Should never be set during normal operation */
866 uint64_t rxlock : 1; /**< Set by HW whenever code group Sync or bit lock
868 Cannot fire in loopback1 mode */
869 uint64_t rxbad : 1; /**< Set by HW whenever rx st machine reaches a bad
870 state. Should never be set during normal operation */
871 uint64_t rxerr : 1; /**< Set whenever RX receives a code group error in
872 10 bit to 8 bit decode logic
873 Cannot fire in loopback1 mode */
874 uint64_t txbad : 1; /**< Set by HW whenever tx st machine reaches a bad
875 state. Should never be set during normal operation */
876 uint64_t txfifo : 1; /**< Set whenever HW detects a TX fifo overflow
878 uint64_t txfifu : 1; /**< Set whenever HW detects a TX fifo underflowflow
880 uint64_t an_err : 1; /**< AN Error, AN resolution function failed */
881 uint64_t xmit : 1; /**< Set whenever HW detects a change in the XMIT
882 variable. XMIT variable states are IDLE, CONFIG and
884 uint64_t lnkspd : 1; /**< Set by HW whenever Link Speed has changed */
896 uint64_t sync_bad : 1;
898 uint64_t reserved_12_63 : 52;
901 struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
902 struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
903 struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
904 struct cvmx_pcsx_intx_reg_s cn61xx;
905 struct cvmx_pcsx_intx_reg_s cn63xx;
906 struct cvmx_pcsx_intx_reg_s cn63xxp1;
907 struct cvmx_pcsx_intx_reg_s cn66xx;
908 struct cvmx_pcsx_intx_reg_s cn68xx;
909 struct cvmx_pcsx_intx_reg_s cn68xxp1;
910 struct cvmx_pcsx_intx_reg_s cnf71xx;
912 typedef union cvmx_pcsx_intx_reg cvmx_pcsx_intx_reg_t;
915 * cvmx_pcs#_link#_timer_count_reg
917 * PCS_LINK_TIMER_COUNT_REG = 1.6ms nominal link timer register
920 union cvmx_pcsx_linkx_timer_count_reg {
922 struct cvmx_pcsx_linkx_timer_count_reg_s {
923 #ifdef __BIG_ENDIAN_BITFIELD
924 uint64_t reserved_16_63 : 48;
925 uint64_t count : 16; /**< (core clock period times 1024) times "COUNT" should
926 be 1.6ms(SGMII)/10ms(otherwise) which is the link
927 timer used in auto negotiation.
928 Reset assums a 700MHz eclk for 1.6ms link timer */
931 uint64_t reserved_16_63 : 48;
934 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
935 struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
936 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
937 struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
938 struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
939 struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
940 struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
941 struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
942 struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
943 struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
944 struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
946 typedef union cvmx_pcsx_linkx_timer_count_reg cvmx_pcsx_linkx_timer_count_reg_t;
949 * cvmx_pcs#_log_anl#_reg
951 * PCS Logic Analyzer Register
954 union cvmx_pcsx_log_anlx_reg {
956 struct cvmx_pcsx_log_anlx_reg_s {
957 #ifdef __BIG_ENDIAN_BITFIELD
958 uint64_t reserved_4_63 : 60;
959 uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed during packetization
960 Write 1 to clear this bit */
961 uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
962 uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size
963 0 0 Packet size 1k bytes
964 0 1 Packet size 4k bytes
965 1 0 Packet size 8k bytes
966 1 1 Packet size 16k bytes */
970 uint64_t lafifovfl : 1;
971 uint64_t reserved_4_63 : 60;
974 struct cvmx_pcsx_log_anlx_reg_s cn52xx;
975 struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
976 struct cvmx_pcsx_log_anlx_reg_s cn56xx;
977 struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
978 struct cvmx_pcsx_log_anlx_reg_s cn61xx;
979 struct cvmx_pcsx_log_anlx_reg_s cn63xx;
980 struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
981 struct cvmx_pcsx_log_anlx_reg_s cn66xx;
982 struct cvmx_pcsx_log_anlx_reg_s cn68xx;
983 struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
984 struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
986 typedef union cvmx_pcsx_log_anlx_reg cvmx_pcsx_log_anlx_reg_t;
989 * cvmx_pcs#_misc#_ctl_reg
991 * SGMII Misc Control Register
994 union cvmx_pcsx_miscx_ctl_reg {
996 struct cvmx_pcsx_miscx_ctl_reg_s {
997 #ifdef __BIG_ENDIAN_BITFIELD
998 uint64_t reserved_13_63 : 51;
999 uint64_t sgmii : 1; /**< 1=SGMII or 1000Base-X mode selected,
1000 0=XAUI or PCIE mode selected
1001 This bit represents pi_qlm1/3_cfg[1:0] pin status */
1002 uint64_t gmxeno : 1; /**< GMX Enable override. When set to 1, forces GMX to
1003 appear disabled. The enable/disable status of GMX
1004 is checked only at SOP of every packet. */
1005 uint64_t loopbck2 : 1; /**< Sets external loopback mode to return rx data back
1006 out via tx data path. 0=no loopback, 1=loopback */
1007 uint64_t mac_phy : 1; /**< 0=MAC, 1=PHY decides the tx_config_reg value to be
1008 sent during auto negotiation.
1009 See SGMII spec ENG-46158 from CISCO */
1010 uint64_t mode : 1; /**< 0=SGMII or 1= 1000 Base X */
1011 uint64_t an_ovrd : 1; /**< 0=disable, 1= enable over ride AN results
1012 Auto negotiation is allowed to happen but the
1013 results are ignored when set. Duplex and Link speed
1014 values are set from the pcs_mr_ctrl reg */
1015 uint64_t samp_pt : 7; /**< Byte# in elongated frames for 10/100Mb/s operation
1016 for data sampling on RX side in PCS.
1017 Recommended values are 0x5 for 100Mb/s operation
1018 and 0x32 for 10Mb/s operation.
1019 For 10Mb/s operaton this field should be set to a
1020 value less than 99 and greater than 0. If set out
1021 of this range a value of 50 will be used for actual
1022 sampling internally without affecting the CSR field
1023 For 100Mb/s operation this field should be set to a
1024 value less than 9 and greater than 0. If set out of
1025 this range a value of 5 will be used for actual
1026 sampling internally without affecting the CSR field */
1028 uint64_t samp_pt : 7;
1029 uint64_t an_ovrd : 1;
1031 uint64_t mac_phy : 1;
1032 uint64_t loopbck2 : 1;
1033 uint64_t gmxeno : 1;
1035 uint64_t reserved_13_63 : 51;
1038 struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
1039 struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
1040 struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
1041 struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
1042 struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
1043 struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
1044 struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
1045 struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
1046 struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
1047 struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
1048 struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
1050 typedef union cvmx_pcsx_miscx_ctl_reg cvmx_pcsx_miscx_ctl_reg_t;
1053 * cvmx_pcs#_mr#_control_reg
1055 * PCS_MR_CONTROL_REG = Control Register0
1058 union cvmx_pcsx_mrx_control_reg {
1060 struct cvmx_pcsx_mrx_control_reg_s {
1061 #ifdef __BIG_ENDIAN_BITFIELD
1062 uint64_t reserved_16_63 : 48;
1063 uint64_t reset : 1; /**< 1=SW Reset, the bit will return to 0 after pcs has
1064 been reset. Takes 32 eclk cycles to reset pcs */
1065 uint64_t loopbck1 : 1; /**< 0=normal operation, 1=loopback. The loopback mode
1066 will return(loopback) tx data from GMII tx back to
1067 GMII rx interface. The loopback happens in the pcs
1068 module. Auto Negotiation will be disabled even if
1069 the AN_EN bit is set, during loopback */
1070 uint64_t spdlsb : 1; /**< See bit 6 description */
1071 uint64_t an_en : 1; /**< 1=AN Enable, 0=AN Disable */
1072 uint64_t pwr_dn : 1; /**< 1=Power Down(HW reset), 0=Normal operation */
1073 uint64_t reserved_10_10 : 1;
1074 uint64_t rst_an : 1; /**< If bit 12 is set and bit 3 of status reg is 1
1075 Auto Negotiation begins. Else,SW writes are ignored
1076 and this bit remians at 0. This bit clears itself
1077 to 0, when AN starts. */
1078 uint64_t dup : 1; /**< 1=full duplex, 0=half duplex; effective only if AN
1079 disabled. If status register bits [15:9] and and
1080 extended status reg bits [15:12] allow only one
1081 duplex mode|, this bit will correspond to that
1082 value and any attempt to write will be ignored. */
1083 uint64_t coltst : 1; /**< 1=enable COL signal test, 0=disable test
1084 During COL test, the COL signal will reflect the
1085 GMII TX_EN signal with less than 16BT delay */
1086 uint64_t spdmsb : 1; /**< [<6>, <13>]Link Speed effective only if AN disabled
1091 uint64_t uni : 1; /**< Unidirectional (Std 802.3-2005, Clause 66.2)
1092 This bit will override the AN_EN bit and disable
1093 auto-negotiation variable mr_an_enable, when set
1094 Used in both 1000Base-X and SGMII modes */
1095 uint64_t reserved_0_4 : 5;
1097 uint64_t reserved_0_4 : 5;
1099 uint64_t spdmsb : 1;
1100 uint64_t coltst : 1;
1102 uint64_t rst_an : 1;
1103 uint64_t reserved_10_10 : 1;
1104 uint64_t pwr_dn : 1;
1106 uint64_t spdlsb : 1;
1107 uint64_t loopbck1 : 1;
1109 uint64_t reserved_16_63 : 48;
1112 struct cvmx_pcsx_mrx_control_reg_s cn52xx;
1113 struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
1114 struct cvmx_pcsx_mrx_control_reg_s cn56xx;
1115 struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
1116 struct cvmx_pcsx_mrx_control_reg_s cn61xx;
1117 struct cvmx_pcsx_mrx_control_reg_s cn63xx;
1118 struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
1119 struct cvmx_pcsx_mrx_control_reg_s cn66xx;
1120 struct cvmx_pcsx_mrx_control_reg_s cn68xx;
1121 struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
1122 struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
1124 typedef union cvmx_pcsx_mrx_control_reg cvmx_pcsx_mrx_control_reg_t;
1127 * cvmx_pcs#_mr#_status_reg
1130 * Whenever AN_EN bit[12] is set, Auto negotiation is allowed to happen. The results
1131 * of the auto negotiation process set the fields in the AN_RESULTS reg. When AN_EN is not set,
1132 * AN_RESULTS reg is don't care. The effective SPD, DUP etc.. get their values
1133 * from the pcs_mr_ctrl reg.
1135 * PCS_MR_STATUS_REG = Status Register1
1137 union cvmx_pcsx_mrx_status_reg {
1139 struct cvmx_pcsx_mrx_status_reg_s {
1140 #ifdef __BIG_ENDIAN_BITFIELD
1141 uint64_t reserved_16_63 : 48;
1142 uint64_t hun_t4 : 1; /**< 1 means 100Base-T4 capable */
1143 uint64_t hun_xfd : 1; /**< 1 means 100Base-X Full Duplex */
1144 uint64_t hun_xhd : 1; /**< 1 means 100Base-X Half Duplex */
1145 uint64_t ten_fd : 1; /**< 1 means 10Mb/s Full Duplex */
1146 uint64_t ten_hd : 1; /**< 1 means 10Mb/s Half Duplex */
1147 uint64_t hun_t2fd : 1; /**< 1 means 100Base-T2 Full Duplex */
1148 uint64_t hun_t2hd : 1; /**< 1 means 100Base-T2 Half Duplex */
1149 uint64_t ext_st : 1; /**< 1 means extended status info in reg15 */
1150 uint64_t reserved_7_7 : 1;
1151 uint64_t prb_sup : 1; /**< 1 means able to work without preamble bytes at the
1152 beginning of frames. 0 means not able to accept
1153 frames without preamble bytes preceding them. */
1154 uint64_t an_cpt : 1; /**< 1 means Auto Negotiation is complete and the
1155 contents of the an_results_reg are valid. */
1156 uint64_t rm_flt : 1; /**< Set to 1 when remote flt condition occurs. This bit
1157 implements a latching Hi behavior. It is cleared by
1158 SW read of this reg or when reset bit [15] in
1159 Control Reg is asserted.
1160 See an adv reg[13:12] for flt conditions */
1161 uint64_t an_abil : 1; /**< 1 means Auto Negotiation capable */
1162 uint64_t lnk_st : 1; /**< 1=link up, 0=link down. Set during AN process
1163 Set whenever XMIT=DATA. Latching Lo behavior when
1164 link goes down. Link down value of the bit stays
1165 low until SW reads the reg. */
1166 uint64_t reserved_1_1 : 1;
1167 uint64_t extnd : 1; /**< Always 0, no extended capability regs present */
1170 uint64_t reserved_1_1 : 1;
1171 uint64_t lnk_st : 1;
1172 uint64_t an_abil : 1;
1173 uint64_t rm_flt : 1;
1174 uint64_t an_cpt : 1;
1175 uint64_t prb_sup : 1;
1176 uint64_t reserved_7_7 : 1;
1177 uint64_t ext_st : 1;
1178 uint64_t hun_t2hd : 1;
1179 uint64_t hun_t2fd : 1;
1180 uint64_t ten_hd : 1;
1181 uint64_t ten_fd : 1;
1182 uint64_t hun_xhd : 1;
1183 uint64_t hun_xfd : 1;
1184 uint64_t hun_t4 : 1;
1185 uint64_t reserved_16_63 : 48;
1188 struct cvmx_pcsx_mrx_status_reg_s cn52xx;
1189 struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
1190 struct cvmx_pcsx_mrx_status_reg_s cn56xx;
1191 struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
1192 struct cvmx_pcsx_mrx_status_reg_s cn61xx;
1193 struct cvmx_pcsx_mrx_status_reg_s cn63xx;
1194 struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
1195 struct cvmx_pcsx_mrx_status_reg_s cn66xx;
1196 struct cvmx_pcsx_mrx_status_reg_s cn68xx;
1197 struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
1198 struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
1200 typedef union cvmx_pcsx_mrx_status_reg cvmx_pcsx_mrx_status_reg_t;
1203 * cvmx_pcs#_rx#_states_reg
1205 * PCS_RX_STATES_REG = RX State Machines states register
1208 union cvmx_pcsx_rxx_states_reg {
1210 struct cvmx_pcsx_rxx_states_reg_s {
1211 #ifdef __BIG_ENDIAN_BITFIELD
1212 uint64_t reserved_16_63 : 48;
1213 uint64_t rx_bad : 1; /**< Receive state machine in an illegal state */
1214 uint64_t rx_st : 5; /**< Receive state machine state */
1215 uint64_t sync_bad : 1; /**< Receive synchronization SM in an illegal state */
1216 uint64_t sync : 4; /**< Receive synchronization SM state */
1217 uint64_t an_bad : 1; /**< Auto Negotiation state machine in an illegal state */
1218 uint64_t an_st : 4; /**< Auto Negotiation state machine state */
1221 uint64_t an_bad : 1;
1223 uint64_t sync_bad : 1;
1225 uint64_t rx_bad : 1;
1226 uint64_t reserved_16_63 : 48;
1229 struct cvmx_pcsx_rxx_states_reg_s cn52xx;
1230 struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
1231 struct cvmx_pcsx_rxx_states_reg_s cn56xx;
1232 struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
1233 struct cvmx_pcsx_rxx_states_reg_s cn61xx;
1234 struct cvmx_pcsx_rxx_states_reg_s cn63xx;
1235 struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
1236 struct cvmx_pcsx_rxx_states_reg_s cn66xx;
1237 struct cvmx_pcsx_rxx_states_reg_s cn68xx;
1238 struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
1239 struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
1241 typedef union cvmx_pcsx_rxx_states_reg cvmx_pcsx_rxx_states_reg_t;
1244 * cvmx_pcs#_rx#_sync_reg
1247 * r_tx_rx_polarity_reg bit [2] will show correct polarity needed on the link receive path after code grp synchronization is achieved.
1250 * PCS_RX_SYNC_REG = Code Group synchronization reg
1252 union cvmx_pcsx_rxx_sync_reg {
1254 struct cvmx_pcsx_rxx_sync_reg_s {
1255 #ifdef __BIG_ENDIAN_BITFIELD
1256 uint64_t reserved_2_63 : 62;
1257 uint64_t sync : 1; /**< 1 means code group synchronization achieved */
1258 uint64_t bit_lock : 1; /**< 1 means bit lock achieved */
1260 uint64_t bit_lock : 1;
1262 uint64_t reserved_2_63 : 62;
1265 struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
1266 struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
1267 struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
1268 struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
1269 struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
1270 struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
1271 struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
1272 struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
1273 struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
1274 struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
1275 struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
1277 typedef union cvmx_pcsx_rxx_sync_reg cvmx_pcsx_rxx_sync_reg_t;
1280 * cvmx_pcs#_sgm#_an_adv_reg
1282 * SGMII AN Advertisement Register (sent out as tx_config_reg)
1285 union cvmx_pcsx_sgmx_an_adv_reg {
1287 struct cvmx_pcsx_sgmx_an_adv_reg_s {
1288 #ifdef __BIG_ENDIAN_BITFIELD
1289 uint64_t reserved_16_63 : 48;
1290 uint64_t link : 1; /**< Link status 1 Link Up, 0 Link Down */
1291 uint64_t ack : 1; /**< Auto negotiation ack */
1292 uint64_t reserved_13_13 : 1;
1293 uint64_t dup : 1; /**< Duplex mode 1=full duplex, 0=half duplex */
1294 uint64_t speed : 2; /**< Link Speed
1299 uint64_t reserved_1_9 : 9;
1300 uint64_t one : 1; /**< Always set to match tx_config_reg<0> */
1303 uint64_t reserved_1_9 : 9;
1306 uint64_t reserved_13_13 : 1;
1309 uint64_t reserved_16_63 : 48;
1312 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
1313 struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
1314 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
1315 struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
1316 struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
1317 struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
1318 struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
1319 struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
1320 struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
1321 struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
1322 struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
1324 typedef union cvmx_pcsx_sgmx_an_adv_reg cvmx_pcsx_sgmx_an_adv_reg_t;
1327 * cvmx_pcs#_sgm#_lp_adv_reg
1329 * NOTE: The SGMII AN Advertisement Register above will be sent during Auto Negotiation if the MAC_PHY mode bit in misc_ctl_reg
1330 * is set (1=PHY mode). If the bit is not set (0=MAC mode), the tx_config_reg[14] becomes ACK bit and [0] is always 1.
1331 * All other bits in tx_config_reg sent will be 0. The PHY dictates the Auto Negotiation results.
1333 * SGMII LP Advertisement Register (received as rx_config_reg)
1335 union cvmx_pcsx_sgmx_lp_adv_reg {
1337 struct cvmx_pcsx_sgmx_lp_adv_reg_s {
1338 #ifdef __BIG_ENDIAN_BITFIELD
1339 uint64_t reserved_16_63 : 48;
1340 uint64_t link : 1; /**< Link status 1 Link Up, 0 Link Down */
1341 uint64_t reserved_13_14 : 2;
1342 uint64_t dup : 1; /**< Duplex mode 1=full duplex, 0=half duplex */
1343 uint64_t speed : 2; /**< Link Speed
1348 uint64_t reserved_1_9 : 9;
1349 uint64_t one : 1; /**< Always set to match tx_config_reg<0> */
1352 uint64_t reserved_1_9 : 9;
1355 uint64_t reserved_13_14 : 2;
1357 uint64_t reserved_16_63 : 48;
1360 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
1361 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
1362 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
1363 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
1364 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
1365 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
1366 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
1367 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
1368 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
1369 struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
1370 struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
1372 typedef union cvmx_pcsx_sgmx_lp_adv_reg cvmx_pcsx_sgmx_lp_adv_reg_t;
1375 * cvmx_pcs#_tx#_states_reg
1377 * PCS_TX_STATES_REG = TX State Machines states register
1380 union cvmx_pcsx_txx_states_reg {
1382 struct cvmx_pcsx_txx_states_reg_s {
1383 #ifdef __BIG_ENDIAN_BITFIELD
1384 uint64_t reserved_7_63 : 57;
1385 uint64_t xmit : 2; /**< 0=undefined, 1=config, 2=idle, 3=data */
1386 uint64_t tx_bad : 1; /**< Xmit state machine in a bad state */
1387 uint64_t ord_st : 4; /**< Xmit ordered set state machine state */
1389 uint64_t ord_st : 4;
1390 uint64_t tx_bad : 1;
1392 uint64_t reserved_7_63 : 57;
1395 struct cvmx_pcsx_txx_states_reg_s cn52xx;
1396 struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
1397 struct cvmx_pcsx_txx_states_reg_s cn56xx;
1398 struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
1399 struct cvmx_pcsx_txx_states_reg_s cn61xx;
1400 struct cvmx_pcsx_txx_states_reg_s cn63xx;
1401 struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
1402 struct cvmx_pcsx_txx_states_reg_s cn66xx;
1403 struct cvmx_pcsx_txx_states_reg_s cn68xx;
1404 struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
1405 struct cvmx_pcsx_txx_states_reg_s cnf71xx;
1407 typedef union cvmx_pcsx_txx_states_reg cvmx_pcsx_txx_states_reg_t;
1410 * cvmx_pcs#_tx_rx#_polarity_reg
1412 * PCS_POLARITY_REG = TX_RX polarity reg
1415 union cvmx_pcsx_tx_rxx_polarity_reg {
1417 struct cvmx_pcsx_tx_rxx_polarity_reg_s {
1418 #ifdef __BIG_ENDIAN_BITFIELD
1419 uint64_t reserved_4_63 : 60;
1420 uint64_t rxovrd : 1; /**< When 0, <2> determines polarity
1421 when 1, <1> determines polarity */
1422 uint64_t autorxpl : 1; /**< Auto RX polarity detected. 1=inverted, 0=normal
1423 This bit always represents the correct rx polarity
1424 setting needed for successful rx path operartion,
1425 once a successful code group sync is obtained */
1426 uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
1427 uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
1429 uint64_t txplrt : 1;
1430 uint64_t rxplrt : 1;
1431 uint64_t autorxpl : 1;
1432 uint64_t rxovrd : 1;
1433 uint64_t reserved_4_63 : 60;
1436 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
1437 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
1438 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
1439 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
1440 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;
1441 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
1442 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
1443 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
1444 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
1445 struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
1446 struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
1448 typedef union cvmx_pcsx_tx_rxx_polarity_reg cvmx_pcsx_tx_rxx_polarity_reg_t;