1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PCSXX_DEFS_H__
53 #define __CVMX_PCSXX_DEFS_H__
55 static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
57 switch(cvmx_get_octeon_family()) {
58 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
59 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
60 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
62 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 1) * 0x8000000ull;
64 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
65 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
67 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 0) * 0x8000000ull;
69 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
71 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
74 cvmx_warn("CVMX_PCSXX_10GBX_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
75 return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + ((block_id) & 7) * 0x1000000ull;
77 static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
79 switch(cvmx_get_octeon_family()) {
80 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
81 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
82 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
84 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 1) * 0x8000000ull;
86 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
87 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
89 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 0) * 0x8000000ull;
91 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
93 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
96 cvmx_warn("CVMX_PCSXX_BIST_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
97 return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + ((block_id) & 7) * 0x1000000ull;
99 static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
101 switch(cvmx_get_octeon_family()) {
102 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
103 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
104 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
106 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 1) * 0x8000000ull;
108 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
109 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
111 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 0) * 0x8000000ull;
113 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
115 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull;
118 cvmx_warn("CVMX_PCSXX_BIT_LOCK_STATUS_REG (block_id = %lu) not supported on this chip\n", block_id);
119 return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + ((block_id) & 7) * 0x1000000ull;
121 static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
123 switch(cvmx_get_octeon_family()) {
124 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
125 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
126 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
128 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 1) * 0x8000000ull;
130 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
131 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
133 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 0) * 0x8000000ull;
135 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
137 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull;
140 cvmx_warn("CVMX_PCSXX_CONTROL1_REG (block_id = %lu) not supported on this chip\n", block_id);
141 return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + ((block_id) & 7) * 0x1000000ull;
143 static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
145 switch(cvmx_get_octeon_family()) {
146 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
147 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
148 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
150 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 1) * 0x8000000ull;
152 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
153 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
155 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 0) * 0x8000000ull;
157 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
159 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull;
162 cvmx_warn("CVMX_PCSXX_CONTROL2_REG (block_id = %lu) not supported on this chip\n", block_id);
163 return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + ((block_id) & 7) * 0x1000000ull;
165 static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
167 switch(cvmx_get_octeon_family()) {
168 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
169 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
170 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
172 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 1) * 0x8000000ull;
174 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
175 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
177 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 0) * 0x8000000ull;
179 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
181 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull;
184 cvmx_warn("CVMX_PCSXX_INT_EN_REG (block_id = %lu) not supported on this chip\n", block_id);
185 return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + ((block_id) & 7) * 0x1000000ull;
187 static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
189 switch(cvmx_get_octeon_family()) {
190 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
191 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
192 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
194 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 1) * 0x8000000ull;
196 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
197 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
199 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 0) * 0x8000000ull;
201 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
203 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull;
206 cvmx_warn("CVMX_PCSXX_INT_REG (block_id = %lu) not supported on this chip\n", block_id);
207 return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + ((block_id) & 7) * 0x1000000ull;
209 static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
211 switch(cvmx_get_octeon_family()) {
212 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
213 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
214 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
216 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 1) * 0x8000000ull;
218 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
219 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
221 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 0) * 0x8000000ull;
223 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
225 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull;
228 cvmx_warn("CVMX_PCSXX_LOG_ANL_REG (block_id = %lu) not supported on this chip\n", block_id);
229 return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + ((block_id) & 7) * 0x1000000ull;
231 static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
233 switch(cvmx_get_octeon_family()) {
234 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
235 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
236 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
238 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 1) * 0x8000000ull;
240 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
241 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
243 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 0) * 0x8000000ull;
245 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
247 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull;
250 cvmx_warn("CVMX_PCSXX_MISC_CTL_REG (block_id = %lu) not supported on this chip\n", block_id);
251 return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + ((block_id) & 7) * 0x1000000ull;
253 static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
255 switch(cvmx_get_octeon_family()) {
256 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
257 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
258 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
260 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 1) * 0x8000000ull;
262 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
263 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
265 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 0) * 0x8000000ull;
267 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
269 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull;
272 cvmx_warn("CVMX_PCSXX_RX_SYNC_STATES_REG (block_id = %lu) not supported on this chip\n", block_id);
273 return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + ((block_id) & 7) * 0x1000000ull;
275 static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
277 switch(cvmx_get_octeon_family()) {
278 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
279 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
280 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
282 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 1) * 0x8000000ull;
284 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
285 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
287 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 0) * 0x8000000ull;
289 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
291 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull;
294 cvmx_warn("CVMX_PCSXX_SPD_ABIL_REG (block_id = %lu) not supported on this chip\n", block_id);
295 return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + ((block_id) & 7) * 0x1000000ull;
297 static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
299 switch(cvmx_get_octeon_family()) {
300 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
301 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
302 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
304 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 1) * 0x8000000ull;
306 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
307 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
309 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 0) * 0x8000000ull;
311 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
313 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull;
316 cvmx_warn("CVMX_PCSXX_STATUS1_REG (block_id = %lu) not supported on this chip\n", block_id);
317 return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + ((block_id) & 7) * 0x1000000ull;
319 static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
321 switch(cvmx_get_octeon_family()) {
322 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
323 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
324 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
326 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 1) * 0x8000000ull;
328 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
329 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
331 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 0) * 0x8000000ull;
333 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
335 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull;
338 cvmx_warn("CVMX_PCSXX_STATUS2_REG (block_id = %lu) not supported on this chip\n", block_id);
339 return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + ((block_id) & 7) * 0x1000000ull;
341 static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
343 switch(cvmx_get_octeon_family()) {
344 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
345 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
346 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
348 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 1) * 0x8000000ull;
350 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
351 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
353 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 0) * 0x8000000ull;
355 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
357 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull;
360 cvmx_warn("CVMX_PCSXX_TX_RX_POLARITY_REG (block_id = %lu) not supported on this chip\n", block_id);
361 return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + ((block_id) & 7) * 0x1000000ull;
363 static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
365 switch(cvmx_get_octeon_family()) {
366 case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
367 case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
368 case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
370 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 1) * 0x8000000ull;
372 case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
373 case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
375 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 0) * 0x8000000ull;
377 case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
379 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull;
382 cvmx_warn("CVMX_PCSXX_TX_RX_STATES_REG (block_id = %lu) not supported on this chip\n", block_id);
383 return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + ((block_id) & 7) * 0x1000000ull;
387 * cvmx_pcsx#_10gbx_status_reg
389 * PCSX_10GBX_STATUS_REG = 10gbx_status_reg
392 union cvmx_pcsxx_10gbx_status_reg {
394 struct cvmx_pcsxx_10gbx_status_reg_s {
395 #ifdef __BIG_ENDIAN_BITFIELD
396 uint64_t reserved_13_63 : 51;
397 uint64_t alignd : 1; /**< 1=Lane alignment achieved, 0=Lanes not aligned */
398 uint64_t pattst : 1; /**< Always at 0, no pattern testing capability */
399 uint64_t reserved_4_10 : 7;
400 uint64_t l3sync : 1; /**< 1=Rcv lane 3 code grp synchronized, 0=not sync'ed */
401 uint64_t l2sync : 1; /**< 1=Rcv lane 2 code grp synchronized, 0=not sync'ed */
402 uint64_t l1sync : 1; /**< 1=Rcv lane 1 code grp synchronized, 0=not sync'ed */
403 uint64_t l0sync : 1; /**< 1=Rcv lane 0 code grp synchronized, 0=not sync'ed */
409 uint64_t reserved_4_10 : 7;
412 uint64_t reserved_13_63 : 51;
415 struct cvmx_pcsxx_10gbx_status_reg_s cn52xx;
416 struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1;
417 struct cvmx_pcsxx_10gbx_status_reg_s cn56xx;
418 struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1;
419 struct cvmx_pcsxx_10gbx_status_reg_s cn61xx;
420 struct cvmx_pcsxx_10gbx_status_reg_s cn63xx;
421 struct cvmx_pcsxx_10gbx_status_reg_s cn63xxp1;
422 struct cvmx_pcsxx_10gbx_status_reg_s cn66xx;
423 struct cvmx_pcsxx_10gbx_status_reg_s cn68xx;
424 struct cvmx_pcsxx_10gbx_status_reg_s cn68xxp1;
426 typedef union cvmx_pcsxx_10gbx_status_reg cvmx_pcsxx_10gbx_status_reg_t;
429 * cvmx_pcsx#_bist_status_reg
431 * NOTE: Logic Analyzer is enabled with LA_EN for xaui only. PKT_SZ is effective only when LA_EN=1
432 * For normal operation(xaui), this bit must be 0. The dropped lane is used to send rxc[3:0].
433 * See pcs.csr for sgmii/1000Base-X logic analyzer mode.
434 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
437 * PCSX Bist Status Register
439 union cvmx_pcsxx_bist_status_reg {
441 struct cvmx_pcsxx_bist_status_reg_s {
442 #ifdef __BIG_ENDIAN_BITFIELD
443 uint64_t reserved_1_63 : 63;
444 uint64_t bist_status : 1; /**< 1=bist failure, 0=bisted memory ok or bist in progress
445 pcsx.tx_sm.drf8x36m1_async_bist */
447 uint64_t bist_status : 1;
448 uint64_t reserved_1_63 : 63;
451 struct cvmx_pcsxx_bist_status_reg_s cn52xx;
452 struct cvmx_pcsxx_bist_status_reg_s cn52xxp1;
453 struct cvmx_pcsxx_bist_status_reg_s cn56xx;
454 struct cvmx_pcsxx_bist_status_reg_s cn56xxp1;
455 struct cvmx_pcsxx_bist_status_reg_s cn61xx;
456 struct cvmx_pcsxx_bist_status_reg_s cn63xx;
457 struct cvmx_pcsxx_bist_status_reg_s cn63xxp1;
458 struct cvmx_pcsxx_bist_status_reg_s cn66xx;
459 struct cvmx_pcsxx_bist_status_reg_s cn68xx;
460 struct cvmx_pcsxx_bist_status_reg_s cn68xxp1;
462 typedef union cvmx_pcsxx_bist_status_reg cvmx_pcsxx_bist_status_reg_t;
465 * cvmx_pcsx#_bit_lock_status_reg
467 * LN_SWAP for XAUI is to simplify interconnection layout between devices
470 * PCSX Bit Lock Status Register
472 union cvmx_pcsxx_bit_lock_status_reg {
474 struct cvmx_pcsxx_bit_lock_status_reg_s {
475 #ifdef __BIG_ENDIAN_BITFIELD
476 uint64_t reserved_4_63 : 60;
477 uint64_t bitlck3 : 1; /**< Receive Lane 3 bit lock status */
478 uint64_t bitlck2 : 1; /**< Receive Lane 2 bit lock status */
479 uint64_t bitlck1 : 1; /**< Receive Lane 1 bit lock status */
480 uint64_t bitlck0 : 1; /**< Receive Lane 0 bit lock status */
482 uint64_t bitlck0 : 1;
483 uint64_t bitlck1 : 1;
484 uint64_t bitlck2 : 1;
485 uint64_t bitlck3 : 1;
486 uint64_t reserved_4_63 : 60;
489 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx;
490 struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1;
491 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx;
492 struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1;
493 struct cvmx_pcsxx_bit_lock_status_reg_s cn61xx;
494 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xx;
495 struct cvmx_pcsxx_bit_lock_status_reg_s cn63xxp1;
496 struct cvmx_pcsxx_bit_lock_status_reg_s cn66xx;
497 struct cvmx_pcsxx_bit_lock_status_reg_s cn68xx;
498 struct cvmx_pcsxx_bit_lock_status_reg_s cn68xxp1;
500 typedef union cvmx_pcsxx_bit_lock_status_reg cvmx_pcsxx_bit_lock_status_reg_t;
503 * cvmx_pcsx#_control1_reg
505 * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
506 * For normal operation(sgmii or 1000Base-X), this bit must be 0.
507 * See pcsx.csr for xaui logic analyzer mode.
508 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
511 * PCSX regs follow IEEE Std 802.3-2005, Section: 45.2.3
514 * PCSX_CONTROL1_REG = Control Register1
516 union cvmx_pcsxx_control1_reg {
518 struct cvmx_pcsxx_control1_reg_s {
519 #ifdef __BIG_ENDIAN_BITFIELD
520 uint64_t reserved_16_63 : 48;
521 uint64_t reset : 1; /**< 1=SW PCSX Reset, the bit will return to 0 after pcs
522 has been reset. Takes 32 eclk cycles to reset pcs
523 0=Normal operation */
524 uint64_t loopbck1 : 1; /**< 0=normal operation, 1=internal loopback mode
525 xgmii tx data received from gmx tx port is returned
526 back into gmx, xgmii rx port. */
527 uint64_t spdsel1 : 1; /**< See bit 6 description */
528 uint64_t reserved_12_12 : 1;
529 uint64_t lo_pwr : 1; /**< 1=Power Down(HW reset), 0=Normal operation */
530 uint64_t reserved_7_10 : 4;
531 uint64_t spdsel0 : 1; /**< SPDSEL1 and SPDSEL0 are always at 1'b1. Write has
533 [<6>, <13>]Link Speed selection
534 1 1 Bits 5:2 select speed */
535 uint64_t spd : 4; /**< Always select 10Gb/s, writes have no effect */
536 uint64_t reserved_0_1 : 2;
538 uint64_t reserved_0_1 : 2;
540 uint64_t spdsel0 : 1;
541 uint64_t reserved_7_10 : 4;
543 uint64_t reserved_12_12 : 1;
544 uint64_t spdsel1 : 1;
545 uint64_t loopbck1 : 1;
547 uint64_t reserved_16_63 : 48;
550 struct cvmx_pcsxx_control1_reg_s cn52xx;
551 struct cvmx_pcsxx_control1_reg_s cn52xxp1;
552 struct cvmx_pcsxx_control1_reg_s cn56xx;
553 struct cvmx_pcsxx_control1_reg_s cn56xxp1;
554 struct cvmx_pcsxx_control1_reg_s cn61xx;
555 struct cvmx_pcsxx_control1_reg_s cn63xx;
556 struct cvmx_pcsxx_control1_reg_s cn63xxp1;
557 struct cvmx_pcsxx_control1_reg_s cn66xx;
558 struct cvmx_pcsxx_control1_reg_s cn68xx;
559 struct cvmx_pcsxx_control1_reg_s cn68xxp1;
561 typedef union cvmx_pcsxx_control1_reg cvmx_pcsxx_control1_reg_t;
564 * cvmx_pcsx#_control2_reg
566 * PCSX_CONTROL2_REG = Control Register2
569 union cvmx_pcsxx_control2_reg {
571 struct cvmx_pcsxx_control2_reg_s {
572 #ifdef __BIG_ENDIAN_BITFIELD
573 uint64_t reserved_2_63 : 62;
574 uint64_t type : 2; /**< Always 2'b01, 10GBASE-X only supported */
577 uint64_t reserved_2_63 : 62;
580 struct cvmx_pcsxx_control2_reg_s cn52xx;
581 struct cvmx_pcsxx_control2_reg_s cn52xxp1;
582 struct cvmx_pcsxx_control2_reg_s cn56xx;
583 struct cvmx_pcsxx_control2_reg_s cn56xxp1;
584 struct cvmx_pcsxx_control2_reg_s cn61xx;
585 struct cvmx_pcsxx_control2_reg_s cn63xx;
586 struct cvmx_pcsxx_control2_reg_s cn63xxp1;
587 struct cvmx_pcsxx_control2_reg_s cn66xx;
588 struct cvmx_pcsxx_control2_reg_s cn68xx;
589 struct cvmx_pcsxx_control2_reg_s cn68xxp1;
591 typedef union cvmx_pcsxx_control2_reg cvmx_pcsxx_control2_reg_t;
594 * cvmx_pcsx#_int_en_reg
596 * Note: DBG_SYNC is a edge triggered interrupt. When set it indicates PCS Synchronization state machine in
597 * Figure 48-7 state diagram in IEEE Std 802.3-2005 changes state SYNC_ACQUIRED_1 to SYNC_ACQUIRED_2
598 * indicating an invalid code group was received on one of the 4 receive lanes.
599 * This interrupt should be always disabled and used only for link problem debugging help.
602 * PCSX Interrupt Enable Register
604 union cvmx_pcsxx_int_en_reg {
606 struct cvmx_pcsxx_int_en_reg_s {
607 #ifdef __BIG_ENDIAN_BITFIELD
608 uint64_t reserved_7_63 : 57;
609 uint64_t dbg_sync_en : 1; /**< Code Group sync failure debug help */
610 uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */
611 uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */
612 uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */
613 uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */
614 uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */
615 uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */
617 uint64_t txflt_en : 1;
618 uint64_t rxbad_en : 1;
619 uint64_t rxsynbad_en : 1;
620 uint64_t bitlckls_en : 1;
621 uint64_t synlos_en : 1;
622 uint64_t algnlos_en : 1;
623 uint64_t dbg_sync_en : 1;
624 uint64_t reserved_7_63 : 57;
627 struct cvmx_pcsxx_int_en_reg_cn52xx {
628 #ifdef __BIG_ENDIAN_BITFIELD
629 uint64_t reserved_6_63 : 58;
630 uint64_t algnlos_en : 1; /**< Enable ALGNLOS interrupt */
631 uint64_t synlos_en : 1; /**< Enable SYNLOS interrupt */
632 uint64_t bitlckls_en : 1; /**< Enable BITLCKLS interrupt */
633 uint64_t rxsynbad_en : 1; /**< Enable RXSYNBAD interrupt */
634 uint64_t rxbad_en : 1; /**< Enable RXBAD interrupt */
635 uint64_t txflt_en : 1; /**< Enable TXFLT interrupt */
637 uint64_t txflt_en : 1;
638 uint64_t rxbad_en : 1;
639 uint64_t rxsynbad_en : 1;
640 uint64_t bitlckls_en : 1;
641 uint64_t synlos_en : 1;
642 uint64_t algnlos_en : 1;
643 uint64_t reserved_6_63 : 58;
646 struct cvmx_pcsxx_int_en_reg_cn52xx cn52xxp1;
647 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xx;
648 struct cvmx_pcsxx_int_en_reg_cn52xx cn56xxp1;
649 struct cvmx_pcsxx_int_en_reg_s cn61xx;
650 struct cvmx_pcsxx_int_en_reg_s cn63xx;
651 struct cvmx_pcsxx_int_en_reg_s cn63xxp1;
652 struct cvmx_pcsxx_int_en_reg_s cn66xx;
653 struct cvmx_pcsxx_int_en_reg_s cn68xx;
654 struct cvmx_pcsxx_int_en_reg_s cn68xxp1;
656 typedef union cvmx_pcsxx_int_en_reg cvmx_pcsxx_int_en_reg_t;
661 * PCSX Interrupt Register
664 union cvmx_pcsxx_int_reg {
666 struct cvmx_pcsxx_int_reg_s {
667 #ifdef __BIG_ENDIAN_BITFIELD
668 uint64_t reserved_7_63 : 57;
669 uint64_t dbg_sync : 1; /**< Code Group sync failure debug help, see Note below */
670 uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */
671 uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */
672 uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */
673 uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state
674 in one of the 4 xaui lanes */
675 uint64_t rxbad : 1; /**< Set when RX state machine in bad state */
676 uint64_t txflt : 1; /**< None defined at this time, always 0x0 */
680 uint64_t rxsynbad : 1;
681 uint64_t bitlckls : 1;
683 uint64_t algnlos : 1;
684 uint64_t dbg_sync : 1;
685 uint64_t reserved_7_63 : 57;
688 struct cvmx_pcsxx_int_reg_cn52xx {
689 #ifdef __BIG_ENDIAN_BITFIELD
690 uint64_t reserved_6_63 : 58;
691 uint64_t algnlos : 1; /**< Set when XAUI lanes lose alignment */
692 uint64_t synlos : 1; /**< Set when Code group sync lost on 1 or more lanes */
693 uint64_t bitlckls : 1; /**< Set when Bit lock lost on 1 or more xaui lanes */
694 uint64_t rxsynbad : 1; /**< Set when RX code grp sync st machine in bad state
695 in one of the 4 xaui lanes */
696 uint64_t rxbad : 1; /**< Set when RX state machine in bad state */
697 uint64_t txflt : 1; /**< None defined at this time, always 0x0 */
701 uint64_t rxsynbad : 1;
702 uint64_t bitlckls : 1;
704 uint64_t algnlos : 1;
705 uint64_t reserved_6_63 : 58;
708 struct cvmx_pcsxx_int_reg_cn52xx cn52xxp1;
709 struct cvmx_pcsxx_int_reg_cn52xx cn56xx;
710 struct cvmx_pcsxx_int_reg_cn52xx cn56xxp1;
711 struct cvmx_pcsxx_int_reg_s cn61xx;
712 struct cvmx_pcsxx_int_reg_s cn63xx;
713 struct cvmx_pcsxx_int_reg_s cn63xxp1;
714 struct cvmx_pcsxx_int_reg_s cn66xx;
715 struct cvmx_pcsxx_int_reg_s cn68xx;
716 struct cvmx_pcsxx_int_reg_s cn68xxp1;
718 typedef union cvmx_pcsxx_int_reg cvmx_pcsxx_int_reg_t;
721 * cvmx_pcsx#_log_anl_reg
723 * PCSX Logic Analyzer Register
726 union cvmx_pcsxx_log_anl_reg {
728 struct cvmx_pcsxx_log_anl_reg_s {
729 #ifdef __BIG_ENDIAN_BITFIELD
730 uint64_t reserved_7_63 : 57;
731 uint64_t enc_mode : 1; /**< 1=send xaui encoded data, 0=send xaui raw data to GMX
732 See .../rtl/pcs/readme_logic_analyzer.txt for details */
733 uint64_t drop_ln : 2; /**< xaui lane# to drop from logic analyzer packets
734 [<5>, <4>] Drop lane \#
738 1 1 Drop lane 3 data */
739 uint64_t lafifovfl : 1; /**< 1=logic analyser fif overflowed one or more times
740 during packetization.
741 Write 1 to clear this bit */
742 uint64_t la_en : 1; /**< 1= Logic Analyzer enabled, 0=Logic Analyzer disabled */
743 uint64_t pkt_sz : 2; /**< [<1>, <0>] Logic Analyzer Packet Size
744 0 0 Packet size 1k bytes
745 0 1 Packet size 4k bytes
746 1 0 Packet size 8k bytes
747 1 1 Packet size 16k bytes */
751 uint64_t lafifovfl : 1;
752 uint64_t drop_ln : 2;
753 uint64_t enc_mode : 1;
754 uint64_t reserved_7_63 : 57;
757 struct cvmx_pcsxx_log_anl_reg_s cn52xx;
758 struct cvmx_pcsxx_log_anl_reg_s cn52xxp1;
759 struct cvmx_pcsxx_log_anl_reg_s cn56xx;
760 struct cvmx_pcsxx_log_anl_reg_s cn56xxp1;
761 struct cvmx_pcsxx_log_anl_reg_s cn61xx;
762 struct cvmx_pcsxx_log_anl_reg_s cn63xx;
763 struct cvmx_pcsxx_log_anl_reg_s cn63xxp1;
764 struct cvmx_pcsxx_log_anl_reg_s cn66xx;
765 struct cvmx_pcsxx_log_anl_reg_s cn68xx;
766 struct cvmx_pcsxx_log_anl_reg_s cn68xxp1;
768 typedef union cvmx_pcsxx_log_anl_reg cvmx_pcsxx_log_anl_reg_t;
771 * cvmx_pcsx#_misc_ctl_reg
773 * RX lane polarity vector [3:0] = XOR_RXPLRT<9:6> ^ [4[RXPLRT<1>]];
775 * TX lane polarity vector [3:0] = XOR_TXPLRT<5:2> ^ [4[TXPLRT<0>]];
777 * In short keep <1:0> to 2'b00, and use <5:2> and <9:6> fields to define per lane polarities
781 * PCSX Misc Control Register
783 union cvmx_pcsxx_misc_ctl_reg {
785 struct cvmx_pcsxx_misc_ctl_reg_s {
786 #ifdef __BIG_ENDIAN_BITFIELD
787 uint64_t reserved_4_63 : 60;
788 uint64_t tx_swap : 1; /**< 0=do not swap xaui lanes going out to qlm's
789 1=swap lanes 3 <-> 0 and 2 <-> 1 */
790 uint64_t rx_swap : 1; /**< 0=do not swap xaui lanes coming in from qlm's
791 1=swap lanes 3 <-> 0 and 2 <-> 1 */
792 uint64_t xaui : 1; /**< 1=XAUI mode selected, 0=not XAUI mode selected
793 This bit represents pi_qlm1/3_cfg[1:0] pin status */
794 uint64_t gmxeno : 1; /**< GMX port enable override, GMX en/dis status is held
795 during data packet reception. */
799 uint64_t rx_swap : 1;
800 uint64_t tx_swap : 1;
801 uint64_t reserved_4_63 : 60;
804 struct cvmx_pcsxx_misc_ctl_reg_s cn52xx;
805 struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1;
806 struct cvmx_pcsxx_misc_ctl_reg_s cn56xx;
807 struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1;
808 struct cvmx_pcsxx_misc_ctl_reg_s cn61xx;
809 struct cvmx_pcsxx_misc_ctl_reg_s cn63xx;
810 struct cvmx_pcsxx_misc_ctl_reg_s cn63xxp1;
811 struct cvmx_pcsxx_misc_ctl_reg_s cn66xx;
812 struct cvmx_pcsxx_misc_ctl_reg_s cn68xx;
813 struct cvmx_pcsxx_misc_ctl_reg_s cn68xxp1;
815 typedef union cvmx_pcsxx_misc_ctl_reg cvmx_pcsxx_misc_ctl_reg_t;
818 * cvmx_pcsx#_rx_sync_states_reg
820 * PCSX_RX_SYNC_STATES_REG = Receive Sync States Register
823 union cvmx_pcsxx_rx_sync_states_reg {
825 struct cvmx_pcsxx_rx_sync_states_reg_s {
826 #ifdef __BIG_ENDIAN_BITFIELD
827 uint64_t reserved_16_63 : 48;
828 uint64_t sync3st : 4; /**< Receive lane 3 code grp sync state machine state */
829 uint64_t sync2st : 4; /**< Receive lane 2 code grp sync state machine state */
830 uint64_t sync1st : 4; /**< Receive lane 1 code grp sync state machine state */
831 uint64_t sync0st : 4; /**< Receive lane 0 code grp sync state machine state */
833 uint64_t sync0st : 4;
834 uint64_t sync1st : 4;
835 uint64_t sync2st : 4;
836 uint64_t sync3st : 4;
837 uint64_t reserved_16_63 : 48;
840 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx;
841 struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1;
842 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx;
843 struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1;
844 struct cvmx_pcsxx_rx_sync_states_reg_s cn61xx;
845 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xx;
846 struct cvmx_pcsxx_rx_sync_states_reg_s cn63xxp1;
847 struct cvmx_pcsxx_rx_sync_states_reg_s cn66xx;
848 struct cvmx_pcsxx_rx_sync_states_reg_s cn68xx;
849 struct cvmx_pcsxx_rx_sync_states_reg_s cn68xxp1;
851 typedef union cvmx_pcsxx_rx_sync_states_reg cvmx_pcsxx_rx_sync_states_reg_t;
854 * cvmx_pcsx#_spd_abil_reg
856 * PCSX_SPD_ABIL_REG = Speed ability register
859 union cvmx_pcsxx_spd_abil_reg {
861 struct cvmx_pcsxx_spd_abil_reg_s {
862 #ifdef __BIG_ENDIAN_BITFIELD
863 uint64_t reserved_2_63 : 62;
864 uint64_t tenpasst : 1; /**< Always 0, no 10PASS-TS/2BASE-TL capability support */
865 uint64_t tengb : 1; /**< Always 1, 10Gb/s supported */
868 uint64_t tenpasst : 1;
869 uint64_t reserved_2_63 : 62;
872 struct cvmx_pcsxx_spd_abil_reg_s cn52xx;
873 struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1;
874 struct cvmx_pcsxx_spd_abil_reg_s cn56xx;
875 struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1;
876 struct cvmx_pcsxx_spd_abil_reg_s cn61xx;
877 struct cvmx_pcsxx_spd_abil_reg_s cn63xx;
878 struct cvmx_pcsxx_spd_abil_reg_s cn63xxp1;
879 struct cvmx_pcsxx_spd_abil_reg_s cn66xx;
880 struct cvmx_pcsxx_spd_abil_reg_s cn68xx;
881 struct cvmx_pcsxx_spd_abil_reg_s cn68xxp1;
883 typedef union cvmx_pcsxx_spd_abil_reg cvmx_pcsxx_spd_abil_reg_t;
886 * cvmx_pcsx#_status1_reg
888 * PCSX_STATUS1_REG = Status Register1
891 union cvmx_pcsxx_status1_reg {
893 struct cvmx_pcsxx_status1_reg_s {
894 #ifdef __BIG_ENDIAN_BITFIELD
895 uint64_t reserved_8_63 : 56;
896 uint64_t flt : 1; /**< 1=Fault condition detected, 0=No fault condition
897 This bit is a logical OR of Status2 reg bits 11,10 */
898 uint64_t reserved_3_6 : 4;
899 uint64_t rcv_lnk : 1; /**< 1=Receive Link up, 0=Receive Link down
900 Latching Low version of r_10gbx_status_reg[12],
901 Link down status continues until SW read. */
902 uint64_t lpable : 1; /**< Always set to 1 for Low Power ablility indication */
903 uint64_t reserved_0_0 : 1;
905 uint64_t reserved_0_0 : 1;
907 uint64_t rcv_lnk : 1;
908 uint64_t reserved_3_6 : 4;
910 uint64_t reserved_8_63 : 56;
913 struct cvmx_pcsxx_status1_reg_s cn52xx;
914 struct cvmx_pcsxx_status1_reg_s cn52xxp1;
915 struct cvmx_pcsxx_status1_reg_s cn56xx;
916 struct cvmx_pcsxx_status1_reg_s cn56xxp1;
917 struct cvmx_pcsxx_status1_reg_s cn61xx;
918 struct cvmx_pcsxx_status1_reg_s cn63xx;
919 struct cvmx_pcsxx_status1_reg_s cn63xxp1;
920 struct cvmx_pcsxx_status1_reg_s cn66xx;
921 struct cvmx_pcsxx_status1_reg_s cn68xx;
922 struct cvmx_pcsxx_status1_reg_s cn68xxp1;
924 typedef union cvmx_pcsxx_status1_reg cvmx_pcsxx_status1_reg_t;
927 * cvmx_pcsx#_status2_reg
929 * PCSX_STATUS2_REG = Status Register2
932 union cvmx_pcsxx_status2_reg {
934 struct cvmx_pcsxx_status2_reg_s {
935 #ifdef __BIG_ENDIAN_BITFIELD
936 uint64_t reserved_16_63 : 48;
937 uint64_t dev : 2; /**< Always at 2'b10, means a Device present at the addr */
938 uint64_t reserved_12_13 : 2;
939 uint64_t xmtflt : 1; /**< 0=No xmit fault, 1=xmit fault. Implements latching
940 High function until SW read. */
941 uint64_t rcvflt : 1; /**< 0=No rcv fault, 1=rcv fault. Implements latching
942 High function until SW read */
943 uint64_t reserved_3_9 : 7;
944 uint64_t tengb_w : 1; /**< Always 0, no 10GBASE-W capability */
945 uint64_t tengb_x : 1; /**< Always 1, 10GBASE-X capable */
946 uint64_t tengb_r : 1; /**< Always 0, no 10GBASE-R capability */
948 uint64_t tengb_r : 1;
949 uint64_t tengb_x : 1;
950 uint64_t tengb_w : 1;
951 uint64_t reserved_3_9 : 7;
954 uint64_t reserved_12_13 : 2;
956 uint64_t reserved_16_63 : 48;
959 struct cvmx_pcsxx_status2_reg_s cn52xx;
960 struct cvmx_pcsxx_status2_reg_s cn52xxp1;
961 struct cvmx_pcsxx_status2_reg_s cn56xx;
962 struct cvmx_pcsxx_status2_reg_s cn56xxp1;
963 struct cvmx_pcsxx_status2_reg_s cn61xx;
964 struct cvmx_pcsxx_status2_reg_s cn63xx;
965 struct cvmx_pcsxx_status2_reg_s cn63xxp1;
966 struct cvmx_pcsxx_status2_reg_s cn66xx;
967 struct cvmx_pcsxx_status2_reg_s cn68xx;
968 struct cvmx_pcsxx_status2_reg_s cn68xxp1;
970 typedef union cvmx_pcsxx_status2_reg cvmx_pcsxx_status2_reg_t;
973 * cvmx_pcsx#_tx_rx_polarity_reg
975 * PCSX_POLARITY_REG = TX_RX polarity reg
978 union cvmx_pcsxx_tx_rx_polarity_reg {
980 struct cvmx_pcsxx_tx_rx_polarity_reg_s {
981 #ifdef __BIG_ENDIAN_BITFIELD
982 uint64_t reserved_10_63 : 54;
983 uint64_t xor_rxplrt : 4; /**< Per lane RX polarity control */
984 uint64_t xor_txplrt : 4; /**< Per lane TX polarity control */
985 uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
986 uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
990 uint64_t xor_txplrt : 4;
991 uint64_t xor_rxplrt : 4;
992 uint64_t reserved_10_63 : 54;
995 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx;
996 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
997 #ifdef __BIG_ENDIAN_BITFIELD
998 uint64_t reserved_2_63 : 62;
999 uint64_t rxplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
1000 uint64_t txplrt : 1; /**< 1 is inverted polarity, 0 is normal polarity */
1002 uint64_t txplrt : 1;
1003 uint64_t rxplrt : 1;
1004 uint64_t reserved_2_63 : 62;
1007 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx;
1008 struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1;
1009 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn61xx;
1010 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xx;
1011 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn63xxp1;
1012 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn66xx;
1013 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xx;
1014 struct cvmx_pcsxx_tx_rx_polarity_reg_s cn68xxp1;
1016 typedef union cvmx_pcsxx_tx_rx_polarity_reg cvmx_pcsxx_tx_rx_polarity_reg_t;
1019 * cvmx_pcsx#_tx_rx_states_reg
1021 * PCSX_TX_RX_STATES_REG = Transmit Receive States Register
1024 union cvmx_pcsxx_tx_rx_states_reg {
1026 struct cvmx_pcsxx_tx_rx_states_reg_s {
1027 #ifdef __BIG_ENDIAN_BITFIELD
1028 uint64_t reserved_14_63 : 50;
1029 uint64_t term_err : 1; /**< 1=Check end function detected error in packet
1030 terminate ||T|| column or the one after it */
1031 uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */
1032 uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */
1033 uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */
1034 uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */
1035 uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */
1036 uint64_t algn_st : 3; /**< Lane alignment state machine state state */
1037 uint64_t rx_st : 2; /**< Receive state machine state state */
1038 uint64_t tx_st : 3; /**< Transmit state machine state state */
1042 uint64_t algn_st : 3;
1044 uint64_t syn0bad : 1;
1045 uint64_t syn1bad : 1;
1046 uint64_t syn2bad : 1;
1047 uint64_t syn3bad : 1;
1048 uint64_t term_err : 1;
1049 uint64_t reserved_14_63 : 50;
1052 struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx;
1053 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
1054 #ifdef __BIG_ENDIAN_BITFIELD
1055 uint64_t reserved_13_63 : 51;
1056 uint64_t syn3bad : 1; /**< 1=lane 3 code grp sync state machine in bad state */
1057 uint64_t syn2bad : 1; /**< 1=lane 2 code grp sync state machine in bad state */
1058 uint64_t syn1bad : 1; /**< 1=lane 1 code grp sync state machine in bad state */
1059 uint64_t syn0bad : 1; /**< 1=lane 0 code grp sync state machine in bad state */
1060 uint64_t rxbad : 1; /**< 1=Rcv state machine in a bad state, HW malfunction */
1061 uint64_t algn_st : 3; /**< Lane alignment state machine state state */
1062 uint64_t rx_st : 2; /**< Receive state machine state state */
1063 uint64_t tx_st : 3; /**< Transmit state machine state state */
1067 uint64_t algn_st : 3;
1069 uint64_t syn0bad : 1;
1070 uint64_t syn1bad : 1;
1071 uint64_t syn2bad : 1;
1072 uint64_t syn3bad : 1;
1073 uint64_t reserved_13_63 : 51;
1076 struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx;
1077 struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1;
1078 struct cvmx_pcsxx_tx_rx_states_reg_s cn61xx;
1079 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xx;
1080 struct cvmx_pcsxx_tx_rx_states_reg_s cn63xxp1;
1081 struct cvmx_pcsxx_tx_rx_states_reg_s cn66xx;
1082 struct cvmx_pcsxx_tx_rx_states_reg_s cn68xx;
1083 struct cvmx_pcsxx_tx_rx_states_reg_s cn68xxp1;
1085 typedef union cvmx_pcsxx_tx_rx_states_reg cvmx_pcsxx_tx_rx_states_reg_t;