1 /***********************license start***************
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7 * modification, are permitted provided that the following conditions are
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16 * with the distribution.
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_PEMX_DEFS_H__
53 #define __CVMX_PEMX_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_PEMX_BAR1_INDEXX(unsigned long offset, unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
61 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
62 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
63 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset <= 15)) && ((block_id <= 1))))))
64 cvmx_warn("CVMX_PEMX_BAR1_INDEXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
65 return CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8;
68 #define CVMX_PEMX_BAR1_INDEXX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A8ull) + (((offset) & 15) + ((block_id) & 1) * 0x200000ull) * 8)
70 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
71 static inline uint64_t CVMX_PEMX_BAR2_MASK(unsigned long block_id)
74 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
77 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
78 cvmx_warn("CVMX_PEMX_BAR2_MASK(%lu) is invalid on this chip\n", block_id);
79 return CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull;
82 #define CVMX_PEMX_BAR2_MASK(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000130ull) + ((block_id) & 1) * 0x1000000ull)
84 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
85 static inline uint64_t CVMX_PEMX_BAR_CTL(unsigned long block_id)
88 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
89 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
92 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
93 cvmx_warn("CVMX_PEMX_BAR_CTL(%lu) is invalid on this chip\n", block_id);
94 return CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull;
97 #define CVMX_PEMX_BAR_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000128ull) + ((block_id) & 1) * 0x1000000ull)
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
100 static inline uint64_t CVMX_PEMX_BIST_STATUS(unsigned long block_id)
103 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
104 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
107 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
108 cvmx_warn("CVMX_PEMX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
109 return CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull;
112 #define CVMX_PEMX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000018ull) + ((block_id) & 1) * 0x1000000ull)
114 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
115 static inline uint64_t CVMX_PEMX_BIST_STATUS2(unsigned long block_id)
118 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
119 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
121 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
122 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
123 cvmx_warn("CVMX_PEMX_BIST_STATUS2(%lu) is invalid on this chip\n", block_id);
124 return CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull;
127 #define CVMX_PEMX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000420ull) + ((block_id) & 1) * 0x1000000ull)
129 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
130 static inline uint64_t CVMX_PEMX_CFG_RD(unsigned long block_id)
133 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
134 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
135 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
136 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
137 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
138 cvmx_warn("CVMX_PEMX_CFG_RD(%lu) is invalid on this chip\n", block_id);
139 return CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull;
142 #define CVMX_PEMX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000030ull) + ((block_id) & 1) * 0x1000000ull)
144 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
145 static inline uint64_t CVMX_PEMX_CFG_WR(unsigned long block_id)
148 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
149 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
152 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
153 cvmx_warn("CVMX_PEMX_CFG_WR(%lu) is invalid on this chip\n", block_id);
154 return CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull;
157 #define CVMX_PEMX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000028ull) + ((block_id) & 1) * 0x1000000ull)
159 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
160 static inline uint64_t CVMX_PEMX_CPL_LUT_VALID(unsigned long block_id)
163 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
164 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
165 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
166 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
167 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
168 cvmx_warn("CVMX_PEMX_CPL_LUT_VALID(%lu) is invalid on this chip\n", block_id);
169 return CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull;
172 #define CVMX_PEMX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000098ull) + ((block_id) & 1) * 0x1000000ull)
174 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
175 static inline uint64_t CVMX_PEMX_CTL_STATUS(unsigned long block_id)
178 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
182 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
183 cvmx_warn("CVMX_PEMX_CTL_STATUS(%lu) is invalid on this chip\n", block_id);
184 return CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull;
187 #define CVMX_PEMX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000000ull) + ((block_id) & 1) * 0x1000000ull)
189 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
190 static inline uint64_t CVMX_PEMX_DBG_INFO(unsigned long block_id)
193 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
194 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
195 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
196 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
197 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
198 cvmx_warn("CVMX_PEMX_DBG_INFO(%lu) is invalid on this chip\n", block_id);
199 return CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull;
202 #define CVMX_PEMX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000008ull) + ((block_id) & 1) * 0x1000000ull)
204 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
205 static inline uint64_t CVMX_PEMX_DBG_INFO_EN(unsigned long block_id)
208 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
209 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
212 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
213 cvmx_warn("CVMX_PEMX_DBG_INFO_EN(%lu) is invalid on this chip\n", block_id);
214 return CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull;
217 #define CVMX_PEMX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C00000A0ull) + ((block_id) & 1) * 0x1000000ull)
219 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
220 static inline uint64_t CVMX_PEMX_DIAG_STATUS(unsigned long block_id)
223 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
224 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
225 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
227 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
228 cvmx_warn("CVMX_PEMX_DIAG_STATUS(%lu) is invalid on this chip\n", block_id);
229 return CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull;
232 #define CVMX_PEMX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000020ull) + ((block_id) & 1) * 0x1000000ull)
234 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
235 static inline uint64_t CVMX_PEMX_INB_READ_CREDITS(unsigned long block_id)
238 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
239 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
241 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
242 cvmx_warn("CVMX_PEMX_INB_READ_CREDITS(%lu) is invalid on this chip\n", block_id);
243 return CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull;
246 #define CVMX_PEMX_INB_READ_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000138ull) + ((block_id) & 1) * 0x1000000ull)
248 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
249 static inline uint64_t CVMX_PEMX_INT_ENB(unsigned long block_id)
252 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
253 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
254 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
256 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
257 cvmx_warn("CVMX_PEMX_INT_ENB(%lu) is invalid on this chip\n", block_id);
258 return CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull;
261 #define CVMX_PEMX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000410ull) + ((block_id) & 1) * 0x1000000ull)
263 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
264 static inline uint64_t CVMX_PEMX_INT_ENB_INT(unsigned long block_id)
267 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
268 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
269 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
270 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
271 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
272 cvmx_warn("CVMX_PEMX_INT_ENB_INT(%lu) is invalid on this chip\n", block_id);
273 return CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull;
276 #define CVMX_PEMX_INT_ENB_INT(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000418ull) + ((block_id) & 1) * 0x1000000ull)
278 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
279 static inline uint64_t CVMX_PEMX_INT_SUM(unsigned long block_id)
282 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
283 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
284 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
285 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
286 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
287 cvmx_warn("CVMX_PEMX_INT_SUM(%lu) is invalid on this chip\n", block_id);
288 return CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull;
291 #define CVMX_PEMX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000408ull) + ((block_id) & 1) * 0x1000000ull)
293 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
294 static inline uint64_t CVMX_PEMX_P2N_BAR0_START(unsigned long block_id)
297 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
298 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
301 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
302 cvmx_warn("CVMX_PEMX_P2N_BAR0_START(%lu) is invalid on this chip\n", block_id);
303 return CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull;
306 #define CVMX_PEMX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000080ull) + ((block_id) & 1) * 0x1000000ull)
308 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
309 static inline uint64_t CVMX_PEMX_P2N_BAR1_START(unsigned long block_id)
312 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
313 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
314 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
315 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
317 cvmx_warn("CVMX_PEMX_P2N_BAR1_START(%lu) is invalid on this chip\n", block_id);
318 return CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull;
321 #define CVMX_PEMX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000088ull) + ((block_id) & 1) * 0x1000000ull)
323 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
324 static inline uint64_t CVMX_PEMX_P2N_BAR2_START(unsigned long block_id)
327 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
328 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
329 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
331 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
332 cvmx_warn("CVMX_PEMX_P2N_BAR2_START(%lu) is invalid on this chip\n", block_id);
333 return CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull;
336 #define CVMX_PEMX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000090ull) + ((block_id) & 1) * 0x1000000ull)
338 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
339 static inline uint64_t CVMX_PEMX_P2P_BARX_END(unsigned long offset, unsigned long block_id)
342 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
343 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
344 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
345 cvmx_warn("CVMX_PEMX_P2P_BARX_END(%lu,%lu) is invalid on this chip\n", offset, block_id);
346 return CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
349 #define CVMX_PEMX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
352 static inline uint64_t CVMX_PEMX_P2P_BARX_START(unsigned long offset, unsigned long block_id)
355 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 1))))))
358 cvmx_warn("CVMX_PEMX_P2P_BARX_START(%lu,%lu) is invalid on this chip\n", offset, block_id);
359 return CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16;
362 #define CVMX_PEMX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C0000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x100000ull) * 16)
364 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
365 static inline uint64_t CVMX_PEMX_TLP_CREDITS(unsigned long block_id)
368 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) ||
369 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
370 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) ||
371 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) ||
372 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1)))))
373 cvmx_warn("CVMX_PEMX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
374 return CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull;
377 #define CVMX_PEMX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C0000038ull) + ((block_id) & 1) * 0x1000000ull)
381 * cvmx_pem#_bar1_index#
383 * PEM_BAR1_INDEXX = PEM BAR1 IndexX Register
385 * Contains address index and control bits for access to memory ranges of BAR-1. Index is build from supplied address [25:22].
387 union cvmx_pemx_bar1_indexx {
389 struct cvmx_pemx_bar1_indexx_s {
390 #ifdef __BIG_ENDIAN_BITFIELD
391 uint64_t reserved_20_63 : 44;
392 uint64_t addr_idx : 16; /**< Address bits [37:22] sent to L2C */
393 uint64_t ca : 1; /**< Set '1' when access is not to be cached in L2. */
394 uint64_t end_swp : 2; /**< Endian Swap Mode */
395 uint64_t addr_v : 1; /**< Set '1' when the selected address range is valid. */
398 uint64_t end_swp : 2;
400 uint64_t addr_idx : 16;
401 uint64_t reserved_20_63 : 44;
404 struct cvmx_pemx_bar1_indexx_s cn61xx;
405 struct cvmx_pemx_bar1_indexx_s cn63xx;
406 struct cvmx_pemx_bar1_indexx_s cn63xxp1;
407 struct cvmx_pemx_bar1_indexx_s cn66xx;
408 struct cvmx_pemx_bar1_indexx_s cn68xx;
409 struct cvmx_pemx_bar1_indexx_s cn68xxp1;
410 struct cvmx_pemx_bar1_indexx_s cnf71xx;
412 typedef union cvmx_pemx_bar1_indexx cvmx_pemx_bar1_indexx_t;
415 * cvmx_pem#_bar2_mask
417 * PEM_BAR2_MASK = PEM BAR2 MASK
419 * The mask pattern that is ANDED with the address from PCIe core for BAR2 hits.
421 union cvmx_pemx_bar2_mask {
423 struct cvmx_pemx_bar2_mask_s {
424 #ifdef __BIG_ENDIAN_BITFIELD
425 uint64_t reserved_38_63 : 26;
426 uint64_t mask : 35; /**< The value to be ANDED with the address sent to
427 the Octeon memory. */
428 uint64_t reserved_0_2 : 3;
430 uint64_t reserved_0_2 : 3;
432 uint64_t reserved_38_63 : 26;
435 struct cvmx_pemx_bar2_mask_s cn61xx;
436 struct cvmx_pemx_bar2_mask_s cn66xx;
437 struct cvmx_pemx_bar2_mask_s cn68xx;
438 struct cvmx_pemx_bar2_mask_s cn68xxp1;
439 struct cvmx_pemx_bar2_mask_s cnf71xx;
441 typedef union cvmx_pemx_bar2_mask cvmx_pemx_bar2_mask_t;
446 * PEM_BAR_CTL = PEM BAR Control
448 * Contains control for BAR accesses.
450 union cvmx_pemx_bar_ctl {
452 struct cvmx_pemx_bar_ctl_s {
453 #ifdef __BIG_ENDIAN_BITFIELD
454 uint64_t reserved_7_63 : 57;
455 uint64_t bar1_siz : 3; /**< Pcie-Port0, Bar1 Size. 1 == 64MB, 2 == 128MB,
456 3 == 256MB, 4 == 512MB, 5 == 1024MB, 6 == 2048MB,
457 0 and 7 are reserved. */
458 uint64_t bar2_enb : 1; /**< When set '1' BAR2 is enable and will respond when
459 clear '0' BAR2 access will cause UR responses. */
460 uint64_t bar2_esx : 2; /**< Value will be XORed with pci-address[39:38] to
461 determine the endian swap mode. */
462 uint64_t bar2_cax : 1; /**< Value will be XORed with pcie-address[40] to
463 determine the L2 cache attribute.
464 Not cached in L2 if XOR result is 1 */
466 uint64_t bar2_cax : 1;
467 uint64_t bar2_esx : 2;
468 uint64_t bar2_enb : 1;
469 uint64_t bar1_siz : 3;
470 uint64_t reserved_7_63 : 57;
473 struct cvmx_pemx_bar_ctl_s cn61xx;
474 struct cvmx_pemx_bar_ctl_s cn63xx;
475 struct cvmx_pemx_bar_ctl_s cn63xxp1;
476 struct cvmx_pemx_bar_ctl_s cn66xx;
477 struct cvmx_pemx_bar_ctl_s cn68xx;
478 struct cvmx_pemx_bar_ctl_s cn68xxp1;
479 struct cvmx_pemx_bar_ctl_s cnf71xx;
481 typedef union cvmx_pemx_bar_ctl cvmx_pemx_bar_ctl_t;
484 * cvmx_pem#_bist_status
486 * PEM_BIST_STATUS = PEM Bist Status
488 * Contains the diffrent interrupt summary bits of the PEM.
490 union cvmx_pemx_bist_status {
492 struct cvmx_pemx_bist_status_s {
493 #ifdef __BIG_ENDIAN_BITFIELD
494 uint64_t reserved_8_63 : 56;
495 uint64_t retry : 1; /**< Retry Buffer. */
496 uint64_t rqdata0 : 1; /**< Rx Queue Data Memory0. */
497 uint64_t rqdata1 : 1; /**< Rx Queue Data Memory1. */
498 uint64_t rqdata2 : 1; /**< Rx Queue Data Memory2. */
499 uint64_t rqdata3 : 1; /**< Rx Queue Data Memory3. */
500 uint64_t rqhdr1 : 1; /**< Rx Queue Header1. */
501 uint64_t rqhdr0 : 1; /**< Rx Queue Header0. */
502 uint64_t sot : 1; /**< SOT Buffer. */
507 uint64_t rqdata3 : 1;
508 uint64_t rqdata2 : 1;
509 uint64_t rqdata1 : 1;
510 uint64_t rqdata0 : 1;
512 uint64_t reserved_8_63 : 56;
515 struct cvmx_pemx_bist_status_s cn61xx;
516 struct cvmx_pemx_bist_status_s cn63xx;
517 struct cvmx_pemx_bist_status_s cn63xxp1;
518 struct cvmx_pemx_bist_status_s cn66xx;
519 struct cvmx_pemx_bist_status_s cn68xx;
520 struct cvmx_pemx_bist_status_s cn68xxp1;
521 struct cvmx_pemx_bist_status_s cnf71xx;
523 typedef union cvmx_pemx_bist_status cvmx_pemx_bist_status_t;
526 * cvmx_pem#_bist_status2
528 * PEM(0..1)_BIST_STATUS2 = PEM BIST Status Register
530 * Results from BIST runs of PEM's memories.
532 union cvmx_pemx_bist_status2 {
534 struct cvmx_pemx_bist_status2_s {
535 #ifdef __BIG_ENDIAN_BITFIELD
536 uint64_t reserved_10_63 : 54;
537 uint64_t e2p_cpl : 1; /**< BIST Status for the e2p_cpl_fifo */
538 uint64_t e2p_n : 1; /**< BIST Status for the e2p_n_fifo */
539 uint64_t e2p_p : 1; /**< BIST Status for the e2p_p_fifo */
540 uint64_t peai_p2e : 1; /**< BIST Status for the peai__pesc_fifo */
541 uint64_t pef_tpf1 : 1; /**< BIST Status for the pef_tlp_p_fifo1 */
542 uint64_t pef_tpf0 : 1; /**< BIST Status for the pef_tlp_p_fifo0 */
543 uint64_t pef_tnf : 1; /**< BIST Status for the pef_tlp_n_fifo */
544 uint64_t pef_tcf1 : 1; /**< BIST Status for the pef_tlp_cpl_fifo1 */
545 uint64_t pef_tc0 : 1; /**< BIST Status for the pef_tlp_cpl_fifo0 */
546 uint64_t ppf : 1; /**< BIST Status for the ppf_fifo */
549 uint64_t pef_tc0 : 1;
550 uint64_t pef_tcf1 : 1;
551 uint64_t pef_tnf : 1;
552 uint64_t pef_tpf0 : 1;
553 uint64_t pef_tpf1 : 1;
554 uint64_t peai_p2e : 1;
557 uint64_t e2p_cpl : 1;
558 uint64_t reserved_10_63 : 54;
561 struct cvmx_pemx_bist_status2_s cn61xx;
562 struct cvmx_pemx_bist_status2_s cn63xx;
563 struct cvmx_pemx_bist_status2_s cn63xxp1;
564 struct cvmx_pemx_bist_status2_s cn66xx;
565 struct cvmx_pemx_bist_status2_s cn68xx;
566 struct cvmx_pemx_bist_status2_s cn68xxp1;
567 struct cvmx_pemx_bist_status2_s cnf71xx;
569 typedef union cvmx_pemx_bist_status2 cvmx_pemx_bist_status2_t;
574 * PEM_CFG_RD = PEM Configuration Read
576 * Allows read access to the configuration in the PCIe Core.
578 union cvmx_pemx_cfg_rd {
580 struct cvmx_pemx_cfg_rd_s {
581 #ifdef __BIG_ENDIAN_BITFIELD
582 uint64_t data : 32; /**< Data. */
583 uint64_t addr : 32; /**< Address to read. A write to this register
584 starts a read operation. */
590 struct cvmx_pemx_cfg_rd_s cn61xx;
591 struct cvmx_pemx_cfg_rd_s cn63xx;
592 struct cvmx_pemx_cfg_rd_s cn63xxp1;
593 struct cvmx_pemx_cfg_rd_s cn66xx;
594 struct cvmx_pemx_cfg_rd_s cn68xx;
595 struct cvmx_pemx_cfg_rd_s cn68xxp1;
596 struct cvmx_pemx_cfg_rd_s cnf71xx;
598 typedef union cvmx_pemx_cfg_rd cvmx_pemx_cfg_rd_t;
603 * PEM_CFG_WR = PEM Configuration Write
605 * Allows write access to the configuration in the PCIe Core.
607 union cvmx_pemx_cfg_wr {
609 struct cvmx_pemx_cfg_wr_s {
610 #ifdef __BIG_ENDIAN_BITFIELD
611 uint64_t data : 32; /**< Data to write. A write to this register starts
612 a write operation. */
613 uint64_t addr : 32; /**< Address to write. A write to this register starts
614 a write operation. */
620 struct cvmx_pemx_cfg_wr_s cn61xx;
621 struct cvmx_pemx_cfg_wr_s cn63xx;
622 struct cvmx_pemx_cfg_wr_s cn63xxp1;
623 struct cvmx_pemx_cfg_wr_s cn66xx;
624 struct cvmx_pemx_cfg_wr_s cn68xx;
625 struct cvmx_pemx_cfg_wr_s cn68xxp1;
626 struct cvmx_pemx_cfg_wr_s cnf71xx;
628 typedef union cvmx_pemx_cfg_wr cvmx_pemx_cfg_wr_t;
631 * cvmx_pem#_cpl_lut_valid
633 * PEM_CPL_LUT_VALID = PEM Cmpletion Lookup Table Valid
635 * Bit set for outstanding tag read.
637 union cvmx_pemx_cpl_lut_valid {
639 struct cvmx_pemx_cpl_lut_valid_s {
640 #ifdef __BIG_ENDIAN_BITFIELD
641 uint64_t reserved_32_63 : 32;
642 uint64_t tag : 32; /**< Bit vector set cooresponds to an outstanding tag
643 expecting a completion. */
646 uint64_t reserved_32_63 : 32;
649 struct cvmx_pemx_cpl_lut_valid_s cn61xx;
650 struct cvmx_pemx_cpl_lut_valid_s cn63xx;
651 struct cvmx_pemx_cpl_lut_valid_s cn63xxp1;
652 struct cvmx_pemx_cpl_lut_valid_s cn66xx;
653 struct cvmx_pemx_cpl_lut_valid_s cn68xx;
654 struct cvmx_pemx_cpl_lut_valid_s cn68xxp1;
655 struct cvmx_pemx_cpl_lut_valid_s cnf71xx;
657 typedef union cvmx_pemx_cpl_lut_valid cvmx_pemx_cpl_lut_valid_t;
660 * cvmx_pem#_ctl_status
662 * NOTE: Logic Analyzer is enabled with LA_EN for the specified PCS lane only. PKT_SZ is effective only when LA_EN=1
663 * For normal operation(sgmii or 1000Base-X), this bit must be 0.
664 * See pcsx.csr for xaui logic analyzer mode.
665 * For full description see document at .../rtl/pcs/readme_logic_analyzer.txt
668 * PEM_CTL_STATUS = PEM Control Status
670 * General control and status of the PEM.
672 union cvmx_pemx_ctl_status {
674 struct cvmx_pemx_ctl_status_s {
675 #ifdef __BIG_ENDIAN_BITFIELD
676 uint64_t reserved_48_63 : 16;
677 uint64_t auto_sd : 1; /**< Link Hardware Autonomous Speed Disable. */
678 uint64_t dnum : 5; /**< Primary bus device number. */
679 uint64_t pbus : 8; /**< Primary bus number. */
680 uint64_t reserved_32_33 : 2;
681 uint64_t cfg_rtry : 16; /**< The time x 0x10000 in core clocks to wait for a
682 CPL to a CFG RD that does not carry a Retry Status.
683 Until such time that the timeout occurs and Retry
684 Status is received for a CFG RD, the Read CFG Read
685 will be resent. A value of 0 disables retries and
686 treats a CPL Retry as a CPL UR.
687 When enabled only one CFG RD may be issued until
688 either successful completion or CPL UR. */
689 uint64_t reserved_12_15 : 4;
690 uint64_t pm_xtoff : 1; /**< When WRITTEN with a '1' a single cycle pulse is
691 to the PCIe core pm_xmt_turnoff port. RC mode. */
692 uint64_t pm_xpme : 1; /**< When WRITTEN with a '1' a single cycle pulse is
693 to the PCIe core pm_xmt_pme port. EP mode. */
694 uint64_t ob_p_cmd : 1; /**< When WRITTEN with a '1' a single cycle pulse is
695 to the PCIe core outband_pwrup_cmd port. EP mode. */
696 uint64_t reserved_7_8 : 2;
697 uint64_t nf_ecrc : 1; /**< Do not forward peer-to-peer ECRC TLPs. */
698 uint64_t dly_one : 1; /**< When set the output client state machines will
699 wait one cycle before starting a new TLP out. */
700 uint64_t lnk_enb : 1; /**< When set '1' the link is enabled when '0' the
701 link is disabled. This bit only is active when in
703 uint64_t ro_ctlp : 1; /**< When set '1' C-TLPs that have the RO bit set will
704 not wait for P-TLPs that normaly would be sent
706 uint64_t fast_lm : 1; /**< When '1' forces fast link mode. */
707 uint64_t inv_ecrc : 1; /**< When '1' causes the LSB of the ECRC to be inverted. */
708 uint64_t inv_lcrc : 1; /**< When '1' causes the LSB of the LCRC to be inverted. */
710 uint64_t inv_lcrc : 1;
711 uint64_t inv_ecrc : 1;
712 uint64_t fast_lm : 1;
713 uint64_t ro_ctlp : 1;
714 uint64_t lnk_enb : 1;
715 uint64_t dly_one : 1;
716 uint64_t nf_ecrc : 1;
717 uint64_t reserved_7_8 : 2;
718 uint64_t ob_p_cmd : 1;
719 uint64_t pm_xpme : 1;
720 uint64_t pm_xtoff : 1;
721 uint64_t reserved_12_15 : 4;
722 uint64_t cfg_rtry : 16;
723 uint64_t reserved_32_33 : 2;
726 uint64_t auto_sd : 1;
727 uint64_t reserved_48_63 : 16;
730 struct cvmx_pemx_ctl_status_s cn61xx;
731 struct cvmx_pemx_ctl_status_s cn63xx;
732 struct cvmx_pemx_ctl_status_s cn63xxp1;
733 struct cvmx_pemx_ctl_status_s cn66xx;
734 struct cvmx_pemx_ctl_status_s cn68xx;
735 struct cvmx_pemx_ctl_status_s cn68xxp1;
736 struct cvmx_pemx_ctl_status_s cnf71xx;
738 typedef union cvmx_pemx_ctl_status cvmx_pemx_ctl_status_t;
743 * PEM(0..1)_DBG_INFO = PEM Debug Information
745 * General debug info.
747 union cvmx_pemx_dbg_info {
749 struct cvmx_pemx_dbg_info_s {
750 #ifdef __BIG_ENDIAN_BITFIELD
751 uint64_t reserved_31_63 : 33;
752 uint64_t ecrc_e : 1; /**< Received a ECRC error.
754 uint64_t rawwpp : 1; /**< Received a write with poisoned payload
755 radm_rcvd_wreq_poisoned */
756 uint64_t racpp : 1; /**< Received a completion with poisoned payload
757 radm_rcvd_cpl_poisoned */
758 uint64_t ramtlp : 1; /**< Received a malformed TLP
760 uint64_t rarwdns : 1; /**< Recieved a request which device does not support
762 uint64_t caar : 1; /**< Completer aborted a request
764 This bit will never be set because Octeon does
765 not generate Completer Aborts. */
766 uint64_t racca : 1; /**< Received a completion with CA status
768 uint64_t racur : 1; /**< Received a completion with UR status
770 uint64_t rauc : 1; /**< Received an unexpected completion
771 radm_unexp_cpl_err */
772 uint64_t rqo : 1; /**< Receive queue overflow. Normally happens only when
773 flow control advertisements are ignored
775 uint64_t fcuv : 1; /**< Flow Control Update Violation (opt. checks)
776 int_xadm_fc_prot_err */
777 uint64_t rpe : 1; /**< When the PHY reports 8B/10B decode error
778 (RxStatus = 3b100) or disparity error
779 (RxStatus = 3b111), the signal rmlh_rcvd_err will
782 uint64_t fcpvwt : 1; /**< Flow Control Protocol Violation (Watchdog Timer)
784 uint64_t dpeoosd : 1; /**< DLLP protocol error (out of sequence DLLP)
786 uint64_t rtwdle : 1; /**< Received TLP with DataLink Layer Error
788 uint64_t rdwdle : 1; /**< Received DLLP with DataLink Layer Error
790 uint64_t mre : 1; /**< Max Retries Exceeded
791 xdlh_replay_num_rlover_err */
792 uint64_t rte : 1; /**< Replay Timer Expired
793 xdlh_replay_timeout_err
794 This bit is set when the REPLAY_TIMER expires in
795 the PCIE core. The probability of this bit being
796 set will increase with the traffic load. */
797 uint64_t acto : 1; /**< A Completion Timeout Occured
798 pedc_radm_cpl_timeout */
799 uint64_t rvdm : 1; /**< Received Vendor-Defined Message
800 pedc_radm_vendor_msg */
801 uint64_t rumep : 1; /**< Received Unlock Message (EP Mode Only)
802 pedc_radm_msg_unlock */
803 uint64_t rptamrc : 1; /**< Received PME Turnoff Acknowledge Message
805 pedc_radm_pm_to_ack */
806 uint64_t rpmerc : 1; /**< Received PME Message (RC Mode only)
808 uint64_t rfemrc : 1; /**< Received Fatal Error Message (RC Mode only)
810 Bit set when a message with ERR_FATAL is set. */
811 uint64_t rnfemrc : 1; /**< Received Non-Fatal Error Message (RC Mode only)
812 pedc_radm_nonfatal_err */
813 uint64_t rcemrc : 1; /**< Received Correctable Error Message (RC Mode only)
814 pedc_radm_correctable_err */
815 uint64_t rpoison : 1; /**< Received Poisoned TLP
816 pedc__radm_trgt1_poisoned & pedc__radm_trgt1_hv */
817 uint64_t recrce : 1; /**< Received ECRC Error
818 pedc_radm_trgt1_ecrc_err & pedc__radm_trgt1_eot */
819 uint64_t rtlplle : 1; /**< Received TLP has link layer error
820 pedc_radm_trgt1_dllp_abort & pedc__radm_trgt1_eot */
821 uint64_t rtlpmal : 1; /**< Received TLP is malformed or a message.
822 pedc_radm_trgt1_tlp_abort & pedc__radm_trgt1_eot
823 If the core receives a MSG (or Vendor Message)
824 this bit will be set. */
825 uint64_t spoison : 1; /**< Poisoned TLP sent
826 peai__client0_tlp_ep & peai__client0_tlp_hv */
828 uint64_t spoison : 1;
829 uint64_t rtlpmal : 1;
830 uint64_t rtlplle : 1;
832 uint64_t rpoison : 1;
834 uint64_t rnfemrc : 1;
837 uint64_t rptamrc : 1;
845 uint64_t dpeoosd : 1;
854 uint64_t rarwdns : 1;
859 uint64_t reserved_31_63 : 33;
862 struct cvmx_pemx_dbg_info_s cn61xx;
863 struct cvmx_pemx_dbg_info_s cn63xx;
864 struct cvmx_pemx_dbg_info_s cn63xxp1;
865 struct cvmx_pemx_dbg_info_s cn66xx;
866 struct cvmx_pemx_dbg_info_s cn68xx;
867 struct cvmx_pemx_dbg_info_s cn68xxp1;
868 struct cvmx_pemx_dbg_info_s cnf71xx;
870 typedef union cvmx_pemx_dbg_info cvmx_pemx_dbg_info_t;
873 * cvmx_pem#_dbg_info_en
875 * PEM(0..1)_DBG_INFO_EN = PEM Debug Information Enable
877 * Allows PEM_DBG_INFO to generate interrupts when cooresponding enable bit is set.
879 union cvmx_pemx_dbg_info_en {
881 struct cvmx_pemx_dbg_info_en_s {
882 #ifdef __BIG_ENDIAN_BITFIELD
883 uint64_t reserved_31_63 : 33;
884 uint64_t ecrc_e : 1; /**< Allows PEM_DBG_INFO[30] to generate an interrupt. */
885 uint64_t rawwpp : 1; /**< Allows PEM_DBG_INFO[29] to generate an interrupt. */
886 uint64_t racpp : 1; /**< Allows PEM_DBG_INFO[28] to generate an interrupt. */
887 uint64_t ramtlp : 1; /**< Allows PEM_DBG_INFO[27] to generate an interrupt. */
888 uint64_t rarwdns : 1; /**< Allows PEM_DBG_INFO[26] to generate an interrupt. */
889 uint64_t caar : 1; /**< Allows PEM_DBG_INFO[25] to generate an interrupt. */
890 uint64_t racca : 1; /**< Allows PEM_DBG_INFO[24] to generate an interrupt. */
891 uint64_t racur : 1; /**< Allows PEM_DBG_INFO[23] to generate an interrupt. */
892 uint64_t rauc : 1; /**< Allows PEM_DBG_INFO[22] to generate an interrupt. */
893 uint64_t rqo : 1; /**< Allows PEM_DBG_INFO[21] to generate an interrupt. */
894 uint64_t fcuv : 1; /**< Allows PEM_DBG_INFO[20] to generate an interrupt. */
895 uint64_t rpe : 1; /**< Allows PEM_DBG_INFO[19] to generate an interrupt. */
896 uint64_t fcpvwt : 1; /**< Allows PEM_DBG_INFO[18] to generate an interrupt. */
897 uint64_t dpeoosd : 1; /**< Allows PEM_DBG_INFO[17] to generate an interrupt. */
898 uint64_t rtwdle : 1; /**< Allows PEM_DBG_INFO[16] to generate an interrupt. */
899 uint64_t rdwdle : 1; /**< Allows PEM_DBG_INFO[15] to generate an interrupt. */
900 uint64_t mre : 1; /**< Allows PEM_DBG_INFO[14] to generate an interrupt. */
901 uint64_t rte : 1; /**< Allows PEM_DBG_INFO[13] to generate an interrupt. */
902 uint64_t acto : 1; /**< Allows PEM_DBG_INFO[12] to generate an interrupt. */
903 uint64_t rvdm : 1; /**< Allows PEM_DBG_INFO[11] to generate an interrupt. */
904 uint64_t rumep : 1; /**< Allows PEM_DBG_INFO[10] to generate an interrupt. */
905 uint64_t rptamrc : 1; /**< Allows PEM_DBG_INFO[9] to generate an interrupt. */
906 uint64_t rpmerc : 1; /**< Allows PEM_DBG_INFO[8] to generate an interrupt. */
907 uint64_t rfemrc : 1; /**< Allows PEM_DBG_INFO[7] to generate an interrupt. */
908 uint64_t rnfemrc : 1; /**< Allows PEM_DBG_INFO[6] to generate an interrupt. */
909 uint64_t rcemrc : 1; /**< Allows PEM_DBG_INFO[5] to generate an interrupt. */
910 uint64_t rpoison : 1; /**< Allows PEM_DBG_INFO[4] to generate an interrupt. */
911 uint64_t recrce : 1; /**< Allows PEM_DBG_INFO[3] to generate an interrupt. */
912 uint64_t rtlplle : 1; /**< Allows PEM_DBG_INFO[2] to generate an interrupt. */
913 uint64_t rtlpmal : 1; /**< Allows PEM_DBG_INFO[1] to generate an interrupt. */
914 uint64_t spoison : 1; /**< Allows PEM_DBG_INFO[0] to generate an interrupt. */
916 uint64_t spoison : 1;
917 uint64_t rtlpmal : 1;
918 uint64_t rtlplle : 1;
920 uint64_t rpoison : 1;
922 uint64_t rnfemrc : 1;
925 uint64_t rptamrc : 1;
933 uint64_t dpeoosd : 1;
942 uint64_t rarwdns : 1;
947 uint64_t reserved_31_63 : 33;
950 struct cvmx_pemx_dbg_info_en_s cn61xx;
951 struct cvmx_pemx_dbg_info_en_s cn63xx;
952 struct cvmx_pemx_dbg_info_en_s cn63xxp1;
953 struct cvmx_pemx_dbg_info_en_s cn66xx;
954 struct cvmx_pemx_dbg_info_en_s cn68xx;
955 struct cvmx_pemx_dbg_info_en_s cn68xxp1;
956 struct cvmx_pemx_dbg_info_en_s cnf71xx;
958 typedef union cvmx_pemx_dbg_info_en cvmx_pemx_dbg_info_en_t;
961 * cvmx_pem#_diag_status
963 * PEM_DIAG_STATUS = PEM Diagnostic Status
965 * Selection control for the cores diagnostic bus.
967 union cvmx_pemx_diag_status {
969 struct cvmx_pemx_diag_status_s {
970 #ifdef __BIG_ENDIAN_BITFIELD
971 uint64_t reserved_4_63 : 60;
972 uint64_t pm_dst : 1; /**< Current power management DSTATE. */
973 uint64_t pm_stat : 1; /**< Power Management Status. */
974 uint64_t pm_en : 1; /**< Power Management Event Enable. */
975 uint64_t aux_en : 1; /**< Auxilary Power Enable. */
979 uint64_t pm_stat : 1;
981 uint64_t reserved_4_63 : 60;
984 struct cvmx_pemx_diag_status_s cn61xx;
985 struct cvmx_pemx_diag_status_s cn63xx;
986 struct cvmx_pemx_diag_status_s cn63xxp1;
987 struct cvmx_pemx_diag_status_s cn66xx;
988 struct cvmx_pemx_diag_status_s cn68xx;
989 struct cvmx_pemx_diag_status_s cn68xxp1;
990 struct cvmx_pemx_diag_status_s cnf71xx;
992 typedef union cvmx_pemx_diag_status cvmx_pemx_diag_status_t;
995 * cvmx_pem#_inb_read_credits
997 * PEM_INB_READ_CREDITS
999 * The number of in flight reads from PCIe core to SLI
1001 union cvmx_pemx_inb_read_credits {
1003 struct cvmx_pemx_inb_read_credits_s {
1004 #ifdef __BIG_ENDIAN_BITFIELD
1005 uint64_t reserved_6_63 : 58;
1006 uint64_t num : 6; /**< The number of reads that may be in flight from
1007 the PCIe core to the SLI. Min number is 2 max
1011 uint64_t reserved_6_63 : 58;
1014 struct cvmx_pemx_inb_read_credits_s cn61xx;
1015 struct cvmx_pemx_inb_read_credits_s cn66xx;
1016 struct cvmx_pemx_inb_read_credits_s cn68xx;
1017 struct cvmx_pemx_inb_read_credits_s cnf71xx;
1019 typedef union cvmx_pemx_inb_read_credits cvmx_pemx_inb_read_credits_t;
1024 * PEM(0..1)_INT_ENB = PEM Interrupt Enable
1026 * Enables interrupt conditions for the PEM to generate an RSL interrupt.
1028 union cvmx_pemx_int_enb {
1030 struct cvmx_pemx_int_enb_s {
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032 uint64_t reserved_14_63 : 50;
1033 uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an
1034 interrupt to the MIO. */
1035 uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an
1036 interrupt to the MIO. */
1037 uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an
1038 interrupt to the MIO. */
1039 uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an
1040 interrupt to the MIO. */
1041 uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an
1042 interrupt to the MIO. */
1043 uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an
1044 interrupt to the MIO. */
1045 uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an
1046 interrupt to the MIO. */
1047 uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an
1048 interrupt to the MIO. */
1049 uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an
1050 interrupt to the MIO. */
1051 uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an
1052 interrupt to the MIO. */
1053 uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an
1054 interrupt to the MIO. */
1055 uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an
1056 interrupt to the MIO. */
1057 uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an
1058 interrupt to the MIO. */
1059 uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an
1060 interrupt to the MIO. */
1074 uint64_t crs_er : 1;
1075 uint64_t crs_dr : 1;
1076 uint64_t reserved_14_63 : 50;
1079 struct cvmx_pemx_int_enb_s cn61xx;
1080 struct cvmx_pemx_int_enb_s cn63xx;
1081 struct cvmx_pemx_int_enb_s cn63xxp1;
1082 struct cvmx_pemx_int_enb_s cn66xx;
1083 struct cvmx_pemx_int_enb_s cn68xx;
1084 struct cvmx_pemx_int_enb_s cn68xxp1;
1085 struct cvmx_pemx_int_enb_s cnf71xx;
1087 typedef union cvmx_pemx_int_enb cvmx_pemx_int_enb_t;
1090 * cvmx_pem#_int_enb_int
1092 * PEM(0..1)_INT_ENB_INT = PEM Interrupt Enable
1094 * Enables interrupt conditions for the PEM to generate an RSL interrupt.
1096 union cvmx_pemx_int_enb_int {
1098 struct cvmx_pemx_int_enb_int_s {
1099 #ifdef __BIG_ENDIAN_BITFIELD
1100 uint64_t reserved_14_63 : 50;
1101 uint64_t crs_dr : 1; /**< Enables PEM_INT_SUM[13] to generate an
1102 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1103 uint64_t crs_er : 1; /**< Enables PEM_INT_SUM[12] to generate an
1104 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1105 uint64_t rdlk : 1; /**< Enables PEM_INT_SUM[11] to generate an
1106 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1107 uint64_t exc : 1; /**< Enables PEM_INT_SUM[10] to generate an
1108 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1109 uint64_t un_bx : 1; /**< Enables PEM_INT_SUM[9] to generate an
1110 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1111 uint64_t un_b2 : 1; /**< Enables PEM_INT_SUM[8] to generate an
1112 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1113 uint64_t un_b1 : 1; /**< Enables PEM_INT_SUM[7] to generate an
1114 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1115 uint64_t up_bx : 1; /**< Enables PEM_INT_SUM[6] to generate an
1116 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1117 uint64_t up_b2 : 1; /**< Enables PEM_INT_SUM[5] to generate an
1118 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1119 uint64_t up_b1 : 1; /**< Enables PEM_INT_SUM[4] to generate an
1120 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1121 uint64_t pmem : 1; /**< Enables PEM_INT_SUM[3] to generate an
1122 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1123 uint64_t pmei : 1; /**< Enables PEM_INT_SUM[2] to generate an
1124 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1125 uint64_t se : 1; /**< Enables PEM_INT_SUM[1] to generate an
1126 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1127 uint64_t aeri : 1; /**< Enables PEM_INT_SUM[0] to generate an
1128 interrupt to the SLI as SLI_INT_SUM[MAC#_INT]. */
1142 uint64_t crs_er : 1;
1143 uint64_t crs_dr : 1;
1144 uint64_t reserved_14_63 : 50;
1147 struct cvmx_pemx_int_enb_int_s cn61xx;
1148 struct cvmx_pemx_int_enb_int_s cn63xx;
1149 struct cvmx_pemx_int_enb_int_s cn63xxp1;
1150 struct cvmx_pemx_int_enb_int_s cn66xx;
1151 struct cvmx_pemx_int_enb_int_s cn68xx;
1152 struct cvmx_pemx_int_enb_int_s cn68xxp1;
1153 struct cvmx_pemx_int_enb_int_s cnf71xx;
1155 typedef union cvmx_pemx_int_enb_int cvmx_pemx_int_enb_int_t;
1160 * Below are in pesc_csr
1162 * PEM(0..1)_INT_SUM = PEM Interrupt Summary
1164 * Interrupt conditions for the PEM.
1166 union cvmx_pemx_int_sum {
1168 struct cvmx_pemx_int_sum_s {
1169 #ifdef __BIG_ENDIAN_BITFIELD
1170 uint64_t reserved_14_63 : 50;
1171 uint64_t crs_dr : 1; /**< Had a CRS Timeout when Retries were disabled. */
1172 uint64_t crs_er : 1; /**< Had a CRS Timeout when Retries were enabled. */
1173 uint64_t rdlk : 1; /**< Received Read Lock TLP. */
1174 uint64_t exc : 1; /**< Set when the PEM_DBG_INFO register has a bit
1175 set and its cooresponding PEM_DBG_INFO_EN bit
1177 uint64_t un_bx : 1; /**< Received N-TLP for an unknown Bar. */
1178 uint64_t un_b2 : 1; /**< Received N-TLP for Bar2 when bar2 is disabled. */
1179 uint64_t un_b1 : 1; /**< Received N-TLP for Bar1 when bar1 index valid
1181 uint64_t up_bx : 1; /**< Received P-TLP for an unknown Bar. */
1182 uint64_t up_b2 : 1; /**< Received P-TLP for Bar2 when bar2 is disabeld. */
1183 uint64_t up_b1 : 1; /**< Received P-TLP for Bar1 when bar1 index valid
1185 uint64_t pmem : 1; /**< Recived PME MSG.
1187 uint64_t pmei : 1; /**< PME Interrupt.
1189 uint64_t se : 1; /**< System Error, RC Mode Only.
1191 uint64_t aeri : 1; /**< Advanced Error Reporting Interrupt, RC Mode Only.
1192 (cfg_aer_rc_err_int). */
1206 uint64_t crs_er : 1;
1207 uint64_t crs_dr : 1;
1208 uint64_t reserved_14_63 : 50;
1211 struct cvmx_pemx_int_sum_s cn61xx;
1212 struct cvmx_pemx_int_sum_s cn63xx;
1213 struct cvmx_pemx_int_sum_s cn63xxp1;
1214 struct cvmx_pemx_int_sum_s cn66xx;
1215 struct cvmx_pemx_int_sum_s cn68xx;
1216 struct cvmx_pemx_int_sum_s cn68xxp1;
1217 struct cvmx_pemx_int_sum_s cnf71xx;
1219 typedef union cvmx_pemx_int_sum cvmx_pemx_int_sum_t;
1222 * cvmx_pem#_p2n_bar0_start
1224 * PEM_P2N_BAR0_START = PEM PCIe to Npei BAR0 Start
1226 * The starting address for addresses to forwarded to the SLI in RC Mode.
1228 union cvmx_pemx_p2n_bar0_start {
1230 struct cvmx_pemx_p2n_bar0_start_s {
1231 #ifdef __BIG_ENDIAN_BITFIELD
1232 uint64_t addr : 50; /**< The starting address of the 16KB address space that
1233 is the BAR0 address space. */
1234 uint64_t reserved_0_13 : 14;
1236 uint64_t reserved_0_13 : 14;
1240 struct cvmx_pemx_p2n_bar0_start_s cn61xx;
1241 struct cvmx_pemx_p2n_bar0_start_s cn63xx;
1242 struct cvmx_pemx_p2n_bar0_start_s cn63xxp1;
1243 struct cvmx_pemx_p2n_bar0_start_s cn66xx;
1244 struct cvmx_pemx_p2n_bar0_start_s cn68xx;
1245 struct cvmx_pemx_p2n_bar0_start_s cn68xxp1;
1246 struct cvmx_pemx_p2n_bar0_start_s cnf71xx;
1248 typedef union cvmx_pemx_p2n_bar0_start cvmx_pemx_p2n_bar0_start_t;
1251 * cvmx_pem#_p2n_bar1_start
1253 * PEM_P2N_BAR1_START = PEM PCIe to Npei BAR1 Start
1255 * The starting address for addresses to forwarded to the SLI in RC Mode.
1257 union cvmx_pemx_p2n_bar1_start {
1259 struct cvmx_pemx_p2n_bar1_start_s {
1260 #ifdef __BIG_ENDIAN_BITFIELD
1261 uint64_t addr : 38; /**< The starting address of the 64KB address space
1262 that is the BAR1 address space. */
1263 uint64_t reserved_0_25 : 26;
1265 uint64_t reserved_0_25 : 26;
1269 struct cvmx_pemx_p2n_bar1_start_s cn61xx;
1270 struct cvmx_pemx_p2n_bar1_start_s cn63xx;
1271 struct cvmx_pemx_p2n_bar1_start_s cn63xxp1;
1272 struct cvmx_pemx_p2n_bar1_start_s cn66xx;
1273 struct cvmx_pemx_p2n_bar1_start_s cn68xx;
1274 struct cvmx_pemx_p2n_bar1_start_s cn68xxp1;
1275 struct cvmx_pemx_p2n_bar1_start_s cnf71xx;
1277 typedef union cvmx_pemx_p2n_bar1_start cvmx_pemx_p2n_bar1_start_t;
1280 * cvmx_pem#_p2n_bar2_start
1282 * PEM_P2N_BAR2_START = PEM PCIe to Npei BAR2 Start
1284 * The starting address for addresses to forwarded to the SLI in RC Mode.
1286 union cvmx_pemx_p2n_bar2_start {
1288 struct cvmx_pemx_p2n_bar2_start_s {
1289 #ifdef __BIG_ENDIAN_BITFIELD
1290 uint64_t addr : 23; /**< The starting address of the 2^41 address space
1291 that is the BAR2 address space. */
1292 uint64_t reserved_0_40 : 41;
1294 uint64_t reserved_0_40 : 41;
1298 struct cvmx_pemx_p2n_bar2_start_s cn61xx;
1299 struct cvmx_pemx_p2n_bar2_start_s cn63xx;
1300 struct cvmx_pemx_p2n_bar2_start_s cn63xxp1;
1301 struct cvmx_pemx_p2n_bar2_start_s cn66xx;
1302 struct cvmx_pemx_p2n_bar2_start_s cn68xx;
1303 struct cvmx_pemx_p2n_bar2_start_s cn68xxp1;
1304 struct cvmx_pemx_p2n_bar2_start_s cnf71xx;
1306 typedef union cvmx_pemx_p2n_bar2_start cvmx_pemx_p2n_bar2_start_t;
1309 * cvmx_pem#_p2p_bar#_end
1311 * PEM_P2P_BAR#_END = PEM Peer-To-Peer BAR0 End
1313 * The ending address for addresses to forwarded to the PCIe peer port.
1315 union cvmx_pemx_p2p_barx_end {
1317 struct cvmx_pemx_p2p_barx_end_s {
1318 #ifdef __BIG_ENDIAN_BITFIELD
1319 uint64_t addr : 52; /**< The ending address of the address window created
1320 this field and the PEM_P2P_BAR0_START[63:12]
1321 field. The full 64-bits of address are created by:
1322 [ADDR[63:12], 12'b0]. */
1323 uint64_t reserved_0_11 : 12;
1325 uint64_t reserved_0_11 : 12;
1329 struct cvmx_pemx_p2p_barx_end_s cn63xx;
1330 struct cvmx_pemx_p2p_barx_end_s cn63xxp1;
1331 struct cvmx_pemx_p2p_barx_end_s cn66xx;
1332 struct cvmx_pemx_p2p_barx_end_s cn68xx;
1333 struct cvmx_pemx_p2p_barx_end_s cn68xxp1;
1335 typedef union cvmx_pemx_p2p_barx_end cvmx_pemx_p2p_barx_end_t;
1338 * cvmx_pem#_p2p_bar#_start
1340 * PEM_P2P_BAR#_START = PEM Peer-To-Peer BAR0 Start
1342 * The starting address and enable for addresses to forwarded to the PCIe peer port.
1344 union cvmx_pemx_p2p_barx_start {
1346 struct cvmx_pemx_p2p_barx_start_s {
1347 #ifdef __BIG_ENDIAN_BITFIELD
1348 uint64_t addr : 52; /**< The starting address of the address window created
1349 by this field and the PEM_P2P_BAR0_END[63:12]
1350 field. The full 64-bits of address are created by:
1351 [ADDR[63:12], 12'b0]. */
1352 uint64_t reserved_0_11 : 12;
1354 uint64_t reserved_0_11 : 12;
1358 struct cvmx_pemx_p2p_barx_start_s cn63xx;
1359 struct cvmx_pemx_p2p_barx_start_s cn63xxp1;
1360 struct cvmx_pemx_p2p_barx_start_s cn66xx;
1361 struct cvmx_pemx_p2p_barx_start_s cn68xx;
1362 struct cvmx_pemx_p2p_barx_start_s cn68xxp1;
1364 typedef union cvmx_pemx_p2p_barx_start cvmx_pemx_p2p_barx_start_t;
1367 * cvmx_pem#_tlp_credits
1369 * PEM_TLP_CREDITS = PEM TLP Credits
1371 * Specifies the number of credits the PEM for use in moving TLPs. When this register is written the credit values are
1372 * reset to the register value. A write to this register should take place BEFORE traffic flow starts.
1374 union cvmx_pemx_tlp_credits {
1376 struct cvmx_pemx_tlp_credits_s {
1377 #ifdef __BIG_ENDIAN_BITFIELD
1378 uint64_t reserved_56_63 : 8;
1379 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer.
1380 The value in this register should not be changed.
1381 Values other than 0x80 can lead to unpredictable
1383 uint64_t pem_cpl : 8; /**< TLP credits for Completion TLPs in the Peer.
1384 Legal values are 0x24 to 0x80. */
1385 uint64_t pem_np : 8; /**< TLP credits for Non-Posted TLPs in the Peer.
1386 Legal values are 0x4 to 0x10. */
1387 uint64_t pem_p : 8; /**< TLP credits for Posted TLPs in the Peer.
1388 Legal values are 0x24 to 0x80. */
1389 uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI.
1390 Legal values are 0x24 to 0x80. */
1391 uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI.
1392 Legal values are 0x4 to 0x10. */
1393 uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI.
1394 Legal values are 0x24 to 0x80. */
1397 uint64_t sli_np : 8;
1398 uint64_t sli_cpl : 8;
1400 uint64_t pem_np : 8;
1401 uint64_t pem_cpl : 8;
1402 uint64_t peai_ppf : 8;
1403 uint64_t reserved_56_63 : 8;
1406 struct cvmx_pemx_tlp_credits_cn61xx {
1407 #ifdef __BIG_ENDIAN_BITFIELD
1408 uint64_t reserved_56_63 : 8;
1409 uint64_t peai_ppf : 8; /**< TLP credits for Completion TLPs in the Peer.
1410 The value in this register should not be changed.
1411 Values other than 0x80 can lead to unpredictable
1413 uint64_t reserved_24_47 : 24;
1414 uint64_t sli_cpl : 8; /**< TLP credits for Completion TLPs in the SLI.
1415 Legal values are 0x24 to 0x80. */
1416 uint64_t sli_np : 8; /**< TLP credits for Non-Posted TLPs in the SLI.
1417 Legal values are 0x4 to 0x10. */
1418 uint64_t sli_p : 8; /**< TLP credits for Posted TLPs in the SLI.
1419 Legal values are 0x24 to 0x80. */
1422 uint64_t sli_np : 8;
1423 uint64_t sli_cpl : 8;
1424 uint64_t reserved_24_47 : 24;
1425 uint64_t peai_ppf : 8;
1426 uint64_t reserved_56_63 : 8;
1429 struct cvmx_pemx_tlp_credits_s cn63xx;
1430 struct cvmx_pemx_tlp_credits_s cn63xxp1;
1431 struct cvmx_pemx_tlp_credits_s cn66xx;
1432 struct cvmx_pemx_tlp_credits_s cn68xx;
1433 struct cvmx_pemx_tlp_credits_s cn68xxp1;
1434 struct cvmx_pemx_tlp_credits_cn61xx cnf71xx;
1436 typedef union cvmx_pemx_tlp_credits cvmx_pemx_tlp_credits_t;