1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * * Neither the name of Cavium Inc. nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
23 * This Software, including technical data, may be subject to U.S. export control
24 * laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
44 * Configuration and status register (CSR) definitions for
49 #ifndef __CVMX_PEXP_DEFS_H__
50 #define __CVMX_PEXP_DEFS_H__
52 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
53 static inline uint64_t CVMX_PEXP_NPEI_BAR1_INDEXX(unsigned long offset)
56 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
57 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
58 cvmx_warn("CVMX_PEXP_NPEI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset);
59 return CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16;
62 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008000ull) + ((offset) & 31) * 16)
64 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
65 #define CVMX_PEXP_NPEI_BIST_STATUS CVMX_PEXP_NPEI_BIST_STATUS_FUNC()
66 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS_FUNC(void)
68 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
69 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS not supported on this chip\n");
70 return CVMX_ADD_IO_SEG(0x00011F0000008580ull);
73 #define CVMX_PEXP_NPEI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008580ull))
75 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
76 #define CVMX_PEXP_NPEI_BIST_STATUS2 CVMX_PEXP_NPEI_BIST_STATUS2_FUNC()
77 static inline uint64_t CVMX_PEXP_NPEI_BIST_STATUS2_FUNC(void)
79 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
80 cvmx_warn("CVMX_PEXP_NPEI_BIST_STATUS2 not supported on this chip\n");
81 return CVMX_ADD_IO_SEG(0x00011F0000008680ull);
84 #define CVMX_PEXP_NPEI_BIST_STATUS2 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
86 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
87 #define CVMX_PEXP_NPEI_CTL_PORT0 CVMX_PEXP_NPEI_CTL_PORT0_FUNC()
88 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT0_FUNC(void)
90 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
91 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT0 not supported on this chip\n");
92 return CVMX_ADD_IO_SEG(0x00011F0000008250ull);
95 #define CVMX_PEXP_NPEI_CTL_PORT0 (CVMX_ADD_IO_SEG(0x00011F0000008250ull))
97 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
98 #define CVMX_PEXP_NPEI_CTL_PORT1 CVMX_PEXP_NPEI_CTL_PORT1_FUNC()
99 static inline uint64_t CVMX_PEXP_NPEI_CTL_PORT1_FUNC(void)
101 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
102 cvmx_warn("CVMX_PEXP_NPEI_CTL_PORT1 not supported on this chip\n");
103 return CVMX_ADD_IO_SEG(0x00011F0000008260ull);
106 #define CVMX_PEXP_NPEI_CTL_PORT1 (CVMX_ADD_IO_SEG(0x00011F0000008260ull))
108 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
109 #define CVMX_PEXP_NPEI_CTL_STATUS CVMX_PEXP_NPEI_CTL_STATUS_FUNC()
110 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS_FUNC(void)
112 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
113 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS not supported on this chip\n");
114 return CVMX_ADD_IO_SEG(0x00011F0000008570ull);
117 #define CVMX_PEXP_NPEI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000008570ull))
119 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
120 #define CVMX_PEXP_NPEI_CTL_STATUS2 CVMX_PEXP_NPEI_CTL_STATUS2_FUNC()
121 static inline uint64_t CVMX_PEXP_NPEI_CTL_STATUS2_FUNC(void)
123 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
124 cvmx_warn("CVMX_PEXP_NPEI_CTL_STATUS2 not supported on this chip\n");
125 return CVMX_ADD_IO_SEG(0x00011F000000BC00ull);
128 #define CVMX_PEXP_NPEI_CTL_STATUS2 (CVMX_ADD_IO_SEG(0x00011F000000BC00ull))
130 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
131 #define CVMX_PEXP_NPEI_DATA_OUT_CNT CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC()
132 static inline uint64_t CVMX_PEXP_NPEI_DATA_OUT_CNT_FUNC(void)
134 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
135 cvmx_warn("CVMX_PEXP_NPEI_DATA_OUT_CNT not supported on this chip\n");
136 return CVMX_ADD_IO_SEG(0x00011F00000085F0ull);
139 #define CVMX_PEXP_NPEI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000085F0ull))
141 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
142 #define CVMX_PEXP_NPEI_DBG_DATA CVMX_PEXP_NPEI_DBG_DATA_FUNC()
143 static inline uint64_t CVMX_PEXP_NPEI_DBG_DATA_FUNC(void)
145 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
146 cvmx_warn("CVMX_PEXP_NPEI_DBG_DATA not supported on this chip\n");
147 return CVMX_ADD_IO_SEG(0x00011F0000008510ull);
150 #define CVMX_PEXP_NPEI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000008510ull))
152 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
153 #define CVMX_PEXP_NPEI_DBG_SELECT CVMX_PEXP_NPEI_DBG_SELECT_FUNC()
154 static inline uint64_t CVMX_PEXP_NPEI_DBG_SELECT_FUNC(void)
156 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
157 cvmx_warn("CVMX_PEXP_NPEI_DBG_SELECT not supported on this chip\n");
158 return CVMX_ADD_IO_SEG(0x00011F0000008500ull);
161 #define CVMX_PEXP_NPEI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000008500ull))
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC()
165 static inline uint64_t CVMX_PEXP_NPEI_DMA0_INT_LEVEL_FUNC(void)
167 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
168 cvmx_warn("CVMX_PEXP_NPEI_DMA0_INT_LEVEL not supported on this chip\n");
169 return CVMX_ADD_IO_SEG(0x00011F00000085C0ull);
172 #define CVMX_PEXP_NPEI_DMA0_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085C0ull))
174 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
175 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC()
176 static inline uint64_t CVMX_PEXP_NPEI_DMA1_INT_LEVEL_FUNC(void)
178 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
179 cvmx_warn("CVMX_PEXP_NPEI_DMA1_INT_LEVEL not supported on this chip\n");
180 return CVMX_ADD_IO_SEG(0x00011F00000085D0ull);
183 #define CVMX_PEXP_NPEI_DMA1_INT_LEVEL (CVMX_ADD_IO_SEG(0x00011F00000085D0ull))
185 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
186 static inline uint64_t CVMX_PEXP_NPEI_DMAX_COUNTS(unsigned long offset)
189 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
190 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
191 cvmx_warn("CVMX_PEXP_NPEI_DMAX_COUNTS(%lu) is invalid on this chip\n", offset);
192 return CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16;
195 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000008450ull) + ((offset) & 7) * 16)
197 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
198 static inline uint64_t CVMX_PEXP_NPEI_DMAX_DBELL(unsigned long offset)
201 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
203 cvmx_warn("CVMX_PEXP_NPEI_DMAX_DBELL(%lu) is invalid on this chip\n", offset);
204 return CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16;
207 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F00000083B0ull) + ((offset) & 7) * 16)
209 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
210 static inline uint64_t CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(unsigned long offset)
213 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
214 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
215 cvmx_warn("CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(%lu) is invalid on this chip\n", offset);
216 return CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16;
219 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000008400ull) + ((offset) & 7) * 16)
221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
222 static inline uint64_t CVMX_PEXP_NPEI_DMAX_NADDR(unsigned long offset)
225 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 4))) ||
226 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 4)))))
227 cvmx_warn("CVMX_PEXP_NPEI_DMAX_NADDR(%lu) is invalid on this chip\n", offset);
228 return CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16;
231 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000084A0ull) + ((offset) & 7) * 16)
233 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
234 #define CVMX_PEXP_NPEI_DMA_CNTS CVMX_PEXP_NPEI_DMA_CNTS_FUNC()
235 static inline uint64_t CVMX_PEXP_NPEI_DMA_CNTS_FUNC(void)
237 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
238 cvmx_warn("CVMX_PEXP_NPEI_DMA_CNTS not supported on this chip\n");
239 return CVMX_ADD_IO_SEG(0x00011F00000085E0ull);
242 #define CVMX_PEXP_NPEI_DMA_CNTS (CVMX_ADD_IO_SEG(0x00011F00000085E0ull))
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
245 #define CVMX_PEXP_NPEI_DMA_CONTROL CVMX_PEXP_NPEI_DMA_CONTROL_FUNC()
246 static inline uint64_t CVMX_PEXP_NPEI_DMA_CONTROL_FUNC(void)
248 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
249 cvmx_warn("CVMX_PEXP_NPEI_DMA_CONTROL not supported on this chip\n");
250 return CVMX_ADD_IO_SEG(0x00011F00000083A0ull);
253 #define CVMX_PEXP_NPEI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000083A0ull))
255 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
256 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC()
257 static inline uint64_t CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM_FUNC(void)
259 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
260 cvmx_warn("CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM not supported on this chip\n");
261 return CVMX_ADD_IO_SEG(0x00011F00000085B0ull);
264 #define CVMX_PEXP_NPEI_DMA_PCIE_REQ_NUM (CVMX_ADD_IO_SEG(0x00011F00000085B0ull))
266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
267 #define CVMX_PEXP_NPEI_DMA_STATE1 CVMX_PEXP_NPEI_DMA_STATE1_FUNC()
268 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE1_FUNC(void)
270 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
271 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE1 not supported on this chip\n");
272 return CVMX_ADD_IO_SEG(0x00011F00000086C0ull);
275 #define CVMX_PEXP_NPEI_DMA_STATE1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
277 #define CVMX_PEXP_NPEI_DMA_STATE1_P1 (CVMX_ADD_IO_SEG(0x00011F0000008680ull))
278 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
279 #define CVMX_PEXP_NPEI_DMA_STATE2 CVMX_PEXP_NPEI_DMA_STATE2_FUNC()
280 static inline uint64_t CVMX_PEXP_NPEI_DMA_STATE2_FUNC(void)
282 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX)))
283 cvmx_warn("CVMX_PEXP_NPEI_DMA_STATE2 not supported on this chip\n");
284 return CVMX_ADD_IO_SEG(0x00011F00000086D0ull);
287 #define CVMX_PEXP_NPEI_DMA_STATE2 (CVMX_ADD_IO_SEG(0x00011F00000086D0ull))
289 #define CVMX_PEXP_NPEI_DMA_STATE2_P1 (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
290 #define CVMX_PEXP_NPEI_DMA_STATE3_P1 (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
291 #define CVMX_PEXP_NPEI_DMA_STATE4_P1 (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
292 #define CVMX_PEXP_NPEI_DMA_STATE5_P1 (CVMX_ADD_IO_SEG(0x00011F00000086C0ull))
293 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
294 #define CVMX_PEXP_NPEI_INT_A_ENB CVMX_PEXP_NPEI_INT_A_ENB_FUNC()
295 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB_FUNC(void)
297 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
298 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB not supported on this chip\n");
299 return CVMX_ADD_IO_SEG(0x00011F0000008560ull);
302 #define CVMX_PEXP_NPEI_INT_A_ENB (CVMX_ADD_IO_SEG(0x00011F0000008560ull))
304 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
305 #define CVMX_PEXP_NPEI_INT_A_ENB2 CVMX_PEXP_NPEI_INT_A_ENB2_FUNC()
306 static inline uint64_t CVMX_PEXP_NPEI_INT_A_ENB2_FUNC(void)
308 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
309 cvmx_warn("CVMX_PEXP_NPEI_INT_A_ENB2 not supported on this chip\n");
310 return CVMX_ADD_IO_SEG(0x00011F000000BCE0ull);
313 #define CVMX_PEXP_NPEI_INT_A_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCE0ull))
315 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
316 #define CVMX_PEXP_NPEI_INT_A_SUM CVMX_PEXP_NPEI_INT_A_SUM_FUNC()
317 static inline uint64_t CVMX_PEXP_NPEI_INT_A_SUM_FUNC(void)
319 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
320 cvmx_warn("CVMX_PEXP_NPEI_INT_A_SUM not supported on this chip\n");
321 return CVMX_ADD_IO_SEG(0x00011F0000008550ull);
324 #define CVMX_PEXP_NPEI_INT_A_SUM (CVMX_ADD_IO_SEG(0x00011F0000008550ull))
326 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
327 #define CVMX_PEXP_NPEI_INT_ENB CVMX_PEXP_NPEI_INT_ENB_FUNC()
328 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB_FUNC(void)
330 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
331 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB not supported on this chip\n");
332 return CVMX_ADD_IO_SEG(0x00011F0000008540ull);
335 #define CVMX_PEXP_NPEI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000008540ull))
337 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
338 #define CVMX_PEXP_NPEI_INT_ENB2 CVMX_PEXP_NPEI_INT_ENB2_FUNC()
339 static inline uint64_t CVMX_PEXP_NPEI_INT_ENB2_FUNC(void)
341 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
342 cvmx_warn("CVMX_PEXP_NPEI_INT_ENB2 not supported on this chip\n");
343 return CVMX_ADD_IO_SEG(0x00011F000000BCD0ull);
346 #define CVMX_PEXP_NPEI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BCD0ull))
348 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
349 #define CVMX_PEXP_NPEI_INT_INFO CVMX_PEXP_NPEI_INT_INFO_FUNC()
350 static inline uint64_t CVMX_PEXP_NPEI_INT_INFO_FUNC(void)
352 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
353 cvmx_warn("CVMX_PEXP_NPEI_INT_INFO not supported on this chip\n");
354 return CVMX_ADD_IO_SEG(0x00011F0000008590ull);
357 #define CVMX_PEXP_NPEI_INT_INFO (CVMX_ADD_IO_SEG(0x00011F0000008590ull))
359 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
360 #define CVMX_PEXP_NPEI_INT_SUM CVMX_PEXP_NPEI_INT_SUM_FUNC()
361 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM_FUNC(void)
363 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
364 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM not supported on this chip\n");
365 return CVMX_ADD_IO_SEG(0x00011F0000008530ull);
368 #define CVMX_PEXP_NPEI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000008530ull))
370 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
371 #define CVMX_PEXP_NPEI_INT_SUM2 CVMX_PEXP_NPEI_INT_SUM2_FUNC()
372 static inline uint64_t CVMX_PEXP_NPEI_INT_SUM2_FUNC(void)
374 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
375 cvmx_warn("CVMX_PEXP_NPEI_INT_SUM2 not supported on this chip\n");
376 return CVMX_ADD_IO_SEG(0x00011F000000BCC0ull);
379 #define CVMX_PEXP_NPEI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F000000BCC0ull))
381 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
382 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC()
383 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA0_FUNC(void)
385 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
386 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA0 not supported on this chip\n");
387 return CVMX_ADD_IO_SEG(0x00011F0000008600ull);
390 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000008600ull))
392 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
393 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC()
394 static inline uint64_t CVMX_PEXP_NPEI_LAST_WIN_RDATA1_FUNC(void)
396 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
397 cvmx_warn("CVMX_PEXP_NPEI_LAST_WIN_RDATA1 not supported on this chip\n");
398 return CVMX_ADD_IO_SEG(0x00011F0000008610ull);
401 #define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000008610ull))
403 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
404 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC()
405 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_CTL_FUNC(void)
407 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
408 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_CTL not supported on this chip\n");
409 return CVMX_ADD_IO_SEG(0x00011F00000084F0ull);
412 #define CVMX_PEXP_NPEI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000084F0ull))
414 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
415 static inline uint64_t CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(unsigned long offset)
418 (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 12) && (offset <= 27)))) ||
419 (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 12) && (offset <= 27))))))
420 cvmx_warn("CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
421 return CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12;
424 #define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000008280ull) + ((offset) & 31) * 16 - 16*12)
426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
427 #define CVMX_PEXP_NPEI_MSI_ENB0 CVMX_PEXP_NPEI_MSI_ENB0_FUNC()
428 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB0_FUNC(void)
430 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
431 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB0 not supported on this chip\n");
432 return CVMX_ADD_IO_SEG(0x00011F000000BC50ull);
435 #define CVMX_PEXP_NPEI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BC50ull))
437 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
438 #define CVMX_PEXP_NPEI_MSI_ENB1 CVMX_PEXP_NPEI_MSI_ENB1_FUNC()
439 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB1_FUNC(void)
441 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
442 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB1 not supported on this chip\n");
443 return CVMX_ADD_IO_SEG(0x00011F000000BC60ull);
446 #define CVMX_PEXP_NPEI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BC60ull))
448 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
449 #define CVMX_PEXP_NPEI_MSI_ENB2 CVMX_PEXP_NPEI_MSI_ENB2_FUNC()
450 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB2_FUNC(void)
452 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
453 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB2 not supported on this chip\n");
454 return CVMX_ADD_IO_SEG(0x00011F000000BC70ull);
457 #define CVMX_PEXP_NPEI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BC70ull))
459 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
460 #define CVMX_PEXP_NPEI_MSI_ENB3 CVMX_PEXP_NPEI_MSI_ENB3_FUNC()
461 static inline uint64_t CVMX_PEXP_NPEI_MSI_ENB3_FUNC(void)
463 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
464 cvmx_warn("CVMX_PEXP_NPEI_MSI_ENB3 not supported on this chip\n");
465 return CVMX_ADD_IO_SEG(0x00011F000000BC80ull);
468 #define CVMX_PEXP_NPEI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BC80ull))
470 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
471 #define CVMX_PEXP_NPEI_MSI_RCV0 CVMX_PEXP_NPEI_MSI_RCV0_FUNC()
472 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV0_FUNC(void)
474 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
475 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV0 not supported on this chip\n");
476 return CVMX_ADD_IO_SEG(0x00011F000000BC10ull);
479 #define CVMX_PEXP_NPEI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F000000BC10ull))
481 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
482 #define CVMX_PEXP_NPEI_MSI_RCV1 CVMX_PEXP_NPEI_MSI_RCV1_FUNC()
483 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV1_FUNC(void)
485 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
486 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV1 not supported on this chip\n");
487 return CVMX_ADD_IO_SEG(0x00011F000000BC20ull);
490 #define CVMX_PEXP_NPEI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F000000BC20ull))
492 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
493 #define CVMX_PEXP_NPEI_MSI_RCV2 CVMX_PEXP_NPEI_MSI_RCV2_FUNC()
494 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV2_FUNC(void)
496 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
497 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV2 not supported on this chip\n");
498 return CVMX_ADD_IO_SEG(0x00011F000000BC30ull);
501 #define CVMX_PEXP_NPEI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F000000BC30ull))
503 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
504 #define CVMX_PEXP_NPEI_MSI_RCV3 CVMX_PEXP_NPEI_MSI_RCV3_FUNC()
505 static inline uint64_t CVMX_PEXP_NPEI_MSI_RCV3_FUNC(void)
507 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
508 cvmx_warn("CVMX_PEXP_NPEI_MSI_RCV3 not supported on this chip\n");
509 return CVMX_ADD_IO_SEG(0x00011F000000BC40ull);
512 #define CVMX_PEXP_NPEI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F000000BC40ull))
514 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
515 #define CVMX_PEXP_NPEI_MSI_RD_MAP CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC()
516 static inline uint64_t CVMX_PEXP_NPEI_MSI_RD_MAP_FUNC(void)
518 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
519 cvmx_warn("CVMX_PEXP_NPEI_MSI_RD_MAP not supported on this chip\n");
520 return CVMX_ADD_IO_SEG(0x00011F000000BCA0ull);
523 #define CVMX_PEXP_NPEI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F000000BCA0ull))
525 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
526 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC()
527 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB0_FUNC(void)
529 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
530 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB0 not supported on this chip\n");
531 return CVMX_ADD_IO_SEG(0x00011F000000BCF0ull);
534 #define CVMX_PEXP_NPEI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BCF0ull))
536 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
537 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC()
538 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB1_FUNC(void)
540 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
541 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB1 not supported on this chip\n");
542 return CVMX_ADD_IO_SEG(0x00011F000000BD00ull);
545 #define CVMX_PEXP_NPEI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD00ull))
547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
548 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC()
549 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB2_FUNC(void)
551 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
552 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB2 not supported on this chip\n");
553 return CVMX_ADD_IO_SEG(0x00011F000000BD10ull);
556 #define CVMX_PEXP_NPEI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD10ull))
558 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
559 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC()
560 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1C_ENB3_FUNC(void)
562 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
563 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1C_ENB3 not supported on this chip\n");
564 return CVMX_ADD_IO_SEG(0x00011F000000BD20ull);
567 #define CVMX_PEXP_NPEI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD20ull))
569 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
570 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC()
571 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB0_FUNC(void)
573 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
574 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB0 not supported on this chip\n");
575 return CVMX_ADD_IO_SEG(0x00011F000000BD30ull);
578 #define CVMX_PEXP_NPEI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F000000BD30ull))
580 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
581 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC()
582 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB1_FUNC(void)
584 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
585 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB1 not supported on this chip\n");
586 return CVMX_ADD_IO_SEG(0x00011F000000BD40ull);
589 #define CVMX_PEXP_NPEI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F000000BD40ull))
591 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
592 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC()
593 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB2_FUNC(void)
595 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
596 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB2 not supported on this chip\n");
597 return CVMX_ADD_IO_SEG(0x00011F000000BD50ull);
600 #define CVMX_PEXP_NPEI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F000000BD50ull))
602 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
603 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC()
604 static inline uint64_t CVMX_PEXP_NPEI_MSI_W1S_ENB3_FUNC(void)
606 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
607 cvmx_warn("CVMX_PEXP_NPEI_MSI_W1S_ENB3 not supported on this chip\n");
608 return CVMX_ADD_IO_SEG(0x00011F000000BD60ull);
611 #define CVMX_PEXP_NPEI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F000000BD60ull))
613 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
614 #define CVMX_PEXP_NPEI_MSI_WR_MAP CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC()
615 static inline uint64_t CVMX_PEXP_NPEI_MSI_WR_MAP_FUNC(void)
617 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
618 cvmx_warn("CVMX_PEXP_NPEI_MSI_WR_MAP not supported on this chip\n");
619 return CVMX_ADD_IO_SEG(0x00011F000000BC90ull);
622 #define CVMX_PEXP_NPEI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F000000BC90ull))
624 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
625 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC()
626 static inline uint64_t CVMX_PEXP_NPEI_PCIE_CREDIT_CNT_FUNC(void)
628 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
629 cvmx_warn("CVMX_PEXP_NPEI_PCIE_CREDIT_CNT not supported on this chip\n");
630 return CVMX_ADD_IO_SEG(0x00011F000000BD70ull);
633 #define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F000000BD70ull))
635 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
636 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC()
637 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_FUNC(void)
639 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
640 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV not supported on this chip\n");
641 return CVMX_ADD_IO_SEG(0x00011F000000BCB0ull);
644 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F000000BCB0ull))
646 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
647 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC()
648 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1_FUNC(void)
650 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
651 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 not supported on this chip\n");
652 return CVMX_ADD_IO_SEG(0x00011F0000008650ull);
655 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000008650ull))
657 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
658 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC()
659 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2_FUNC(void)
661 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
662 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 not supported on this chip\n");
663 return CVMX_ADD_IO_SEG(0x00011F0000008660ull);
666 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000008660ull))
668 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
669 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC()
670 static inline uint64_t CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3_FUNC(void)
672 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
673 cvmx_warn("CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 not supported on this chip\n");
674 return CVMX_ADD_IO_SEG(0x00011F0000008670ull);
677 #define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000008670ull))
679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
680 static inline uint64_t CVMX_PEXP_NPEI_PKTX_CNTS(unsigned long offset)
683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
685 cvmx_warn("CVMX_PEXP_NPEI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
686 return CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16;
689 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A400ull) + ((offset) & 31) * 16)
691 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
692 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(unsigned long offset)
695 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
696 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
697 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
698 return CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16;
701 #define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F000000A800ull) + ((offset) & 31) * 16)
703 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
704 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
707 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
708 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
709 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
710 return CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16;
713 #define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F000000AC00ull) + ((offset) & 31) * 16)
715 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
716 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
719 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
721 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
722 return CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16;
725 #define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F000000B000ull) + ((offset) & 31) * 16)
727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
728 static inline uint64_t CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(unsigned long offset)
731 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
732 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
733 cvmx_warn("CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
734 return CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16;
737 #define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F000000B400ull) + ((offset) & 31) * 16)
739 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
740 static inline uint64_t CVMX_PEXP_NPEI_PKTX_IN_BP(unsigned long offset)
743 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
744 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
745 cvmx_warn("CVMX_PEXP_NPEI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
746 return CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16;
749 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F000000B800ull) + ((offset) & 31) * 16)
751 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
752 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(unsigned long offset)
755 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
757 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
758 return CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16;
761 #define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000009400ull) + ((offset) & 31) * 16)
763 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
764 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
767 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
769 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
770 return CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16;
773 #define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000009800ull) + ((offset) & 31) * 16)
775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
776 static inline uint64_t CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
779 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
781 cvmx_warn("CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
782 return CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16;
785 #define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000009C00ull) + ((offset) & 31) * 16)
787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
788 #define CVMX_PEXP_NPEI_PKT_CNT_INT CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC()
789 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_FUNC(void)
791 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
792 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT not supported on this chip\n");
793 return CVMX_ADD_IO_SEG(0x00011F0000009110ull);
796 #define CVMX_PEXP_NPEI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000009110ull))
798 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
799 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC()
800 static inline uint64_t CVMX_PEXP_NPEI_PKT_CNT_INT_ENB_FUNC(void)
802 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
803 cvmx_warn("CVMX_PEXP_NPEI_PKT_CNT_INT_ENB not supported on this chip\n");
804 return CVMX_ADD_IO_SEG(0x00011F0000009130ull);
807 #define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009130ull))
809 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
810 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC()
811 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ES_FUNC(void)
813 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
814 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ES not supported on this chip\n");
815 return CVMX_ADD_IO_SEG(0x00011F00000090B0ull);
818 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000090B0ull))
820 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
821 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC()
822 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_NS_FUNC(void)
824 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
825 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_NS not supported on this chip\n");
826 return CVMX_ADD_IO_SEG(0x00011F00000090A0ull);
829 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000090A0ull))
831 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
832 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC()
833 static inline uint64_t CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR_FUNC(void)
835 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
836 cvmx_warn("CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR not supported on this chip\n");
837 return CVMX_ADD_IO_SEG(0x00011F0000009090ull);
840 #define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000009090ull))
842 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
843 #define CVMX_PEXP_NPEI_PKT_DPADDR CVMX_PEXP_NPEI_PKT_DPADDR_FUNC()
844 static inline uint64_t CVMX_PEXP_NPEI_PKT_DPADDR_FUNC(void)
846 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
847 cvmx_warn("CVMX_PEXP_NPEI_PKT_DPADDR not supported on this chip\n");
848 return CVMX_ADD_IO_SEG(0x00011F0000009080ull);
851 #define CVMX_PEXP_NPEI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000009080ull))
853 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
854 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC()
855 static inline uint64_t CVMX_PEXP_NPEI_PKT_INPUT_CONTROL_FUNC(void)
857 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
858 cvmx_warn("CVMX_PEXP_NPEI_PKT_INPUT_CONTROL not supported on this chip\n");
859 return CVMX_ADD_IO_SEG(0x00011F0000009150ull);
862 #define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000009150ull))
864 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
865 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC()
866 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_ENB_FUNC(void)
868 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
869 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_ENB not supported on this chip\n");
870 return CVMX_ADD_IO_SEG(0x00011F0000009000ull);
873 #define CVMX_PEXP_NPEI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000009000ull))
875 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
876 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC()
877 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE_FUNC(void)
879 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
880 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE not supported on this chip\n");
881 return CVMX_ADD_IO_SEG(0x00011F0000009190ull);
884 #define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009190ull))
886 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
887 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC()
888 static inline uint64_t CVMX_PEXP_NPEI_PKT_INSTR_SIZE_FUNC(void)
890 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
891 cvmx_warn("CVMX_PEXP_NPEI_PKT_INSTR_SIZE not supported on this chip\n");
892 return CVMX_ADD_IO_SEG(0x00011F0000009020ull);
895 #define CVMX_PEXP_NPEI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009020ull))
897 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
898 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC()
899 static inline uint64_t CVMX_PEXP_NPEI_PKT_INT_LEVELS_FUNC(void)
901 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
902 cvmx_warn("CVMX_PEXP_NPEI_PKT_INT_LEVELS not supported on this chip\n");
903 return CVMX_ADD_IO_SEG(0x00011F0000009100ull);
906 #define CVMX_PEXP_NPEI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000009100ull))
908 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
909 #define CVMX_PEXP_NPEI_PKT_IN_BP CVMX_PEXP_NPEI_PKT_IN_BP_FUNC()
910 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_BP_FUNC(void)
912 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
913 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_BP not supported on this chip\n");
914 return CVMX_ADD_IO_SEG(0x00011F00000086B0ull);
917 #define CVMX_PEXP_NPEI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F00000086B0ull))
919 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
920 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(unsigned long offset)
923 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31)))))
925 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
926 return CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16;
929 #define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F000000A000ull) + ((offset) & 31) * 16)
931 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
932 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC()
933 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS_FUNC(void)
935 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
936 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
937 return CVMX_ADD_IO_SEG(0x00011F00000086A0ull);
940 #define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F00000086A0ull))
942 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
943 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC()
944 static inline uint64_t CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT_FUNC(void)
946 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
947 cvmx_warn("CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT not supported on this chip\n");
948 return CVMX_ADD_IO_SEG(0x00011F00000091A0ull);
951 #define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000091A0ull))
953 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
954 #define CVMX_PEXP_NPEI_PKT_IPTR CVMX_PEXP_NPEI_PKT_IPTR_FUNC()
955 static inline uint64_t CVMX_PEXP_NPEI_PKT_IPTR_FUNC(void)
957 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
958 cvmx_warn("CVMX_PEXP_NPEI_PKT_IPTR not supported on this chip\n");
959 return CVMX_ADD_IO_SEG(0x00011F0000009070ull);
962 #define CVMX_PEXP_NPEI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000009070ull))
964 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
965 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC()
966 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK_FUNC(void)
968 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
969 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK not supported on this chip\n");
970 return CVMX_ADD_IO_SEG(0x00011F0000009160ull);
973 #define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000009160ull))
975 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
976 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC()
977 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_BMODE_FUNC(void)
979 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
980 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_BMODE not supported on this chip\n");
981 return CVMX_ADD_IO_SEG(0x00011F00000090D0ull);
984 #define CVMX_PEXP_NPEI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000090D0ull))
986 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
987 #define CVMX_PEXP_NPEI_PKT_OUT_ENB CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC()
988 static inline uint64_t CVMX_PEXP_NPEI_PKT_OUT_ENB_FUNC(void)
990 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
991 cvmx_warn("CVMX_PEXP_NPEI_PKT_OUT_ENB not supported on this chip\n");
992 return CVMX_ADD_IO_SEG(0x00011F0000009010ull);
995 #define CVMX_PEXP_NPEI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009010ull))
997 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
998 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC()
999 static inline uint64_t CVMX_PEXP_NPEI_PKT_PCIE_PORT_FUNC(void)
1001 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1002 cvmx_warn("CVMX_PEXP_NPEI_PKT_PCIE_PORT not supported on this chip\n");
1003 return CVMX_ADD_IO_SEG(0x00011F00000090E0ull);
1006 #define CVMX_PEXP_NPEI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000090E0ull))
1008 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1009 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC()
1010 static inline uint64_t CVMX_PEXP_NPEI_PKT_PORT_IN_RST_FUNC(void)
1012 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1013 cvmx_warn("CVMX_PEXP_NPEI_PKT_PORT_IN_RST not supported on this chip\n");
1014 return CVMX_ADD_IO_SEG(0x00011F0000008690ull);
1017 #define CVMX_PEXP_NPEI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F0000008690ull))
1019 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1020 #define CVMX_PEXP_NPEI_PKT_SLIST_ES CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC()
1021 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ES_FUNC(void)
1023 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1024 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ES not supported on this chip\n");
1025 return CVMX_ADD_IO_SEG(0x00011F0000009050ull);
1028 #define CVMX_PEXP_NPEI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000009050ull))
1030 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1031 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC()
1032 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE_FUNC(void)
1034 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1035 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE not supported on this chip\n");
1036 return CVMX_ADD_IO_SEG(0x00011F0000009180ull);
1039 #define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE (CVMX_ADD_IO_SEG(0x00011F0000009180ull))
1041 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1042 #define CVMX_PEXP_NPEI_PKT_SLIST_NS CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC()
1043 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_NS_FUNC(void)
1045 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1046 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_NS not supported on this chip\n");
1047 return CVMX_ADD_IO_SEG(0x00011F0000009040ull);
1050 #define CVMX_PEXP_NPEI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000009040ull))
1052 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1053 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC()
1054 static inline uint64_t CVMX_PEXP_NPEI_PKT_SLIST_ROR_FUNC(void)
1056 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1057 cvmx_warn("CVMX_PEXP_NPEI_PKT_SLIST_ROR not supported on this chip\n");
1058 return CVMX_ADD_IO_SEG(0x00011F0000009030ull);
1061 #define CVMX_PEXP_NPEI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000009030ull))
1063 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1064 #define CVMX_PEXP_NPEI_PKT_TIME_INT CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC()
1065 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_FUNC(void)
1067 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1068 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT not supported on this chip\n");
1069 return CVMX_ADD_IO_SEG(0x00011F0000009120ull);
1072 #define CVMX_PEXP_NPEI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000009120ull))
1074 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1075 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC()
1076 static inline uint64_t CVMX_PEXP_NPEI_PKT_TIME_INT_ENB_FUNC(void)
1078 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1079 cvmx_warn("CVMX_PEXP_NPEI_PKT_TIME_INT_ENB not supported on this chip\n");
1080 return CVMX_ADD_IO_SEG(0x00011F0000009140ull);
1083 #define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000009140ull))
1085 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1086 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC()
1087 static inline uint64_t CVMX_PEXP_NPEI_RSL_INT_BLOCKS_FUNC(void)
1089 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1090 cvmx_warn("CVMX_PEXP_NPEI_RSL_INT_BLOCKS not supported on this chip\n");
1091 return CVMX_ADD_IO_SEG(0x00011F0000008520ull);
1094 #define CVMX_PEXP_NPEI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000008520ull))
1096 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1097 #define CVMX_PEXP_NPEI_SCRATCH_1 CVMX_PEXP_NPEI_SCRATCH_1_FUNC()
1098 static inline uint64_t CVMX_PEXP_NPEI_SCRATCH_1_FUNC(void)
1100 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1101 cvmx_warn("CVMX_PEXP_NPEI_SCRATCH_1 not supported on this chip\n");
1102 return CVMX_ADD_IO_SEG(0x00011F0000008270ull);
1105 #define CVMX_PEXP_NPEI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F0000008270ull))
1107 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1108 #define CVMX_PEXP_NPEI_STATE1 CVMX_PEXP_NPEI_STATE1_FUNC()
1109 static inline uint64_t CVMX_PEXP_NPEI_STATE1_FUNC(void)
1111 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1112 cvmx_warn("CVMX_PEXP_NPEI_STATE1 not supported on this chip\n");
1113 return CVMX_ADD_IO_SEG(0x00011F0000008620ull);
1116 #define CVMX_PEXP_NPEI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000008620ull))
1118 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1119 #define CVMX_PEXP_NPEI_STATE2 CVMX_PEXP_NPEI_STATE2_FUNC()
1120 static inline uint64_t CVMX_PEXP_NPEI_STATE2_FUNC(void)
1122 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1123 cvmx_warn("CVMX_PEXP_NPEI_STATE2 not supported on this chip\n");
1124 return CVMX_ADD_IO_SEG(0x00011F0000008630ull);
1127 #define CVMX_PEXP_NPEI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000008630ull))
1129 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1130 #define CVMX_PEXP_NPEI_STATE3 CVMX_PEXP_NPEI_STATE3_FUNC()
1131 static inline uint64_t CVMX_PEXP_NPEI_STATE3_FUNC(void)
1133 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1134 cvmx_warn("CVMX_PEXP_NPEI_STATE3 not supported on this chip\n");
1135 return CVMX_ADD_IO_SEG(0x00011F0000008640ull);
1138 #define CVMX_PEXP_NPEI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000008640ull))
1140 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1141 #define CVMX_PEXP_NPEI_WINDOW_CTL CVMX_PEXP_NPEI_WINDOW_CTL_FUNC()
1142 static inline uint64_t CVMX_PEXP_NPEI_WINDOW_CTL_FUNC(void)
1144 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)))
1145 cvmx_warn("CVMX_PEXP_NPEI_WINDOW_CTL not supported on this chip\n");
1146 return CVMX_ADD_IO_SEG(0x00011F0000008380ull);
1149 #define CVMX_PEXP_NPEI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F0000008380ull))
1151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1152 #define CVMX_PEXP_SLI_BIST_STATUS CVMX_PEXP_SLI_BIST_STATUS_FUNC()
1153 static inline uint64_t CVMX_PEXP_SLI_BIST_STATUS_FUNC(void)
1155 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1156 cvmx_warn("CVMX_PEXP_SLI_BIST_STATUS not supported on this chip\n");
1157 return CVMX_ADD_IO_SEG(0x00011F0000010580ull);
1160 #define CVMX_PEXP_SLI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010580ull))
1162 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1163 static inline uint64_t CVMX_PEXP_SLI_CTL_PORTX(unsigned long offset)
1166 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
1169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1170 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1171 cvmx_warn("CVMX_PEXP_SLI_CTL_PORTX(%lu) is invalid on this chip\n", offset);
1172 return CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16;
1175 #define CVMX_PEXP_SLI_CTL_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010050ull) + ((offset) & 3) * 16)
1177 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1178 #define CVMX_PEXP_SLI_CTL_STATUS CVMX_PEXP_SLI_CTL_STATUS_FUNC()
1179 static inline uint64_t CVMX_PEXP_SLI_CTL_STATUS_FUNC(void)
1181 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1182 cvmx_warn("CVMX_PEXP_SLI_CTL_STATUS not supported on this chip\n");
1183 return CVMX_ADD_IO_SEG(0x00011F0000010570ull);
1186 #define CVMX_PEXP_SLI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000010570ull))
1188 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1189 #define CVMX_PEXP_SLI_DATA_OUT_CNT CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC()
1190 static inline uint64_t CVMX_PEXP_SLI_DATA_OUT_CNT_FUNC(void)
1192 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1193 cvmx_warn("CVMX_PEXP_SLI_DATA_OUT_CNT not supported on this chip\n");
1194 return CVMX_ADD_IO_SEG(0x00011F00000105F0ull);
1197 #define CVMX_PEXP_SLI_DATA_OUT_CNT (CVMX_ADD_IO_SEG(0x00011F00000105F0ull))
1199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1200 #define CVMX_PEXP_SLI_DBG_DATA CVMX_PEXP_SLI_DBG_DATA_FUNC()
1201 static inline uint64_t CVMX_PEXP_SLI_DBG_DATA_FUNC(void)
1203 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1204 cvmx_warn("CVMX_PEXP_SLI_DBG_DATA not supported on this chip\n");
1205 return CVMX_ADD_IO_SEG(0x00011F0000010310ull);
1208 #define CVMX_PEXP_SLI_DBG_DATA (CVMX_ADD_IO_SEG(0x00011F0000010310ull))
1210 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1211 #define CVMX_PEXP_SLI_DBG_SELECT CVMX_PEXP_SLI_DBG_SELECT_FUNC()
1212 static inline uint64_t CVMX_PEXP_SLI_DBG_SELECT_FUNC(void)
1214 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1215 cvmx_warn("CVMX_PEXP_SLI_DBG_SELECT not supported on this chip\n");
1216 return CVMX_ADD_IO_SEG(0x00011F0000010300ull);
1219 #define CVMX_PEXP_SLI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000010300ull))
1221 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1222 static inline uint64_t CVMX_PEXP_SLI_DMAX_CNT(unsigned long offset)
1225 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1226 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1227 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1228 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1229 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1230 cvmx_warn("CVMX_PEXP_SLI_DMAX_CNT(%lu) is invalid on this chip\n", offset);
1231 return CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16;
1234 #define CVMX_PEXP_SLI_DMAX_CNT(offset) (CVMX_ADD_IO_SEG(0x00011F0000010400ull) + ((offset) & 1) * 16)
1236 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1237 static inline uint64_t CVMX_PEXP_SLI_DMAX_INT_LEVEL(unsigned long offset)
1240 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1241 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1242 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1243 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1244 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1245 cvmx_warn("CVMX_PEXP_SLI_DMAX_INT_LEVEL(%lu) is invalid on this chip\n", offset);
1246 return CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16;
1249 #define CVMX_PEXP_SLI_DMAX_INT_LEVEL(offset) (CVMX_ADD_IO_SEG(0x00011F00000103E0ull) + ((offset) & 1) * 16)
1251 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1252 static inline uint64_t CVMX_PEXP_SLI_DMAX_TIM(unsigned long offset)
1255 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1257 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1258 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1259 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1260 cvmx_warn("CVMX_PEXP_SLI_DMAX_TIM(%lu) is invalid on this chip\n", offset);
1261 return CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16;
1264 #define CVMX_PEXP_SLI_DMAX_TIM(offset) (CVMX_ADD_IO_SEG(0x00011F0000010420ull) + ((offset) & 1) * 16)
1266 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1267 #define CVMX_PEXP_SLI_INT_ENB_CIU CVMX_PEXP_SLI_INT_ENB_CIU_FUNC()
1268 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_CIU_FUNC(void)
1270 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1271 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_CIU not supported on this chip\n");
1272 return CVMX_ADD_IO_SEG(0x00011F0000013CD0ull);
1275 #define CVMX_PEXP_SLI_INT_ENB_CIU (CVMX_ADD_IO_SEG(0x00011F0000013CD0ull))
1277 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1278 static inline uint64_t CVMX_PEXP_SLI_INT_ENB_PORTX(unsigned long offset)
1281 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1282 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1283 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1284 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1285 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1286 cvmx_warn("CVMX_PEXP_SLI_INT_ENB_PORTX(%lu) is invalid on this chip\n", offset);
1287 return CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16;
1290 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000010340ull) + ((offset) & 1) * 16)
1292 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1293 #define CVMX_PEXP_SLI_INT_SUM CVMX_PEXP_SLI_INT_SUM_FUNC()
1294 static inline uint64_t CVMX_PEXP_SLI_INT_SUM_FUNC(void)
1296 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1297 cvmx_warn("CVMX_PEXP_SLI_INT_SUM not supported on this chip\n");
1298 return CVMX_ADD_IO_SEG(0x00011F0000010330ull);
1301 #define CVMX_PEXP_SLI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000010330ull))
1303 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1304 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC()
1305 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA0_FUNC(void)
1307 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1308 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA0 not supported on this chip\n");
1309 return CVMX_ADD_IO_SEG(0x00011F0000010600ull);
1312 #define CVMX_PEXP_SLI_LAST_WIN_RDATA0 (CVMX_ADD_IO_SEG(0x00011F0000010600ull))
1314 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1315 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC()
1316 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA1_FUNC(void)
1318 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1319 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA1 not supported on this chip\n");
1320 return CVMX_ADD_IO_SEG(0x00011F0000010610ull);
1323 #define CVMX_PEXP_SLI_LAST_WIN_RDATA1 (CVMX_ADD_IO_SEG(0x00011F0000010610ull))
1325 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1326 #define CVMX_PEXP_SLI_LAST_WIN_RDATA2 CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC()
1327 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA2_FUNC(void)
1329 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1330 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA2 not supported on this chip\n");
1331 return CVMX_ADD_IO_SEG(0x00011F00000106C0ull);
1334 #define CVMX_PEXP_SLI_LAST_WIN_RDATA2 (CVMX_ADD_IO_SEG(0x00011F00000106C0ull))
1336 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1337 #define CVMX_PEXP_SLI_LAST_WIN_RDATA3 CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC()
1338 static inline uint64_t CVMX_PEXP_SLI_LAST_WIN_RDATA3_FUNC(void)
1340 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1341 cvmx_warn("CVMX_PEXP_SLI_LAST_WIN_RDATA3 not supported on this chip\n");
1342 return CVMX_ADD_IO_SEG(0x00011F00000106D0ull);
1345 #define CVMX_PEXP_SLI_LAST_WIN_RDATA3 (CVMX_ADD_IO_SEG(0x00011F00000106D0ull))
1347 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1348 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC()
1349 static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT_FUNC(void)
1351 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1352 cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT not supported on this chip\n");
1353 return CVMX_ADD_IO_SEG(0x00011F0000013D70ull);
1356 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT (CVMX_ADD_IO_SEG(0x00011F0000013D70ull))
1358 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1359 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC()
1360 static inline uint64_t CVMX_PEXP_SLI_MAC_CREDIT_CNT2_FUNC(void)
1362 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1363 cvmx_warn("CVMX_PEXP_SLI_MAC_CREDIT_CNT2 not supported on this chip\n");
1364 return CVMX_ADD_IO_SEG(0x00011F0000013E10ull);
1367 #define CVMX_PEXP_SLI_MAC_CREDIT_CNT2 (CVMX_ADD_IO_SEG(0x00011F0000013E10ull))
1369 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1370 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC()
1371 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_CTL_FUNC(void)
1373 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1374 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_CTL not supported on this chip\n");
1375 return CVMX_ADD_IO_SEG(0x00011F00000102F0ull);
1378 #define CVMX_PEXP_SLI_MEM_ACCESS_CTL (CVMX_ADD_IO_SEG(0x00011F00000102F0ull))
1380 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1381 static inline uint64_t CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(unsigned long offset)
1384 (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 12) && (offset <= 27)))) ||
1385 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 12) && (offset <= 27)))) ||
1386 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 12) && (offset <= 27)))) ||
1387 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset >= 12) && (offset <= 27)))) ||
1388 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 12) && (offset <= 27))))))
1389 cvmx_warn("CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset);
1390 return CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12;
1393 #define CVMX_PEXP_SLI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F00000100E0ull) + ((offset) & 31) * 16 - 16*12)
1395 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1396 #define CVMX_PEXP_SLI_MSI_ENB0 CVMX_PEXP_SLI_MSI_ENB0_FUNC()
1397 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB0_FUNC(void)
1399 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1400 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB0 not supported on this chip\n");
1401 return CVMX_ADD_IO_SEG(0x00011F0000013C50ull);
1404 #define CVMX_PEXP_SLI_MSI_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013C50ull))
1406 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1407 #define CVMX_PEXP_SLI_MSI_ENB1 CVMX_PEXP_SLI_MSI_ENB1_FUNC()
1408 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB1_FUNC(void)
1410 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1411 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB1 not supported on this chip\n");
1412 return CVMX_ADD_IO_SEG(0x00011F0000013C60ull);
1415 #define CVMX_PEXP_SLI_MSI_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013C60ull))
1417 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1418 #define CVMX_PEXP_SLI_MSI_ENB2 CVMX_PEXP_SLI_MSI_ENB2_FUNC()
1419 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB2_FUNC(void)
1421 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1422 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB2 not supported on this chip\n");
1423 return CVMX_ADD_IO_SEG(0x00011F0000013C70ull);
1426 #define CVMX_PEXP_SLI_MSI_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013C70ull))
1428 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1429 #define CVMX_PEXP_SLI_MSI_ENB3 CVMX_PEXP_SLI_MSI_ENB3_FUNC()
1430 static inline uint64_t CVMX_PEXP_SLI_MSI_ENB3_FUNC(void)
1432 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1433 cvmx_warn("CVMX_PEXP_SLI_MSI_ENB3 not supported on this chip\n");
1434 return CVMX_ADD_IO_SEG(0x00011F0000013C80ull);
1437 #define CVMX_PEXP_SLI_MSI_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013C80ull))
1439 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1440 #define CVMX_PEXP_SLI_MSI_RCV0 CVMX_PEXP_SLI_MSI_RCV0_FUNC()
1441 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV0_FUNC(void)
1443 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1444 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV0 not supported on this chip\n");
1445 return CVMX_ADD_IO_SEG(0x00011F0000013C10ull);
1448 #define CVMX_PEXP_SLI_MSI_RCV0 (CVMX_ADD_IO_SEG(0x00011F0000013C10ull))
1450 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1451 #define CVMX_PEXP_SLI_MSI_RCV1 CVMX_PEXP_SLI_MSI_RCV1_FUNC()
1452 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV1_FUNC(void)
1454 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1455 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV1 not supported on this chip\n");
1456 return CVMX_ADD_IO_SEG(0x00011F0000013C20ull);
1459 #define CVMX_PEXP_SLI_MSI_RCV1 (CVMX_ADD_IO_SEG(0x00011F0000013C20ull))
1461 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1462 #define CVMX_PEXP_SLI_MSI_RCV2 CVMX_PEXP_SLI_MSI_RCV2_FUNC()
1463 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV2_FUNC(void)
1465 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1466 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV2 not supported on this chip\n");
1467 return CVMX_ADD_IO_SEG(0x00011F0000013C30ull);
1470 #define CVMX_PEXP_SLI_MSI_RCV2 (CVMX_ADD_IO_SEG(0x00011F0000013C30ull))
1472 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1473 #define CVMX_PEXP_SLI_MSI_RCV3 CVMX_PEXP_SLI_MSI_RCV3_FUNC()
1474 static inline uint64_t CVMX_PEXP_SLI_MSI_RCV3_FUNC(void)
1476 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1477 cvmx_warn("CVMX_PEXP_SLI_MSI_RCV3 not supported on this chip\n");
1478 return CVMX_ADD_IO_SEG(0x00011F0000013C40ull);
1481 #define CVMX_PEXP_SLI_MSI_RCV3 (CVMX_ADD_IO_SEG(0x00011F0000013C40ull))
1483 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1484 #define CVMX_PEXP_SLI_MSI_RD_MAP CVMX_PEXP_SLI_MSI_RD_MAP_FUNC()
1485 static inline uint64_t CVMX_PEXP_SLI_MSI_RD_MAP_FUNC(void)
1487 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1488 cvmx_warn("CVMX_PEXP_SLI_MSI_RD_MAP not supported on this chip\n");
1489 return CVMX_ADD_IO_SEG(0x00011F0000013CA0ull);
1492 #define CVMX_PEXP_SLI_MSI_RD_MAP (CVMX_ADD_IO_SEG(0x00011F0000013CA0ull))
1494 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1495 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC()
1496 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB0_FUNC(void)
1498 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1499 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB0 not supported on this chip\n");
1500 return CVMX_ADD_IO_SEG(0x00011F0000013CF0ull);
1503 #define CVMX_PEXP_SLI_MSI_W1C_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013CF0ull))
1505 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1506 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC()
1507 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB1_FUNC(void)
1509 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1510 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB1 not supported on this chip\n");
1511 return CVMX_ADD_IO_SEG(0x00011F0000013D00ull);
1514 #define CVMX_PEXP_SLI_MSI_W1C_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D00ull))
1516 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1517 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC()
1518 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB2_FUNC(void)
1520 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1521 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB2 not supported on this chip\n");
1522 return CVMX_ADD_IO_SEG(0x00011F0000013D10ull);
1525 #define CVMX_PEXP_SLI_MSI_W1C_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D10ull))
1527 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1528 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC()
1529 static inline uint64_t CVMX_PEXP_SLI_MSI_W1C_ENB3_FUNC(void)
1531 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1532 cvmx_warn("CVMX_PEXP_SLI_MSI_W1C_ENB3 not supported on this chip\n");
1533 return CVMX_ADD_IO_SEG(0x00011F0000013D20ull);
1536 #define CVMX_PEXP_SLI_MSI_W1C_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D20ull))
1538 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1539 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC()
1540 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB0_FUNC(void)
1542 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1543 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB0 not supported on this chip\n");
1544 return CVMX_ADD_IO_SEG(0x00011F0000013D30ull);
1547 #define CVMX_PEXP_SLI_MSI_W1S_ENB0 (CVMX_ADD_IO_SEG(0x00011F0000013D30ull))
1549 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1550 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC()
1551 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB1_FUNC(void)
1553 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1554 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB1 not supported on this chip\n");
1555 return CVMX_ADD_IO_SEG(0x00011F0000013D40ull);
1558 #define CVMX_PEXP_SLI_MSI_W1S_ENB1 (CVMX_ADD_IO_SEG(0x00011F0000013D40ull))
1560 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1561 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC()
1562 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB2_FUNC(void)
1564 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1565 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB2 not supported on this chip\n");
1566 return CVMX_ADD_IO_SEG(0x00011F0000013D50ull);
1569 #define CVMX_PEXP_SLI_MSI_W1S_ENB2 (CVMX_ADD_IO_SEG(0x00011F0000013D50ull))
1571 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1572 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC()
1573 static inline uint64_t CVMX_PEXP_SLI_MSI_W1S_ENB3_FUNC(void)
1575 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1576 cvmx_warn("CVMX_PEXP_SLI_MSI_W1S_ENB3 not supported on this chip\n");
1577 return CVMX_ADD_IO_SEG(0x00011F0000013D60ull);
1580 #define CVMX_PEXP_SLI_MSI_W1S_ENB3 (CVMX_ADD_IO_SEG(0x00011F0000013D60ull))
1582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1583 #define CVMX_PEXP_SLI_MSI_WR_MAP CVMX_PEXP_SLI_MSI_WR_MAP_FUNC()
1584 static inline uint64_t CVMX_PEXP_SLI_MSI_WR_MAP_FUNC(void)
1586 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1587 cvmx_warn("CVMX_PEXP_SLI_MSI_WR_MAP not supported on this chip\n");
1588 return CVMX_ADD_IO_SEG(0x00011F0000013C90ull);
1591 #define CVMX_PEXP_SLI_MSI_WR_MAP (CVMX_ADD_IO_SEG(0x00011F0000013C90ull))
1593 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1594 #define CVMX_PEXP_SLI_PCIE_MSI_RCV CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC()
1595 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_FUNC(void)
1597 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1598 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV not supported on this chip\n");
1599 return CVMX_ADD_IO_SEG(0x00011F0000013CB0ull);
1602 #define CVMX_PEXP_SLI_PCIE_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000013CB0ull))
1604 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1605 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC()
1606 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B1_FUNC(void)
1608 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1609 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 not supported on this chip\n");
1610 return CVMX_ADD_IO_SEG(0x00011F0000010650ull);
1613 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B1 (CVMX_ADD_IO_SEG(0x00011F0000010650ull))
1615 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1616 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC()
1617 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B2_FUNC(void)
1619 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1620 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 not supported on this chip\n");
1621 return CVMX_ADD_IO_SEG(0x00011F0000010660ull);
1624 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B2 (CVMX_ADD_IO_SEG(0x00011F0000010660ull))
1626 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1627 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC()
1628 static inline uint64_t CVMX_PEXP_SLI_PCIE_MSI_RCV_B3_FUNC(void)
1630 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1631 cvmx_warn("CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 not supported on this chip\n");
1632 return CVMX_ADD_IO_SEG(0x00011F0000010670ull);
1635 #define CVMX_PEXP_SLI_PCIE_MSI_RCV_B3 (CVMX_ADD_IO_SEG(0x00011F0000010670ull))
1637 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1638 static inline uint64_t CVMX_PEXP_SLI_PKTX_CNTS(unsigned long offset)
1641 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1642 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1643 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1644 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1645 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1646 cvmx_warn("CVMX_PEXP_SLI_PKTX_CNTS(%lu) is invalid on this chip\n", offset);
1647 return CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16;
1650 #define CVMX_PEXP_SLI_PKTX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012400ull) + ((offset) & 31) * 16)
1652 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1653 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BADDR(unsigned long offset)
1656 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1657 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1658 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1659 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1660 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1661 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BADDR(%lu) is invalid on this chip\n", offset);
1662 return CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16;
1665 #define CVMX_PEXP_SLI_PKTX_INSTR_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000012800ull) + ((offset) & 31) * 16)
1667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1668 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(unsigned long offset)
1671 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1672 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1673 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1674 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1675 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1676 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1677 return CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16;
1680 #define CVMX_PEXP_SLI_PKTX_INSTR_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000012C00ull) + ((offset) & 31) * 16)
1682 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1683 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(unsigned long offset)
1686 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1687 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1688 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1689 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1690 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1691 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1692 return CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16;
1695 #define CVMX_PEXP_SLI_PKTX_INSTR_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000013000ull) + ((offset) & 31) * 16)
1697 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1698 static inline uint64_t CVMX_PEXP_SLI_PKTX_INSTR_HEADER(unsigned long offset)
1701 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1702 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1703 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1704 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1705 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1706 cvmx_warn("CVMX_PEXP_SLI_PKTX_INSTR_HEADER(%lu) is invalid on this chip\n", offset);
1707 return CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16;
1710 #define CVMX_PEXP_SLI_PKTX_INSTR_HEADER(offset) (CVMX_ADD_IO_SEG(0x00011F0000013400ull) + ((offset) & 31) * 16)
1712 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1713 static inline uint64_t CVMX_PEXP_SLI_PKTX_IN_BP(unsigned long offset)
1716 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1717 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1718 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1719 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1720 cvmx_warn("CVMX_PEXP_SLI_PKTX_IN_BP(%lu) is invalid on this chip\n", offset);
1721 return CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16;
1724 #define CVMX_PEXP_SLI_PKTX_IN_BP(offset) (CVMX_ADD_IO_SEG(0x00011F0000013800ull) + ((offset) & 31) * 16)
1726 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1727 static inline uint64_t CVMX_PEXP_SLI_PKTX_OUT_SIZE(unsigned long offset)
1730 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1731 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1732 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1733 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1734 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1735 cvmx_warn("CVMX_PEXP_SLI_PKTX_OUT_SIZE(%lu) is invalid on this chip\n", offset);
1736 return CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16;
1739 #define CVMX_PEXP_SLI_PKTX_OUT_SIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000010C00ull) + ((offset) & 31) * 16)
1741 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1742 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BADDR(unsigned long offset)
1745 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1746 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1747 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1748 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1749 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1750 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BADDR(%lu) is invalid on this chip\n", offset);
1751 return CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16;
1754 #define CVMX_PEXP_SLI_PKTX_SLIST_BADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000011400ull) + ((offset) & 31) * 16)
1756 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1757 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(unsigned long offset)
1760 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1761 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1762 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1763 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1764 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1765 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(%lu) is invalid on this chip\n", offset);
1766 return CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16;
1769 #define CVMX_PEXP_SLI_PKTX_SLIST_BAOFF_DBELL(offset) (CVMX_ADD_IO_SEG(0x00011F0000011800ull) + ((offset) & 31) * 16)
1771 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1772 static inline uint64_t CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(unsigned long offset)
1775 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1776 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1777 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1778 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1779 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1780 cvmx_warn("CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(%lu) is invalid on this chip\n", offset);
1781 return CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16;
1784 #define CVMX_PEXP_SLI_PKTX_SLIST_FIFO_RSIZE(offset) (CVMX_ADD_IO_SEG(0x00011F0000011C00ull) + ((offset) & 31) * 16)
1786 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1787 #define CVMX_PEXP_SLI_PKT_CNT_INT CVMX_PEXP_SLI_PKT_CNT_INT_FUNC()
1788 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_FUNC(void)
1790 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1791 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT not supported on this chip\n");
1792 return CVMX_ADD_IO_SEG(0x00011F0000011130ull);
1795 #define CVMX_PEXP_SLI_PKT_CNT_INT (CVMX_ADD_IO_SEG(0x00011F0000011130ull))
1797 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1798 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC()
1799 static inline uint64_t CVMX_PEXP_SLI_PKT_CNT_INT_ENB_FUNC(void)
1801 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1802 cvmx_warn("CVMX_PEXP_SLI_PKT_CNT_INT_ENB not supported on this chip\n");
1803 return CVMX_ADD_IO_SEG(0x00011F0000011150ull);
1806 #define CVMX_PEXP_SLI_PKT_CNT_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011150ull))
1808 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1809 #define CVMX_PEXP_SLI_PKT_CTL CVMX_PEXP_SLI_PKT_CTL_FUNC()
1810 static inline uint64_t CVMX_PEXP_SLI_PKT_CTL_FUNC(void)
1812 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1813 cvmx_warn("CVMX_PEXP_SLI_PKT_CTL not supported on this chip\n");
1814 return CVMX_ADD_IO_SEG(0x00011F0000011220ull);
1817 #define CVMX_PEXP_SLI_PKT_CTL (CVMX_ADD_IO_SEG(0x00011F0000011220ull))
1819 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1820 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC()
1821 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ES_FUNC(void)
1823 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1824 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ES not supported on this chip\n");
1825 return CVMX_ADD_IO_SEG(0x00011F00000110B0ull);
1828 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ES (CVMX_ADD_IO_SEG(0x00011F00000110B0ull))
1830 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1831 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC()
1832 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_NS_FUNC(void)
1834 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1835 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_NS not supported on this chip\n");
1836 return CVMX_ADD_IO_SEG(0x00011F00000110A0ull);
1839 #define CVMX_PEXP_SLI_PKT_DATA_OUT_NS (CVMX_ADD_IO_SEG(0x00011F00000110A0ull))
1841 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1842 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC()
1843 static inline uint64_t CVMX_PEXP_SLI_PKT_DATA_OUT_ROR_FUNC(void)
1845 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1846 cvmx_warn("CVMX_PEXP_SLI_PKT_DATA_OUT_ROR not supported on this chip\n");
1847 return CVMX_ADD_IO_SEG(0x00011F0000011090ull);
1850 #define CVMX_PEXP_SLI_PKT_DATA_OUT_ROR (CVMX_ADD_IO_SEG(0x00011F0000011090ull))
1852 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1853 #define CVMX_PEXP_SLI_PKT_DPADDR CVMX_PEXP_SLI_PKT_DPADDR_FUNC()
1854 static inline uint64_t CVMX_PEXP_SLI_PKT_DPADDR_FUNC(void)
1856 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1857 cvmx_warn("CVMX_PEXP_SLI_PKT_DPADDR not supported on this chip\n");
1858 return CVMX_ADD_IO_SEG(0x00011F0000011080ull);
1861 #define CVMX_PEXP_SLI_PKT_DPADDR (CVMX_ADD_IO_SEG(0x00011F0000011080ull))
1863 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1864 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC()
1865 static inline uint64_t CVMX_PEXP_SLI_PKT_INPUT_CONTROL_FUNC(void)
1867 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1868 cvmx_warn("CVMX_PEXP_SLI_PKT_INPUT_CONTROL not supported on this chip\n");
1869 return CVMX_ADD_IO_SEG(0x00011F0000011170ull);
1872 #define CVMX_PEXP_SLI_PKT_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000011170ull))
1874 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1875 #define CVMX_PEXP_SLI_PKT_INSTR_ENB CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC()
1876 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_ENB_FUNC(void)
1878 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1879 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_ENB not supported on this chip\n");
1880 return CVMX_ADD_IO_SEG(0x00011F0000011000ull);
1883 #define CVMX_PEXP_SLI_PKT_INSTR_ENB (CVMX_ADD_IO_SEG(0x00011F0000011000ull))
1885 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1886 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC()
1887 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE_FUNC(void)
1889 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1890 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE not supported on this chip\n");
1891 return CVMX_ADD_IO_SEG(0x00011F00000111A0ull);
1894 #define CVMX_PEXP_SLI_PKT_INSTR_RD_SIZE (CVMX_ADD_IO_SEG(0x00011F00000111A0ull))
1896 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1897 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC()
1898 static inline uint64_t CVMX_PEXP_SLI_PKT_INSTR_SIZE_FUNC(void)
1900 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1901 cvmx_warn("CVMX_PEXP_SLI_PKT_INSTR_SIZE not supported on this chip\n");
1902 return CVMX_ADD_IO_SEG(0x00011F0000011020ull);
1905 #define CVMX_PEXP_SLI_PKT_INSTR_SIZE (CVMX_ADD_IO_SEG(0x00011F0000011020ull))
1907 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1908 #define CVMX_PEXP_SLI_PKT_INT_LEVELS CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC()
1909 static inline uint64_t CVMX_PEXP_SLI_PKT_INT_LEVELS_FUNC(void)
1911 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1912 cvmx_warn("CVMX_PEXP_SLI_PKT_INT_LEVELS not supported on this chip\n");
1913 return CVMX_ADD_IO_SEG(0x00011F0000011120ull);
1916 #define CVMX_PEXP_SLI_PKT_INT_LEVELS (CVMX_ADD_IO_SEG(0x00011F0000011120ull))
1918 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1919 #define CVMX_PEXP_SLI_PKT_IN_BP CVMX_PEXP_SLI_PKT_IN_BP_FUNC()
1920 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_BP_FUNC(void)
1922 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1923 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_BP not supported on this chip\n");
1924 return CVMX_ADD_IO_SEG(0x00011F0000011210ull);
1927 #define CVMX_PEXP_SLI_PKT_IN_BP (CVMX_ADD_IO_SEG(0x00011F0000011210ull))
1929 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1930 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(unsigned long offset)
1933 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31))) ||
1934 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31))) ||
1935 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31))) ||
1936 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31))) ||
1937 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31)))))
1938 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(%lu) is invalid on this chip\n", offset);
1939 return CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16;
1942 #define CVMX_PEXP_SLI_PKT_IN_DONEX_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000012000ull) + ((offset) & 31) * 16)
1944 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1945 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC()
1946 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS_FUNC(void)
1948 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1949 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS not supported on this chip\n");
1950 return CVMX_ADD_IO_SEG(0x00011F0000011200ull);
1953 #define CVMX_PEXP_SLI_PKT_IN_INSTR_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000011200ull))
1955 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1956 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC()
1957 static inline uint64_t CVMX_PEXP_SLI_PKT_IN_PCIE_PORT_FUNC(void)
1959 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1960 cvmx_warn("CVMX_PEXP_SLI_PKT_IN_PCIE_PORT not supported on this chip\n");
1961 return CVMX_ADD_IO_SEG(0x00011F00000111B0ull);
1964 #define CVMX_PEXP_SLI_PKT_IN_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000111B0ull))
1966 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1967 #define CVMX_PEXP_SLI_PKT_IPTR CVMX_PEXP_SLI_PKT_IPTR_FUNC()
1968 static inline uint64_t CVMX_PEXP_SLI_PKT_IPTR_FUNC(void)
1970 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1971 cvmx_warn("CVMX_PEXP_SLI_PKT_IPTR not supported on this chip\n");
1972 return CVMX_ADD_IO_SEG(0x00011F0000011070ull);
1975 #define CVMX_PEXP_SLI_PKT_IPTR (CVMX_ADD_IO_SEG(0x00011F0000011070ull))
1977 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1978 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC()
1979 static inline uint64_t CVMX_PEXP_SLI_PKT_OUTPUT_WMARK_FUNC(void)
1981 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1982 cvmx_warn("CVMX_PEXP_SLI_PKT_OUTPUT_WMARK not supported on this chip\n");
1983 return CVMX_ADD_IO_SEG(0x00011F0000011180ull);
1986 #define CVMX_PEXP_SLI_PKT_OUTPUT_WMARK (CVMX_ADD_IO_SEG(0x00011F0000011180ull))
1988 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
1989 #define CVMX_PEXP_SLI_PKT_OUT_BMODE CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC()
1990 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BMODE_FUNC(void)
1992 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
1993 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BMODE not supported on this chip\n");
1994 return CVMX_ADD_IO_SEG(0x00011F00000110D0ull);
1997 #define CVMX_PEXP_SLI_PKT_OUT_BMODE (CVMX_ADD_IO_SEG(0x00011F00000110D0ull))
1999 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2000 #define CVMX_PEXP_SLI_PKT_OUT_BP_EN CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC()
2001 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_BP_EN_FUNC(void)
2003 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
2004 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_BP_EN not supported on this chip\n");
2005 return CVMX_ADD_IO_SEG(0x00011F0000011240ull);
2008 #define CVMX_PEXP_SLI_PKT_OUT_BP_EN (CVMX_ADD_IO_SEG(0x00011F0000011240ull))
2010 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2011 #define CVMX_PEXP_SLI_PKT_OUT_ENB CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC()
2012 static inline uint64_t CVMX_PEXP_SLI_PKT_OUT_ENB_FUNC(void)
2014 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2015 cvmx_warn("CVMX_PEXP_SLI_PKT_OUT_ENB not supported on this chip\n");
2016 return CVMX_ADD_IO_SEG(0x00011F0000011010ull);
2019 #define CVMX_PEXP_SLI_PKT_OUT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011010ull))
2021 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2022 #define CVMX_PEXP_SLI_PKT_PCIE_PORT CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC()
2023 static inline uint64_t CVMX_PEXP_SLI_PKT_PCIE_PORT_FUNC(void)
2025 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2026 cvmx_warn("CVMX_PEXP_SLI_PKT_PCIE_PORT not supported on this chip\n");
2027 return CVMX_ADD_IO_SEG(0x00011F00000110E0ull);
2030 #define CVMX_PEXP_SLI_PKT_PCIE_PORT (CVMX_ADD_IO_SEG(0x00011F00000110E0ull))
2032 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2033 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC()
2034 static inline uint64_t CVMX_PEXP_SLI_PKT_PORT_IN_RST_FUNC(void)
2036 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2037 cvmx_warn("CVMX_PEXP_SLI_PKT_PORT_IN_RST not supported on this chip\n");
2038 return CVMX_ADD_IO_SEG(0x00011F00000111F0ull);
2041 #define CVMX_PEXP_SLI_PKT_PORT_IN_RST (CVMX_ADD_IO_SEG(0x00011F00000111F0ull))
2043 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2044 #define CVMX_PEXP_SLI_PKT_SLIST_ES CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC()
2045 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ES_FUNC(void)
2047 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2048 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ES not supported on this chip\n");
2049 return CVMX_ADD_IO_SEG(0x00011F0000011050ull);
2052 #define CVMX_PEXP_SLI_PKT_SLIST_ES (CVMX_ADD_IO_SEG(0x00011F0000011050ull))
2054 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2055 #define CVMX_PEXP_SLI_PKT_SLIST_NS CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC()
2056 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_NS_FUNC(void)
2058 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2059 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_NS not supported on this chip\n");
2060 return CVMX_ADD_IO_SEG(0x00011F0000011040ull);
2063 #define CVMX_PEXP_SLI_PKT_SLIST_NS (CVMX_ADD_IO_SEG(0x00011F0000011040ull))
2065 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2066 #define CVMX_PEXP_SLI_PKT_SLIST_ROR CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC()
2067 static inline uint64_t CVMX_PEXP_SLI_PKT_SLIST_ROR_FUNC(void)
2069 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2070 cvmx_warn("CVMX_PEXP_SLI_PKT_SLIST_ROR not supported on this chip\n");
2071 return CVMX_ADD_IO_SEG(0x00011F0000011030ull);
2074 #define CVMX_PEXP_SLI_PKT_SLIST_ROR (CVMX_ADD_IO_SEG(0x00011F0000011030ull))
2076 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2077 #define CVMX_PEXP_SLI_PKT_TIME_INT CVMX_PEXP_SLI_PKT_TIME_INT_FUNC()
2078 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_FUNC(void)
2080 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2081 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT not supported on this chip\n");
2082 return CVMX_ADD_IO_SEG(0x00011F0000011140ull);
2085 #define CVMX_PEXP_SLI_PKT_TIME_INT (CVMX_ADD_IO_SEG(0x00011F0000011140ull))
2087 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2088 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC()
2089 static inline uint64_t CVMX_PEXP_SLI_PKT_TIME_INT_ENB_FUNC(void)
2091 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2092 cvmx_warn("CVMX_PEXP_SLI_PKT_TIME_INT_ENB not supported on this chip\n");
2093 return CVMX_ADD_IO_SEG(0x00011F0000011160ull);
2096 #define CVMX_PEXP_SLI_PKT_TIME_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000011160ull))
2098 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2099 static inline uint64_t CVMX_PEXP_SLI_PORTX_PKIND(unsigned long offset)
2102 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 31)))))
2103 cvmx_warn("CVMX_PEXP_SLI_PORTX_PKIND(%lu) is invalid on this chip\n", offset);
2104 return CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16;
2107 #define CVMX_PEXP_SLI_PORTX_PKIND(offset) (CVMX_ADD_IO_SEG(0x00011F0000010800ull) + ((offset) & 31) * 16)
2109 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2110 static inline uint64_t CVMX_PEXP_SLI_S2M_PORTX_CTL(unsigned long offset)
2113 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
2114 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
2115 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
2116 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
2117 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
2118 cvmx_warn("CVMX_PEXP_SLI_S2M_PORTX_CTL(%lu) is invalid on this chip\n", offset);
2119 return CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16;
2122 #define CVMX_PEXP_SLI_S2M_PORTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011F0000013D80ull) + ((offset) & 3) * 16)
2124 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2125 #define CVMX_PEXP_SLI_SCRATCH_1 CVMX_PEXP_SLI_SCRATCH_1_FUNC()
2126 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_1_FUNC(void)
2128 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2129 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_1 not supported on this chip\n");
2130 return CVMX_ADD_IO_SEG(0x00011F00000103C0ull);
2133 #define CVMX_PEXP_SLI_SCRATCH_1 (CVMX_ADD_IO_SEG(0x00011F00000103C0ull))
2135 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2136 #define CVMX_PEXP_SLI_SCRATCH_2 CVMX_PEXP_SLI_SCRATCH_2_FUNC()
2137 static inline uint64_t CVMX_PEXP_SLI_SCRATCH_2_FUNC(void)
2139 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2140 cvmx_warn("CVMX_PEXP_SLI_SCRATCH_2 not supported on this chip\n");
2141 return CVMX_ADD_IO_SEG(0x00011F00000103D0ull);
2144 #define CVMX_PEXP_SLI_SCRATCH_2 (CVMX_ADD_IO_SEG(0x00011F00000103D0ull))
2146 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2147 #define CVMX_PEXP_SLI_STATE1 CVMX_PEXP_SLI_STATE1_FUNC()
2148 static inline uint64_t CVMX_PEXP_SLI_STATE1_FUNC(void)
2150 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2151 cvmx_warn("CVMX_PEXP_SLI_STATE1 not supported on this chip\n");
2152 return CVMX_ADD_IO_SEG(0x00011F0000010620ull);
2155 #define CVMX_PEXP_SLI_STATE1 (CVMX_ADD_IO_SEG(0x00011F0000010620ull))
2157 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2158 #define CVMX_PEXP_SLI_STATE2 CVMX_PEXP_SLI_STATE2_FUNC()
2159 static inline uint64_t CVMX_PEXP_SLI_STATE2_FUNC(void)
2161 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2162 cvmx_warn("CVMX_PEXP_SLI_STATE2 not supported on this chip\n");
2163 return CVMX_ADD_IO_SEG(0x00011F0000010630ull);
2166 #define CVMX_PEXP_SLI_STATE2 (CVMX_ADD_IO_SEG(0x00011F0000010630ull))
2168 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2169 #define CVMX_PEXP_SLI_STATE3 CVMX_PEXP_SLI_STATE3_FUNC()
2170 static inline uint64_t CVMX_PEXP_SLI_STATE3_FUNC(void)
2172 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2173 cvmx_warn("CVMX_PEXP_SLI_STATE3 not supported on this chip\n");
2174 return CVMX_ADD_IO_SEG(0x00011F0000010640ull);
2177 #define CVMX_PEXP_SLI_STATE3 (CVMX_ADD_IO_SEG(0x00011F0000010640ull))
2179 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2180 #define CVMX_PEXP_SLI_TX_PIPE CVMX_PEXP_SLI_TX_PIPE_FUNC()
2181 static inline uint64_t CVMX_PEXP_SLI_TX_PIPE_FUNC(void)
2183 if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
2184 cvmx_warn("CVMX_PEXP_SLI_TX_PIPE not supported on this chip\n");
2185 return CVMX_ADD_IO_SEG(0x00011F0000011230ull);
2188 #define CVMX_PEXP_SLI_TX_PIPE (CVMX_ADD_IO_SEG(0x00011F0000011230ull))
2190 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
2191 #define CVMX_PEXP_SLI_WINDOW_CTL CVMX_PEXP_SLI_WINDOW_CTL_FUNC()
2192 static inline uint64_t CVMX_PEXP_SLI_WINDOW_CTL_FUNC(void)
2194 if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
2195 cvmx_warn("CVMX_PEXP_SLI_WINDOW_CTL not supported on this chip\n");
2196 return CVMX_ADD_IO_SEG(0x00011F00000102E0ull);
2199 #define CVMX_PEXP_SLI_WINDOW_CTL (CVMX_ADD_IO_SEG(0x00011F00000102E0ull))