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44 * Interface to the hardware Packet Input Processing unit.
46 * <hr>$Revision: 70030 $<hr>
50 #ifndef __CVMX_PIP_H__
51 #define __CVMX_PIP_H__
55 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
56 #include "cvmx-pip-defs.h"
58 #ifndef CVMX_DONT_INCLUDE_CONFIG
59 #include "executive-config.h"
63 #include "cvmx-helper.h"
64 #include "cvmx-helper-util.h"
71 #define CVMX_PIP_NUM_INPUT_PORTS 46
74 * Encodes the different error and exception codes
78 CVMX_PIP_L4_NO_ERR = 0ull,
79 /* 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header */
80 CVMX_PIP_L4_MAL_ERR = 1ull,
81 /* 2 = TCP/UDP checksum failure */
82 CVMX_PIP_CHK_ERR = 2ull,
83 /* 3 = TCP/UDP length check (TCP/UDP length does not match IP length) */
84 CVMX_PIP_L4_LENGTH_ERR = 3ull,
85 /* 4 = illegal TCP/UDP port (either source or dest port is zero) */
86 CVMX_PIP_BAD_PRT_ERR = 4ull,
87 /* 8 = TCP flags = FIN only */
88 CVMX_PIP_TCP_FLG8_ERR = 8ull,
89 /* 9 = TCP flags = 0 */
90 CVMX_PIP_TCP_FLG9_ERR = 9ull,
91 /* 10 = TCP flags = FIN+RST+* */
92 CVMX_PIP_TCP_FLG10_ERR = 10ull,
93 /* 11 = TCP flags = SYN+URG+* */
94 CVMX_PIP_TCP_FLG11_ERR = 11ull,
95 /* 12 = TCP flags = SYN+RST+* */
96 CVMX_PIP_TCP_FLG12_ERR = 12ull,
97 /* 13 = TCP flags = SYN+FIN+* */
98 CVMX_PIP_TCP_FLG13_ERR = 13ull
104 CVMX_PIP_IP_NO_ERR = 0ull,
105 /* 1 = not IPv4 or IPv6 */
106 CVMX_PIP_NOT_IP = 1ull,
107 /* 2 = IPv4 header checksum violation */
108 CVMX_PIP_IPV4_HDR_CHK = 2ull,
109 /* 3 = malformed (packet not long enough to cover IP hdr) */
110 CVMX_PIP_IP_MAL_HDR = 3ull,
111 /* 4 = malformed (packet not long enough to cover len in IP hdr) */
112 CVMX_PIP_IP_MAL_PKT = 4ull,
113 /* 5 = TTL / hop count equal zero */
114 CVMX_PIP_TTL_HOP = 5ull,
115 /* 6 = IPv4 options / IPv6 early extension headers */
122 * late collision (data received before collision)
123 * late collisions cannot be detected by the receiver
124 * they would appear as JAM bits which would appear as bad FCS
125 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
132 CVMX_PIP_RX_NO_ERR = 0ull,
134 CVMX_PIP_PARTIAL_ERR = 1ull, /* RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate) */
135 CVMX_PIP_JABBER_ERR = 2ull, /* RGM+SPI 2 = receive packet too large and truncated */
136 CVMX_PIP_OVER_FCS_ERR = 3ull, /* RGM 3 = max frame error (pkt len > max frame len) (with FCS error) */
137 CVMX_PIP_OVER_ERR = 4ull, /* RGM+SPI 4 = max frame error (pkt len > max frame len) */
138 CVMX_PIP_ALIGN_ERR = 5ull, /* RGM 5 = nibble error (data not byte multiple - 100M and 10M only) */
139 CVMX_PIP_UNDER_FCS_ERR = 6ull, /* RGM 6 = min frame error (pkt len < min frame len) (with FCS error) */
140 CVMX_PIP_GMX_FCS_ERR = 7ull, /* RGM 7 = FCS error */
141 CVMX_PIP_UNDER_ERR = 8ull, /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
142 CVMX_PIP_EXTEND_ERR = 9ull, /* RGM 9 = Frame carrier extend error */
143 CVMX_PIP_TERMINATE_ERR = 9ull, /* XAUI 9 = Packet was terminated with an idle cycle */
144 CVMX_PIP_LENGTH_ERR = 10ull, /* RGM 10 = length mismatch (len did not match len in L2 length/type) */
145 CVMX_PIP_DAT_ERR = 11ull, /* RGM 11 = Frame error (some or all data bits marked err) */
146 CVMX_PIP_DIP_ERR = 11ull, /* SPI 11 = DIP4 error */
147 CVMX_PIP_SKIP_ERR = 12ull, /* RGM 12 = packet was not large enough to pass the skipper - no inspection could occur */
148 CVMX_PIP_NIBBLE_ERR = 13ull, /* RGM 13 = studder error (data not repeated - 100M and 10M only) */
149 CVMX_PIP_PIP_FCS = 16L, /* RGM+SPI 16 = FCS error */
150 CVMX_PIP_PIP_SKIP_ERR = 17L, /* RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur */
151 CVMX_PIP_PIP_L2_MAL_HDR= 18L, /* RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr) */
152 CVMX_PIP_PUNY_ERR = 47L /* SGMII 47 = PUNY error (packet was 4B or less when FCS stripping is enabled) */
154 * xx = late collision (data received before collision)
155 * late collisions cannot be detected by the receiver
156 * they would appear as JAM bits which would appear as bad FCS
157 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
159 } cvmx_pip_rcv_err_t;
162 * This defines the err_code field errors in the work Q entry
166 cvmx_pip_l4_err_t l4_err;
167 cvmx_pip_ip_exc_t ip_exc;
168 cvmx_pip_rcv_err_t rcv_err;
173 * Status statistics for a port
177 uint32_t dropped_octets; /**< Inbound octets marked to be dropped by the IPD */
178 uint32_t dropped_packets; /**< Inbound packets marked to be dropped by the IPD */
179 uint32_t pci_raw_packets; /**< RAW PCI Packets received by PIP per port */
180 uint32_t octets; /**< Number of octets processed by PIP */
181 uint32_t packets; /**< Number of packets processed by PIP */
182 uint32_t multicast_packets; /**< Number of indentified L2 multicast packets.
183 Does not include broadcast packets.
184 Only includes packets whose parse mode is
186 uint32_t broadcast_packets; /**< Number of indentified L2 broadcast packets.
187 Does not include multicast packets.
188 Only includes packets whose parse mode is
190 uint32_t len_64_packets; /**< Number of 64B packets */
191 uint32_t len_65_127_packets; /**< Number of 65-127B packets */
192 uint32_t len_128_255_packets; /**< Number of 128-255B packets */
193 uint32_t len_256_511_packets; /**< Number of 256-511B packets */
194 uint32_t len_512_1023_packets; /**< Number of 512-1023B packets */
195 uint32_t len_1024_1518_packets; /**< Number of 1024-1518B packets */
196 uint32_t len_1519_max_packets; /**< Number of 1519-max packets */
197 uint32_t fcs_align_err_packets; /**< Number of packets with FCS or Align opcode errors */
198 uint32_t runt_packets; /**< Number of packets with length < min */
199 uint32_t runt_crc_packets; /**< Number of packets with length < min and FCS error */
200 uint32_t oversize_packets; /**< Number of packets with length > max */
201 uint32_t oversize_crc_packets; /**< Number of packets with length > max and FCS error */
202 uint32_t inb_packets; /**< Number of packets without GMX/SPX/PCI errors received by PIP */
203 uint64_t inb_octets; /**< Total number of octets from all packets received by PIP, including CRC */
204 uint16_t inb_errors; /**< Number of packets with GMX/SPX/PCI errors received by PIP */
205 uint32_t mcast_l2_red_packets; /**< Number of packets with L2 Multicast DMAC
206 that were dropped due to RED.
207 The HW will consider a packet to be an L2
208 multicast packet when the least-significant bit
209 of the first byte of the DMAC is set and the
210 packet is not an L2 broadcast packet.
211 Only applies when the parse mode for the packets
213 uint32_t bcast_l2_red_packets; /**< Number of packets with L2 Broadcast DMAC
214 that were dropped due to RED.
215 The HW will consider a packet to be an L2
216 broadcast packet when the 48-bit DMAC is all 1's.
217 Only applies when the parse mode for the packets
219 uint32_t mcast_l3_red_packets; /**< Number of packets with L3 Multicast Dest Address
220 that were dropped due to RED.
221 The HW considers an IPv4 packet to be multicast
222 when the most-significant nibble of the 32-bit
223 destination address is 0xE (i.e it is a class D
224 address). The HW considers an IPv6 packet to be
225 multicast when the most-significant byte of the
226 128-bit destination address is all 1's.
227 Only applies when the parse mode for the packets
228 is SKIP-TO-L2 and the packet is IP or the parse
229 mode for the packet is SKIP-TO-IP */
230 uint32_t bcast_l3_red_packets; /**< Number of packets with L3 Broadcast Dest Address
231 that were dropped due to RED.
232 The HW considers an IPv4 packet to be broadcast
233 when all bits are set in the MSB of the
234 destination address. IPv6 does not have the
235 concept of a broadcast packets.
236 Only applies when the parse mode for the packet
237 is SKIP-TO-L2 and the packet is IP or the parse
238 mode for the packet is SKIP-TO-IP */
239 } cvmx_pip_port_status_t;
243 * Definition of the PIP custom header that can be prepended
244 * to a packet by external hardware.
251 uint64_t rawfull : 1; /**< Documented as R - Set if the Packet is RAWFULL. If set,
252 this header must be the full 8 bytes */
253 uint64_t reserved0 : 5; /**< Must be zero */
254 cvmx_pip_port_parse_mode_t parse_mode : 2; /**< PIP parse mode for this packet */
255 uint64_t reserved1 : 1; /**< Must be zero */
256 uint64_t skip_len : 7; /**< Skip amount, including this header, to the beginning of the packet */
257 uint64_t grpext : 2; /**< These bits get concatenated with the
258 PKT_INST_HDR[GRP] bits, creating a 6-bit
259 GRP field. Added in pass2. */
260 uint64_t nqos : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
261 When set to 1, NQOS prevents PIP from directly using
262 PKT_INST_HDR[QOS] for the QOS value in WQE.
263 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NQOS */
264 uint64_t ngrp : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
265 When set to 1, NGPR prevents PIP from directly using
266 PKT_INST_HDR[GPR] for the GPR value in WQE.
267 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NGRP */
268 uint64_t ntt : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
269 When set to 1, NTT prevents PIP from directly using
270 PKT_INST_HDR[TT] for the TT value in WQE.
271 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTT */
272 uint64_t ntag : 1; /**< Must be 0 when PKT_INST_HDR[R] = 0.
273 When set to 1, NTAG prevents PIP from directly using
274 PKT_INST_HDR[TAG] for the TAG value in WQE.
275 When PIP_GBL_CTL[IHMSK_DIS] = 1, Octeon2 does not use NTAG */
276 uint64_t qos : 3; /**< POW input queue for this packet */
277 uint64_t grp : 4; /**< POW input group for this packet */
278 uint64_t rs : 1; /**< Flag to store this packet in the work queue entry, if possible */
279 cvmx_pow_tag_type_t tag_type : 2; /**< POW input tag type */
280 uint64_t tag : 32; /**< POW input tag */
282 } cvmx_pip_pkt_inst_hdr_t;
284 /* CSR typedefs have been moved to cvmx-pip-defs.h */
287 * Configure an ethernet input port
289 * @param port_num Port number to configure
290 * @param port_cfg Port hardware configuration
291 * @param port_tag_cfg
292 * Port POW tagging configuration
294 static inline void cvmx_pip_config_port(uint64_t port_num,
295 cvmx_pip_prt_cfgx_t port_cfg,
296 cvmx_pip_prt_tagx_t port_tag_cfg)
299 if (octeon_has_feature(OCTEON_FEATURE_PKND))
301 int interface, index, pknd;
303 interface = cvmx_helper_get_interface_num(port_num);
304 index = cvmx_helper_get_interface_index_num(port_num);
305 pknd = cvmx_helper_get_pknd(interface, index);
307 port_num = pknd; /* overload port_num with pknd */
310 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
311 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
316 * Configure the VLAN priority to QoS queue mapping.
318 * @param vlan_priority
319 * VLAN priority (0-7)
320 * @param qos QoS queue for packets matching this watcher
322 static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos)
324 if (octeon_has_feature(OCTEON_FEATURE_PKND))
326 /* FIXME for 68xx. */
330 cvmx_pip_qos_vlanx_t pip_qos_vlanx;
331 pip_qos_vlanx.u64 = 0;
332 pip_qos_vlanx.s.qos = qos;
333 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
339 * Configure the Diffserv to QoS queue mapping.
341 * @param diffserv Diffserv field value (0-63)
342 * @param qos QoS queue for packets matching this watcher
344 static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
346 if (octeon_has_feature(OCTEON_FEATURE_PKND))
348 /* FIXME for 68xx. */
352 cvmx_pip_qos_diffx_t pip_qos_diffx;
353 pip_qos_diffx.u64 = 0;
354 pip_qos_diffx.s.qos = qos;
355 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
361 * Get the status counters for a port.
363 * @param port_num Port number (ipd_port) to get statistics for.
364 * @param clear Set to 1 to clear the counters after they are read
365 * @param status Where to put the results.
367 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pip_port_status_t *status)
369 cvmx_pip_stat_ctl_t pip_stat_ctl;
370 cvmx_pip_stat0_prtx_t stat0;
371 cvmx_pip_stat1_prtx_t stat1;
372 cvmx_pip_stat2_prtx_t stat2;
373 cvmx_pip_stat3_prtx_t stat3;
374 cvmx_pip_stat4_prtx_t stat4;
375 cvmx_pip_stat5_prtx_t stat5;
376 cvmx_pip_stat6_prtx_t stat6;
377 cvmx_pip_stat7_prtx_t stat7;
378 cvmx_pip_stat8_prtx_t stat8;
379 cvmx_pip_stat9_prtx_t stat9;
380 cvmx_pip_stat10_x_t stat10;
381 cvmx_pip_stat11_x_t stat11;
382 cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
383 cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
384 cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
385 int interface = cvmx_helper_get_interface_num(port_num);
386 int index = cvmx_helper_get_interface_index_num(port_num);
388 pip_stat_ctl.u64 = 0;
389 pip_stat_ctl.s.rdclr = clear;
390 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
392 if (octeon_has_feature(OCTEON_FEATURE_PKND))
394 int pknd = cvmx_helper_get_pknd(interface, index);
396 * PIP_STAT_CTL[MODE] 0 means pkind.
398 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_X(pknd));
399 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_X(pknd));
400 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_X(pknd));
401 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_X(pknd));
402 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_X(pknd));
403 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_X(pknd));
404 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_X(pknd));
405 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_X(pknd));
406 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_X(pknd));
407 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_X(pknd));
408 stat10.u64 = cvmx_read_csr(CVMX_PIP_STAT10_X(pknd));
409 stat11.u64 = cvmx_read_csr(CVMX_PIP_STAT11_X(pknd));
415 stat0.u64 = cvmx_read_csr(CVMX_PIP_XSTAT0_PRTX(port_num));
416 stat1.u64 = cvmx_read_csr(CVMX_PIP_XSTAT1_PRTX(port_num));
417 stat2.u64 = cvmx_read_csr(CVMX_PIP_XSTAT2_PRTX(port_num));
418 stat3.u64 = cvmx_read_csr(CVMX_PIP_XSTAT3_PRTX(port_num));
419 stat4.u64 = cvmx_read_csr(CVMX_PIP_XSTAT4_PRTX(port_num));
420 stat5.u64 = cvmx_read_csr(CVMX_PIP_XSTAT5_PRTX(port_num));
421 stat6.u64 = cvmx_read_csr(CVMX_PIP_XSTAT6_PRTX(port_num));
422 stat7.u64 = cvmx_read_csr(CVMX_PIP_XSTAT7_PRTX(port_num));
423 stat8.u64 = cvmx_read_csr(CVMX_PIP_XSTAT8_PRTX(port_num));
424 stat9.u64 = cvmx_read_csr(CVMX_PIP_XSTAT9_PRTX(port_num));
425 if (OCTEON_IS_MODEL(OCTEON_CN6XXX))
427 stat10.u64 = cvmx_read_csr(CVMX_PIP_XSTAT10_PRTX(port_num));
428 stat11.u64 = cvmx_read_csr(CVMX_PIP_XSTAT11_PRTX(port_num));
433 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
434 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
435 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
436 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
437 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
438 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
439 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
440 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
441 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
442 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
443 if (OCTEON_IS_MODEL(OCTEON_CN52XX)
444 || OCTEON_IS_MODEL(OCTEON_CN56XX)
445 || OCTEON_IS_MODEL(OCTEON_CN6XXX)
446 || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
448 stat10.u64 = cvmx_read_csr(CVMX_PIP_STAT10_PRTX(port_num));
449 stat11.u64 = cvmx_read_csr(CVMX_PIP_STAT11_PRTX(port_num));
453 if (octeon_has_feature(OCTEON_FEATURE_PKND))
455 int pknd = cvmx_helper_get_pknd(interface, index);
457 pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTS_PKNDX(pknd));
458 pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTS_PKNDX(pknd));
459 pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRS_PKNDX(pknd));
463 pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
464 pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
465 pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
468 status->dropped_octets = stat0.s.drp_octs;
469 status->dropped_packets = stat0.s.drp_pkts;
470 status->octets = stat1.s.octs;
471 status->pci_raw_packets = stat2.s.raw;
472 status->packets = stat2.s.pkts;
473 status->multicast_packets = stat3.s.mcst;
474 status->broadcast_packets = stat3.s.bcst;
475 status->len_64_packets = stat4.s.h64;
476 status->len_65_127_packets = stat4.s.h65to127;
477 status->len_128_255_packets = stat5.s.h128to255;
478 status->len_256_511_packets = stat5.s.h256to511;
479 status->len_512_1023_packets = stat6.s.h512to1023;
480 status->len_1024_1518_packets = stat6.s.h1024to1518;
481 status->len_1519_max_packets = stat7.s.h1519;
482 status->fcs_align_err_packets = stat7.s.fcs;
483 status->runt_packets = stat8.s.undersz;
484 status->runt_crc_packets = stat8.s.frag;
485 status->oversize_packets = stat9.s.oversz;
486 status->oversize_crc_packets = stat9.s.jabber;
487 if (OCTEON_IS_MODEL(OCTEON_CN52XX)
488 || OCTEON_IS_MODEL(OCTEON_CN56XX)
489 || OCTEON_IS_MODEL(OCTEON_CN6XXX)
490 || OCTEON_IS_MODEL(OCTEON_CNF7XXX))
492 status->mcast_l2_red_packets = stat10.s.mcast;
493 status->bcast_l2_red_packets = stat10.s.bcast;
494 status->mcast_l3_red_packets = stat11.s.mcast;
495 status->bcast_l3_red_packets = stat11.s.bcast;
497 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
498 status->inb_octets = pip_stat_inb_octsx.s.octs;
499 status->inb_errors = pip_stat_inb_errsx.s.errs;
504 * Configure the hardware CRC engine
506 * @param interface Interface to configure (0 or 1)
507 * @param invert_result
508 * Invert the result of the CRC
509 * @param reflect Reflect
510 * @param initialization_vector
511 * CRC initialization vector
513 static inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, uint32_t initialization_vector)
515 if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
517 cvmx_pip_crc_ctlx_t config;
518 cvmx_pip_crc_ivx_t pip_crc_ivx;
521 config.s.invres = invert_result;
522 config.s.reflect = reflect;
523 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
526 pip_crc_ivx.s.iv = initialization_vector;
527 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
533 * Clear all bits in a tag mask. This should be called on
534 * startup before any calls to cvmx_pip_tag_mask_set. Each bit
535 * set in the final mask represent a byte used in the packet for
538 * @param mask_index Which tag mask to clear (0..3)
540 static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
543 cvmx_pip_tag_incx_t pip_tag_incx;
544 pip_tag_incx.u64 = 0;
545 pip_tag_incx.s.en = 0;
546 for (index=mask_index*16; index<(mask_index+1)*16; index++)
547 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
552 * Sets a range of bits in the tag mask. The tag mask is used
553 * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
554 * There are four separate masks that can be configured.
556 * @param mask_index Which tag mask to modify (0..3)
557 * @param offset Offset into the bitmask to set bits at. Use the GCC macro
558 * offsetof() to determine the offsets into packet headers.
559 * For example, offsetof(ethhdr, protocol) returns the offset
560 * of the ethernet protocol field. The bitmask selects which bytes
561 * to include the the tag, with bit offset X selecting byte at offset X
562 * from the beginning of the packet data.
563 * @param len Number of bytes to include. Usually this is the sizeof()
566 static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len)
570 cvmx_pip_tag_incx_t pip_tag_incx;
571 uint64_t index = mask_index*16 + offset/8;
572 pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
573 pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
574 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
580 * Initialize Bit Select Extractor config. Their are 8 bit positions and valids
581 * to be used when using the corresponding extractor.
583 * @param bit Bit Select Extractor to use
584 * @param pos Which position to update
585 * @param val The value to update the position with
587 static inline void cvmx_pip_set_bsel_pos(int bit, int pos, int val)
589 cvmx_pip_bsel_ext_posx_t bsel_pos;
591 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
592 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
595 if (bit < 0 || bit > 3)
597 cvmx_dprintf("ERROR: cvmx_pip_set_bsel_pos: Invalid Bit-Select Extractor (%d) passed\n", bit);
601 bsel_pos.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_POSX(bit));
605 bsel_pos.s.pos0_val = 1;
606 bsel_pos.s.pos0 = val & 0x7f;
609 bsel_pos.s.pos1_val = 1;
610 bsel_pos.s.pos1 = val & 0x7f;
613 bsel_pos.s.pos2_val = 1;
614 bsel_pos.s.pos2 = val & 0x7f;
617 bsel_pos.s.pos3_val = 1;
618 bsel_pos.s.pos3 = val & 0x7f;
621 bsel_pos.s.pos4_val = 1;
622 bsel_pos.s.pos4 = val & 0x7f;
625 bsel_pos.s.pos5_val = 1;
626 bsel_pos.s.pos5 = val & 0x7f;
629 bsel_pos.s.pos6_val = 1;
630 bsel_pos.s.pos6 = val & 0x7f;
633 bsel_pos.s.pos7_val = 1;
634 bsel_pos.s.pos7 = val & 0x7f;
637 cvmx_dprintf("Warning: cvmx_pip_set_bsel_pos: Invalid pos(%d)\n", pos);
640 cvmx_write_csr(CVMX_PIP_BSEL_EXT_POSX(bit), bsel_pos.u64);
644 * Initialize offset and skip values to use by bit select extractor.
646 * @param bit Bit Select Extractor to use
647 * @param offset Offset to add to extractor mem addr to get final address
649 * @param skip Number of bytes to skip from start of packet 0-64
651 static inline void cvmx_pip_bsel_config(int bit, int offset, int skip)
653 cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
655 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
656 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
659 bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit));
660 bsel_cfg.s.offset = offset;
661 bsel_cfg.s.skip = skip;
662 cvmx_write_csr(CVMX_PIP_BSEL_EXT_CFGX(bit), bsel_cfg.u64);
667 * Get the entry for the Bit Select Extractor Table.
668 * @param work pointer to work queue entry
669 * @return Index of the Bit Select Extractor Table
671 static inline int cvmx_pip_get_bsel_table_index(cvmx_wqe_t *work)
673 int bit = cvmx_wqe_get_port(work) & 0x3;
674 /* Get the Bit select table index. */
677 cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
678 cvmx_pip_bsel_ext_posx_t bsel_pos;
680 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
681 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
684 bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit));
685 bsel_pos.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_POSX(bit));
687 for (y = 0; y < 8; y++)
689 char *ptr = (char *)cvmx_phys_to_ptr(work->packet_ptr.s.addr);
693 ptr += bsel_cfg.s.skip;
697 ptr += (bsel_pos.s.pos0 >> 3);
698 bit_loc = 7 - (bsel_pos.s.pos0 & 0x3);
701 ptr += (bsel_pos.s.pos1 >> 3);
702 bit_loc = 7 - (bsel_pos.s.pos1 & 0x3);
705 ptr += (bsel_pos.s.pos2 >> 3);
706 bit_loc = 7 - (bsel_pos.s.pos2 & 0x3);
709 ptr += (bsel_pos.s.pos3 >> 3);
710 bit_loc = 7 - (bsel_pos.s.pos3 & 0x3);
713 ptr += (bsel_pos.s.pos4 >> 3);
714 bit_loc = 7 - (bsel_pos.s.pos4 & 0x3);
717 ptr += (bsel_pos.s.pos5 >> 3);
718 bit_loc = 7 - (bsel_pos.s.pos5 & 0x3);
721 ptr += (bsel_pos.s.pos6 >> 3);
722 bit_loc = 7 - (bsel_pos.s.pos6 & 0x3);
725 ptr += (bsel_pos.s.pos7 >> 3);
726 bit_loc = 7 - (bsel_pos.s.pos7 & 0x3);
729 bit = (*ptr >> bit_loc) & 1;
732 index += bsel_cfg.s.offset;
737 static inline int cvmx_pip_get_bsel_qos(cvmx_wqe_t *work)
739 int index = cvmx_pip_get_bsel_table_index(work);
740 cvmx_pip_bsel_tbl_entx_t bsel_tbl;
742 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
743 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
746 bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
748 return bsel_tbl.s.qos;
751 static inline int cvmx_pip_get_bsel_grp(cvmx_wqe_t *work)
753 int index = cvmx_pip_get_bsel_table_index(work);
754 cvmx_pip_bsel_tbl_entx_t bsel_tbl;
756 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
757 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
760 bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
762 return bsel_tbl.s.grp;
765 static inline int cvmx_pip_get_bsel_tt(cvmx_wqe_t *work)
767 int index = cvmx_pip_get_bsel_table_index(work);
768 cvmx_pip_bsel_tbl_entx_t bsel_tbl;
770 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
771 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
774 bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
776 return bsel_tbl.s.tt;
779 static inline int cvmx_pip_get_bsel_tag(cvmx_wqe_t *work)
781 int index = cvmx_pip_get_bsel_table_index(work);
782 int port = cvmx_wqe_get_port(work);
783 int bit = port & 0x3;
785 cvmx_pip_bsel_tbl_entx_t bsel_tbl;
786 cvmx_pip_bsel_ext_cfgx_t bsel_cfg;
787 cvmx_pip_prt_tagx_t prt_tag;
789 /* The bit select extractor is available in CN61XX and CN68XX pass2.0 onwards. */
790 if (!octeon_has_feature(OCTEON_FEATURE_BIT_EXTRACTOR))
793 bsel_tbl.u64 = cvmx_read_csr(CVMX_PIP_BSEL_TBL_ENTX(index));
794 bsel_cfg.u64 = cvmx_read_csr(CVMX_PIP_BSEL_EXT_CFGX(bit));
796 prt_tag.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
797 if (prt_tag.s.inc_prt_flag == 0)
798 upper_tag = bsel_cfg.s.upper_tag;
799 return (bsel_tbl.s.tag | ((bsel_cfg.s.tag << 8) & 0xff00) | ((upper_tag << 16) & 0xffff0000));
806 #endif /* __CVMX_PIP_H__ */