1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_SPX0_DEFS_H__
53 #define __CVMX_SPX0_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
57 static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
59 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
60 cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x0001180090000388ull);
64 #define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
68 static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
70 if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
71 cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001180090000380ull);
75 #define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
79 * cvmx_spx0_pll_bw_ctl
81 union cvmx_spx0_pll_bw_ctl {
83 struct cvmx_spx0_pll_bw_ctl_s {
84 #ifdef __BIG_ENDIAN_BITFIELD
85 uint64_t reserved_5_63 : 59;
86 uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */
89 uint64_t reserved_5_63 : 59;
92 struct cvmx_spx0_pll_bw_ctl_s cn38xx;
93 struct cvmx_spx0_pll_bw_ctl_s cn38xxp2;
95 typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;
98 * cvmx_spx0_pll_setting
100 union cvmx_spx0_pll_setting {
102 struct cvmx_spx0_pll_setting_s {
103 #ifdef __BIG_ENDIAN_BITFIELD
104 uint64_t reserved_17_63 : 47;
105 uint64_t setting : 17; /**< Core PLL setting */
107 uint64_t setting : 17;
108 uint64_t reserved_17_63 : 47;
111 struct cvmx_spx0_pll_setting_s cn38xx;
112 struct cvmx_spx0_pll_setting_s cn38xxp2;
114 typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t;