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47 * <hr>$Revision: 41586 $<hr>
50 #ifndef __CVMX_SRIO_H__
51 #define __CVMX_SRIO_H__
58 * Enumeration of the type of operations that can be performed
59 * by a mapped write operation.
63 CVMX_SRIO_WRITE_MODE_NWRITE = 0, /**< Only create NWrite operations */
64 CVMX_SRIO_WRITE_MODE_NWRITE_RESP = 1, /**< Create NWrite with response */
65 CVMX_SRIO_WRITE_MODE_AUTO = 2, /**< Intelligently breaks writes into multiple transactions based on alignment */
66 CVMX_SRIO_WRITE_MODE_AUTO_RESP = 3, /**< CVMX_SRIO_WRITE_MODE_WRITE followed with a response */
67 CVMX_SRIO_WRITE_MODE_MAINTENANCE = 6, /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_write32() instead */
68 CVMX_SRIO_WRITE_MODE_PORT = 7 /**< Port Write? */
69 } cvmx_srio_write_mode_t;
72 * Enumeration of the type of operations that can be performed
73 * by a mapped read operation.
77 CVMX_SRIO_READ_MODE_NORMAL = 0, /**< Perform a normal read */
78 CVMX_SRIO_READ_MODE_ATOMIC_SET = 2, /**< Atomically sets bits in data on remote device */
79 CVMX_SRIO_READ_MODE_ATOMIC_CLEAR = 3, /**< Atomically clears bits in data on remote device */
80 CVMX_SRIO_READ_MODE_ATOMIC_INCREMENT = 4,/**< Atomically increments data on remote device */
81 CVMX_SRIO_READ_MODE_ATOMIC_DECREMENT = 5,/**< Atomically decrements data on remote device */
82 CVMX_SRIO_READ_MODE_MAINTENANCE = 6 /**< Create a MAINTENANCE transaction. Use cvmx_srio_config_read32() instead */
83 } cvmx_srio_read_mode_t;
86 * Initialization flags for SRIO
90 CVMX_SRIO_INITIALIZE_DEBUG = 1,
91 } cvmx_srio_initialize_flags_t;
94 * The possible results from a doorbell operation
98 CVMX_SRIO_DOORBELL_DONE, /**< The doorbell is complete */
99 CVMX_SRIO_DOORBELL_NONE, /**< There wasn't an outstanding doorbell */
100 CVMX_SRIO_DOORBELL_BUSY, /**< The doorbell is still processing */
101 CVMX_SRIO_DOORBELL_RETRY, /**< The doorbell needs to be retried */
102 CVMX_SRIO_DOORBELL_ERROR, /**< The doorbell failed with an error */
103 CVMX_SRIO_DOORBELL_TMOUT /**< The doorbell failed due to timeout */
104 } cvmx_srio_doorbell_status_t;
107 * This structure represents the SRIO header received from SRIO on
108 * the top of every received message. This header passes through
109 * IPD/PIP unmodified.
118 #ifdef __BIG_ENDIAN_BITFIELD
119 uint64_t prio : 2; /**< The sRIO prio (priority) field in the
120 first sRIO message segment received for the
122 uint64_t tt : 1; /**< When set, indicates that the first sRIO
123 message segment received for the message had
124 16-bit source and destination ID's. When
125 clear, indicates 8-bit ID were present. */
126 uint64_t dis : 1; /**< When set, indicates that the destination
127 ID in the first sRIO message segment received
128 for the message matched the 63xx's secondary
129 ID. When clear, indicates that the destination
130 ID in the first sRIO message segment
131 received for the message matched the 63xx's
132 primary ID. Note that the full destination
133 ID in the received sRIO message can be
134 determined via the combination of
135 WORD0[DIS] in the sRIO inbound message
136 header and WORD1[iprt] in the work queue
137 entry created by PIP/IPD. */
138 uint64_t ssize : 4; /**< The RIO ssize (standard message packet data
139 size) field used for the message. */
140 uint64_t sid : 16; /**< The source ID in the first sRIO message
141 segment received for the message. When TT is
142 clear, the most-significant 8 bits are zero. */
143 uint64_t xmbox : 4; /**< The RIO xmbox (recipient mailbox extension)
144 field in the first sRIO message segment
145 received for the message. Always zero for
146 multi-segment messages. */
147 uint64_t mbox : 2; /**< The RIO mbox (recipient mailbox) field in
148 the first sRIO message segment received for
150 uint64_t letter : 2; /**< The RIO letter (slot within a mailbox)
151 field in the first sRIO message segment
152 received for the message. */
153 uint64_t seq : 32; /**< A sequence number. Whenever the OCTEON
154 63xx sRIO hardware accepts the first sRIO
155 segment of either a message or doorbell, it
156 samples the current value of a counter
157 register and increments the counter
158 register. SEQ is the value sampled for the
159 message. The counter increments once per
160 message/doorbell. SEQ can be used to
161 determine the relative order of
162 packets/doorbells. Note that the SEQ-implied
163 order may differ from the order that the
164 WQE's are received by software for a number
165 of reasons, including the fact that the WQE
166 is not created until the end of the message,
167 while SEQ is sampled when the first segment. */
186 #ifdef __BIG_ENDIAN_BITFIELD
187 uint64_t r : 1; /**< When set, WORD1[R]/PKT_INST_HDR[R] selects
188 either RAWFULL or RAWSCHED special PIP
189 instruction form. WORD1[R] may commonly be
190 set so that WORD1[QOS,GRP] will be directly
191 used by the PIP hardware. */
192 uint64_t reserved_62_58 : 5;
193 uint64_t pm : 2; /**< WORD1[PM]/PKT_INST_HDR[PM] selects the PIP
194 parse mode (uninterpreted, skip-to-L2,
195 skip-to-IP), and chooses between
196 RAWFULL/RAWSCHED when WORD1[R] is set. */
197 uint64_t reserved_55 : 1;
198 uint64_t sl : 7; /**< WORD1[SL]/PKT_INST_HDR[SL] selects the
199 skip II length. WORD1[SL] may typically be
200 set to 8 (or larger) so that PIP skips this
202 uint64_t reserved_47_46 : 2;
203 uint64_t nqos : 1; /**< WORD1[NQOS] must not be set when WORD1[R]
204 is clear and PIP interprets WORD1 as a
205 PKT_INST_HDR. When set, WORD1[NQOS]/PKT_INST_HDR[NQOS]
206 prevents PIP from directly using
207 WORD1[QOS]/PKT_INST_HDR[QOS] for the QOS
208 value in the work queue entry created by
209 PIP. WORD1[NQOS] may commonly be clear so
210 that WORD1[QOS] will be directly used by the
211 PIP hardware. PKT_INST_HDR[NQOS] is new to
212 63xx - this functionality did not exist in
214 uint64_t ngrp : 1; /**< WORD1[NGRP] must not be set when WORD1[R]
215 is clear and PIP interprets WORD1 as a
216 PKT_INST_HDR. When set, WORD1[NGRP]/PKT_INST_HDR[NGRP]
217 prevents PIP from directly using
218 WORD1[GRP]/PKT_INST_HDR[GRP] for the GRP
219 value in the work queue entry created by
220 PIP. WORD1[NGRP] may commonly be clear so
221 that WORD1[GRP] will be directly used by the
222 PIP hardware. PKT_INST_HDR[NGRP] is new to
223 63xx - this functionality did not exist in
225 uint64_t ntt : 1; /**< WORD1[NTT] must not be set when WORD1[R]
226 is clear and PIP interprets WORD1 as a
227 PKT_INST_HDR. When set, WORD1[NTT]/PKT_INST_HDR[NTT]
228 prevents PIP from directly using
229 WORD1[TT]/PKT_INST_HDR[TT] for the TT value
230 in the work queue entry created by PIP.
231 PKT_INST_HDR[NTT] is new to 63xx - this
232 functionality did not exist in prior OCTEON's. */
233 uint64_t ntag : 1; /**< WORD1[NTAG] must not be set when WORD1[R]
234 is clear and PIP interprets WORD1 as a
235 PKT_INST_HDR. When set, WORD1[NTAG]/PKT_INST_HDR[NTAG]
236 prevents PIP from directly using
237 WORD1[TAG]/PKT_INST_HDR[TAG] for the TAG
238 value in the work queue entry created by PIP.
239 PKT_INST_HDR[NTAG] is new to 63xx - this
240 functionality did not exist in prior OCTEON's. */
241 uint64_t qos : 3; /**< Created by the hardware from an entry in a
242 256-entry table. The 8-bit value
243 WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the
244 table entry. When WORD1[R] is set and WORD1[NQOS]
245 is clear, WORD1[QOS] becomes the QOS value
246 in the work queue entry created by PIP. The
247 QOS value in the work queue entry determines
248 the priority that SSO/POW will schedule the
249 work, and can also control how/if the sRIO
250 message gets dropped by PIP/IPD. The 256-entry
251 table is unique to each sRIO core, but
252 shared by the two controllers associated
253 with the sRIO core. */
254 uint64_t grp : 4; /**< Created by the hardware from an entry in a
255 256-entry table. The 8-bit value
256 WORD0[PRIO,TT,DIS,MBOX,LETTER] selects the
257 table entry. When WORD1[R] is set and WORD1[NGRP]
258 is clear, WORD1[GRP] becomes the GRP value
259 in the work queue entry created by PIP. The
260 GRP value in the work queue entry can direct
261 the work to particular cores or particular
262 groups of cores. The 256-entry table is
263 unique to each sRIO core, but shared by the
264 two controllers associated with the sRIO core. */
265 uint64_t rs : 1; /**< In some configurations, enables the sRIO
266 message to be buffered solely in the work
267 queue entry, and not otherwise in L2/DRAM. */
268 uint64_t tt : 2; /**< When WORD1[R] is set and WORD1[NTT] is
269 clear, WORD1[TT]/PKT_INST_HDR[TT] becomes
270 the TT value in the work queue entry created
271 by PIP. The TT and TAG values in the work
272 queue entry determine the scheduling/synchronization
273 constraints for the work (no constraints,
274 tag order, atomic tag order). */
275 uint64_t tag : 32; /**< Created by the hardware from a CSR
276 associated with the sRIO inbound message
277 controller. When WORD1[R] is set and WORD1[NTAG]
278 is clear, WORD1[TAG]/PKT_INST_HDR[TAG]
279 becomes the TAG value in the work queue
280 entry created by PIP. The TT and TAG values
281 in the work queue entry determine the
282 scheduling/synchronization constraints for
283 the work (no constraints, tag order, atomic
295 uint64_t reserved_47_46 : 2;
297 uint64_t reserved_55 : 1;
299 uint64_t reserved_62_58 : 5;
304 } cvmx_srio_rx_message_header_t;
307 * This structure represents the SRIO header required on the front
308 * of PKO packets destine for SRIO message queues.
315 #ifdef __BIG_ENDIAN_BITFIELD
316 uint64_t prio : 2; /**< The sRIO prio (priority) field for all
317 segments in the message. */
318 uint64_t tt : 1; /**< When set, the sRIO message segments use a
319 16-bit source and destination ID for all the
320 segments in the message. When clear, the
321 message segments use an 8-bit ID. */
322 uint64_t sis : 1; /**< When set, the sRIO message segments use the
323 63xx's secondary ID as the source ID. When
324 clear, the sRIO message segments use the
325 primary ID as the source ID. */
326 uint64_t ssize : 4; /**< The RIO ssize (standard message segment
327 data size) field used for the message. */
328 uint64_t did : 16; /**< The destination ID in the sRIO message
329 segments of the message. When TT is clear,
330 the most-significant 8 bits must be zero. */
331 uint64_t xmbox : 4; /**< The RIO xmbox (recipient mailbox extension)
332 field in the sRIO message segment for a
333 single-segment message. Must be zero for
334 multi-segment messages. */
335 uint64_t mbox : 2; /**< The RIO mbox (recipient mailbox) field in
336 the sRIO message segments of the message. */
337 uint64_t letter : 2; /**< The RIO letter (slot within mailbox) field
338 in the sRIO message segments of the message
339 when LNS is clear. When LNS is set, this
340 LETTER field is not used and must be zero. */
341 uint64_t reserved_31_2 : 30;
342 uint64_t lns : 1; /**< When set, the outbound message controller
343 will dynamically selects an sRIO letter
344 field for the message (based on LETTER_SP or
345 LETTER_MP - see appendix A), and the LETTER
346 field in this sRIO outbound message
347 descriptor is unused. When clear, the LETTER
348 field in this sRIO outbound message
349 descriptor selects the sRIO letter used for
351 uint64_t intr : 1; /**< When set, the outbound message controller
352 will set an interrupt bit after all sRIO
353 segments of the message receive a message
354 DONE response. If the message transfer has
355 errors, the interrupt bit is not set (but
360 uint64_t reserved_31_2 : 30;
371 } cvmx_srio_tx_message_header_t;
374 * Reset SRIO to link partner
376 * @param srio_port SRIO port to initialize
378 * @return Zero on success
380 int cvmx_srio_link_rst(int srio_port);
383 * Initialize a SRIO port for use.
385 * @param srio_port SRIO port to initialize
386 * @param flags Optional flags
388 * @return Zero on success
390 int cvmx_srio_initialize(int srio_port, cvmx_srio_initialize_flags_t flags);
393 * Read 32bits from a Device's config space
395 * @param srio_port SRIO port the device is on
397 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
398 * @param destid RapidIO device ID, or -1 for the local Octeon.
399 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
400 * if transactions should use 8bit device IDs.
401 * @param hopcount Number of hops to the remote device. Use 0 for the local Octeon.
402 * @param offset Offset in config space. This must be a multiple of 32 bits.
403 * @param result Result of the read. This will be unmodified on failure.
405 * @return Zero on success, negative on failure.
407 int cvmx_srio_config_read32(int srio_port, int srcid_index, int destid,
408 int is16bit, uint8_t hopcount, uint32_t offset,
412 * Write 32bits to a Device's config space
414 * @param srio_port SRIO port the device is on
416 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
417 * @param destid RapidIO device ID, or -1 for the local Octeon.
418 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
419 * if transactions should use 8bit device IDs.
420 * @param hopcount Number of hops to the remote device. Use 0 for the local Octeon.
421 * @param offset Offset in config space. This must be a multiple of 32 bits.
422 * @param data Data to write.
424 * @return Zero on success, negative on failure.
426 int cvmx_srio_config_write32(int srio_port, int srcid_index, int destid,
427 int is16bit, uint8_t hopcount, uint32_t offset,
431 * Send a RapidIO doorbell to a remote device
433 * @param srio_port SRIO port the device is on
435 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
436 * @param destid RapidIO device ID.
437 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
438 * if transactions should use 8bit device IDs.
439 * @param priority Doorbell priority (0-3)
440 * @param data Data for doorbell.
442 * @return Zero on success, negative on failure.
444 int cvmx_srio_send_doorbell(int srio_port, int srcid_index, int destid,
445 int is16bit, int priority, uint16_t data);
448 * Get the status of the last doorbell sent. If the dooorbell
449 * hardware is done, then the status is cleared to get ready for
450 * the next doorbell (or retry).
452 * @param srio_port SRIO port to check doorbell on
454 * @return Doorbell status
456 cvmx_srio_doorbell_status_t cvmx_srio_send_doorbell_status(int srio_port);
459 * Read a received doorbell and report data about it.
461 * @param srio_port SRIO port to check for the received doorbell
462 * @param destid_index
463 * Which Octeon destination ID was the doorbell for
464 * @param sequence_num
465 * Sequence number of doorbell (32bits)
466 * @param srcid RapidIO source ID of the doorbell sender
467 * @param priority Priority of the doorbell (0-3)
468 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
469 * if transactions should use 8bit device IDs.
470 * @param data Data in the doorbell (16 bits)
472 * @return Doorbell status. Either DONE, NONE, or ERROR.
474 cvmx_srio_doorbell_status_t cvmx_srio_receive_doorbell(int srio_port,
475 int *destid_index, uint32_t *sequence_num, int *srcid, int *priority,
476 int *is16bit, uint16_t *data);
479 * Receive a packet from the Soft Packet FIFO (SPF).
481 * @param srio_port SRIO port to read the packet from.
482 * @param buffer Buffer to receive the packet.
483 * @param buffer_length
484 * Length of the buffer in bytes.
486 * @return Returns the length of the packet read. Negative on failure.
487 * Zero if no packets are available.
489 int cvmx_srio_receive_spf(int srio_port, void *buffer, int buffer_length);
492 * Map a remote device's memory region into Octeon's physical
493 * address area. The caller can then map this into a core using
496 * @param srio_port SRIO port to map the device on
497 * @param write_op Type of operation to perform on a write to the device.
498 * Normally should be CVMX_SRIO_WRITE_MODE_AUTO.
499 * @param write_priority
500 * SRIO priority of writes (0-3)
501 * @param read_op Type of operation to perform on reads to the device.
502 * Normally should be CVMX_SRIO_READ_MODE_NORMAL.
503 * @param read_priority
504 * SRIO priority of reads (0-3)
506 * Which SRIO source ID to use. 0 = Primary, 1 = Secondary
507 * @param destid RapidIO device ID.
508 * @param is16bit Non zero if the transactions should use 16bit device IDs. Zero
509 * if transactions should use 8bit device IDs.
510 * @param base Device base address to start the mapping
511 * @param size Size of the mapping in bytes
513 * @return Octeon 64bit physical address that accesses the remote device,
514 * or zero on failure.
516 uint64_t cvmx_srio_physical_map(int srio_port, cvmx_srio_write_mode_t write_op,
517 int write_priority, cvmx_srio_read_mode_t read_op, int read_priority,
518 int srcid_index, int destid, int is16bit, uint64_t base, uint64_t size);
521 * Unmap a physical address window created by cvmx_srio_phys_map().
523 * @param physical_address
524 * Physical address returned by cvmx_srio_phys_map().
525 * @param size Size used on original call.
527 * @return Zero on success, negative on failure.
529 int cvmx_srio_physical_unmap(uint64_t physical_address, uint64_t size);
531 #ifdef CVMX_ENABLE_PKO_FUNCTIONS
533 * fill out outbound message descriptor
535 * @param buf_ptr pointer to a buffer pointer. the buffer pointer points
536 * to a chain of buffers that hold an outbound srio packet.
537 * the packet can take the format of (1) a pip/ipd inbound
538 * message or (2) an application-generated outbound message
539 * @param desc_ptr pointer to an outbound message descriptor. should be null
540 * if *buf_ptr is in the format (1)
542 * @return 0 on success; negative of failure.
544 int cvmx_srio_omsg_desc (uint64_t port, cvmx_buf_ptr_t *buf_ptr,
545 cvmx_srio_tx_message_header_t *desc_ptr);