1 /***********************license start***************
2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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7 * modification, are permitted provided that the following conditions are
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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19 * its contributors may be used to endorse or promote products
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38 ***********************license end**************************************/
42 * cvmx-sriomaintx-defs.h
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_SRIOMAINTX_DEFS_H__
53 #define __CVMX_SRIOMAINTX_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_ID(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
61 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
62 return 0x0000000000000008ull;
65 #define CVMX_SRIOMAINTX_ASMBLY_ID(block_id) (0x0000000000000008ull)
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_SRIOMAINTX_ASMBLY_INFO(unsigned long block_id)
71 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
73 cvmx_warn("CVMX_SRIOMAINTX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
74 return 0x000000000000000Cull;
77 #define CVMX_SRIOMAINTX_ASMBLY_INFO(block_id) (0x000000000000000Cull)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 static inline uint64_t CVMX_SRIOMAINTX_BAR1_IDXX(unsigned long offset, unsigned long block_id)
83 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
85 cvmx_warn("CVMX_SRIOMAINTX_BAR1_IDXX(%lu,%lu) is invalid on this chip\n", offset, block_id);
86 return 0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4;
89 #define CVMX_SRIOMAINTX_BAR1_IDXX(offset, block_id) (0x0000000000200010ull + (((offset) & 15) + ((block_id) & 3) * 0x0ull) * 4)
91 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92 static inline uint64_t CVMX_SRIOMAINTX_BELL_STATUS(unsigned long block_id)
95 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
97 cvmx_warn("CVMX_SRIOMAINTX_BELL_STATUS(%lu) is invalid on this chip\n", block_id);
98 return 0x0000000000200080ull;
101 #define CVMX_SRIOMAINTX_BELL_STATUS(block_id) (0x0000000000200080ull)
103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104 static inline uint64_t CVMX_SRIOMAINTX_COMP_TAG(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
109 cvmx_warn("CVMX_SRIOMAINTX_COMP_TAG(%lu) is invalid on this chip\n", block_id);
110 return 0x000000000000006Cull;
113 #define CVMX_SRIOMAINTX_COMP_TAG(block_id) (0x000000000000006Cull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_SRIOMAINTX_CORE_ENABLES(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
121 cvmx_warn("CVMX_SRIOMAINTX_CORE_ENABLES(%lu) is invalid on this chip\n", block_id);
122 return 0x0000000000200070ull;
125 #define CVMX_SRIOMAINTX_CORE_ENABLES(block_id) (0x0000000000200070ull)
127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
128 static inline uint64_t CVMX_SRIOMAINTX_DEV_ID(unsigned long block_id)
131 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
132 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
133 cvmx_warn("CVMX_SRIOMAINTX_DEV_ID(%lu) is invalid on this chip\n", block_id);
134 return 0x0000000000000000ull;
137 #define CVMX_SRIOMAINTX_DEV_ID(block_id) (0x0000000000000000ull)
139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
140 static inline uint64_t CVMX_SRIOMAINTX_DEV_REV(unsigned long block_id)
143 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
145 cvmx_warn("CVMX_SRIOMAINTX_DEV_REV(%lu) is invalid on this chip\n", block_id);
146 return 0x0000000000000004ull;
149 #define CVMX_SRIOMAINTX_DEV_REV(block_id) (0x0000000000000004ull)
151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
152 static inline uint64_t CVMX_SRIOMAINTX_DST_OPS(unsigned long block_id)
155 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
156 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
157 cvmx_warn("CVMX_SRIOMAINTX_DST_OPS(%lu) is invalid on this chip\n", block_id);
158 return 0x000000000000001Cull;
161 #define CVMX_SRIOMAINTX_DST_OPS(block_id) (0x000000000000001Cull)
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 static inline uint64_t CVMX_SRIOMAINTX_ERB_ATTR_CAPT(unsigned long block_id)
167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
169 cvmx_warn("CVMX_SRIOMAINTX_ERB_ATTR_CAPT(%lu) is invalid on this chip\n", block_id);
170 return 0x0000000000002048ull;
173 #define CVMX_SRIOMAINTX_ERB_ATTR_CAPT(block_id) (0x0000000000002048ull)
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_DET(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
181 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_DET(%lu) is invalid on this chip\n", block_id);
182 return 0x0000000000002040ull;
185 #define CVMX_SRIOMAINTX_ERB_ERR_DET(block_id) (0x0000000000002040ull)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
192 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
193 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE(%lu) is invalid on this chip\n", block_id);
194 return 0x0000000000002068ull;
197 #define CVMX_SRIOMAINTX_ERB_ERR_RATE(block_id) (0x0000000000002068ull)
199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
200 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(unsigned long block_id)
203 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
205 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(%lu) is invalid on this chip\n", block_id);
206 return 0x0000000000002044ull;
209 #define CVMX_SRIOMAINTX_ERB_ERR_RATE_EN(block_id) (0x0000000000002044ull)
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 static inline uint64_t CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(unsigned long block_id)
215 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
216 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
217 cvmx_warn("CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(%lu) is invalid on this chip\n", block_id);
218 return 0x000000000000206Cull;
221 #define CVMX_SRIOMAINTX_ERB_ERR_RATE_THR(block_id) (0x000000000000206Cull)
223 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
224 static inline uint64_t CVMX_SRIOMAINTX_ERB_HDR(unsigned long block_id)
227 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
229 cvmx_warn("CVMX_SRIOMAINTX_ERB_HDR(%lu) is invalid on this chip\n", block_id);
230 return 0x0000000000002000ull;
233 #define CVMX_SRIOMAINTX_ERB_HDR(block_id) (0x0000000000002000ull)
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
236 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
241 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(%lu) is invalid on this chip\n", block_id);
242 return 0x0000000000002010ull;
245 #define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_H(block_id) (0x0000000000002010ull)
247 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
248 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(unsigned long block_id)
251 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
252 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
253 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(%lu) is invalid on this chip\n", block_id);
254 return 0x0000000000002014ull;
257 #define CVMX_SRIOMAINTX_ERB_LT_ADDR_CAPT_L(block_id) (0x0000000000002014ull)
259 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
260 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(unsigned long block_id)
263 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
264 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
265 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(%lu) is invalid on this chip\n", block_id);
266 return 0x000000000000201Cull;
269 #define CVMX_SRIOMAINTX_ERB_LT_CTRL_CAPT(block_id) (0x000000000000201Cull)
271 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
272 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID(unsigned long block_id)
275 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
276 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
277 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID(%lu) is invalid on this chip\n", block_id);
278 return 0x0000000000002028ull;
281 #define CVMX_SRIOMAINTX_ERB_LT_DEV_ID(block_id) (0x0000000000002028ull)
283 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
284 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(unsigned long block_id)
287 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
288 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
289 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(%lu) is invalid on this chip\n", block_id);
290 return 0x0000000000002018ull;
293 #define CVMX_SRIOMAINTX_ERB_LT_DEV_ID_CAPT(block_id) (0x0000000000002018ull)
295 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
296 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_DET(unsigned long block_id)
299 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
301 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_DET(%lu) is invalid on this chip\n", block_id);
302 return 0x0000000000002008ull;
305 #define CVMX_SRIOMAINTX_ERB_LT_ERR_DET(block_id) (0x0000000000002008ull)
307 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
308 static inline uint64_t CVMX_SRIOMAINTX_ERB_LT_ERR_EN(unsigned long block_id)
311 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
312 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
313 cvmx_warn("CVMX_SRIOMAINTX_ERB_LT_ERR_EN(%lu) is invalid on this chip\n", block_id);
314 return 0x000000000000200Cull;
317 #define CVMX_SRIOMAINTX_ERB_LT_ERR_EN(block_id) (0x000000000000200Cull)
319 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
320 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(unsigned long block_id)
323 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
324 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
325 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(%lu) is invalid on this chip\n", block_id);
326 return 0x0000000000002050ull;
329 #define CVMX_SRIOMAINTX_ERB_PACK_CAPT_1(block_id) (0x0000000000002050ull)
331 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
332 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(unsigned long block_id)
335 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
336 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
337 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(%lu) is invalid on this chip\n", block_id);
338 return 0x0000000000002054ull;
341 #define CVMX_SRIOMAINTX_ERB_PACK_CAPT_2(block_id) (0x0000000000002054ull)
343 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
344 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(unsigned long block_id)
347 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
348 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
349 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(%lu) is invalid on this chip\n", block_id);
350 return 0x0000000000002058ull;
353 #define CVMX_SRIOMAINTX_ERB_PACK_CAPT_3(block_id) (0x0000000000002058ull)
355 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
356 static inline uint64_t CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(unsigned long block_id)
359 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
361 cvmx_warn("CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(%lu) is invalid on this chip\n", block_id);
362 return 0x000000000000204Cull;
365 #define CVMX_SRIOMAINTX_ERB_PACK_SYM_CAPT(block_id) (0x000000000000204Cull)
367 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
368 static inline uint64_t CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(unsigned long block_id)
371 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
372 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
373 cvmx_warn("CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(%lu) is invalid on this chip\n", block_id);
374 return 0x0000000000000068ull;
377 #define CVMX_SRIOMAINTX_HB_DEV_ID_LOCK(block_id) (0x0000000000000068ull)
379 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
380 static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(unsigned long block_id)
383 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
384 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
385 cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(%lu) is invalid on this chip\n", block_id);
386 return 0x0000000000102000ull;
389 #define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG(block_id) (0x0000000000102000ull)
391 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
392 static inline uint64_t CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(unsigned long block_id)
395 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
396 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
397 cvmx_warn("CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(%lu) is invalid on this chip\n", block_id);
398 return 0x0000000000102004ull;
401 #define CVMX_SRIOMAINTX_IR_BUFFER_CONFIG2(block_id) (0x0000000000102004ull)
403 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
404 static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(unsigned long block_id)
407 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
408 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
409 cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
410 return 0x0000000000107028ull;
413 #define CVMX_SRIOMAINTX_IR_PD_PHY_CTRL(block_id) (0x0000000000107028ull)
415 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
416 static inline uint64_t CVMX_SRIOMAINTX_IR_PD_PHY_STAT(unsigned long block_id)
419 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
420 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
421 cvmx_warn("CVMX_SRIOMAINTX_IR_PD_PHY_STAT(%lu) is invalid on this chip\n", block_id);
422 return 0x000000000010702Cull;
425 #define CVMX_SRIOMAINTX_IR_PD_PHY_STAT(block_id) (0x000000000010702Cull)
427 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
428 static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(unsigned long block_id)
431 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
432 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
433 cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(%lu) is invalid on this chip\n", block_id);
434 return 0x0000000000107020ull;
437 #define CVMX_SRIOMAINTX_IR_PI_PHY_CTRL(block_id) (0x0000000000107020ull)
439 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
440 static inline uint64_t CVMX_SRIOMAINTX_IR_PI_PHY_STAT(unsigned long block_id)
443 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
444 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
445 cvmx_warn("CVMX_SRIOMAINTX_IR_PI_PHY_STAT(%lu) is invalid on this chip\n", block_id);
446 return 0x0000000000107024ull;
449 #define CVMX_SRIOMAINTX_IR_PI_PHY_STAT(block_id) (0x0000000000107024ull)
451 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
452 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_CTRL(unsigned long block_id)
455 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
456 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
457 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_CTRL(%lu) is invalid on this chip\n", block_id);
458 return 0x000000000010700Cull;
461 #define CVMX_SRIOMAINTX_IR_SP_RX_CTRL(block_id) (0x000000000010700Cull)
463 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
464 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_DATA(unsigned long block_id)
467 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
468 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
469 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_DATA(%lu) is invalid on this chip\n", block_id);
470 return 0x0000000000107014ull;
473 #define CVMX_SRIOMAINTX_IR_SP_RX_DATA(block_id) (0x0000000000107014ull)
475 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
476 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_RX_STAT(unsigned long block_id)
479 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
480 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
481 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_RX_STAT(%lu) is invalid on this chip\n", block_id);
482 return 0x0000000000107010ull;
485 #define CVMX_SRIOMAINTX_IR_SP_RX_STAT(block_id) (0x0000000000107010ull)
487 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
488 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_CTRL(unsigned long block_id)
491 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
492 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
493 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_CTRL(%lu) is invalid on this chip\n", block_id);
494 return 0x0000000000107000ull;
497 #define CVMX_SRIOMAINTX_IR_SP_TX_CTRL(block_id) (0x0000000000107000ull)
499 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
500 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_DATA(unsigned long block_id)
503 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
504 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
505 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_DATA(%lu) is invalid on this chip\n", block_id);
506 return 0x0000000000107008ull;
509 #define CVMX_SRIOMAINTX_IR_SP_TX_DATA(block_id) (0x0000000000107008ull)
511 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
512 static inline uint64_t CVMX_SRIOMAINTX_IR_SP_TX_STAT(unsigned long block_id)
515 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
516 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
517 cvmx_warn("CVMX_SRIOMAINTX_IR_SP_TX_STAT(%lu) is invalid on this chip\n", block_id);
518 return 0x0000000000107004ull;
521 #define CVMX_SRIOMAINTX_IR_SP_TX_STAT(block_id) (0x0000000000107004ull)
523 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
524 static inline uint64_t CVMX_SRIOMAINTX_LANE_X_STATUS_0(unsigned long offset, unsigned long block_id)
527 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
528 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
529 cvmx_warn("CVMX_SRIOMAINTX_LANE_X_STATUS_0(%lu,%lu) is invalid on this chip\n", offset, block_id);
530 return 0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32;
533 #define CVMX_SRIOMAINTX_LANE_X_STATUS_0(offset, block_id) (0x0000000000001010ull + (((offset) & 3) + ((block_id) & 3) * 0x0ull) * 32)
535 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
536 static inline uint64_t CVMX_SRIOMAINTX_LCS_BA0(unsigned long block_id)
539 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
540 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
541 cvmx_warn("CVMX_SRIOMAINTX_LCS_BA0(%lu) is invalid on this chip\n", block_id);
542 return 0x0000000000000058ull;
545 #define CVMX_SRIOMAINTX_LCS_BA0(block_id) (0x0000000000000058ull)
547 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
548 static inline uint64_t CVMX_SRIOMAINTX_LCS_BA1(unsigned long block_id)
551 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
552 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
553 cvmx_warn("CVMX_SRIOMAINTX_LCS_BA1(%lu) is invalid on this chip\n", block_id);
554 return 0x000000000000005Cull;
557 #define CVMX_SRIOMAINTX_LCS_BA1(block_id) (0x000000000000005Cull)
559 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
560 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START0(unsigned long block_id)
563 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
564 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
565 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START0(%lu) is invalid on this chip\n", block_id);
566 return 0x0000000000200000ull;
569 #define CVMX_SRIOMAINTX_M2S_BAR0_START0(block_id) (0x0000000000200000ull)
571 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
572 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR0_START1(unsigned long block_id)
575 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
576 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
577 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR0_START1(%lu) is invalid on this chip\n", block_id);
578 return 0x0000000000200004ull;
581 #define CVMX_SRIOMAINTX_M2S_BAR0_START1(block_id) (0x0000000000200004ull)
583 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
584 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START0(unsigned long block_id)
587 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
588 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
589 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START0(%lu) is invalid on this chip\n", block_id);
590 return 0x0000000000200008ull;
593 #define CVMX_SRIOMAINTX_M2S_BAR1_START0(block_id) (0x0000000000200008ull)
595 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
596 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR1_START1(unsigned long block_id)
599 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
600 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
601 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR1_START1(%lu) is invalid on this chip\n", block_id);
602 return 0x000000000020000Cull;
605 #define CVMX_SRIOMAINTX_M2S_BAR1_START1(block_id) (0x000000000020000Cull)
607 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
608 static inline uint64_t CVMX_SRIOMAINTX_M2S_BAR2_START(unsigned long block_id)
611 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
612 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
613 cvmx_warn("CVMX_SRIOMAINTX_M2S_BAR2_START(%lu) is invalid on this chip\n", block_id);
614 return 0x0000000000200050ull;
617 #define CVMX_SRIOMAINTX_M2S_BAR2_START(block_id) (0x0000000000200050ull)
619 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
620 static inline uint64_t CVMX_SRIOMAINTX_MAC_CTRL(unsigned long block_id)
623 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
624 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
625 cvmx_warn("CVMX_SRIOMAINTX_MAC_CTRL(%lu) is invalid on this chip\n", block_id);
626 return 0x0000000000200068ull;
629 #define CVMX_SRIOMAINTX_MAC_CTRL(block_id) (0x0000000000200068ull)
631 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
632 static inline uint64_t CVMX_SRIOMAINTX_PE_FEAT(unsigned long block_id)
635 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
636 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
637 cvmx_warn("CVMX_SRIOMAINTX_PE_FEAT(%lu) is invalid on this chip\n", block_id);
638 return 0x0000000000000010ull;
641 #define CVMX_SRIOMAINTX_PE_FEAT(block_id) (0x0000000000000010ull)
643 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
644 static inline uint64_t CVMX_SRIOMAINTX_PE_LLC(unsigned long block_id)
647 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
648 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
649 cvmx_warn("CVMX_SRIOMAINTX_PE_LLC(%lu) is invalid on this chip\n", block_id);
650 return 0x000000000000004Cull;
653 #define CVMX_SRIOMAINTX_PE_LLC(block_id) (0x000000000000004Cull)
655 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
656 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL(unsigned long block_id)
659 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
660 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
661 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL(%lu) is invalid on this chip\n", block_id);
662 return 0x000000000000015Cull;
665 #define CVMX_SRIOMAINTX_PORT_0_CTL(block_id) (0x000000000000015Cull)
667 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
668 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_CTL2(unsigned long block_id)
671 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
672 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
673 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_CTL2(%lu) is invalid on this chip\n", block_id);
674 return 0x0000000000000154ull;
677 #define CVMX_SRIOMAINTX_PORT_0_CTL2(block_id) (0x0000000000000154ull)
679 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
680 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_ERR_STAT(unsigned long block_id)
683 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
684 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
685 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_ERR_STAT(%lu) is invalid on this chip\n", block_id);
686 return 0x0000000000000158ull;
689 #define CVMX_SRIOMAINTX_PORT_0_ERR_STAT(block_id) (0x0000000000000158ull)
691 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
692 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_REQ(unsigned long block_id)
695 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
696 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
697 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_REQ(%lu) is invalid on this chip\n", block_id);
698 return 0x0000000000000140ull;
701 #define CVMX_SRIOMAINTX_PORT_0_LINK_REQ(block_id) (0x0000000000000140ull)
703 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
704 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LINK_RESP(unsigned long block_id)
707 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
708 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
709 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LINK_RESP(%lu) is invalid on this chip\n", block_id);
710 return 0x0000000000000144ull;
713 #define CVMX_SRIOMAINTX_PORT_0_LINK_RESP(block_id) (0x0000000000000144ull)
715 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
716 static inline uint64_t CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(unsigned long block_id)
719 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
720 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
721 cvmx_warn("CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(%lu) is invalid on this chip\n", block_id);
722 return 0x0000000000000148ull;
725 #define CVMX_SRIOMAINTX_PORT_0_LOCAL_ACKID(block_id) (0x0000000000000148ull)
727 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
728 static inline uint64_t CVMX_SRIOMAINTX_PORT_GEN_CTL(unsigned long block_id)
731 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
732 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
733 cvmx_warn("CVMX_SRIOMAINTX_PORT_GEN_CTL(%lu) is invalid on this chip\n", block_id);
734 return 0x000000000000013Cull;
737 #define CVMX_SRIOMAINTX_PORT_GEN_CTL(block_id) (0x000000000000013Cull)
739 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
740 static inline uint64_t CVMX_SRIOMAINTX_PORT_LT_CTL(unsigned long block_id)
743 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
744 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
745 cvmx_warn("CVMX_SRIOMAINTX_PORT_LT_CTL(%lu) is invalid on this chip\n", block_id);
746 return 0x0000000000000120ull;
749 #define CVMX_SRIOMAINTX_PORT_LT_CTL(block_id) (0x0000000000000120ull)
751 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
752 static inline uint64_t CVMX_SRIOMAINTX_PORT_MBH0(unsigned long block_id)
755 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
756 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
757 cvmx_warn("CVMX_SRIOMAINTX_PORT_MBH0(%lu) is invalid on this chip\n", block_id);
758 return 0x0000000000000100ull;
761 #define CVMX_SRIOMAINTX_PORT_MBH0(block_id) (0x0000000000000100ull)
763 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
764 static inline uint64_t CVMX_SRIOMAINTX_PORT_RT_CTL(unsigned long block_id)
767 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
769 cvmx_warn("CVMX_SRIOMAINTX_PORT_RT_CTL(%lu) is invalid on this chip\n", block_id);
770 return 0x0000000000000124ull;
773 #define CVMX_SRIOMAINTX_PORT_RT_CTL(block_id) (0x0000000000000124ull)
775 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
776 static inline uint64_t CVMX_SRIOMAINTX_PORT_TTL_CTL(unsigned long block_id)
779 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
780 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
781 cvmx_warn("CVMX_SRIOMAINTX_PORT_TTL_CTL(%lu) is invalid on this chip\n", block_id);
782 return 0x000000000000012Cull;
785 #define CVMX_SRIOMAINTX_PORT_TTL_CTL(block_id) (0x000000000000012Cull)
787 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
788 static inline uint64_t CVMX_SRIOMAINTX_PRI_DEV_ID(unsigned long block_id)
791 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
792 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
793 cvmx_warn("CVMX_SRIOMAINTX_PRI_DEV_ID(%lu) is invalid on this chip\n", block_id);
794 return 0x0000000000000060ull;
797 #define CVMX_SRIOMAINTX_PRI_DEV_ID(block_id) (0x0000000000000060ull)
799 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
800 static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_CTRL(unsigned long block_id)
803 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
804 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
805 cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_CTRL(%lu) is invalid on this chip\n", block_id);
806 return 0x0000000000200064ull;
809 #define CVMX_SRIOMAINTX_SEC_DEV_CTRL(block_id) (0x0000000000200064ull)
811 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
812 static inline uint64_t CVMX_SRIOMAINTX_SEC_DEV_ID(unsigned long block_id)
815 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
816 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
817 cvmx_warn("CVMX_SRIOMAINTX_SEC_DEV_ID(%lu) is invalid on this chip\n", block_id);
818 return 0x0000000000200060ull;
821 #define CVMX_SRIOMAINTX_SEC_DEV_ID(block_id) (0x0000000000200060ull)
823 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
824 static inline uint64_t CVMX_SRIOMAINTX_SERIAL_LANE_HDR(unsigned long block_id)
827 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
828 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
829 cvmx_warn("CVMX_SRIOMAINTX_SERIAL_LANE_HDR(%lu) is invalid on this chip\n", block_id);
830 return 0x0000000000001000ull;
833 #define CVMX_SRIOMAINTX_SERIAL_LANE_HDR(block_id) (0x0000000000001000ull)
835 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
836 static inline uint64_t CVMX_SRIOMAINTX_SRC_OPS(unsigned long block_id)
839 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
840 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
841 cvmx_warn("CVMX_SRIOMAINTX_SRC_OPS(%lu) is invalid on this chip\n", block_id);
842 return 0x0000000000000018ull;
845 #define CVMX_SRIOMAINTX_SRC_OPS(block_id) (0x0000000000000018ull)
847 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
848 static inline uint64_t CVMX_SRIOMAINTX_TX_DROP(unsigned long block_id)
851 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
852 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
853 cvmx_warn("CVMX_SRIOMAINTX_TX_DROP(%lu) is invalid on this chip\n", block_id);
854 return 0x000000000020006Cull;
857 #define CVMX_SRIOMAINTX_TX_DROP(block_id) (0x000000000020006Cull)
861 * cvmx_sriomaint#_asmbly_id
863 * SRIOMAINT_ASMBLY_ID = SRIO Assembly ID
865 * The Assembly ID register shows the Assembly ID and Vendor
868 * The Assembly ID register shows the Assembly ID and Vendor specified in $SRIO_ASMBLY_ID.
870 * Clk_Rst: SRIOMAINT(0,2..3)_ASMBLY_ID hclk hrst_n
872 union cvmx_sriomaintx_asmbly_id {
874 struct cvmx_sriomaintx_asmbly_id_s {
875 #ifdef __BIG_ENDIAN_BITFIELD
876 uint32_t assy_id : 16; /**< Assembly Identifer */
877 uint32_t assy_ven : 16; /**< Assembly Vendor Identifer */
879 uint32_t assy_ven : 16;
880 uint32_t assy_id : 16;
883 struct cvmx_sriomaintx_asmbly_id_s cn63xx;
884 struct cvmx_sriomaintx_asmbly_id_s cn63xxp1;
885 struct cvmx_sriomaintx_asmbly_id_s cn66xx;
887 typedef union cvmx_sriomaintx_asmbly_id cvmx_sriomaintx_asmbly_id_t;
890 * cvmx_sriomaint#_asmbly_info
892 * SRIOMAINT_ASMBLY_INFO = SRIO Assembly Information
894 * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO
897 * The Assembly Info register shows the Assembly Revision specified in $SRIO_ASMBLY_INFO and Extended
900 * Clk_Rst: SRIOMAINT(0,2..3)_ASMBLY_INFO hclk hrst_n
902 union cvmx_sriomaintx_asmbly_info {
904 struct cvmx_sriomaintx_asmbly_info_s {
905 #ifdef __BIG_ENDIAN_BITFIELD
906 uint32_t assy_rev : 16; /**< Assembly Revision */
907 uint32_t ext_fptr : 16; /**< Pointer to the first entry in the extended feature
910 uint32_t ext_fptr : 16;
911 uint32_t assy_rev : 16;
914 struct cvmx_sriomaintx_asmbly_info_s cn63xx;
915 struct cvmx_sriomaintx_asmbly_info_s cn63xxp1;
916 struct cvmx_sriomaintx_asmbly_info_s cn66xx;
918 typedef union cvmx_sriomaintx_asmbly_info cvmx_sriomaintx_asmbly_info_t;
921 * cvmx_sriomaint#_bar1_idx#
923 * SRIOMAINT_BAR1_IDXX = SRIO BAR1 IndexX Register
925 * Contains address index and control bits for access to memory ranges of BAR1.
928 * This register specifies the Octeon address, endian swap and cache status associated with each of
929 * the 16 BAR1 entries. The local address bits used are based on the BARSIZE field located in the
930 * SRIOMAINT(0,2..3)_M2S_BAR1_START0 register. This register is only writeable over SRIO if the
931 * SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero.
933 * Clk_Rst: SRIOMAINT(0,2..3)_BAR1_IDX[0:15] hclk hrst_n
935 union cvmx_sriomaintx_bar1_idxx {
937 struct cvmx_sriomaintx_bar1_idxx_s {
938 #ifdef __BIG_ENDIAN_BITFIELD
939 uint32_t reserved_30_31 : 2;
940 uint32_t la : 22; /**< L2/DRAM Address bits [37:16]
941 Not all LA[21:0] bits are used by SRIO hardware,
942 depending on SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE].
947 BARSIZE LA Bits Used Bits Size
948 0 LA[21:0] [37:16] 64KB
949 1 LA[21:1] [37:17] 128KB
950 2 LA[21:2] [37:18] 256KB
951 3 LA[21:3] [37:19] 512KB
952 4 LA[21:4] [37:20] 1MB
953 5 LA[21:5] [37:21] 2MB
954 6 LA[21:6] [37:22] 4MB
955 7 LA[21:7] [37:23] 8MB
956 8 LA[21:8] [37:24] 16MB
957 9 LA[21:9] [37:25] 32MB
958 10 LA[21:10] [37:26] 64MB
959 11 LA[21:11] [37:27] 128MB
960 12 LA[21:12] [37:28] 256MB
961 13 LA[21:13] [37:29] 512MB */
962 uint32_t reserved_6_7 : 2;
963 uint32_t es : 2; /**< Endian Swap Mode.
965 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA]
966 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE]
967 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */
968 uint32_t nca : 1; /**< Non-Cacheable Access Mode. When set, transfers
969 through this window are not cacheable. */
970 uint32_t reserved_1_2 : 2;
971 uint32_t enable : 1; /**< When set the selected index address is valid. */
974 uint32_t reserved_1_2 : 2;
977 uint32_t reserved_6_7 : 2;
979 uint32_t reserved_30_31 : 2;
982 struct cvmx_sriomaintx_bar1_idxx_s cn63xx;
983 struct cvmx_sriomaintx_bar1_idxx_s cn63xxp1;
984 struct cvmx_sriomaintx_bar1_idxx_s cn66xx;
986 typedef union cvmx_sriomaintx_bar1_idxx cvmx_sriomaintx_bar1_idxx_t;
989 * cvmx_sriomaint#_bell_status
991 * SRIOMAINT_BELL_STATUS = SRIO Incoming Doorbell Status
993 * The SRIO Incoming (RX) Doorbell Status
996 * This register displays the status of the doorbells received. If FULL is set the SRIO device will
997 * retry incoming transactions.
999 * Clk_Rst: SRIOMAINT(0,2..3)_BELL_STATUS hclk hrst_n
1001 union cvmx_sriomaintx_bell_status {
1003 struct cvmx_sriomaintx_bell_status_s {
1004 #ifdef __BIG_ENDIAN_BITFIELD
1005 uint32_t reserved_1_31 : 31;
1006 uint32_t full : 1; /**< Not able to receive Doorbell Transactions */
1009 uint32_t reserved_1_31 : 31;
1012 struct cvmx_sriomaintx_bell_status_s cn63xx;
1013 struct cvmx_sriomaintx_bell_status_s cn63xxp1;
1014 struct cvmx_sriomaintx_bell_status_s cn66xx;
1016 typedef union cvmx_sriomaintx_bell_status cvmx_sriomaintx_bell_status_t;
1019 * cvmx_sriomaint#_comp_tag
1021 * SRIOMAINT_COMP_TAG = SRIO Component Tag
1026 * This register contains a component tag value for the processing element and the value can be
1027 * assigned by software when the device is initialized.
1029 * Clk_Rst: SRIOMAINT(0,2..3)_COMP_TAG hclk hrst_n
1031 union cvmx_sriomaintx_comp_tag {
1033 struct cvmx_sriomaintx_comp_tag_s {
1034 #ifdef __BIG_ENDIAN_BITFIELD
1035 uint32_t comp_tag : 32; /**< Component Tag for Firmware Use */
1037 uint32_t comp_tag : 32;
1040 struct cvmx_sriomaintx_comp_tag_s cn63xx;
1041 struct cvmx_sriomaintx_comp_tag_s cn63xxp1;
1042 struct cvmx_sriomaintx_comp_tag_s cn66xx;
1044 typedef union cvmx_sriomaintx_comp_tag cvmx_sriomaintx_comp_tag_t;
1047 * cvmx_sriomaint#_core_enables
1049 * SRIOMAINT_CORE_ENABLES = SRIO Core Control
1054 * This register displays the reset state of the Octeon Core Logic while the SRIO Link is running.
1055 * The bit should be set after the software has initialized the chip to allow memory operations.
1057 * Clk_Rst: SRIOMAINT(0,2..3)_CORE_ENABLES hclk hrst_n, srst_n
1059 union cvmx_sriomaintx_core_enables {
1061 struct cvmx_sriomaintx_core_enables_s {
1062 #ifdef __BIG_ENDIAN_BITFIELD
1063 uint32_t reserved_5_31 : 27;
1064 uint32_t halt : 1; /**< OCTEON currently in Reset
1065 0 = All OCTEON resources are available.
1066 1 = The OCTEON is in reset. When this bit is set,
1067 SRIO maintenance registers can be accessed,
1068 but BAR0, BAR1, and BAR2 cannot be. */
1069 uint32_t imsg1 : 1; /**< Allow Incoming Message Unit 1 Operations
1070 Note: This bit is cleared when the C63XX is reset
1071 0 = SRIO Incoming Messages to Unit 1 ignored and
1072 return error response
1073 1 = SRIO Incoming Messages to Unit 1 */
1074 uint32_t imsg0 : 1; /**< Allow Incoming Message Unit 0 Operations
1075 Note: This bit is cleared when the C63XX is reset
1076 0 = SRIO Incoming Messages to Unit 0 ignored and
1077 return error response
1078 1 = SRIO Incoming Messages to Unit 0 */
1079 uint32_t doorbell : 1; /**< Allow Inbound Doorbell Operations
1080 Note: This bit is cleared when the C63XX is reset
1081 0 = SRIO Doorbell OPs ignored and return error
1083 1 = SRIO Doorbell OPs Allowed */
1084 uint32_t memory : 1; /**< Allow Inbound/Outbound Memory Operations
1085 Note: This bit is cleared when the C63XX is reset
1086 0 = SRIO Incoming Nwrites and Swrites are
1087 dropped. Incoming Nreads, Atomics and
1088 NwriteRs return responses with ERROR status.
1089 SRIO Incoming Maintenance BAR Memory Accesses
1090 are processed normally.
1091 Outgoing Store Operations are Dropped
1092 Outgoing Load Operations are not issued and
1093 return all 1's with an ERROR status.
1094 In Flight Operations started while the bit is
1095 set in both directions will complete normally.
1096 1 = SRIO Memory Read/Write OPs Allowed */
1098 uint32_t memory : 1;
1099 uint32_t doorbell : 1;
1103 uint32_t reserved_5_31 : 27;
1106 struct cvmx_sriomaintx_core_enables_s cn63xx;
1107 struct cvmx_sriomaintx_core_enables_s cn63xxp1;
1108 struct cvmx_sriomaintx_core_enables_s cn66xx;
1110 typedef union cvmx_sriomaintx_core_enables cvmx_sriomaintx_core_enables_t;
1113 * cvmx_sriomaint#_dev_id
1115 * SRIOMAINT_DEV_ID = SRIO Device ID
1117 * The DeviceVendor Identity field identifies the vendor that manufactured the device
1120 * This register identifies Cavium Inc. and the Product ID.
1122 * Clk_Rst: SRIOMAINT(0,2..3)_DEV_ID hclk hrst_n
1124 union cvmx_sriomaintx_dev_id {
1126 struct cvmx_sriomaintx_dev_id_s {
1127 #ifdef __BIG_ENDIAN_BITFIELD
1128 uint32_t device : 16; /**< Product Identity */
1129 uint32_t vendor : 16; /**< Cavium Vendor Identity */
1131 uint32_t vendor : 16;
1132 uint32_t device : 16;
1135 struct cvmx_sriomaintx_dev_id_s cn63xx;
1136 struct cvmx_sriomaintx_dev_id_s cn63xxp1;
1137 struct cvmx_sriomaintx_dev_id_s cn66xx;
1139 typedef union cvmx_sriomaintx_dev_id cvmx_sriomaintx_dev_id_t;
1142 * cvmx_sriomaint#_dev_rev
1144 * SRIOMAINT_DEV_REV = SRIO Device Revision
1146 * The Device Revision register identifies the chip pass and revision
1149 * This register identifies the chip pass and revision derived from the fuses.
1151 * Clk_Rst: SRIOMAINT(0,2..3)_DEV_REV hclk hrst_n
1153 union cvmx_sriomaintx_dev_rev {
1155 struct cvmx_sriomaintx_dev_rev_s {
1156 #ifdef __BIG_ENDIAN_BITFIELD
1157 uint32_t reserved_8_31 : 24;
1158 uint32_t revision : 8; /**< Chip Pass/Revision */
1160 uint32_t revision : 8;
1161 uint32_t reserved_8_31 : 24;
1164 struct cvmx_sriomaintx_dev_rev_s cn63xx;
1165 struct cvmx_sriomaintx_dev_rev_s cn63xxp1;
1166 struct cvmx_sriomaintx_dev_rev_s cn66xx;
1168 typedef union cvmx_sriomaintx_dev_rev cvmx_sriomaintx_dev_rev_t;
1171 * cvmx_sriomaint#_dst_ops
1173 * SRIOMAINT_DST_OPS = SRIO Source Operations
1175 * The logical operations supported from external devices.
1178 * The logical operations supported from external devices. The Destination OPs register shows the
1179 * operations specified in the SRIO(0,2..3)_IP_FEATURE.OPS register.
1181 * Clk_Rst: SRIOMAINT(0,2..3)_DST_OPS hclk hrst_n
1183 union cvmx_sriomaintx_dst_ops {
1185 struct cvmx_sriomaintx_dst_ops_s {
1186 #ifdef __BIG_ENDIAN_BITFIELD
1187 uint32_t gsm_read : 1; /**< PE does not support Read Home operations.
1188 This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */
1189 uint32_t i_read : 1; /**< PE does not support Instruction Read.
1190 This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */
1191 uint32_t rd_own : 1; /**< PE does not support Read for Ownership.
1192 This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */
1193 uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate.
1194 This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */
1195 uint32_t castout : 1; /**< PE does not support Castout Operations.
1196 This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */
1197 uint32_t d_flush : 1; /**< PE does not support Data Cache Flush.
1198 This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */
1199 uint32_t io_read : 1; /**< PE does not support IO Read.
1200 This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */
1201 uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate.
1202 This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */
1203 uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate.
1204 This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */
1205 uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync.
1206 This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */
1207 uint32_t reserved_16_21 : 6;
1208 uint32_t read : 1; /**< PE can support Nread operations.
1209 This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */
1210 uint32_t write : 1; /**< PE can support Nwrite operations.
1211 This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */
1212 uint32_t swrite : 1; /**< PE can support Swrite operations.
1213 This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */
1214 uint32_t write_r : 1; /**< PE can support Write with Response operations.
1215 This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */
1216 uint32_t msg : 1; /**< PE can support Data Message operations.
1217 This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */
1218 uint32_t doorbell : 1; /**< PE can support Doorbell operations.
1219 This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */
1220 uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap.
1221 This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */
1222 uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap.
1223 This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */
1224 uint32_t atom_inc : 1; /**< PE can support Atomic increment operations.
1225 This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */
1226 uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations.
1227 This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */
1228 uint32_t atom_set : 1; /**< PE can support Atomic set operations.
1229 This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */
1230 uint32_t atom_clr : 1; /**< PE can support Atomic clear operations.
1231 This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */
1232 uint32_t atom_swp : 1; /**< PE does not support Atomic Swap.
1233 This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */
1234 uint32_t port_wr : 1; /**< PE can Port Write operations.
1235 This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */
1236 uint32_t reserved_0_1 : 2;
1238 uint32_t reserved_0_1 : 2;
1239 uint32_t port_wr : 1;
1240 uint32_t atom_swp : 1;
1241 uint32_t atom_clr : 1;
1242 uint32_t atom_set : 1;
1243 uint32_t atom_dec : 1;
1244 uint32_t atom_inc : 1;
1245 uint32_t testswap : 1;
1246 uint32_t compswap : 1;
1247 uint32_t doorbell : 1;
1249 uint32_t write_r : 1;
1250 uint32_t swrite : 1;
1253 uint32_t reserved_16_21 : 6;
1254 uint32_t tlb_invs : 1;
1255 uint32_t tlb_inv : 1;
1256 uint32_t i_invald : 1;
1257 uint32_t io_read : 1;
1258 uint32_t d_flush : 1;
1259 uint32_t castout : 1;
1260 uint32_t d_invald : 1;
1261 uint32_t rd_own : 1;
1262 uint32_t i_read : 1;
1263 uint32_t gsm_read : 1;
1266 struct cvmx_sriomaintx_dst_ops_s cn63xx;
1267 struct cvmx_sriomaintx_dst_ops_s cn63xxp1;
1268 struct cvmx_sriomaintx_dst_ops_s cn66xx;
1270 typedef union cvmx_sriomaintx_dst_ops cvmx_sriomaintx_dst_ops_t;
1273 * cvmx_sriomaint#_erb_attr_capt
1275 * SRIOMAINT_ERB_ATTR_CAPT = SRIO Attributes Capture
1277 * Attributes Capture
1280 * This register contains the information captured during the error.
1281 * The HW will not update this register (i.e. this register is locked) while
1282 * VALID is set in this CSR.
1283 * The HW sets SRIO_INT_REG[PHY_ERB] every time it sets VALID in this CSR.
1284 * To handle the interrupt, the following procedure may be best:
1285 * (1) clear SRIO_INT_REG[PHY_ERB],
1286 * (2) read this CSR, corresponding SRIOMAINT*_ERB_ERR_DET, SRIOMAINT*_ERB_PACK_SYM_CAPT,
1287 * SRIOMAINT*_ERB_PACK_CAPT_1, SRIOMAINT*_ERB_PACK_CAPT_2, and SRIOMAINT*_ERB_PACK_CAPT_3
1288 * (3) Write VALID in this CSR to 0.
1290 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ATTR_CAPT hclk hrst_n
1292 union cvmx_sriomaintx_erb_attr_capt {
1294 struct cvmx_sriomaintx_erb_attr_capt_s {
1295 #ifdef __BIG_ENDIAN_BITFIELD
1296 uint32_t inf_type : 3; /**< Type of Information Logged.
1298 010 - Short Control Symbol
1299 (use only first capture register)
1300 100 - Implementation Specific Error Reporting
1301 All Others Reserved */
1302 uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in
1303 SRIOMAINT(0,2..3)_ERB_ERR_DET that describes the error
1304 captured in SRIOMAINT(0,2..3)_ERB_*CAPT Registers.
1305 (For example a value of 5 indicates 31-5 = bit 26) */
1306 uint32_t err_info : 20; /**< Error Info.
1307 ERR_TYPE Bits Description
1308 0 23 TX Protocol Error
1309 22 RX Protocol Error
1310 21 TX Link Response Timeout
1313 - 15:12 TX Protocol ID
1314 1 = Rcvd Unexpected Link Response
1315 2 = Rcvd Link Response before Req
1316 3 = Rcvd NACK servicing NACK
1318 5 = Rcvd RETRY servicing RETRY
1319 6 = Rcvd RETRY servicing NACK
1320 7 = Rcvd ACK servicing RETRY
1321 8 = Rcvd ACK servicing NACK
1322 9 = Unexp ACKID on ACK or RETRY
1323 10 = Unexp ACK or RETRY
1325 - 7:4 RX Protocol ID
1326 1 = Rcvd EOP w/o Prev SOP
1327 2 = Rcvd STOMP w/o Prev SOP
1329 4 = Redundant Status from LinkReq
1330 9-16 23:20 RX K Bits
1337 - 11:8 RX or TX Protocol ID (see above)
1341 31 23:16 ACKID Timeout 0x2
1345 All others ERR_TYPEs are reserved. */
1346 uint32_t reserved_1_3 : 3;
1347 uint32_t valid : 1; /**< This bit is set by hardware to indicate that the
1348 Packet/control symbol capture registers contain
1349 valid information. For control symbols, only
1350 capture register 0 will contain meaningful
1351 information. This bit must be cleared by software
1352 to allow capture of other errors. */
1355 uint32_t reserved_1_3 : 3;
1356 uint32_t err_info : 20;
1357 uint32_t err_type : 5;
1358 uint32_t inf_type : 3;
1361 struct cvmx_sriomaintx_erb_attr_capt_s cn63xx;
1362 struct cvmx_sriomaintx_erb_attr_capt_cn63xxp1 {
1363 #ifdef __BIG_ENDIAN_BITFIELD
1364 uint32_t inf_type : 3; /**< Type of Information Logged.
1366 010 - Short Control Symbol
1367 (use only first capture register)
1368 All Others Reserved */
1369 uint32_t err_type : 5; /**< The encoded value of the 31 minus the bit in
1370 SRIOMAINT(0..1)_ERB_ERR_DET that describes the error
1371 captured in SRIOMAINT(0..1)_ERB_*CAPT Registers.
1372 (For example a value of 5 indicates 31-5 = bit 26) */
1373 uint32_t reserved_1_23 : 23;
1374 uint32_t valid : 1; /**< This bit is set by hardware to indicate that the
1375 Packet/control symbol capture registers contain
1376 valid information. For control symbols, only
1377 capture register 0 will contain meaningful
1378 information. This bit must be cleared by software
1379 to allow capture of other errors. */
1382 uint32_t reserved_1_23 : 23;
1383 uint32_t err_type : 5;
1384 uint32_t inf_type : 3;
1387 struct cvmx_sriomaintx_erb_attr_capt_s cn66xx;
1389 typedef union cvmx_sriomaintx_erb_attr_capt cvmx_sriomaintx_erb_attr_capt_t;
1392 * cvmx_sriomaint#_erb_err_det
1394 * SRIOMAINT_ERB_ERR_DET = SRIO Error Detect
1399 * The Error Detect Register indicates physical layer transmission errors detected by the hardware.
1400 * The HW will not update this register (i.e. this register is locked) while
1401 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set.
1403 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_DET hclk hrst_n
1405 union cvmx_sriomaintx_erb_err_det {
1407 struct cvmx_sriomaintx_erb_err_det_s {
1408 #ifdef __BIG_ENDIAN_BITFIELD
1409 uint32_t imp_err : 1; /**< Implementation Specific Error. */
1410 uint32_t reserved_23_30 : 8;
1411 uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value
1412 Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1413 uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an
1414 unexpected ackID (packet-accepted or packet_retry)
1415 Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1416 uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control
1418 Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1419 uint32_t out_ack : 1; /**< Received packet with unexpected ackID value
1420 Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1421 uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value
1422 Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1423 uint32_t size : 1; /**< Received packet which exceeds the maximum allowed
1425 Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1426 uint32_t inv_char : 1; /**< Received illegal, 8B/10B error or undefined
1427 codegroup within a packet.
1428 Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1429 uint32_t inv_data : 1; /**< Received data codegroup or 8B/10B error within an
1431 Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1432 uint32_t reserved_6_14 : 9;
1433 uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not
1435 Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1436 uint32_t proterr : 1; /**< An unexpected packet or control symbol was
1438 Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1439 uint32_t f_toggle : 1; /**< Reserved. */
1440 uint32_t del_err : 1; /**< Received illegal or undefined codegroup.
1441 (either INV_DATA or INV_CHAR)
1442 Complete Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1443 uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was
1445 Partial Symbol in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1446 uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is
1447 not received within the specified timeout interval
1448 Partial Header in SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT */
1450 uint32_t lnk_tout : 1;
1451 uint32_t uns_ack : 1;
1452 uint32_t del_err : 1;
1453 uint32_t f_toggle : 1;
1454 uint32_t proterr : 1;
1455 uint32_t bad_ack : 1;
1456 uint32_t reserved_6_14 : 9;
1457 uint32_t inv_data : 1;
1458 uint32_t inv_char : 1;
1460 uint32_t pkt_crc : 1;
1461 uint32_t out_ack : 1;
1463 uint32_t uns_id : 1;
1464 uint32_t ctl_crc : 1;
1465 uint32_t reserved_23_30 : 8;
1466 uint32_t imp_err : 1;
1469 struct cvmx_sriomaintx_erb_err_det_s cn63xx;
1470 struct cvmx_sriomaintx_erb_err_det_cn63xxp1 {
1471 #ifdef __BIG_ENDIAN_BITFIELD
1472 uint32_t reserved_23_31 : 9;
1473 uint32_t ctl_crc : 1; /**< Received a control symbol with a bad CRC value
1474 Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1475 uint32_t uns_id : 1; /**< Received an acknowledge control symbol with an
1476 unexpected ackID (packet-accepted or packet_retry)
1477 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1478 uint32_t nack : 1; /**< Received packet-not-accepted acknowledge control
1480 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1481 uint32_t out_ack : 1; /**< Received packet with unexpected ackID value
1482 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1483 uint32_t pkt_crc : 1; /**< Received a packet with a bad CRC value
1484 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1485 uint32_t size : 1; /**< Received packet which exceeds the maximum allowed
1487 Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1488 uint32_t reserved_6_16 : 11;
1489 uint32_t bad_ack : 1; /**< Link_response received with an ackID that is not
1491 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1492 uint32_t proterr : 1; /**< An unexpected packet or control symbol was
1494 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1495 uint32_t f_toggle : 1; /**< Reserved. */
1496 uint32_t del_err : 1; /**< Received illegal or undefined codegroup.
1497 (either INV_DATA or INV_CHAR) (Pass 2)
1498 Complete Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1499 uint32_t uns_ack : 1; /**< An unexpected acknowledge control symbol was
1501 Partial Symbol in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1502 uint32_t lnk_tout : 1; /**< An acknowledge or link-response control symbol is
1503 not received within the specified timeout interval
1504 Partial Header in SRIOMAINT(0..1)_ERB_PACK_SYM_CAPT */
1506 uint32_t lnk_tout : 1;
1507 uint32_t uns_ack : 1;
1508 uint32_t del_err : 1;
1509 uint32_t f_toggle : 1;
1510 uint32_t proterr : 1;
1511 uint32_t bad_ack : 1;
1512 uint32_t reserved_6_16 : 11;
1514 uint32_t pkt_crc : 1;
1515 uint32_t out_ack : 1;
1517 uint32_t uns_id : 1;
1518 uint32_t ctl_crc : 1;
1519 uint32_t reserved_23_31 : 9;
1522 struct cvmx_sriomaintx_erb_err_det_s cn66xx;
1524 typedef union cvmx_sriomaintx_erb_err_det cvmx_sriomaintx_erb_err_det_t;
1527 * cvmx_sriomaint#_erb_err_rate
1529 * SRIOMAINT_ERB_ERR_RATE = SRIO Error Rate
1534 * The Error Rate register is used with the Error Rate Threshold register to monitor and control the
1535 * reporting of transmission errors.
1537 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE hclk hrst_n
1539 union cvmx_sriomaintx_erb_err_rate {
1541 struct cvmx_sriomaintx_erb_err_rate_s {
1542 #ifdef __BIG_ENDIAN_BITFIELD
1543 uint32_t err_bias : 8; /**< These bits provide the error rate bias value.
1544 0x00 - do not decrement the error rate counter
1545 0x01 - decrement every 1ms (+/-34%)
1546 0x02 - decrement every 10ms (+/-34%)
1547 0x04 - decrement every 100ms (+/-34%)
1548 0x08 - decrement every 1s (+/-34%)
1549 0x10 - decrement every 10s (+/-34%)
1550 0x20 - decrement every 100s (+/-34%)
1551 0x40 - decrement every 1000s (+/-34%)
1552 0x80 - decrement every 10000s (+/-34%)
1553 All other values are reserved */
1554 uint32_t reserved_18_23 : 6;
1555 uint32_t rate_lim : 2; /**< These bits limit the incrementing of the error
1556 rate counter above the failed threshold trigger.
1557 00 - only count 2 errors above
1558 01 - only count 4 errors above
1559 10 - only count 16 error above
1560 11 - do not limit incrementing the error rate ct */
1561 uint32_t pk_rate : 8; /**< Peak Value attainted by the error rate counter */
1562 uint32_t rate_cnt : 8; /**< These bits maintain a count of the number of
1563 transmission errors that have been detected by the
1564 port, decremented by the Error Rate Bias
1565 mechanism, to create an indication of the link
1568 uint32_t rate_cnt : 8;
1569 uint32_t pk_rate : 8;
1570 uint32_t rate_lim : 2;
1571 uint32_t reserved_18_23 : 6;
1572 uint32_t err_bias : 8;
1575 struct cvmx_sriomaintx_erb_err_rate_s cn63xx;
1576 struct cvmx_sriomaintx_erb_err_rate_s cn63xxp1;
1577 struct cvmx_sriomaintx_erb_err_rate_s cn66xx;
1579 typedef union cvmx_sriomaintx_erb_err_rate cvmx_sriomaintx_erb_err_rate_t;
1582 * cvmx_sriomaint#_erb_err_rate_en
1584 * SRIOMAINT_ERB_ERR_RATE_EN = SRIO Error Rate Enable
1589 * This register contains the bits that control when an error condition is allowed to increment the
1590 * error rate counter in the Error Rate Threshold Register and lock the Error Capture registers.
1592 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE_EN hclk hrst_n
1594 union cvmx_sriomaintx_erb_err_rate_en {
1596 struct cvmx_sriomaintx_erb_err_rate_en_s {
1597 #ifdef __BIG_ENDIAN_BITFIELD
1598 uint32_t imp_err : 1; /**< Enable Implementation Specific Error. */
1599 uint32_t reserved_23_30 : 8;
1600 uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with
1602 uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control
1603 symbol with unexpected ackIDs
1604 (packet-accepted or packet_retry) */
1605 uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted
1606 acknowledge control symbols. */
1607 uint32_t out_ack : 1; /**< Enable error rate counting of received packet with
1608 unexpected ackID value */
1609 uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet
1610 with a bad CRC value */
1611 uint32_t size : 1; /**< Enable error rate counting of received packet
1612 which exceeds the maximum size of 276 bytes. */
1613 uint32_t inv_char : 1; /**< Enable error rate counting of received illegal
1614 illegal, 8B/10B error or undefined codegroup
1616 uint32_t inv_data : 1; /**< Enable error rate counting of received data
1617 codegroup or 8B/10B error within IDLE sequence. */
1618 uint32_t reserved_6_14 : 9;
1619 uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with
1620 an ackID that is not outstanding. */
1621 uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or
1622 control symbols received. */
1623 uint32_t f_toggle : 1; /**< Reserved. */
1624 uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined
1625 codegroups (either INV_DATA or INV_CHAR). */
1626 uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected
1627 acknowledge control symbols received. */
1628 uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or
1629 link-response control symbols not received within
1630 the specified timeout interval */
1632 uint32_t lnk_tout : 1;
1633 uint32_t uns_ack : 1;
1634 uint32_t del_err : 1;
1635 uint32_t f_toggle : 1;
1636 uint32_t proterr : 1;
1637 uint32_t bad_ack : 1;
1638 uint32_t reserved_6_14 : 9;
1639 uint32_t inv_data : 1;
1640 uint32_t inv_char : 1;
1642 uint32_t pkt_crc : 1;
1643 uint32_t out_ack : 1;
1645 uint32_t uns_id : 1;
1646 uint32_t ctl_crc : 1;
1647 uint32_t reserved_23_30 : 8;
1648 uint32_t imp_err : 1;
1651 struct cvmx_sriomaintx_erb_err_rate_en_s cn63xx;
1652 struct cvmx_sriomaintx_erb_err_rate_en_cn63xxp1 {
1653 #ifdef __BIG_ENDIAN_BITFIELD
1654 uint32_t reserved_23_31 : 9;
1655 uint32_t ctl_crc : 1; /**< Enable error rate counting of control symbols with
1657 uint32_t uns_id : 1; /**< Enable error rate counting of acknowledge control
1658 symbol with unexpected ackIDs
1659 (packet-accepted or packet_retry) */
1660 uint32_t nack : 1; /**< Enable error rate counting of packet-not-accepted
1661 acknowledge control symbols. */
1662 uint32_t out_ack : 1; /**< Enable error rate counting of received packet with
1663 unexpected ackID value */
1664 uint32_t pkt_crc : 1; /**< Enable error rate counting of received a packet
1665 with a bad CRC value */
1666 uint32_t size : 1; /**< Enable error rate counting of received packet
1667 which exceeds the maximum size of 276 bytes. */
1668 uint32_t reserved_6_16 : 11;
1669 uint32_t bad_ack : 1; /**< Enable error rate counting of link_responses with
1670 an ackID that is not outstanding. */
1671 uint32_t proterr : 1; /**< Enable error rate counting of unexpected packet or
1672 control symbols received. */
1673 uint32_t f_toggle : 1; /**< Reserved. */
1674 uint32_t del_err : 1; /**< Enable error rate counting of illegal or undefined
1675 codegroups (either INV_DATA or INV_CHAR). (Pass 2) */
1676 uint32_t uns_ack : 1; /**< Enable error rate counting of unexpected
1677 acknowledge control symbols received. */
1678 uint32_t lnk_tout : 1; /**< Enable error rate counting of acknowledge or
1679 link-response control symbols not received within
1680 the specified timeout interval */
1682 uint32_t lnk_tout : 1;
1683 uint32_t uns_ack : 1;
1684 uint32_t del_err : 1;
1685 uint32_t f_toggle : 1;
1686 uint32_t proterr : 1;
1687 uint32_t bad_ack : 1;
1688 uint32_t reserved_6_16 : 11;
1690 uint32_t pkt_crc : 1;
1691 uint32_t out_ack : 1;
1693 uint32_t uns_id : 1;
1694 uint32_t ctl_crc : 1;
1695 uint32_t reserved_23_31 : 9;
1698 struct cvmx_sriomaintx_erb_err_rate_en_s cn66xx;
1700 typedef union cvmx_sriomaintx_erb_err_rate_en cvmx_sriomaintx_erb_err_rate_en_t;
1703 * cvmx_sriomaint#_erb_err_rate_thr
1705 * SRIOMAINT_ERB_ERR_RATE_THR = SRIO Error Rate Threshold
1707 * Error Rate Threshold
1710 * The Error Rate Threshold register is used to control the reporting of errors to the link status.
1711 * Typically the Degraded Threshold is less than the Fail Threshold.
1713 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR hclk hrst_n
1715 union cvmx_sriomaintx_erb_err_rate_thr {
1717 struct cvmx_sriomaintx_erb_err_rate_thr_s {
1718 #ifdef __BIG_ENDIAN_BITFIELD
1719 uint32_t fail_th : 8; /**< These bits provide the threshold value for
1720 reporting an error condition due to a possibly
1722 0x00 - Disable the Error Rate Failed Threshold
1724 0x01 - Set the error reporting threshold to 1
1725 0x02 - Set the error reporting threshold to 2
1727 0xFF - Set the error reporting threshold to 255 */
1728 uint32_t dgrad_th : 8; /**< These bits provide the threshold value for
1729 reporting an error condition due to a possibly
1731 0x00 - Disable the Degrade Rate Failed Threshold
1733 0x01 - Set the error reporting threshold to 1
1734 0x02 - Set the error reporting threshold to 2
1736 0xFF - Set the error reporting threshold to 255 */
1737 uint32_t reserved_0_15 : 16;
1739 uint32_t reserved_0_15 : 16;
1740 uint32_t dgrad_th : 8;
1741 uint32_t fail_th : 8;
1744 struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xx;
1745 struct cvmx_sriomaintx_erb_err_rate_thr_s cn63xxp1;
1746 struct cvmx_sriomaintx_erb_err_rate_thr_s cn66xx;
1748 typedef union cvmx_sriomaintx_erb_err_rate_thr cvmx_sriomaintx_erb_err_rate_thr_t;
1751 * cvmx_sriomaint#_erb_hdr
1753 * SRIOMAINT_ERB_HDR = SRIO Error Reporting Block Header
1755 * Error Reporting Block Header
1758 * The error management extensions block header register contains the EF_PTR to the next EF_BLK and
1759 * the EF_ID that identifies this as the error management extensions block header. In this
1760 * implementation this is the last block and therefore the EF_PTR is a NULL pointer.
1762 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_HDR hclk hrst_n
1764 union cvmx_sriomaintx_erb_hdr {
1766 struct cvmx_sriomaintx_erb_hdr_s {
1767 #ifdef __BIG_ENDIAN_BITFIELD
1768 uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features
1770 uint32_t ef_id : 16; /**< Single Port ID */
1772 uint32_t ef_id : 16;
1773 uint32_t ef_ptr : 16;
1776 struct cvmx_sriomaintx_erb_hdr_s cn63xx;
1777 struct cvmx_sriomaintx_erb_hdr_s cn63xxp1;
1778 struct cvmx_sriomaintx_erb_hdr_s cn66xx;
1780 typedef union cvmx_sriomaintx_erb_hdr cvmx_sriomaintx_erb_hdr_t;
1783 * cvmx_sriomaint#_erb_lt_addr_capt_h
1785 * SRIOMAINT_ERB_LT_ADDR_CAPT_H = SRIO Logical/Transport Layer High Address Capture
1787 * Logical/Transport Layer High Address Capture
1790 * This register contains error information. It is locked when a Logical/Transport error is detected
1791 * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be
1792 * written only when error detection is disabled. This register is only required for end point
1793 * transactions of 50 or 66 bits.
1795 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_H hclk hrst_n
1797 union cvmx_sriomaintx_erb_lt_addr_capt_h {
1799 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s {
1800 #ifdef __BIG_ENDIAN_BITFIELD
1801 uint32_t addr : 32; /**< Most significant 32 bits of the address associated
1802 with the error. Information supplied for requests
1803 and responses if available. */
1808 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xx;
1809 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn63xxp1;
1810 struct cvmx_sriomaintx_erb_lt_addr_capt_h_s cn66xx;
1812 typedef union cvmx_sriomaintx_erb_lt_addr_capt_h cvmx_sriomaintx_erb_lt_addr_capt_h_t;
1815 * cvmx_sriomaint#_erb_lt_addr_capt_l
1817 * SRIOMAINT_ERB_LT_ADDR_CAPT_L = SRIO Logical/Transport Layer Low Address Capture
1819 * Logical/Transport Layer Low Address Capture
1822 * This register contains error information. It is locked when a Logical/Transport error is detected
1823 * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be
1824 * written only when error detection is disabled.
1826 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ADDR_CAPT_L hclk hrst_n
1828 union cvmx_sriomaintx_erb_lt_addr_capt_l {
1830 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s {
1831 #ifdef __BIG_ENDIAN_BITFIELD
1832 uint32_t addr : 29; /**< Least significant 29 bits of the address
1833 associated with the error. Bits 31:24 specify the
1834 request HOP count for Maintenance Operations.
1835 Information supplied for requests and responses if
1837 uint32_t reserved_2_2 : 1;
1838 uint32_t xaddr : 2; /**< Extended address bits of the address associated
1839 with the error. Information supplied for requests
1840 and responses if available. */
1843 uint32_t reserved_2_2 : 1;
1847 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xx;
1848 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn63xxp1;
1849 struct cvmx_sriomaintx_erb_lt_addr_capt_l_s cn66xx;
1851 typedef union cvmx_sriomaintx_erb_lt_addr_capt_l cvmx_sriomaintx_erb_lt_addr_capt_l_t;
1854 * cvmx_sriomaint#_erb_lt_ctrl_capt
1856 * SRIOMAINT_ERB_LT_CTRL_CAPT = SRIO Logical/Transport Layer Control Capture
1858 * Logical/Transport Layer Control Capture
1861 * This register contains error information. It is locked when a Logical/Transport error is detected
1862 * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be
1863 * written only when error detection is disabled.
1865 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_CTRL_CAPT hclk hrst_n
1867 union cvmx_sriomaintx_erb_lt_ctrl_capt {
1869 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s {
1870 #ifdef __BIG_ENDIAN_BITFIELD
1871 uint32_t ftype : 4; /**< Format Type associated with the error */
1872 uint32_t ttype : 4; /**< Transaction Type associated with the error
1875 uint32_t extra : 8; /**< Additional Information
1879 - 19:16 Msgseg/xmbox
1880 Information for the last message request sent
1881 for the mailbox that had an error
1883 - 23:20 Response Request FTYPE
1884 - 19:16 Response Request TTYPE
1885 (For all other types)
1887 uint32_t status : 4; /**< Response Status.
1888 (For all other Requests)
1890 uint32_t size : 4; /**< Size associated with the transaction. */
1891 uint32_t tt : 1; /**< Transfer Type 0=ID8, 1=ID16. */
1892 uint32_t wdptr : 1; /**< Word Pointer associated with the error. */
1893 uint32_t reserved_5_5 : 1;
1894 uint32_t capt_idx : 5; /**< Capture Index. 31 - Bit set in
1895 SRIOMAINT(0,2..3)_ERB_LT_ERR_DET. */
1897 uint32_t capt_idx : 5;
1898 uint32_t reserved_5_5 : 1;
1902 uint32_t status : 4;
1908 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xx;
1909 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn63xxp1;
1910 struct cvmx_sriomaintx_erb_lt_ctrl_capt_s cn66xx;
1912 typedef union cvmx_sriomaintx_erb_lt_ctrl_capt cvmx_sriomaintx_erb_lt_ctrl_capt_t;
1915 * cvmx_sriomaint#_erb_lt_dev_id
1917 * SRIOMAINT_ERB_LT_DEV_ID = SRIO Port-write Target deviceID
1919 * Port-write Target deviceID
1922 * This SRIO interface does not support generating Port-Writes based on ERB Errors. This register is
1923 * currently unused and should be treated as reserved.
1925 * Clk_Rst: SRIOMAINT_ERB_LT_DEV_ID hclk hrst_n
1927 union cvmx_sriomaintx_erb_lt_dev_id {
1929 struct cvmx_sriomaintx_erb_lt_dev_id_s {
1930 #ifdef __BIG_ENDIAN_BITFIELD
1931 uint32_t id16 : 8; /**< This is the most significant byte of the
1932 port-write destination deviceID (large transport
1934 destination ID used for Port Write errors */
1935 uint32_t id8 : 8; /**< This is the port-write destination deviceID */
1936 uint32_t tt : 1; /**< Transport Type used for Port Write
1937 0 = Small Transport, ID8 Only
1938 1 = Large Transport, ID16 and ID8 */
1939 uint32_t reserved_0_14 : 15;
1941 uint32_t reserved_0_14 : 15;
1947 struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xx;
1948 struct cvmx_sriomaintx_erb_lt_dev_id_s cn63xxp1;
1949 struct cvmx_sriomaintx_erb_lt_dev_id_s cn66xx;
1951 typedef union cvmx_sriomaintx_erb_lt_dev_id cvmx_sriomaintx_erb_lt_dev_id_t;
1954 * cvmx_sriomaint#_erb_lt_dev_id_capt
1956 * SRIOMAINT_ERB_LT_DEV_ID_CAPT = SRIO Logical/Transport Layer Device ID Capture
1958 * Logical/Transport Layer Device ID Capture
1961 * This register contains error information. It is locked when a Logical/Transport error is detected
1962 * and unlocked when the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET is written to zero. This register should be
1963 * written only when error detection is disabled.
1965 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_DEV_ID_CAPT hclk hrst_n
1967 union cvmx_sriomaintx_erb_lt_dev_id_capt {
1969 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s {
1970 #ifdef __BIG_ENDIAN_BITFIELD
1971 uint32_t dst_id16 : 8; /**< Most significant byte of the large transport
1972 destination ID associated with the error */
1973 uint32_t dst_id8 : 8; /**< Least significant byte of the large transport
1974 destination ID or the 8-bit small transport
1975 destination ID associated with the error */
1976 uint32_t src_id16 : 8; /**< Most significant byte of the large transport
1977 source ID associated with the error */
1978 uint32_t src_id8 : 8; /**< Least significant byte of the large transport
1979 source ID or the 8-bit small transport source ID
1980 associated with the error */
1982 uint32_t src_id8 : 8;
1983 uint32_t src_id16 : 8;
1984 uint32_t dst_id8 : 8;
1985 uint32_t dst_id16 : 8;
1988 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xx;
1989 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn63xxp1;
1990 struct cvmx_sriomaintx_erb_lt_dev_id_capt_s cn66xx;
1992 typedef union cvmx_sriomaintx_erb_lt_dev_id_capt cvmx_sriomaintx_erb_lt_dev_id_capt_t;
1995 * cvmx_sriomaint#_erb_lt_err_det
1997 * SRIOMAINT_ERB_LT_ERR_DET = SRIO Logical/Transport Layer Error Detect
1999 * SRIO Logical/Transport Layer Error Detect
2002 * This register indicates the error that was detected by the Logical or Transport logic layer.
2003 * Once a bit is set in this CSR, HW will lock the register until SW writes a zero to clear all the
2004 * fields. The HW sets SRIO_INT_REG[LOG_ERB] every time it sets one of the bits.
2005 * To handle the interrupt, the following procedure may be best:
2006 * (1) clear SRIO_INT_REG[LOG_ERB],
2007 * (2) read this CSR, corresponding SRIOMAINT*_ERB_LT_ADDR_CAPT_H, SRIOMAINT*_ERB_LT_ADDR_CAPT_L,
2008 * SRIOMAINT*_ERB_LT_DEV_ID_CAPT, and SRIOMAINT*_ERB_LT_CTRL_CAPT
2009 * (3) Write this CSR to 0.
2011 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ERR_DET hclk hrst_n
2013 union cvmx_sriomaintx_erb_lt_err_det {
2015 struct cvmx_sriomaintx_erb_lt_err_det_s {
2016 #ifdef __BIG_ENDIAN_BITFIELD
2017 uint32_t io_err : 1; /**< Received a response of ERROR for an IO Logical
2018 Layer Request. This includes all Maintenance and
2019 Memory Responses not destined for the RX Soft
2020 Packet FIFO. When SRIO receives an ERROR response
2021 for a read, the issuing core or DPI DMA engine
2022 receives result bytes with all bits set. In the
2023 case of writes with response, this bit is the only
2024 indication of failure. */
2025 uint32_t msg_err : 1; /**< Received a response of ERROR for an outgoing
2026 message segment. This bit is the only direct
2027 indication of a MSG_ERR. When a MSG_ERR occurs,
2028 SRIO drops the message segment and will not set
2029 SRIO*_INT_REG[OMSG*] after the message
2030 "transfer". NOTE: SRIO can continue to send or
2031 retry other segments from the same message after
2033 uint32_t gsm_err : 1; /**< Received a response of ERROR for an GSM Logical
2034 Request. SRIO hardware never sets this bit. GSM
2035 operations are not supported (outside of the Soft
2037 uint32_t msg_fmt : 1; /**< Received an incoming Message Segment with a
2038 formating error. A MSG_FMT error occurs when SRIO
2039 receives a message segment with a reserved SSIZE,
2040 or a illegal data payload size, or a MSGSEG greater
2041 than MSGLEN, or a MSGSEG that is the duplicate of
2042 one already received by an inflight message.
2043 When a non-duplicate MSG_FMT error occurs, SRIO
2044 drops the segment and sends an ERROR response.
2045 When a duplicate MSG_FMT error occurs, SRIO
2046 (internally) terminates the currently-inflight
2047 message with an error and processes the duplicate,
2048 which may result in a new message being generated
2049 internally for the duplicate. */
2050 uint32_t ill_tran : 1; /**< Received illegal fields in the request/response
2051 packet for a supported transaction or any packet
2052 with a reserved transaction type. When an ILL_TRAN
2053 error occurs, SRIO ignores the packet. ILL_TRAN
2054 errors are 2nd priority after ILL_TGT and may mask
2055 other problems. Packets with ILL_TRAN errors cannot
2056 enter the RX Soft Packet FIFO.
2057 There are two things that can set ILL_TRAN:
2058 (1) SRIO received a packet with a tt value is not
2059 0 or 1, or (2) SRIO received a response to an
2060 outstanding message segment whose status was not
2061 DONE, RETRY, or ERROR. */
2062 uint32_t ill_tgt : 1; /**< Received a packet that contained a destination ID
2063 other than SRIOMAINT*_PRI_DEV_ID or
2064 SRIOMAINT*_SEC_DEV_ID. When an ILL_TGT error
2065 occurs, SRIO drops the packet. ILL_TGT errors are
2066 highest priority, so may mask other problems.
2067 Packets with ILL_TGT errors cannot enter the RX
2068 soft packet fifo. */
2069 uint32_t msg_tout : 1; /**< An expected incoming message request has not been
2070 received within the time-out interval specified in
2071 SRIOMAINT(0,2..3)_PORT_RT_CTL. When a MSG_TOUT occurs,
2072 SRIO (internally) terminates the inflight message
2074 uint32_t pkt_tout : 1; /**< A required response has not been received to an
2075 outgoing memory, maintenance or message request
2076 before the time-out interval specified in
2077 SRIOMAINT(0,2..3)_PORT_RT_CTL. When an IO or maintenance
2078 read request operation has a PKT_TOUT, the issuing
2079 core load or DPI DMA engine receive all ones for
2080 the result. When an IO NWRITE_R has a PKT_TOUT,
2081 this bit is the only indication of failure. When a
2082 message request operation has a PKT_TOUT, SRIO
2083 discards the the outgoing message segment, and
2084 this bit is the only direct indication of failure.
2085 NOTE: SRIO may continue to send or retry other
2086 segments from the same message. When one or more of
2087 the segments in an outgoing message have a
2088 PKT_TOUT, SRIO will not set SRIO*_INT_REG[OMSG*]
2089 after the message "transfer". */
2090 uint32_t uns_resp : 1; /**< An unsolicited/unexpected memory, maintenance or
2091 message response packet was received that was not
2092 destined for the RX Soft Packet FIFO. When this
2093 condition is detected, the packet is dropped. */
2094 uint32_t uns_tran : 1; /**< A transaction is received that is not supported.
2095 SRIO HW will never set this bit - SRIO routes all
2096 unsupported transactions to the RX soft packet
2098 uint32_t reserved_1_21 : 21;
2099 uint32_t resp_sz : 1; /**< Received an incoming Memory or Maintenance
2100 Read response packet with a DONE status and less
2101 data then expected. This condition causes the
2102 Read to be completed and an error response to be
2103 returned with all the data bits set to the issuing
2104 Core or DMA Engine. */
2106 uint32_t resp_sz : 1;
2107 uint32_t reserved_1_21 : 21;
2108 uint32_t uns_tran : 1;
2109 uint32_t uns_resp : 1;
2110 uint32_t pkt_tout : 1;
2111 uint32_t msg_tout : 1;
2112 uint32_t ill_tgt : 1;
2113 uint32_t ill_tran : 1;
2114 uint32_t msg_fmt : 1;
2115 uint32_t gsm_err : 1;
2116 uint32_t msg_err : 1;
2117 uint32_t io_err : 1;
2120 struct cvmx_sriomaintx_erb_lt_err_det_s cn63xx;
2121 struct cvmx_sriomaintx_erb_lt_err_det_s cn63xxp1;
2122 struct cvmx_sriomaintx_erb_lt_err_det_s cn66xx;
2124 typedef union cvmx_sriomaintx_erb_lt_err_det cvmx_sriomaintx_erb_lt_err_det_t;
2127 * cvmx_sriomaint#_erb_lt_err_en
2129 * SRIOMAINT_ERB_LT_ERR_EN = SRIO Logical/Transport Layer Error Enable
2131 * SRIO Logical/Transport Layer Error Enable
2134 * This register contains the bits that control if an error condition locks the Logical/Transport
2135 * Layer Error Detect and Capture registers and is reported to the system host.
2137 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_LT_ERR_EN hclk hrst_n
2139 union cvmx_sriomaintx_erb_lt_err_en {
2141 struct cvmx_sriomaintx_erb_lt_err_en_s {
2142 #ifdef __BIG_ENDIAN_BITFIELD
2143 uint32_t io_err : 1; /**< Enable reporting of an IO error response. Save and
2144 lock original request transaction information in
2145 all Logical/Transport Layer Capture CSRs. */
2146 uint32_t msg_err : 1; /**< Enable reporting of a Message error response. Save
2147 and lock original request transaction information
2148 in all Logical/Transport Layer Capture CSRs. */
2149 uint32_t gsm_err : 1; /**< Enable reporting of a GSM error response. Save and
2150 lock original request transaction capture
2151 information in all Logical/Transport Layer Capture
2153 uint32_t msg_fmt : 1; /**< Enable reporting of a message format error. Save
2154 and lock transaction capture information in
2155 Logical/Transport Layer Device ID and Control
2157 uint32_t ill_tran : 1; /**< Enable reporting of an illegal transaction decode
2158 error Save and lock transaction capture
2159 information in Logical/Transport Layer Device ID
2160 and Control Capture CSRs. */
2161 uint32_t ill_tgt : 1; /**< Enable reporting of an illegal transaction target
2162 error. Save and lock transaction capture
2163 information in Logical/Transport Layer Device ID
2164 and Control Capture CSRs. */
2165 uint32_t msg_tout : 1; /**< Enable reporting of a Message Request time-out
2166 error. Save and lock transaction capture
2167 information in Logical/Transport Layer Device ID
2168 and Control Capture CSRs for the last Message
2169 request segment packet received. */
2170 uint32_t pkt_tout : 1; /**< Enable reporting of a packet response time-out
2171 error. Save and lock original request address in
2172 Logical/Transport Layer Address Capture CSRs.
2173 Save and lock original request Destination ID in
2174 Logical/Transport Layer Device ID Capture CSR. */
2175 uint32_t uns_resp : 1; /**< Enable reporting of an unsolicited response error.
2176 Save and lock transaction capture information in
2177 Logical/Transport Layer Device ID and Control
2179 uint32_t uns_tran : 1; /**< Enable reporting of an unsupported transaction
2180 error. Save and lock transaction capture
2181 information in Logical/Transport Layer Device ID
2182 and Control Capture CSRs. */
2183 uint32_t reserved_1_21 : 21;
2184 uint32_t resp_sz : 1; /**< Enable reporting of an incoming response with
2185 unexpected data size */
2187 uint32_t resp_sz : 1;
2188 uint32_t reserved_1_21 : 21;
2189 uint32_t uns_tran : 1;
2190 uint32_t uns_resp : 1;
2191 uint32_t pkt_tout : 1;
2192 uint32_t msg_tout : 1;
2193 uint32_t ill_tgt : 1;
2194 uint32_t ill_tran : 1;
2195 uint32_t msg_fmt : 1;
2196 uint32_t gsm_err : 1;
2197 uint32_t msg_err : 1;
2198 uint32_t io_err : 1;
2201 struct cvmx_sriomaintx_erb_lt_err_en_s cn63xx;
2202 struct cvmx_sriomaintx_erb_lt_err_en_s cn63xxp1;
2203 struct cvmx_sriomaintx_erb_lt_err_en_s cn66xx;
2205 typedef union cvmx_sriomaintx_erb_lt_err_en cvmx_sriomaintx_erb_lt_err_en_t;
2208 * cvmx_sriomaint#_erb_pack_capt_1
2210 * SRIOMAINT_ERB_PACK_CAPT_1 = SRIO Packet Capture 1
2215 * Error capture register 1 contains either long symbol capture information or bytes 4 through 7 of
2216 * the packet header.
2217 * The HW will not update this register (i.e. this register is locked) while
2218 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set.
2220 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_1 hclk hrst_n
2222 union cvmx_sriomaintx_erb_pack_capt_1 {
2224 struct cvmx_sriomaintx_erb_pack_capt_1_s {
2225 #ifdef __BIG_ENDIAN_BITFIELD
2226 uint32_t capture : 32; /**< Bytes 4 thru 7 of the packet header. */
2228 uint32_t capture : 32;
2231 struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xx;
2232 struct cvmx_sriomaintx_erb_pack_capt_1_s cn63xxp1;
2233 struct cvmx_sriomaintx_erb_pack_capt_1_s cn66xx;
2235 typedef union cvmx_sriomaintx_erb_pack_capt_1 cvmx_sriomaintx_erb_pack_capt_1_t;
2238 * cvmx_sriomaint#_erb_pack_capt_2
2240 * SRIOMAINT_ERB_PACK_CAPT_2 = SRIO Packet Capture 2
2245 * Error capture register 2 contains bytes 8 through 11 of the packet header.
2246 * The HW will not update this register (i.e. this register is locked) while
2247 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set.
2249 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_2 hclk hrst_n
2251 union cvmx_sriomaintx_erb_pack_capt_2 {
2253 struct cvmx_sriomaintx_erb_pack_capt_2_s {
2254 #ifdef __BIG_ENDIAN_BITFIELD
2255 uint32_t capture : 32; /**< Bytes 8 thru 11 of the packet header. */
2257 uint32_t capture : 32;
2260 struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xx;
2261 struct cvmx_sriomaintx_erb_pack_capt_2_s cn63xxp1;
2262 struct cvmx_sriomaintx_erb_pack_capt_2_s cn66xx;
2264 typedef union cvmx_sriomaintx_erb_pack_capt_2 cvmx_sriomaintx_erb_pack_capt_2_t;
2267 * cvmx_sriomaint#_erb_pack_capt_3
2269 * SRIOMAINT_ERB_PACK_CAPT_3 = SRIO Packet Capture 3
2274 * Error capture register 3 contains bytes 12 through 15 of the packet header.
2275 * The HW will not update this register (i.e. this register is locked) while
2276 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set.
2278 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_CAPT_3 hclk hrst_n
2280 union cvmx_sriomaintx_erb_pack_capt_3 {
2282 struct cvmx_sriomaintx_erb_pack_capt_3_s {
2283 #ifdef __BIG_ENDIAN_BITFIELD
2284 uint32_t capture : 32; /**< Bytes 12 thru 15 of the packet header. */
2286 uint32_t capture : 32;
2289 struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xx;
2290 struct cvmx_sriomaintx_erb_pack_capt_3_s cn63xxp1;
2291 struct cvmx_sriomaintx_erb_pack_capt_3_s cn66xx;
2293 typedef union cvmx_sriomaintx_erb_pack_capt_3 cvmx_sriomaintx_erb_pack_capt_3_t;
2296 * cvmx_sriomaint#_erb_pack_sym_capt
2298 * SRIOMAINT_ERB_PACK_SYM_CAPT = SRIO Packet/Control Symbol Capture
2300 * Packet/Control Symbol Capture
2303 * This register contains either captured control symbol information or the first 4 bytes of captured
2304 * packet information. The Errors that generate Partial Control Symbols can be found in
2305 * SRIOMAINT*_ERB_ERR_DET. The HW will not update this register (i.e. this register is locked) while
2306 * SRIOMAINT*_ERB_ATTR_CAPT[VALID] is set. This register should only be read while this bit is set.
2308 * Clk_Rst: SRIOMAINT(0,2..3)_ERB_PACK_SYM_CAPT hclk hrst_n
2310 union cvmx_sriomaintx_erb_pack_sym_capt {
2312 struct cvmx_sriomaintx_erb_pack_sym_capt_s {
2313 #ifdef __BIG_ENDIAN_BITFIELD
2314 uint32_t capture : 32; /**< Control Character and Control Symbol or Bytes 0 to
2316 The Control Symbol consists of
2317 - 31:24 - SC Character (0 in Partial Symbol)
2319 - 20:16 - Parameter 0
2320 - 15:11 - Parameter 1
2321 - 10: 8 - Stype 1 (0 in Partial Symbol)
2322 - 7: 5 - Command (0 in Partial Symbol)
2323 - 4: 0 - CRC5 (0 in Partial Symbol) */
2325 uint32_t capture : 32;
2328 struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xx;
2329 struct cvmx_sriomaintx_erb_pack_sym_capt_s cn63xxp1;
2330 struct cvmx_sriomaintx_erb_pack_sym_capt_s cn66xx;
2332 typedef union cvmx_sriomaintx_erb_pack_sym_capt cvmx_sriomaintx_erb_pack_sym_capt_t;
2335 * cvmx_sriomaint#_hb_dev_id_lock
2337 * SRIOMAINT_HB_DEV_ID_LOCK = SRIO Host Device ID Lock
2339 * The Host Base Device ID
2342 * This register contains the Device ID of the Host responsible for initializing this SRIO device.
2343 * The register contains a special write once function that captures the first HOSTID written to it
2344 * after reset. The function allows several potential hosts to write to this register and then read
2345 * it to see if they have responsibility for initialization. The register can be unlocked by
2346 * rewriting the current host value. This will reset the lock and restore the value to 0xFFFF.
2348 * Clk_Rst: SRIOMAINT(0,2..3)_HB_DEV_ID_LOCK hclk hrst_n
2350 union cvmx_sriomaintx_hb_dev_id_lock {
2352 struct cvmx_sriomaintx_hb_dev_id_lock_s {
2353 #ifdef __BIG_ENDIAN_BITFIELD
2354 uint32_t reserved_16_31 : 16;
2355 uint32_t hostid : 16; /**< Primary 16-bit Device ID */
2357 uint32_t hostid : 16;
2358 uint32_t reserved_16_31 : 16;
2361 struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xx;
2362 struct cvmx_sriomaintx_hb_dev_id_lock_s cn63xxp1;
2363 struct cvmx_sriomaintx_hb_dev_id_lock_s cn66xx;
2365 typedef union cvmx_sriomaintx_hb_dev_id_lock cvmx_sriomaintx_hb_dev_id_lock_t;
2368 * cvmx_sriomaint#_ir_buffer_config
2370 * SRIOMAINT_IR_BUFFER_CONFIG = SRIO Buffer Configuration
2372 * Buffer Configuration
2375 * This register controls the operation of the SRIO Core buffer mux logic.
2377 * Clk_Rst: SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG hclk hrst_n
2379 union cvmx_sriomaintx_ir_buffer_config {
2381 struct cvmx_sriomaintx_ir_buffer_config_s {
2382 #ifdef __BIG_ENDIAN_BITFIELD
2383 uint32_t tx_wm0 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
2384 uint32_t tx_wm1 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
2385 uint32_t tx_wm2 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
2386 uint32_t reserved_3_19 : 17;
2387 uint32_t tx_flow : 1; /**< Controls whether Transmitter Flow Control is
2388 permitted on this device.
2391 The reset value of this field is
2392 SRIO*_IP_FEATURE[TX_FLOW]. */
2393 uint32_t tx_sync : 1; /**< Reserved. */
2394 uint32_t rx_sync : 1; /**< Reserved. */
2396 uint32_t rx_sync : 1;
2397 uint32_t tx_sync : 1;
2398 uint32_t tx_flow : 1;
2399 uint32_t reserved_3_19 : 17;
2400 uint32_t tx_wm2 : 4;
2401 uint32_t tx_wm1 : 4;
2402 uint32_t tx_wm0 : 4;
2405 struct cvmx_sriomaintx_ir_buffer_config_s cn63xx;
2406 struct cvmx_sriomaintx_ir_buffer_config_s cn63xxp1;
2407 struct cvmx_sriomaintx_ir_buffer_config_s cn66xx;
2409 typedef union cvmx_sriomaintx_ir_buffer_config cvmx_sriomaintx_ir_buffer_config_t;
2412 * cvmx_sriomaint#_ir_buffer_config2
2414 * SRIOMAINT_IR_BUFFER_CONFIG2 = SRIO Buffer Configuration 2
2416 * Buffer Configuration 2
2419 * This register controls the RX and TX Buffer availablility by priority. The typical values are
2420 * optimized for normal operation. Care must be taken when changing these values to avoid values
2421 * which can result in deadlocks. Disabling a priority is not recommended and can result in system
2424 * Clk_Rst: SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2 hclk hrst_n
2426 union cvmx_sriomaintx_ir_buffer_config2 {
2428 struct cvmx_sriomaintx_ir_buffer_config2_s {
2429 #ifdef __BIG_ENDIAN_BITFIELD
2430 uint32_t tx_wm3 : 4; /**< Number of buffers free before a priority 3 packet
2431 will be transmitted. A value of 9 will disable
2433 uint32_t tx_wm2 : 4; /**< Number of buffers free before a priority 2 packet
2434 will be transmitted. A value of 9 will disable
2436 uint32_t tx_wm1 : 4; /**< Number of buffers free before a priority 1 packet
2437 will be transmitted. A value of 9 will disable
2439 uint32_t tx_wm0 : 4; /**< Number of buffers free before a priority 0 packet
2440 will be transmitted. A value of 9 will disable
2442 uint32_t rx_wm3 : 4; /**< Number of buffers free before a priority 3 packet
2443 will be accepted. A value of 9 will disable this
2444 priority and always cause a physical layer RETRY. */
2445 uint32_t rx_wm2 : 4; /**< Number of buffers free before a priority 2 packet
2446 will be accepted. A value of 9 will disable this
2447 priority and always cause a physical layer RETRY. */
2448 uint32_t rx_wm1 : 4; /**< Number of buffers free before a priority 1 packet
2449 will be accepted. A value of 9 will disable this
2450 priority and always cause a physical layer RETRY. */
2451 uint32_t rx_wm0 : 4; /**< Number of buffers free before a priority 0 packet
2452 will be accepted. A value of 9 will disable this
2453 priority and always cause a physical layer RETRY. */
2455 uint32_t rx_wm0 : 4;
2456 uint32_t rx_wm1 : 4;
2457 uint32_t rx_wm2 : 4;
2458 uint32_t rx_wm3 : 4;
2459 uint32_t tx_wm0 : 4;
2460 uint32_t tx_wm1 : 4;
2461 uint32_t tx_wm2 : 4;
2462 uint32_t tx_wm3 : 4;
2465 struct cvmx_sriomaintx_ir_buffer_config2_s cn63xx;
2466 struct cvmx_sriomaintx_ir_buffer_config2_s cn66xx;
2468 typedef union cvmx_sriomaintx_ir_buffer_config2 cvmx_sriomaintx_ir_buffer_config2_t;
2471 * cvmx_sriomaint#_ir_pd_phy_ctrl
2473 * SRIOMAINT_IR_PD_PHY_CTRL = SRIO Platform Dependent PHY Control
2475 * Platform Dependent PHY Control
2478 * This register can be used for testing. The register is otherwise unused by the hardware.
2480 * Clk_Rst: SRIOMAINT(0,2..3)_IR_PD_PHY_CTRL hclk hrst_n
2482 union cvmx_sriomaintx_ir_pd_phy_ctrl {
2484 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s {
2485 #ifdef __BIG_ENDIAN_BITFIELD
2486 uint32_t pd_ctrl : 32; /**< Unused Register available for testing */
2488 uint32_t pd_ctrl : 32;
2491 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xx;
2492 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn63xxp1;
2493 struct cvmx_sriomaintx_ir_pd_phy_ctrl_s cn66xx;
2495 typedef union cvmx_sriomaintx_ir_pd_phy_ctrl cvmx_sriomaintx_ir_pd_phy_ctrl_t;
2498 * cvmx_sriomaint#_ir_pd_phy_stat
2500 * SRIOMAINT_IR_PD_PHY_STAT = SRIO Platform Dependent PHY Status
2502 * Platform Dependent PHY Status
2505 * This register is used to monitor PHY status on each lane. They are documented here to assist in
2506 * debugging only. The lane numbers take into account the lane swap pin.
2508 * Clk_Rst: SRIOMAINT(0,2..3)_IR_PD_PHY_STAT hclk hrst_n
2510 union cvmx_sriomaintx_ir_pd_phy_stat {
2512 struct cvmx_sriomaintx_ir_pd_phy_stat_s {
2513 #ifdef __BIG_ENDIAN_BITFIELD
2514 uint32_t reserved_16_31 : 16;
2515 uint32_t ln3_rx : 3; /**< Phy Lane 3 RX Status
2516 0XX = Normal Operation
2518 101 = Elastic Buffer Overflow (Data Lost)
2519 110 = Elastic Buffer Underflow (Data Corrupted)
2520 111 = Disparity Error */
2521 uint32_t ln3_dis : 1; /**< Lane 3 Phy Clock Disabled
2523 1 = Phy Clock InValid */
2524 uint32_t ln2_rx : 3; /**< Phy Lane 2 RX Status
2525 0XX = Normal Operation
2527 101 = Elastic Buffer Overflow (Data Lost)
2528 110 = Elastic Buffer Underflow (Data Corrupted)
2529 111 = Disparity Error */
2530 uint32_t ln2_dis : 1; /**< Lane 2 Phy Clock Disabled
2532 1 = Phy Clock InValid */
2533 uint32_t ln1_rx : 3; /**< Phy Lane 1 RX Status
2534 0XX = Normal Operation
2536 101 = Elastic Buffer Overflow (Data Lost)
2537 110 = Elastic Buffer Underflow (Data Corrupted)
2538 111 = Disparity Error */
2539 uint32_t ln1_dis : 1; /**< Lane 1 Phy Clock Disabled
2541 1 = Phy Clock InValid */
2542 uint32_t ln0_rx : 3; /**< Phy Lane 0 RX Status
2543 0XX = Normal Operation
2545 101 = Elastic Buffer Overflow (Data Lost)
2546 110 = Elastic Buffer Underflow (Data Corrupted)
2547 111 = Disparity Error */
2548 uint32_t ln0_dis : 1; /**< Lane 0 Phy Clock Disabled
2550 1 = Phy Clock InValid */
2552 uint32_t ln0_dis : 1;
2553 uint32_t ln0_rx : 3;
2554 uint32_t ln1_dis : 1;
2555 uint32_t ln1_rx : 3;
2556 uint32_t ln2_dis : 1;
2557 uint32_t ln2_rx : 3;
2558 uint32_t ln3_dis : 1;
2559 uint32_t ln3_rx : 3;
2560 uint32_t reserved_16_31 : 16;
2563 struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xx;
2564 struct cvmx_sriomaintx_ir_pd_phy_stat_s cn63xxp1;
2565 struct cvmx_sriomaintx_ir_pd_phy_stat_s cn66xx;
2567 typedef union cvmx_sriomaintx_ir_pd_phy_stat cvmx_sriomaintx_ir_pd_phy_stat_t;
2570 * cvmx_sriomaint#_ir_pi_phy_ctrl
2572 * SRIOMAINT_IR_PI_PHY_CTRL = SRIO Platform Independent PHY Control
2574 * Platform Independent PHY Control
2577 * This register is used to control platform independent operating modes of the transceivers. These
2578 * control bits are uniform across all platforms.
2580 * Clk_Rst: SRIOMAINT(0,2..3)_IR_PI_PHY_CTRL hclk hrst_n
2582 union cvmx_sriomaintx_ir_pi_phy_ctrl {
2584 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s {
2585 #ifdef __BIG_ENDIAN_BITFIELD
2586 uint32_t tx_reset : 1; /**< Outgoing PHY Logic Reset. 0=Reset, 1=Normal Op */
2587 uint32_t rx_reset : 1; /**< Incoming PHY Logic Reset. 0=Reset, 1=Normal Op */
2588 uint32_t reserved_29_29 : 1;
2589 uint32_t loopback : 2; /**< These bits control the state of the loopback
2590 control vector on the transceiver interface. The
2591 loopback modes are enumerated as follows:
2593 01 - Near End PCS Loopback
2594 10 - Far End PCS Loopback
2595 11 - Both Near and Far End PCS Loopback */
2596 uint32_t reserved_0_26 : 27;
2598 uint32_t reserved_0_26 : 27;
2599 uint32_t loopback : 2;
2600 uint32_t reserved_29_29 : 1;
2601 uint32_t rx_reset : 1;
2602 uint32_t tx_reset : 1;
2605 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xx;
2606 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn63xxp1;
2607 struct cvmx_sriomaintx_ir_pi_phy_ctrl_s cn66xx;
2609 typedef union cvmx_sriomaintx_ir_pi_phy_ctrl cvmx_sriomaintx_ir_pi_phy_ctrl_t;
2612 * cvmx_sriomaint#_ir_pi_phy_stat
2614 * SRIOMAINT_IR_PI_PHY_STAT = SRIO Platform Independent PHY Status
2616 * Platform Independent PHY Status
2619 * This register displays the status of the link initialization state machine. Changes to this state
2620 * cause the SRIO(0,2..3)_INT_REG.LINK_UP or SRIO(0,2..3)_INT_REG.LINK_DOWN interrupts.
2622 * Clk_Rst: SRIOMAINT(0,2..3)_IR_PI_PHY_STAT hclk hrst_n
2624 union cvmx_sriomaintx_ir_pi_phy_stat {
2626 struct cvmx_sriomaintx_ir_pi_phy_stat_s {
2627 #ifdef __BIG_ENDIAN_BITFIELD
2628 uint32_t reserved_12_31 : 20;
2629 uint32_t tx_rdy : 1; /**< Minimum number of Status Transmitted */
2630 uint32_t rx_rdy : 1; /**< Minimum number of Good Status Received */
2631 uint32_t init_sm : 10; /**< Initialization State Machine
2642 All others are reserved */
2644 uint32_t init_sm : 10;
2645 uint32_t rx_rdy : 1;
2646 uint32_t tx_rdy : 1;
2647 uint32_t reserved_12_31 : 20;
2650 struct cvmx_sriomaintx_ir_pi_phy_stat_s cn63xx;
2651 struct cvmx_sriomaintx_ir_pi_phy_stat_cn63xxp1 {
2652 #ifdef __BIG_ENDIAN_BITFIELD
2653 uint32_t reserved_10_31 : 22;
2654 uint32_t init_sm : 10; /**< Initialization State Machine
2665 All others are reserved */
2667 uint32_t init_sm : 10;
2668 uint32_t reserved_10_31 : 22;
2671 struct cvmx_sriomaintx_ir_pi_phy_stat_s cn66xx;
2673 typedef union cvmx_sriomaintx_ir_pi_phy_stat cvmx_sriomaintx_ir_pi_phy_stat_t;
2676 * cvmx_sriomaint#_ir_sp_rx_ctrl
2678 * SRIOMAINT_IR_SP_RX_CTRL = SRIO Soft Packet FIFO Receive Control
2680 * Soft Packet FIFO Receive Control
2683 * This register is used to configure events generated by the reception of packets using the soft
2686 * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_CTRL hclk hrst_n
2688 union cvmx_sriomaintx_ir_sp_rx_ctrl {
2690 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s {
2691 #ifdef __BIG_ENDIAN_BITFIELD
2692 uint32_t reserved_1_31 : 31;
2693 uint32_t overwrt : 1; /**< When clear, SRIO drops received packets that should
2694 enter the soft packet FIFO when the FIFO is full.
2695 In this case, SRIO also increments
2696 SRIOMAINT(0,2..3)_IR_SP_RX_STAT.DROP_CNT. When set, SRIO
2697 stalls received packets that should enter the soft
2698 packet FIFO when the FIFO is full. SRIO may stop
2699 receiving any packets in this stall case if
2700 software does not drain the receive soft packet
2703 uint32_t overwrt : 1;
2704 uint32_t reserved_1_31 : 31;
2707 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xx;
2708 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn63xxp1;
2709 struct cvmx_sriomaintx_ir_sp_rx_ctrl_s cn66xx;
2711 typedef union cvmx_sriomaintx_ir_sp_rx_ctrl cvmx_sriomaintx_ir_sp_rx_ctrl_t;
2714 * cvmx_sriomaint#_ir_sp_rx_data
2716 * SRIOMAINT_IR_SP_RX_DATA = SRIO Soft Packet FIFO Receive Data
2718 * Soft Packet FIFO Receive Data
2721 * This register is used to read data from the soft packet FIFO. The Soft Packet FIFO contains the
2722 * majority of the packet data received from the SRIO link. The packet does not include the Control
2723 * Symbols or the initial byte containing AckId, 2 Reserved Bits and the CRF. In the case of packets
2724 * with less than 80 bytes (including AckId byte) both the trailing CRC and Pad (if present) are
2725 * included in the FIFO and Octet Count. In the case of a packet with exactly 80 bytes (including
2726 * the AckId byte) the CRC is removed and the Pad is maintained so the Octet Count will read 81 bytes
2727 * instead of the expected 83. In cases over 80 bytes the CRC at 80 bytes is removed but the
2728 * trailing CRC and Pad (if necessary) are present.
2730 * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_DATA hclk hrst_n
2732 union cvmx_sriomaintx_ir_sp_rx_data {
2734 struct cvmx_sriomaintx_ir_sp_rx_data_s {
2735 #ifdef __BIG_ENDIAN_BITFIELD
2736 uint32_t pkt_data : 32; /**< This register is used to read packet data from the
2739 uint32_t pkt_data : 32;
2742 struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xx;
2743 struct cvmx_sriomaintx_ir_sp_rx_data_s cn63xxp1;
2744 struct cvmx_sriomaintx_ir_sp_rx_data_s cn66xx;
2746 typedef union cvmx_sriomaintx_ir_sp_rx_data cvmx_sriomaintx_ir_sp_rx_data_t;
2749 * cvmx_sriomaint#_ir_sp_rx_stat
2751 * SRIOMAINT_IR_SP_RX_STAT = SRIO Soft Packet FIFO Receive Status
2753 * Soft Packet FIFO Receive Status
2756 * This register is used to monitor the reception of packets using the soft packet FIFO.
2757 * The HW sets SRIO_INT_REG[SOFT_RX] every time a packet arrives in the soft packet FIFO. To read
2758 * out (one or more) packets, the following procedure may be best:
2759 * (1) clear SRIO_INT_REG[SOFT_RX],
2760 * (2) read this CSR to determine how many packets there are,
2761 * (3) read the packets out (via SRIOMAINT*_IR_SP_RX_DATA).
2762 * This procedure could lead to situations where SOFT_RX will be set even though there are currently
2763 * no packets - the SW interrupt handler would need to properly handle this case
2765 * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_RX_STAT hclk hrst_n
2767 union cvmx_sriomaintx_ir_sp_rx_stat {
2769 struct cvmx_sriomaintx_ir_sp_rx_stat_s {
2770 #ifdef __BIG_ENDIAN_BITFIELD
2771 uint32_t octets : 16; /**< This field shows how many octets are remaining
2772 in the current packet in the RX FIFO. */
2773 uint32_t buffers : 4; /**< This field indicates how many complete packets are
2774 stored in the Rx FIFO. */
2775 uint32_t drop_cnt : 7; /**< Number of Packets Received when the RX FIFO was
2776 full and then discarded. */
2777 uint32_t full : 1; /**< This bit is set when the value of Buffers Filled
2778 equals the number of available reception buffers. */
2779 uint32_t fifo_st : 4; /**< These bits display the state of the state machine
2780 that controls loading of packet data into the RX
2781 FIFO. The enumeration of states are as follows:
2785 All other states are reserved. */
2787 uint32_t fifo_st : 4;
2789 uint32_t drop_cnt : 7;
2790 uint32_t buffers : 4;
2791 uint32_t octets : 16;
2794 struct cvmx_sriomaintx_ir_sp_rx_stat_s cn63xx;
2795 struct cvmx_sriomaintx_ir_sp_rx_stat_cn63xxp1 {
2796 #ifdef __BIG_ENDIAN_BITFIELD
2797 uint32_t octets : 16; /**< This field shows how many octets are remaining
2798 in the current packet in the RX FIFO. */
2799 uint32_t buffers : 4; /**< This field indicates how many complete packets are
2800 stored in the Rx FIFO. */
2801 uint32_t reserved_5_11 : 7;
2802 uint32_t full : 1; /**< This bit is set when the value of Buffers Filled
2803 equals the number of available reception buffers.
2804 This bit always reads zero in Pass 1 */
2805 uint32_t fifo_st : 4; /**< These bits display the state of the state machine
2806 that controls loading of packet data into the RX
2807 FIFO. The enumeration of states are as follows:
2811 All other states are reserved. */
2813 uint32_t fifo_st : 4;
2815 uint32_t reserved_5_11 : 7;
2816 uint32_t buffers : 4;
2817 uint32_t octets : 16;
2820 struct cvmx_sriomaintx_ir_sp_rx_stat_s cn66xx;
2822 typedef union cvmx_sriomaintx_ir_sp_rx_stat cvmx_sriomaintx_ir_sp_rx_stat_t;
2825 * cvmx_sriomaint#_ir_sp_tx_ctrl
2827 * SRIOMAINT_IR_SP_TX_CTRL = SRIO Soft Packet FIFO Transmit Control
2829 * Soft Packet FIFO Transmit Control
2832 * This register is used to configure and control the transmission of packets using the soft packet
2835 * Clk_Rst: SRIOMAINT_IR_SP_TX_CTRL hclk hrst_n
2837 union cvmx_sriomaintx_ir_sp_tx_ctrl {
2839 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s {
2840 #ifdef __BIG_ENDIAN_BITFIELD
2841 uint32_t octets : 16; /**< Writing a non-zero value (N) to this field arms
2842 the packet FIFO for packet transmission. The FIFO
2843 control logic will transmit the next N bytes
2844 written 4-bytes at a time to the
2845 SRIOMAINT(0,2..3)_IR_SP_TX_DATA Register and create a
2846 single RapidIO packet. */
2847 uint32_t reserved_0_15 : 16;
2849 uint32_t reserved_0_15 : 16;
2850 uint32_t octets : 16;
2853 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xx;
2854 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn63xxp1;
2855 struct cvmx_sriomaintx_ir_sp_tx_ctrl_s cn66xx;
2857 typedef union cvmx_sriomaintx_ir_sp_tx_ctrl cvmx_sriomaintx_ir_sp_tx_ctrl_t;
2860 * cvmx_sriomaint#_ir_sp_tx_data
2862 * SRIOMAINT_IR_SP_TX_DATA = SRIO Soft Packet FIFO Transmit Data
2864 * Soft Packet FIFO Transmit Data
2867 * This register is used to write data to the soft packet FIFO. The format of the packet follows the
2868 * Internal Packet Format (add link here). Care must be taken on creating TIDs for the packets which
2869 * generate a response. Bits [7:6] of the 8 bit TID must be set for all Soft Packet FIFO generated
2870 * packets. TID values of 0x00 - 0xBF are reserved for hardware generated Tags. The remainer of the
2871 * TID[5:0] must be unique for each packet in flight and cannot be reused until a response is received
2872 * in the SRIOMAINT(0,2..3)_IR_SP_RX_DATA register.
2874 * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_TX_DATA hclk hrst_n
2876 union cvmx_sriomaintx_ir_sp_tx_data {
2878 struct cvmx_sriomaintx_ir_sp_tx_data_s {
2879 #ifdef __BIG_ENDIAN_BITFIELD
2880 uint32_t pkt_data : 32; /**< This register is used to write packet data to the
2881 Tx FIFO. Reads of this register will return zero. */
2883 uint32_t pkt_data : 32;
2886 struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xx;
2887 struct cvmx_sriomaintx_ir_sp_tx_data_s cn63xxp1;
2888 struct cvmx_sriomaintx_ir_sp_tx_data_s cn66xx;
2890 typedef union cvmx_sriomaintx_ir_sp_tx_data cvmx_sriomaintx_ir_sp_tx_data_t;
2893 * cvmx_sriomaint#_ir_sp_tx_stat
2895 * SRIOMAINT_IR_SP_TX_STAT = SRIO Soft Packet FIFO Transmit Status
2897 * Soft Packet FIFO Transmit Status
2900 * This register is used to monitor the transmission of packets using the soft packet FIFO.
2902 * Clk_Rst: SRIOMAINT(0,2..3)_IR_SP_TX_STAT hclk hrst_n
2904 union cvmx_sriomaintx_ir_sp_tx_stat {
2906 struct cvmx_sriomaintx_ir_sp_tx_stat_s {
2907 #ifdef __BIG_ENDIAN_BITFIELD
2908 uint32_t octets : 16; /**< This field shows how many octets are still to be
2909 loaded in the current packet. */
2910 uint32_t buffers : 4; /**< This field indicates how many complete packets are
2911 stored in the Tx FIFO. The field always reads
2912 zero in the current hardware. */
2913 uint32_t reserved_5_11 : 7;
2914 uint32_t full : 1; /**< This bit is set when the value of Buffers Filled
2915 equals the number of available transmission
2917 uint32_t fifo_st : 4; /**< These bits display the state of the state machine
2918 that controls loading of packet data into the TX
2919 FIFO. The enumeration of states are as follows:
2923 All other states are reserved. */
2925 uint32_t fifo_st : 4;
2927 uint32_t reserved_5_11 : 7;
2928 uint32_t buffers : 4;
2929 uint32_t octets : 16;
2932 struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xx;
2933 struct cvmx_sriomaintx_ir_sp_tx_stat_s cn63xxp1;
2934 struct cvmx_sriomaintx_ir_sp_tx_stat_s cn66xx;
2936 typedef union cvmx_sriomaintx_ir_sp_tx_stat cvmx_sriomaintx_ir_sp_tx_stat_t;
2939 * cvmx_sriomaint#_lane_#_status_0
2941 * SRIOMAINT_LANE_X_STATUS_0 = SRIO Lane X Status 0
2943 * SRIO Lane Status 0
2946 * This register contains status information about the local lane transceiver.
2948 * Clk_Rst: SRIOMAINT(0,2..3)_LANE_[0:3]_STATUS_0 hclk hrst_n
2950 union cvmx_sriomaintx_lane_x_status_0 {
2952 struct cvmx_sriomaintx_lane_x_status_0_s {
2953 #ifdef __BIG_ENDIAN_BITFIELD
2954 uint32_t port : 8; /**< The number of the port within the device to which
2955 the lane is assigned. */
2956 uint32_t lane : 4; /**< Lane Number within the port. */
2957 uint32_t tx_type : 1; /**< Transmitter Type
2960 uint32_t tx_mode : 1; /**< Transmitter Operating Mode
2963 uint32_t rx_type : 2; /**< Receiver Type
2968 uint32_t rx_inv : 1; /**< Receiver Input Inverted
2970 1 = Input Inverted */
2971 uint32_t rx_adapt : 1; /**< Receiver Trained
2972 0 = One or more adaptive equalizers are
2973 controlled by the lane receiver and at least
2975 1 = The lane receiver controls no adaptive
2976 equalizers or all the equalizers are trained. */
2977 uint32_t rx_sync : 1; /**< Receiver Lane Sync'd */
2978 uint32_t rx_train : 1; /**< Receiver Lane Trained */
2979 uint32_t dec_err : 4; /**< 8Bit/10Bit Decoding Errors
2980 0 = No Errors since last read
2981 1-14 = Number of Errors since last read
2982 15 = Fifteen or more Errors since last read */
2983 uint32_t xsync : 1; /**< Receiver Lane Sync Change
2984 0 = Lane Sync has not changed since last read
2985 1 = Lane Sync has changed since last read */
2986 uint32_t xtrain : 1; /**< Receiver Training Change
2987 0 = Training has not changed since last read
2988 1 = Training has changed since last read */
2989 uint32_t reserved_4_5 : 2;
2990 uint32_t status1 : 1; /**< Status 1 CSR Implemented */
2991 uint32_t statusn : 3; /**< Status 2-7 Not Implemented */
2993 uint32_t statusn : 3;
2994 uint32_t status1 : 1;
2995 uint32_t reserved_4_5 : 2;
2996 uint32_t xtrain : 1;
2998 uint32_t dec_err : 4;
2999 uint32_t rx_train : 1;
3000 uint32_t rx_sync : 1;
3001 uint32_t rx_adapt : 1;
3002 uint32_t rx_inv : 1;
3003 uint32_t rx_type : 2;
3004 uint32_t tx_mode : 1;
3005 uint32_t tx_type : 1;
3010 struct cvmx_sriomaintx_lane_x_status_0_s cn63xx;
3011 struct cvmx_sriomaintx_lane_x_status_0_s cn63xxp1;
3012 struct cvmx_sriomaintx_lane_x_status_0_s cn66xx;
3014 typedef union cvmx_sriomaintx_lane_x_status_0 cvmx_sriomaintx_lane_x_status_0_t;
3017 * cvmx_sriomaint#_lcs_ba0
3019 * SRIOMAINT_LCS_BA0 = SRIO Local Configuration Space MSB Base Address
3021 * MSBs of SRIO Address Space mapped to Maintenance BAR.
3024 * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has
3025 * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Note: Address bits
3026 * not supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to
3027 * zero to match in a 34-bit access. SRIO Address 65:50 must be set to zero to match in a 50-bit
3028 * access. This coding allows the Maintenance Bar window to appear in specific address spaces. The
3029 * remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA1. This SRIO maintenance BAR is effectively
3030 * disabled when LCSBA[30] is set with 34 or 50-bit addressing.
3032 * Clk_Rst: SRIOMAINT(0,2..3)_LCS_BA0 hclk hrst_n
3034 union cvmx_sriomaintx_lcs_ba0 {
3036 struct cvmx_sriomaintx_lcs_ba0_s {
3037 #ifdef __BIG_ENDIAN_BITFIELD
3038 uint32_t reserved_31_31 : 1;
3039 uint32_t lcsba : 31; /**< SRIO Address 65:35 */
3041 uint32_t lcsba : 31;
3042 uint32_t reserved_31_31 : 1;
3045 struct cvmx_sriomaintx_lcs_ba0_s cn63xx;
3046 struct cvmx_sriomaintx_lcs_ba0_s cn63xxp1;
3047 struct cvmx_sriomaintx_lcs_ba0_s cn66xx;
3049 typedef union cvmx_sriomaintx_lcs_ba0 cvmx_sriomaintx_lcs_ba0_t;
3052 * cvmx_sriomaint#_lcs_ba1
3054 * SRIOMAINT_LCS_BA1 = SRIO Local Configuration Space LSB Base Address
3056 * LSBs of SRIO Address Space mapped to Maintenance BAR.
3059 * The double word aligned SRIO address window mapped to the SRIO Maintenance BAR. This window has
3060 * the highest priority and eclipses matches to the BAR0, BAR1 and BAR2 windows. Address bits not
3061 * supplied in the transfer are considered zero. For example, SRIO Address 65:35 must be set to zero
3062 * to match in a 34-bit access and SRIO Address 65:50 must be set to zero to match in a 50-bit access.
3063 * This coding allows the Maintenance Bar window to appear in specific address spaces. Accesses
3064 * through this BAR are limited to single word (32-bit) aligned transfers of one to four bytes.
3065 * Accesses which violate this rule will return an error response if possible and be otherwise
3066 * ignored. The remaining bits are located in SRIOMAINT(0,2..3)_LCS_BA0.
3068 * Clk_Rst: SRIOMAINT(0,2..3)_LCS_BA1 hclk hrst_n
3070 union cvmx_sriomaintx_lcs_ba1 {
3072 struct cvmx_sriomaintx_lcs_ba1_s {
3073 #ifdef __BIG_ENDIAN_BITFIELD
3074 uint32_t lcsba : 11; /**< SRIO Address 34:24 */
3075 uint32_t reserved_0_20 : 21;
3077 uint32_t reserved_0_20 : 21;
3078 uint32_t lcsba : 11;
3081 struct cvmx_sriomaintx_lcs_ba1_s cn63xx;
3082 struct cvmx_sriomaintx_lcs_ba1_s cn63xxp1;
3083 struct cvmx_sriomaintx_lcs_ba1_s cn66xx;
3085 typedef union cvmx_sriomaintx_lcs_ba1 cvmx_sriomaintx_lcs_ba1_t;
3088 * cvmx_sriomaint#_m2s_bar0_start0
3090 * SRIOMAINT_M2S_BAR0_START0 = SRIO Device Access BAR0 MSB Start
3092 * The starting SRIO address to forwarded to the NPEI Configuration Space.
3095 * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR0 Space. See
3096 * SRIOMAINT(0,2..3)_M2S_BAR0_START1 for more details. This register is only writeable over SRIO if the
3097 * SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero.
3099 * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR0_START0 hclk hrst_n
3101 union cvmx_sriomaintx_m2s_bar0_start0 {
3103 struct cvmx_sriomaintx_m2s_bar0_start0_s {
3104 #ifdef __BIG_ENDIAN_BITFIELD
3105 uint32_t addr64 : 16; /**< SRIO Address 63:48 */
3106 uint32_t addr48 : 16; /**< SRIO Address 47:32 */
3108 uint32_t addr48 : 16;
3109 uint32_t addr64 : 16;
3112 struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xx;
3113 struct cvmx_sriomaintx_m2s_bar0_start0_s cn63xxp1;
3114 struct cvmx_sriomaintx_m2s_bar0_start0_s cn66xx;
3116 typedef union cvmx_sriomaintx_m2s_bar0_start0 cvmx_sriomaintx_m2s_bar0_start0_t;
3119 * cvmx_sriomaint#_m2s_bar0_start1
3121 * SRIOMAINT_M2S_BAR0_START1 = SRIO Device Access BAR0 LSB Start
3123 * The starting SRIO address to forwarded to the NPEI Configuration Space.
3126 * This register specifies the SRIO Address mapped to the BAR0 RSL Space. If the transaction has not
3127 * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers, if
3128 * ENABLE is set and the address bits match then the SRIO Memory transactions will map to Octeon SLI
3129 * Registers. 34-bit address transactions require a match in SRIO Address 33:14 and require all the
3130 * other bits in ADDR48, ADDR64 and ADDR66 fields to be zero. 50-bit address transactions a match of
3131 * SRIO Address 49:14 and require all the other bits of ADDR64 and ADDR66 to be zero. 66-bit address
3132 * transactions require matches of all valid address field bits. Reads and Writes through Bar0
3133 * have a size limit of 8 bytes and cannot cross a 64-bit boundry. All accesses with sizes greater
3134 * than this limit will be ignored and return an error on any SRIO responses. Note: ADDR48 and
3135 * ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR0_START0. The ADDR32/66 fields of this register
3136 * are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR0 bit is zero. The ENABLE field is
3137 * writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR0 bit is zero.
3139 * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR0_START1 hclk hrst_n
3141 union cvmx_sriomaintx_m2s_bar0_start1 {
3143 struct cvmx_sriomaintx_m2s_bar0_start1_s {
3144 #ifdef __BIG_ENDIAN_BITFIELD
3145 uint32_t addr32 : 18; /**< SRIO Address 31:14 */
3146 uint32_t reserved_3_13 : 11;
3147 uint32_t addr66 : 2; /**< SRIO Address 65:64 */
3148 uint32_t enable : 1; /**< Enable BAR0 Access */
3150 uint32_t enable : 1;
3151 uint32_t addr66 : 2;
3152 uint32_t reserved_3_13 : 11;
3153 uint32_t addr32 : 18;
3156 struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xx;
3157 struct cvmx_sriomaintx_m2s_bar0_start1_s cn63xxp1;
3158 struct cvmx_sriomaintx_m2s_bar0_start1_s cn66xx;
3160 typedef union cvmx_sriomaintx_m2s_bar0_start1 cvmx_sriomaintx_m2s_bar0_start1_t;
3163 * cvmx_sriomaint#_m2s_bar1_start0
3165 * SRIOMAINT_M2S_BAR1_START0 = SRIO Device Access BAR1 MSB Start
3167 * The starting SRIO address to forwarded to the BAR1 Memory Space.
3170 * This register specifies the 50-bit and 66-bit SRIO Address mapped to the BAR1 Space. See
3171 * SRIOMAINT(0,2..3)_M2S_BAR1_START1 for more details. This register is only writeable over SRIO if the
3172 * SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero.
3174 * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR1_START0 hclk hrst_n
3176 union cvmx_sriomaintx_m2s_bar1_start0 {
3178 struct cvmx_sriomaintx_m2s_bar1_start0_s {
3179 #ifdef __BIG_ENDIAN_BITFIELD
3180 uint32_t addr64 : 16; /**< SRIO Address 63:48 */
3181 uint32_t addr48 : 16; /**< SRIO Address 47:32
3182 The SRIO hardware does not use the low order
3183 one or two bits of this field when BARSIZE is 12
3184 or 13, respectively.
3185 (BARSIZE is SRIOMAINT(0,2..3)_M2S_BAR1_START1[BARSIZE].) */
3187 uint32_t addr48 : 16;
3188 uint32_t addr64 : 16;
3191 struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xx;
3192 struct cvmx_sriomaintx_m2s_bar1_start0_s cn63xxp1;
3193 struct cvmx_sriomaintx_m2s_bar1_start0_s cn66xx;
3195 typedef union cvmx_sriomaintx_m2s_bar1_start0 cvmx_sriomaintx_m2s_bar1_start0_t;
3198 * cvmx_sriomaint#_m2s_bar1_start1
3200 * SRIOMAINT_M2S_BAR1_START1 = SRIO Device to BAR1 Start
3202 * The starting SRIO address to forwarded to the BAR1 Memory Space.
3205 * This register specifies the SRIO Address mapped to the BAR1 Space. If the transaction has not
3206 * already been mapped to SRIO Maintenance Space through the SRIOMAINT_LCS_BA[1:0] registers and the
3207 * address bits do not match enabled BAR0 addresses and if ENABLE is set and the addresses match the
3208 * BAR1 addresses then SRIO Memory transactions will map to Octeon Memory Space specified by
3209 * SRIOMAINT(0,2..3)_BAR1_IDX[31:0] registers. The BARSIZE field determines the size of BAR1, the entry
3210 * select bits, and the size of each entry. A 34-bit address matches BAR1 when it matches
3211 * SRIO_Address[33:20+BARSIZE] while all the other bits in ADDR48, ADDR64 and ADDR66 are zero.
3212 * A 50-bit address matches BAR1 when it matches SRIO_Address[49:20+BARSIZE] while all the
3213 * other bits of ADDR64 and ADDR66 are zero. A 66-bit address matches BAR1 when all of
3214 * SRIO_Address[65:20+BARSIZE] match all corresponding address CSR field bits. Note: ADDR48 and
3215 * ADDR64 fields are located in SRIOMAINT(0,2..3)_M2S_BAR1_START0. The ADDR32/66 fields of this register
3216 * are writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_ADR1 bit is zero. The remaining fields are
3217 * writeable over SRIO if the SRIO(0,2..3)_ACC_CTRL.DENY_BAR1 bit is zero.
3219 * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR1_START1 hclk hrst_n
3221 union cvmx_sriomaintx_m2s_bar1_start1 {
3223 struct cvmx_sriomaintx_m2s_bar1_start1_s {
3224 #ifdef __BIG_ENDIAN_BITFIELD
3225 uint32_t addr32 : 12; /**< SRIO Address 31:20
3226 This field is not used by the SRIO hardware for
3227 BARSIZE values 12 or 13.
3228 With BARSIZE < 12, the upper 12-BARSIZE
3229 bits of this field are used, and the lower BARSIZE
3230 bits of this field are unused by the SRIO hardware. */
3231 uint32_t reserved_7_19 : 13;
3232 uint32_t barsize : 4; /**< Bar Size.
3234 ---------------------
3236 BARSIZE BAR Entry Entry Entry
3237 Value BAR compare Select Offset Size
3239 0 1MB 65:20 19:16 15:0 64KB
3240 1 2MB 65:21 20:17 16:0 128KB
3241 2 4MB 65:22 21:18 17:0 256KB
3242 3 8MB 65:23 22:19 18:0 512KB
3243 4 16MB 65:24 23:20 19:0 1MB
3244 5 32MB 65:25 24:21 20:0 2MB
3245 6 64MB 65:26 25:22 21:0 4MB
3246 7 128MB 65:27 26:23 22:0 8MB
3247 8 256MB 65:28 27:24 23:0 16MB
3248 9 512MB 65:29 28:25 24:0 32MB
3249 10 1024MB 65:30 29:26 25:0 64MB
3250 11 2048MB 65:31 30:27 26:0 128MB
3251 12 4096MB 65:32 31:28 27:0 256MB
3252 13 8192MB 65:33 32:29 28:0 512MB
3254 *The SRIO Transaction Address
3255 The entry select bits is the X that select an
3256 SRIOMAINT(0,2..3)_BAR1_IDXX entry. */
3257 uint32_t addr66 : 2; /**< SRIO Address 65:64 */
3258 uint32_t enable : 1; /**< Enable BAR1 Access */
3260 uint32_t enable : 1;
3261 uint32_t addr66 : 2;
3262 uint32_t barsize : 4;
3263 uint32_t reserved_7_19 : 13;
3264 uint32_t addr32 : 12;
3267 struct cvmx_sriomaintx_m2s_bar1_start1_s cn63xx;
3268 struct cvmx_sriomaintx_m2s_bar1_start1_cn63xxp1 {
3269 #ifdef __BIG_ENDIAN_BITFIELD
3270 uint32_t addr32 : 12; /**< SRIO Address 31:20
3271 With BARSIZE < 12, the upper 12-BARSIZE
3272 bits of this field are used, and the lower BARSIZE
3273 bits of this field are unused by the SRIO hardware. */
3274 uint32_t reserved_6_19 : 14;
3275 uint32_t barsize : 3; /**< Bar Size.
3277 ---------------------
3279 BARSIZE BAR Entry Entry Entry
3280 Value BAR compare Select Offset Size
3282 0 1MB 65:20 19:16 15:0 64KB
3283 1 2MB 65:21 20:17 16:0 128KB
3284 2 4MB 65:22 21:18 17:0 256KB
3285 3 8MB 65:23 22:19 18:0 512KB
3286 4 16MB 65:24 23:20 19:0 1MB
3287 5 32MB 65:25 24:21 20:0 2MB
3288 6 64MB 65:26 25:22 21:0 4MB
3289 7 128MB 65:27 26:23 22:0 8MB
3290 8 256MB ** not in pass 1
3291 9 512MB ** not in pass 1
3292 10 1GB ** not in pass 1
3293 11 2GB ** not in pass 1
3294 12 4GB ** not in pass 1
3295 13 8GB ** not in pass 1
3297 *The SRIO Transaction Address
3298 The entry select bits is the X that select an
3299 SRIOMAINT(0..1)_BAR1_IDXX entry.
3301 In O63 pass 2, BARSIZE is 4 bits (6:3 in this
3302 CSR), and BARSIZE values 8-13 are implemented,
3303 providing a total possible BAR1 size range from
3305 uint32_t addr66 : 2; /**< SRIO Address 65:64 */
3306 uint32_t enable : 1; /**< Enable BAR1 Access */
3308 uint32_t enable : 1;
3309 uint32_t addr66 : 2;
3310 uint32_t barsize : 3;
3311 uint32_t reserved_6_19 : 14;
3312 uint32_t addr32 : 12;
3315 struct cvmx_sriomaintx_m2s_bar1_start1_s cn66xx;
3317 typedef union cvmx_sriomaintx_m2s_bar1_start1 cvmx_sriomaintx_m2s_bar1_start1_t;
3320 * cvmx_sriomaint#_m2s_bar2_start
3322 * SRIOMAINT_M2S_BAR2_START = SRIO Device to BAR2 Start
3324 * The starting SRIO address to forwarded to the BAR2 Memory Space.
3327 * This register specifies the SRIO Address mapped to the BAR2 Space. If ENABLE is set and the
3328 * address bits do not match and other enabled BAR address and match the BAR2 addresses then the SRIO
3329 * Memory transactions will map to Octeon BAR2 Memory Space. 34-bit address transactions require
3330 * ADDR66, ADDR64 and ADDR48 fields set to zero and supplies zeros for unused addresses 40:34.
3331 * 50-bit address transactions a match of SRIO Address 49:41 and require all the other bits of ADDR64
3332 * and ADDR66 to be zero. 66-bit address transactions require matches of all valid address field
3333 * bits. The ADDR32/48/64/66 fields of this register are writeable over SRIO if the
3334 * SRIO(0,2..3)_ACC_CTRL.DENY_ADR2 bit is zero. The remaining fields are writeable over SRIO if the
3335 * SRIO(0,2..3)_ACC_CTRL.DENY_BAR2 bit is zero.
3337 * Clk_Rst: SRIOMAINT(0,2..3)_M2S_BAR2_START hclk hrst_n
3339 union cvmx_sriomaintx_m2s_bar2_start {
3341 struct cvmx_sriomaintx_m2s_bar2_start_s {
3342 #ifdef __BIG_ENDIAN_BITFIELD
3343 uint32_t addr64 : 16; /**< SRIO Address 63:48 */
3344 uint32_t addr48 : 7; /**< SRIO Address 47:41 */
3345 uint32_t reserved_6_8 : 3;
3346 uint32_t esx : 2; /**< Endian Swap Mode used for SRIO 34-bit access.
3347 For 50/66-bit assesses Endian Swap is determine
3348 by ESX XOR'd with SRIO Addr 39:38.
3350 1 = 64-bit Swap Bytes [ABCD_EFGH] -> [HGFE_DCBA]
3351 2 = 32-bit Swap Words [ABCD_EFGH] -> [DCBA_HGFE]
3352 3 = 32-bit Word Exch [ABCD_EFGH] -> [EFGH_ABCD] */
3353 uint32_t cax : 1; /**< Cacheable Access Mode. When set transfer is
3354 cached. This bit is used for SRIO 34-bit access.
3355 For 50/66-bit accessas NCA is determine by CAX
3356 XOR'd with SRIO Addr 40. */
3357 uint32_t addr66 : 2; /**< SRIO Address 65:64 */
3358 uint32_t enable : 1; /**< Enable BAR2 Access */
3360 uint32_t enable : 1;
3361 uint32_t addr66 : 2;
3364 uint32_t reserved_6_8 : 3;
3365 uint32_t addr48 : 7;
3366 uint32_t addr64 : 16;
3369 struct cvmx_sriomaintx_m2s_bar2_start_s cn63xx;
3370 struct cvmx_sriomaintx_m2s_bar2_start_s cn63xxp1;
3371 struct cvmx_sriomaintx_m2s_bar2_start_s cn66xx;
3373 typedef union cvmx_sriomaintx_m2s_bar2_start cvmx_sriomaintx_m2s_bar2_start_t;
3376 * cvmx_sriomaint#_mac_ctrl
3378 * SRIOMAINT_MAC_CTRL = SRIO MAC Control
3380 * Control for MAC Features
3383 * This register enables MAC optimizations that may not be supported by all SRIO devices. The
3384 * default values should be supported. This register can be changed at any time while the MAC is
3387 * Clk_Rst: SRIOMAINT(0,2..3)_MAC_CTRL hclk hrst_n
3389 union cvmx_sriomaintx_mac_ctrl {
3391 struct cvmx_sriomaintx_mac_ctrl_s {
3392 #ifdef __BIG_ENDIAN_BITFIELD
3393 uint32_t reserved_21_31 : 11;
3394 uint32_t sec_spf : 1; /**< Send all Incoming Packets matching Secondary ID to
3395 RX Soft Packet FIFO. This bit is ignored if
3397 uint32_t ack_zero : 1; /**< Generate ACKs for all incoming Zero Byte packets.
3398 Default behavior is to issue a NACK. Regardless
3399 of this setting the SRIO(0,2..3)_INT_REG.ZERO_PKT
3400 interrupt is generated.
3401 SRIO(0,2..3)_INT_REG. */
3402 uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO.
3403 No logical layer ERB Errors will be reported.
3404 Used for Diagnostics Only. */
3405 uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on
3406 back to back packets. */
3407 uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */
3408 uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request
3409 after timeout. If retry count is exceeded Fatal
3410 Port Error will occur (see SRIO(0,2..3)_INT_REG.F_ERROR) */
3412 uint32_t lnk_rtry : 16;
3413 uint32_t type_mrg : 1;
3414 uint32_t eop_mrg : 1;
3415 uint32_t rx_spf : 1;
3416 uint32_t ack_zero : 1;
3417 uint32_t sec_spf : 1;
3418 uint32_t reserved_21_31 : 11;
3421 struct cvmx_sriomaintx_mac_ctrl_cn63xx {
3422 #ifdef __BIG_ENDIAN_BITFIELD
3423 uint32_t reserved_20_31 : 12;
3424 uint32_t ack_zero : 1; /**< Generate ACKs for all incoming Zero Byte packets.
3425 Default behavior is to issue a NACK. Regardless
3426 of this setting the SRIO(0..1)_INT_REG.ZERO_PKT
3427 interrupt is generated.
3428 SRIO(0..1)_INT_REG. */
3429 uint32_t rx_spf : 1; /**< Route all received packets to RX Soft Packet FIFO.
3430 No logical layer ERB Errors will be reported.
3431 Used for Diagnostics Only. */
3432 uint32_t eop_mrg : 1; /**< Transmitted Packets can eliminate EOP Symbol on
3433 back to back packets. */
3434 uint32_t type_mrg : 1; /**< Allow STYPE Merging on Transmit. */
3435 uint32_t lnk_rtry : 16; /**< Number of times MAC will reissue Link Request
3436 after timeout. If retry count is exceeded Fatal
3437 Port Error will occur (see SRIO(0..1)_INT_REG.F_ERROR) */
3439 uint32_t lnk_rtry : 16;
3440 uint32_t type_mrg : 1;
3441 uint32_t eop_mrg : 1;
3442 uint32_t rx_spf : 1;
3443 uint32_t ack_zero : 1;
3444 uint32_t reserved_20_31 : 12;
3447 struct cvmx_sriomaintx_mac_ctrl_s cn66xx;
3449 typedef union cvmx_sriomaintx_mac_ctrl cvmx_sriomaintx_mac_ctrl_t;
3452 * cvmx_sriomaint#_pe_feat
3454 * SRIOMAINT_PE_FEAT = SRIO Processing Element Features
3456 * The Supported Processing Element Features.
3459 * The Processing Element Feature register describes the major functionality provided by the SRIO
3462 * Clk_Rst: SRIOMAINT(0,2..3)_PE_FEAT hclk hrst_n
3464 union cvmx_sriomaintx_pe_feat {
3466 struct cvmx_sriomaintx_pe_feat_s {
3467 #ifdef __BIG_ENDIAN_BITFIELD
3468 uint32_t bridge : 1; /**< Bridge Functions not supported. */
3469 uint32_t memory : 1; /**< PE contains addressable memory. */
3470 uint32_t proc : 1; /**< PE contains a local processor. */
3471 uint32_t switchf : 1; /**< Switch Functions not supported. */
3472 uint32_t mult_prt : 1; /**< Multiport Functions not supported. */
3473 uint32_t reserved_7_26 : 20;
3474 uint32_t suppress : 1; /**< Error Recovery Suppression not supported. */
3475 uint32_t crf : 1; /**< Critical Request Flow not supported. */
3476 uint32_t lg_tran : 1; /**< Large Transport (16-bit Device IDs) supported. */
3477 uint32_t ex_feat : 1; /**< Extended Feature Pointer is valid. */
3478 uint32_t ex_addr : 3; /**< PE supports 66, 50 and 34-bit addresses.
3479 [2:1] are a RO copy of SRIO*_IP_FEATURE[A66,A50]. */
3481 uint32_t ex_addr : 3;
3482 uint32_t ex_feat : 1;
3483 uint32_t lg_tran : 1;
3485 uint32_t suppress : 1;
3486 uint32_t reserved_7_26 : 20;
3487 uint32_t mult_prt : 1;
3488 uint32_t switchf : 1;
3490 uint32_t memory : 1;
3491 uint32_t bridge : 1;
3494 struct cvmx_sriomaintx_pe_feat_s cn63xx;
3495 struct cvmx_sriomaintx_pe_feat_s cn63xxp1;
3496 struct cvmx_sriomaintx_pe_feat_s cn66xx;
3498 typedef union cvmx_sriomaintx_pe_feat cvmx_sriomaintx_pe_feat_t;
3501 * cvmx_sriomaint#_pe_llc
3503 * SRIOMAINT_PE_LLC = SRIO Processing Element Logical Layer Control
3505 * Addresses supported by the SRIO Device.
3508 * The Processing Element Logical Layer is used for general configuration for the logical interface.
3510 * Clk_Rst: SRIOMAINT(0,2..3)_PE_LLC hclk hrst_n
3512 union cvmx_sriomaintx_pe_llc {
3514 struct cvmx_sriomaintx_pe_llc_s {
3515 #ifdef __BIG_ENDIAN_BITFIELD
3516 uint32_t reserved_3_31 : 29;
3517 uint32_t ex_addr : 3; /**< Controls the number of address bits generated by
3518 PE as a source and processed by the PE as a
3519 target of an operation.
3520 001 = 34-bit Addresses
3521 010 = 50-bit Addresses
3522 100 = 66-bit Addresses
3523 All other encodings are reserved. */
3525 uint32_t ex_addr : 3;
3526 uint32_t reserved_3_31 : 29;
3529 struct cvmx_sriomaintx_pe_llc_s cn63xx;
3530 struct cvmx_sriomaintx_pe_llc_s cn63xxp1;
3531 struct cvmx_sriomaintx_pe_llc_s cn66xx;
3533 typedef union cvmx_sriomaintx_pe_llc cvmx_sriomaintx_pe_llc_t;
3536 * cvmx_sriomaint#_port_0_ctl
3538 * SRIOMAINT_PORT_0_CTL = SRIO Port 0 Control
3543 * This register contains assorted control bits.
3545 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_CTL hclk hrst_n
3547 union cvmx_sriomaintx_port_0_ctl {
3549 struct cvmx_sriomaintx_port_0_ctl_s {
3550 #ifdef __BIG_ENDIAN_BITFIELD
3551 uint32_t pt_width : 2; /**< Hardware Port Width.
3552 00 = One Lane supported.
3553 01 = One/Four Lanes supported.
3554 10 = One/Two Lanes supported.
3555 11 = One/Two/Four Lanes supported.
3556 This value is a copy of SRIO*_IP_FEATURE[PT_WIDTH]
3557 limited by the number of lanes the MAC has. */
3558 uint32_t it_width : 3; /**< Initialized Port Width
3559 000 = Single-lane, Lane 0
3560 001 = Single-lane, Lane 1 or 2
3563 111 = Link Uninitialized
3564 Others = Reserved */
3565 uint32_t ov_width : 3; /**< Override Port Width. Writing this register causes
3566 the port to reinitialize.
3567 000 = No Override all lanes possible
3569 010 = Force Single-lane, Lane 0
3570 If Ln 0 is unavailable try Ln 2 then Ln 1
3571 011 = Force Single-lane, Lane 2
3572 If Ln 2 is unavailable try Ln 1 then Ln 0
3574 101 = Enable Two-lane, Disable Four-Lane
3575 110 = Enable Four-lane, Disable Two-Lane
3576 111 = All lanes sizes enabled */
3577 uint32_t disable : 1; /**< Port Disable. Setting this bit disables both
3578 drivers and receivers. */
3579 uint32_t o_enable : 1; /**< Port Output Enable. When cleared, port will
3580 generate control symbols and respond to
3581 maintenance transactions only. When set, all
3582 transactions are allowed. */
3583 uint32_t i_enable : 1; /**< Port Input Enable. When cleared, port will
3584 generate control symbols and respond to
3585 maintenance packets only. All other packets will
3587 uint32_t dis_err : 1; /**< Disable Error Checking. Diagnostic Only. */
3588 uint32_t mcast : 1; /**< Reserved. */
3589 uint32_t reserved_18_18 : 1;
3590 uint32_t enumb : 1; /**< Enumeration Boundry. SW can use this bit to
3591 determine port enumeration. */
3592 uint32_t reserved_16_16 : 1;
3593 uint32_t ex_width : 2; /**< Extended Port Width not supported. */
3594 uint32_t ex_stat : 2; /**< Extended Port Width Status. 00 = not supported */
3595 uint32_t suppress : 8; /**< Retransmit Suppression Mask. CRF not Supported. */
3596 uint32_t stp_port : 1; /**< Stop on Failed Port. This bit is used with the
3597 DROP_PKT bit to force certain behavior when the
3598 Error Rate Failed Threshold has been met or
3600 uint32_t drop_pkt : 1; /**< Drop on Failed Port. This bit is used with the
3601 STP_PORT bit to force certain behavior when the
3602 Error Rate Failed Threshold has been met or
3604 uint32_t prt_lock : 1; /**< When this bit is cleared, the packets that may be
3605 received and issued are controlled by the state of
3606 the O_ENABLE and I_ENABLE bits. When this bit is
3607 set, this port is stopped and is not enabled to
3608 issue or receive any packets; the input port can
3609 still follow the training procedure and can still
3610 send and respond to link-requests; all received
3611 packets return packet-not-accepted control symbols
3612 to force an error condition to be signaled by the
3614 uint32_t pt_type : 1; /**< Port Type. 1 = Serial port. */
3616 uint32_t pt_type : 1;
3617 uint32_t prt_lock : 1;
3618 uint32_t drop_pkt : 1;
3619 uint32_t stp_port : 1;
3620 uint32_t suppress : 8;
3621 uint32_t ex_stat : 2;
3622 uint32_t ex_width : 2;
3623 uint32_t reserved_16_16 : 1;
3625 uint32_t reserved_18_18 : 1;
3627 uint32_t dis_err : 1;
3628 uint32_t i_enable : 1;
3629 uint32_t o_enable : 1;
3630 uint32_t disable : 1;
3631 uint32_t ov_width : 3;
3632 uint32_t it_width : 3;
3633 uint32_t pt_width : 2;
3636 struct cvmx_sriomaintx_port_0_ctl_s cn63xx;
3637 struct cvmx_sriomaintx_port_0_ctl_s cn63xxp1;
3638 struct cvmx_sriomaintx_port_0_ctl_s cn66xx;
3640 typedef union cvmx_sriomaintx_port_0_ctl cvmx_sriomaintx_port_0_ctl_t;
3643 * cvmx_sriomaint#_port_0_ctl2
3645 * SRIOMAINT_PORT_0_CTL2 = SRIO Port 0 Control 2
3650 * These registers are accessed when a local processor or an external device wishes to examine the
3651 * port baudrate information. The Automatic Baud Rate Feature is not available on this device. The
3652 * SUP_* and ENB_* fields are set directly by the QLM_SPD bits as a reference but otherwise have
3653 * no effect. WARNING: Writes to this register will reinitialize the SRIO link.
3655 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_CTL2 hclk hrst_n
3657 union cvmx_sriomaintx_port_0_ctl2 {
3659 struct cvmx_sriomaintx_port_0_ctl2_s {
3660 #ifdef __BIG_ENDIAN_BITFIELD
3661 uint32_t sel_baud : 4; /**< Link Baud Rate Selected.
3662 0000 - No rate selected
3667 0101 - 6.25 GBaud (reserved)
3668 0110 - 0b1111 - Reserved
3669 Indicates the speed of the interface SERDES lanes
3670 (selected by the QLM*_SPD straps). */
3671 uint32_t baud_sup : 1; /**< Automatic Baud Rate Discovery not supported. */
3672 uint32_t baud_enb : 1; /**< Auto Baud Rate Discovery Enable. */
3673 uint32_t sup_125g : 1; /**< 1.25GB Rate Operation supported.
3674 Set when the interface SERDES lanes are operating
3675 at 1.25 Gbaud (as selected by QLM*_SPD straps). */
3676 uint32_t enb_125g : 1; /**< 1.25GB Rate Operation enable.
3677 Reset to 1 when the interface SERDES lanes are
3678 operating at 1.25 Gbaud (as selected by QLM*_SPD
3679 straps). Reset to 0 otherwise. */
3680 uint32_t sup_250g : 1; /**< 2.50GB Rate Operation supported.
3681 Set when the interface SERDES lanes are operating
3682 at 2.5 Gbaud (as selected by QLM*_SPD straps). */
3683 uint32_t enb_250g : 1; /**< 2.50GB Rate Operation enable.
3684 Reset to 1 when the interface SERDES lanes are
3685 operating at 2.5 Gbaud (as selected by QLM*_SPD
3686 straps). Reset to 0 otherwise. */
3687 uint32_t sup_312g : 1; /**< 3.125GB Rate Operation supported.
3688 Set when the interface SERDES lanes are operating
3689 at 3.125 Gbaud (as selected by QLM*_SPD straps). */
3690 uint32_t enb_312g : 1; /**< 3.125GB Rate Operation enable.
3691 Reset to 1 when the interface SERDES lanes are
3692 operating at 3.125 Gbaud (as selected by QLM*_SPD
3693 straps). Reset to 0 otherwise. */
3694 uint32_t sub_500g : 1; /**< 5.0GB Rate Operation supported.
3695 Set when the interface SERDES lanes are operating
3696 at 5.0 Gbaud (as selected by QLM*_SPD straps). */
3697 uint32_t enb_500g : 1; /**< 5.0GB Rate Operation enable.
3698 Reset to 1 when the interface SERDES lanes are
3699 operating at 5.0 Gbaud (as selected by QLM*_SPD
3700 straps). Reset to 0 otherwise. */
3701 uint32_t sup_625g : 1; /**< 6.25GB Rate Operation (not supported). */
3702 uint32_t enb_625g : 1; /**< 6.25GB Rate Operation enable. */
3703 uint32_t reserved_2_15 : 14;
3704 uint32_t tx_emph : 1; /**< Indicates whether is port is able to transmit
3705 commands to control the transmit emphasis in the
3707 uint32_t emph_en : 1; /**< Controls whether a port may adjust the
3708 transmit emphasis in the connected port. This bit
3709 should be cleared for normal operation. */
3711 uint32_t emph_en : 1;
3712 uint32_t tx_emph : 1;
3713 uint32_t reserved_2_15 : 14;
3714 uint32_t enb_625g : 1;
3715 uint32_t sup_625g : 1;
3716 uint32_t enb_500g : 1;
3717 uint32_t sub_500g : 1;
3718 uint32_t enb_312g : 1;
3719 uint32_t sup_312g : 1;
3720 uint32_t enb_250g : 1;
3721 uint32_t sup_250g : 1;
3722 uint32_t enb_125g : 1;
3723 uint32_t sup_125g : 1;
3724 uint32_t baud_enb : 1;
3725 uint32_t baud_sup : 1;
3726 uint32_t sel_baud : 4;
3729 struct cvmx_sriomaintx_port_0_ctl2_s cn63xx;
3730 struct cvmx_sriomaintx_port_0_ctl2_s cn63xxp1;
3731 struct cvmx_sriomaintx_port_0_ctl2_s cn66xx;
3733 typedef union cvmx_sriomaintx_port_0_ctl2 cvmx_sriomaintx_port_0_ctl2_t;
3736 * cvmx_sriomaint#_port_0_err_stat
3738 * SRIOMAINT_PORT_0_ERR_STAT = SRIO Port 0 Error and Status
3740 * Port 0 Error and Status
3743 * This register displays port error and status information. Several port error conditions are
3744 * captured here and must be cleared by writing 1's to the individual bits.
3745 * Bits are R/W on 65/66xx pass 1 and R/W1C on pass 1.2
3747 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_ERR_STAT hclk hrst_n
3749 union cvmx_sriomaintx_port_0_err_stat {
3751 struct cvmx_sriomaintx_port_0_err_stat_s {
3752 #ifdef __BIG_ENDIAN_BITFIELD
3753 uint32_t reserved_27_31 : 5;
3754 uint32_t pkt_drop : 1; /**< Output Packet Dropped. */
3755 uint32_t o_fail : 1; /**< Output Port has encountered a failure condition,
3756 meaning the port's failed error threshold has
3757 reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_FAIL value. */
3758 uint32_t o_dgrad : 1; /**< Output Port has encountered a degraded condition,
3759 meaning the port's degraded threshold has
3760 reached SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR.ER_DGRAD
3762 uint32_t reserved_21_23 : 3;
3763 uint32_t o_retry : 1; /**< Output Retry Encountered. This bit is set when
3765 uint32_t o_rtried : 1; /**< Output Port has received a packet-retry condition
3766 and cannot make forward progress. This bit is set
3767 when bit 18 is set and is cleared when a packet-
3768 accepted or a packet-not-accepted control symbol
3770 uint32_t o_sm_ret : 1; /**< Output Port State Machine has received a
3771 packet-retry control symbol and is retrying the
3773 uint32_t o_error : 1; /**< Output Error Encountered and possibly recovered
3774 from. This sticky bit is set with bit 16. */
3775 uint32_t o_sm_err : 1; /**< Output Port State Machine has encountered an
3777 uint32_t reserved_11_15 : 5;
3778 uint32_t i_sm_ret : 1; /**< Input Port State Machine has received a
3779 packet-retry control symbol and is retrying the
3781 uint32_t i_error : 1; /**< Input Error Encountered and possibly recovered
3782 from. This sticky bit is set with bit 8. */
3783 uint32_t i_sm_err : 1; /**< Input Port State Machine has encountered an
3785 uint32_t reserved_5_7 : 3;
3786 uint32_t pt_write : 1; /**< Port has encountered a condition which required it
3787 initiate a Maintenance Port-Write Operation.
3788 Never set by hardware. */
3789 uint32_t reserved_3_3 : 1;
3790 uint32_t pt_error : 1; /**< Input or Output Port has encountered an
3791 unrecoverable error condition. */
3792 uint32_t pt_ok : 1; /**< Input or Output Port are intitialized and the port
3793 is exchanging error free control symbols with
3795 uint32_t pt_uinit : 1; /**< Port is uninitialized. This bit and bit 1 are
3796 mutually exclusive. */
3798 uint32_t pt_uinit : 1;
3800 uint32_t pt_error : 1;
3801 uint32_t reserved_3_3 : 1;
3802 uint32_t pt_write : 1;
3803 uint32_t reserved_5_7 : 3;
3804 uint32_t i_sm_err : 1;
3805 uint32_t i_error : 1;
3806 uint32_t i_sm_ret : 1;
3807 uint32_t reserved_11_15 : 5;
3808 uint32_t o_sm_err : 1;
3809 uint32_t o_error : 1;
3810 uint32_t o_sm_ret : 1;
3811 uint32_t o_rtried : 1;
3812 uint32_t o_retry : 1;
3813 uint32_t reserved_21_23 : 3;
3814 uint32_t o_dgrad : 1;
3815 uint32_t o_fail : 1;
3816 uint32_t pkt_drop : 1;
3817 uint32_t reserved_27_31 : 5;
3820 struct cvmx_sriomaintx_port_0_err_stat_s cn63xx;
3821 struct cvmx_sriomaintx_port_0_err_stat_s cn63xxp1;
3822 struct cvmx_sriomaintx_port_0_err_stat_s cn66xx;
3824 typedef union cvmx_sriomaintx_port_0_err_stat cvmx_sriomaintx_port_0_err_stat_t;
3827 * cvmx_sriomaint#_port_0_link_req
3829 * SRIOMAINT_PORT_0_LINK_REQ = SRIO Port 0 Link Request
3831 * Port 0 Manual Link Request
3834 * Writing this register generates the link request symbol or eight device reset symbols. The
3835 * progress of the request can be determined by reading SRIOMAINT(0,2..3)_PORT_0_LINK_RESP. Only a single
3836 * request should be generated at a time.
3838 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LINK_REQ hclk hrst_n
3840 union cvmx_sriomaintx_port_0_link_req {
3842 struct cvmx_sriomaintx_port_0_link_req_s {
3843 #ifdef __BIG_ENDIAN_BITFIELD
3844 uint32_t reserved_3_31 : 29;
3845 uint32_t cmd : 3; /**< Link Request Command.
3848 All other values reserved. */
3851 uint32_t reserved_3_31 : 29;
3854 struct cvmx_sriomaintx_port_0_link_req_s cn63xx;
3855 struct cvmx_sriomaintx_port_0_link_req_s cn66xx;
3857 typedef union cvmx_sriomaintx_port_0_link_req cvmx_sriomaintx_port_0_link_req_t;
3860 * cvmx_sriomaint#_port_0_link_resp
3862 * SRIOMAINT_PORT_0_LINK_RESP = SRIO Port 0 Link Response
3864 * Port 0 Manual Link Response
3867 * This register only returns responses generated by writes to SRIOMAINT(0,2..3)_PORT_0_LINK_REQ.
3869 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LINK_RESP hclk hrst_n
3871 union cvmx_sriomaintx_port_0_link_resp {
3873 struct cvmx_sriomaintx_port_0_link_resp_s {
3874 #ifdef __BIG_ENDIAN_BITFIELD
3875 uint32_t valid : 1; /**< Link Response Valid.
3876 1 = Link Response Received or Reset Device
3877 Symbols Transmitted. Value cleared on read.
3878 0 = No response received. */
3879 uint32_t reserved_11_30 : 20;
3880 uint32_t ackid : 6; /**< AckID received from link response.
3881 Reset Device symbol response is always zero.
3882 Bit 10 is used for IDLE2 and always reads zero. */
3883 uint32_t status : 5; /**< Link Response Status.
3884 Status supplied by link response.
3885 Reset Device symbol response is always zero. */
3887 uint32_t status : 5;
3889 uint32_t reserved_11_30 : 20;
3893 struct cvmx_sriomaintx_port_0_link_resp_s cn63xx;
3894 struct cvmx_sriomaintx_port_0_link_resp_s cn66xx;
3896 typedef union cvmx_sriomaintx_port_0_link_resp cvmx_sriomaintx_port_0_link_resp_t;
3899 * cvmx_sriomaint#_port_0_local_ackid
3901 * SRIOMAINT_PORT_0_LOCAL_ACKID = SRIO Port 0 Local AckID
3903 * Port 0 Local AckID Control
3906 * This register is typically only written when recovering from a failed link. It may be read at any
3907 * time the MAC is out of reset. Writes to the O_ACKID field will be used for both the O_ACKID and
3908 * E_ACKID. Care must be taken to ensure that no packets are pending at the time of a write. The
3909 * number of pending packets can be read in the TX_INUSE field of SRIO(0,2..3)_MAC_BUFFERS.
3911 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_0_LOCAL_ACKID hclk hrst_n
3913 union cvmx_sriomaintx_port_0_local_ackid {
3915 struct cvmx_sriomaintx_port_0_local_ackid_s {
3916 #ifdef __BIG_ENDIAN_BITFIELD
3917 uint32_t reserved_30_31 : 2;
3918 uint32_t i_ackid : 6; /**< Next Expected Inbound AckID.
3919 Bit 29 is used for IDLE2 and should be zero. */
3920 uint32_t reserved_14_23 : 10;
3921 uint32_t e_ackid : 6; /**< Next Expected Unacknowledged AckID.
3922 Bit 13 is used for IDLE2 and should be zero. */
3923 uint32_t reserved_6_7 : 2;
3924 uint32_t o_ackid : 6; /**< Next Outgoing Packet AckID.
3925 Bit 5 is used for IDLE2 and should be zero. */
3927 uint32_t o_ackid : 6;
3928 uint32_t reserved_6_7 : 2;
3929 uint32_t e_ackid : 6;
3930 uint32_t reserved_14_23 : 10;
3931 uint32_t i_ackid : 6;
3932 uint32_t reserved_30_31 : 2;
3935 struct cvmx_sriomaintx_port_0_local_ackid_s cn63xx;
3936 struct cvmx_sriomaintx_port_0_local_ackid_s cn66xx;
3938 typedef union cvmx_sriomaintx_port_0_local_ackid cvmx_sriomaintx_port_0_local_ackid_t;
3941 * cvmx_sriomaint#_port_gen_ctl
3943 * SRIOMAINT_PORT_GEN_CTL = SRIO Port General Control
3945 * Port General Control
3948 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_GEN_CTL hclk hrst_n
3951 union cvmx_sriomaintx_port_gen_ctl {
3953 struct cvmx_sriomaintx_port_gen_ctl_s {
3954 #ifdef __BIG_ENDIAN_BITFIELD
3955 uint32_t host : 1; /**< Host Device.
3956 The HOST reset value is based on corresponding
3957 MIO_RST_CTL*[PRTMODE]. HOST resets to 1 when
3958 this field selects RC (i.e. host) mode, else 0. */
3959 uint32_t menable : 1; /**< Master Enable. Must be set for device to issue
3960 read, write, doorbell, message requests. */
3961 uint32_t discover : 1; /**< Discovered. The device has been discovered by the
3962 host responsible for initialization. */
3963 uint32_t reserved_0_28 : 29;
3965 uint32_t reserved_0_28 : 29;
3966 uint32_t discover : 1;
3967 uint32_t menable : 1;
3971 struct cvmx_sriomaintx_port_gen_ctl_s cn63xx;
3972 struct cvmx_sriomaintx_port_gen_ctl_s cn63xxp1;
3973 struct cvmx_sriomaintx_port_gen_ctl_s cn66xx;
3975 typedef union cvmx_sriomaintx_port_gen_ctl cvmx_sriomaintx_port_gen_ctl_t;
3978 * cvmx_sriomaint#_port_lt_ctl
3980 * SRIOMAINT_PORT_LT_CTL = SRIO Link Layer Timeout Control
3982 * Link Layer Timeout Control
3985 * This register controls the timeout for link layer transactions. It is used as the timeout between
3986 * sending a packet (of any type) or link request to receiving the corresponding link acknowledge or
3987 * link-response. Each count represents 200ns. The minimum timeout period is the TIMEOUT x 200nS
3988 * and the maximum is twice that number. A value less than 32 may not guarantee that all timeout
3989 * errors will be reported correctly. When the timeout period expires the packet or link request is
3990 * dropped and the error is logged in the LNK_TOUT field of the SRIOMAINT(0,2..3)_ERB_ERR_DET register. A
3991 * value of 0 in this register will allow the packet or link request to be issued but it will timeout
3992 * immediately. This value is not recommended for normal operation.
3994 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_LT_CTL hclk hrst_n
3996 union cvmx_sriomaintx_port_lt_ctl {
3998 struct cvmx_sriomaintx_port_lt_ctl_s {
3999 #ifdef __BIG_ENDIAN_BITFIELD
4000 uint32_t timeout : 24; /**< Timeout Value */
4001 uint32_t reserved_0_7 : 8;
4003 uint32_t reserved_0_7 : 8;
4004 uint32_t timeout : 24;
4007 struct cvmx_sriomaintx_port_lt_ctl_s cn63xx;
4008 struct cvmx_sriomaintx_port_lt_ctl_s cn63xxp1;
4009 struct cvmx_sriomaintx_port_lt_ctl_s cn66xx;
4011 typedef union cvmx_sriomaintx_port_lt_ctl cvmx_sriomaintx_port_lt_ctl_t;
4014 * cvmx_sriomaint#_port_mbh0
4016 * SRIOMAINT_PORT_MBH0 = SRIO Port Maintenance Block Header 0
4018 * Port Maintenance Block Header 0
4021 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_MBH0 hclk hrst_n
4024 union cvmx_sriomaintx_port_mbh0 {
4026 struct cvmx_sriomaintx_port_mbh0_s {
4027 #ifdef __BIG_ENDIAN_BITFIELD
4028 uint32_t ef_ptr : 16; /**< Pointer to Error Management Block. */
4029 uint32_t ef_id : 16; /**< Extended Feature ID (Generic Endpoint Device) */
4031 uint32_t ef_id : 16;
4032 uint32_t ef_ptr : 16;
4035 struct cvmx_sriomaintx_port_mbh0_s cn63xx;
4036 struct cvmx_sriomaintx_port_mbh0_s cn63xxp1;
4037 struct cvmx_sriomaintx_port_mbh0_s cn66xx;
4039 typedef union cvmx_sriomaintx_port_mbh0 cvmx_sriomaintx_port_mbh0_t;
4042 * cvmx_sriomaint#_port_rt_ctl
4044 * SRIOMAINT_PORT_RT_CTL = SRIO Logical Layer Timeout Control
4046 * Logical Layer Timeout Control
4049 * This register controls the timeout for logical layer transactions. It is used under two
4050 * conditions. First, it is used as the timeout period between sending a packet requiring a packet
4051 * response being sent to receiving the corresponding response. This is used for all outgoing packet
4052 * types including memory, maintenance, doorbells and message operations. When the timeout period
4053 * expires the packet is disgarded and the error is logged in the PKT_TOUT field of the
4054 * SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register. The second use of this register is as a timeout period
4055 * between incoming message segments of the same message. If a message segment is received then the
4056 * MSG_TOUT field of the SRIOMAINT(0,2..3)_ERB_LT_ERR_DET register is set if the next segment has not been
4057 * received before the time expires. In both cases, each count represents 200ns. The minimum
4058 * timeout period is the TIMEOUT x 200nS and the maximum is twice that number. A value less than 32
4059 * may not guarantee that all timeout errors will be reported correctly. A value of 0 disables the
4060 * logical layer timeouts and is not recommended for normal operation.
4062 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_RT_CTL hclk hrst_n
4064 union cvmx_sriomaintx_port_rt_ctl {
4066 struct cvmx_sriomaintx_port_rt_ctl_s {
4067 #ifdef __BIG_ENDIAN_BITFIELD
4068 uint32_t timeout : 24; /**< Timeout Value */
4069 uint32_t reserved_0_7 : 8;
4071 uint32_t reserved_0_7 : 8;
4072 uint32_t timeout : 24;
4075 struct cvmx_sriomaintx_port_rt_ctl_s cn63xx;
4076 struct cvmx_sriomaintx_port_rt_ctl_s cn63xxp1;
4077 struct cvmx_sriomaintx_port_rt_ctl_s cn66xx;
4079 typedef union cvmx_sriomaintx_port_rt_ctl cvmx_sriomaintx_port_rt_ctl_t;
4082 * cvmx_sriomaint#_port_ttl_ctl
4084 * SRIOMAINT_PORT_TTL_CTL = SRIO Packet Time to Live Control
4086 * Packet Time to Live
4089 * This register controls the timeout for outgoing packets. It is used to make sure packets are
4090 * being transmitted and acknowledged within a reasonable period of time. The timeout value
4091 * corresponds to TIMEOUT x 200ns and a value of 0 disables the timer. The actualy value of the
4092 * should be greater than the physical layer timout specified in SRIOMAINT(0,2..3)_PORT_LT_CTL and is
4093 * typically a less SRIOMAINT(0,2..3)_PORT_LT_CTL timeout than the response timeout specified in
4094 * SRIOMAINT(0,2..3)_PORT_RT_CTL. A second application of this timer is to remove all the packets waiting
4095 * to be transmitted including those already in flight. This may necessary in the case of a link
4096 * going down (see SRIO(0,2..3)_INT_REG.LINK_DWN). This can accomplished by setting the TIMEOUT to small
4097 * value all so that all TX packets can be dropped. In either case, when the timeout expires the TTL
4098 * interrupt is asserted, any packets currently being transmitted are dropped, the
4099 * SRIOMAINT(0,2..3)_TX_DROP.DROP bit is set (causing any scheduled packets to be dropped), the
4100 * SRIOMAINT(0,2..3)_TX_DROP.DROP_CNT is incremented for each packet and the SRIO output state is set to
4101 * IDLE (all errors are cleared). Software must clear the SRIOMAINT(0,2..3)_TX_DROP.DROP bit to resume
4102 * transmitting packets.
4104 * Clk_Rst: SRIOMAINT(0,2..3)_PORT_RT_CTL hclk hrst_n
4106 union cvmx_sriomaintx_port_ttl_ctl {
4108 struct cvmx_sriomaintx_port_ttl_ctl_s {
4109 #ifdef __BIG_ENDIAN_BITFIELD
4110 uint32_t timeout : 24; /**< Timeout Value */
4111 uint32_t reserved_0_7 : 8;
4113 uint32_t reserved_0_7 : 8;
4114 uint32_t timeout : 24;
4117 struct cvmx_sriomaintx_port_ttl_ctl_s cn63xx;
4118 struct cvmx_sriomaintx_port_ttl_ctl_s cn66xx;
4120 typedef union cvmx_sriomaintx_port_ttl_ctl cvmx_sriomaintx_port_ttl_ctl_t;
4123 * cvmx_sriomaint#_pri_dev_id
4125 * SRIOMAINT_PRI_DEV_ID = SRIO Primary Device ID
4127 * Primary 8 and 16 bit Device IDs
4130 * This register defines the primary 8 and 16 bit device IDs used for large and small transport. An
4131 * optional secondary set of device IDs are located in SRIOMAINT(0,2..3)_SEC_DEV_ID.
4133 * Clk_Rst: SRIOMAINT(0,2..3)_PRI_DEV_ID hclk hrst_n
4135 union cvmx_sriomaintx_pri_dev_id {
4137 struct cvmx_sriomaintx_pri_dev_id_s {
4138 #ifdef __BIG_ENDIAN_BITFIELD
4139 uint32_t reserved_24_31 : 8;
4140 uint32_t id8 : 8; /**< Primary 8-bit Device ID */
4141 uint32_t id16 : 16; /**< Primary 16-bit Device ID */
4145 uint32_t reserved_24_31 : 8;
4148 struct cvmx_sriomaintx_pri_dev_id_s cn63xx;
4149 struct cvmx_sriomaintx_pri_dev_id_s cn63xxp1;
4150 struct cvmx_sriomaintx_pri_dev_id_s cn66xx;
4152 typedef union cvmx_sriomaintx_pri_dev_id cvmx_sriomaintx_pri_dev_id_t;
4155 * cvmx_sriomaint#_sec_dev_ctrl
4157 * SRIOMAINT_SEC_DEV_CTRL = SRIO Secondary Device ID Control
4159 * Control for Secondary Device IDs
4162 * This register enables the secondary 8 and 16 bit device IDs used for large and small transport.
4163 * The corresponding secondary ID must be written before the ID is enabled. The secondary IDs should
4164 * not be enabled if the values of the primary and secondary IDs are identical.
4166 * Clk_Rst: SRIOMAINT(0,2..3)_SEC_DEV_CTRL hclk hrst_n
4168 union cvmx_sriomaintx_sec_dev_ctrl {
4170 struct cvmx_sriomaintx_sec_dev_ctrl_s {
4171 #ifdef __BIG_ENDIAN_BITFIELD
4172 uint32_t reserved_2_31 : 30;
4173 uint32_t enable8 : 1; /**< Enable matches to secondary 8-bit Device ID */
4174 uint32_t enable16 : 1; /**< Enable matches to secondary 16-bit Device ID */
4176 uint32_t enable16 : 1;
4177 uint32_t enable8 : 1;
4178 uint32_t reserved_2_31 : 30;
4181 struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xx;
4182 struct cvmx_sriomaintx_sec_dev_ctrl_s cn63xxp1;
4183 struct cvmx_sriomaintx_sec_dev_ctrl_s cn66xx;
4185 typedef union cvmx_sriomaintx_sec_dev_ctrl cvmx_sriomaintx_sec_dev_ctrl_t;
4188 * cvmx_sriomaint#_sec_dev_id
4190 * SRIOMAINT_SEC_DEV_ID = SRIO Secondary Device ID
4192 * Secondary 8 and 16 bit Device IDs
4195 * This register defines the secondary 8 and 16 bit device IDs used for large and small transport.
4196 * The corresponding secondary ID must be written before the ID is enabled in the
4197 * SRIOMAINT(0,2..3)_SEC_DEV_CTRL register. The primary set of device IDs are located in
4198 * SRIOMAINT(0,2..3)_PRI_DEV_ID register. The secondary IDs should not be written to the same values as the
4199 * corresponding primary IDs.
4201 * Clk_Rst: SRIOMAINT(0,2..3)_SEC_DEV_ID hclk hrst_n
4203 union cvmx_sriomaintx_sec_dev_id {
4205 struct cvmx_sriomaintx_sec_dev_id_s {
4206 #ifdef __BIG_ENDIAN_BITFIELD
4207 uint32_t reserved_24_31 : 8;
4208 uint32_t id8 : 8; /**< Secondary 8-bit Device ID */
4209 uint32_t id16 : 16; /**< Secondary 16-bit Device ID */
4213 uint32_t reserved_24_31 : 8;
4216 struct cvmx_sriomaintx_sec_dev_id_s cn63xx;
4217 struct cvmx_sriomaintx_sec_dev_id_s cn63xxp1;
4218 struct cvmx_sriomaintx_sec_dev_id_s cn66xx;
4220 typedef union cvmx_sriomaintx_sec_dev_id cvmx_sriomaintx_sec_dev_id_t;
4223 * cvmx_sriomaint#_serial_lane_hdr
4225 * SRIOMAINT_SERIAL_LANE_HDR = SRIO Serial Lane Header
4227 * SRIO Serial Lane Header
4230 * The error management extensions block header register contains the EF_PTR to the next EF_BLK and
4231 * the EF_ID that identifies this as the Serial Lane Status Block.
4233 * Clk_Rst: SRIOMAINT(0,2..3)_SERIAL_LANE_HDR hclk hrst_n
4235 union cvmx_sriomaintx_serial_lane_hdr {
4237 struct cvmx_sriomaintx_serial_lane_hdr_s {
4238 #ifdef __BIG_ENDIAN_BITFIELD
4239 uint32_t ef_ptr : 16; /**< Pointer to the next block in the extended features
4241 uint32_t ef_id : 16;
4243 uint32_t ef_id : 16;
4244 uint32_t ef_ptr : 16;
4247 struct cvmx_sriomaintx_serial_lane_hdr_s cn63xx;
4248 struct cvmx_sriomaintx_serial_lane_hdr_s cn63xxp1;
4249 struct cvmx_sriomaintx_serial_lane_hdr_s cn66xx;
4251 typedef union cvmx_sriomaintx_serial_lane_hdr cvmx_sriomaintx_serial_lane_hdr_t;
4254 * cvmx_sriomaint#_src_ops
4256 * SRIOMAINT_SRC_OPS = SRIO Source Operations
4258 * The logical operations initiated by the Octeon.
4261 * The logical operations initiated by the Cores. The Source OPs register shows the operations
4262 * specified in the SRIO(0,2..3)_IP_FEATURE.OPS register.
4264 * Clk_Rst: SRIOMAINT(0,2..3)_SRC_OPS hclk hrst_n
4266 union cvmx_sriomaintx_src_ops {
4268 struct cvmx_sriomaintx_src_ops_s {
4269 #ifdef __BIG_ENDIAN_BITFIELD
4270 uint32_t gsm_read : 1; /**< PE does not support Read Home operations.
4271 This is a RO copy of SRIO*_IP_FEATURE[OPS<31>] */
4272 uint32_t i_read : 1; /**< PE does not support Instruction Read.
4273 This is a RO copy of SRIO*_IP_FEATURE[OPS<30>] */
4274 uint32_t rd_own : 1; /**< PE does not support Read for Ownership.
4275 This is a RO copy of SRIO*_IP_FEATURE[OPS<29>] */
4276 uint32_t d_invald : 1; /**< PE does not support Data Cache Invalidate.
4277 This is a RO copy of SRIO*_IP_FEATURE[OPS<28>] */
4278 uint32_t castout : 1; /**< PE does not support Castout Operations.
4279 This is a RO copy of SRIO*_IP_FEATURE[OPS<27>] */
4280 uint32_t d_flush : 1; /**< PE does not support Data Cache Flush.
4281 This is a RO copy of SRIO*_IP_FEATURE[OPS<26>] */
4282 uint32_t io_read : 1; /**< PE does not support IO Read.
4283 This is a RO copy of SRIO*_IP_FEATURE[OPS<25>] */
4284 uint32_t i_invald : 1; /**< PE does not support Instruction Cache Invalidate.
4285 This is a RO copy of SRIO*_IP_FEATURE[OPS<24>] */
4286 uint32_t tlb_inv : 1; /**< PE does not support TLB Entry Invalidate.
4287 This is a RO copy of SRIO*_IP_FEATURE[OPS<23>] */
4288 uint32_t tlb_invs : 1; /**< PE does not support TLB Entry Invalidate Sync.
4289 This is a RO copy of SRIO*_IP_FEATURE[OPS<22>] */
4290 uint32_t reserved_16_21 : 6;
4291 uint32_t read : 1; /**< PE can support Nread operations.
4292 This is a RO copy of SRIO*_IP_FEATURE[OPS<15>] */
4293 uint32_t write : 1; /**< PE can support Nwrite operations.
4294 This is a RO copy of SRIO*_IP_FEATURE[OPS<14>] */
4295 uint32_t swrite : 1; /**< PE can support Swrite operations.
4296 This is a RO copy of SRIO*_IP_FEATURE[OPS<13>] */
4297 uint32_t write_r : 1; /**< PE can support Write with Response operations.
4298 This is a RO copy of SRIO*_IP_FEATURE[OPS<12>] */
4299 uint32_t msg : 1; /**< PE can support Data Message operations.
4300 This is a RO copy of SRIO*_IP_FEATURE[OPS<11>] */
4301 uint32_t doorbell : 1; /**< PE can support Doorbell operations.
4302 This is a RO copy of SRIO*_IP_FEATURE[OPS<10>] */
4303 uint32_t compswap : 1; /**< PE does not support Atomic Compare and Swap.
4304 This is a RO copy of SRIO*_IP_FEATURE[OPS<9>] */
4305 uint32_t testswap : 1; /**< PE does not support Atomic Test and Swap.
4306 This is a RO copy of SRIO*_IP_FEATURE[OPS<8>] */
4307 uint32_t atom_inc : 1; /**< PE can support Atomic increment operations.
4308 This is a RO copy of SRIO*_IP_FEATURE[OPS<7>] */
4309 uint32_t atom_dec : 1; /**< PE can support Atomic decrement operations.
4310 This is a RO copy of SRIO*_IP_FEATURE[OPS<6>] */
4311 uint32_t atom_set : 1; /**< PE can support Atomic set operations.
4312 This is a RO copy of SRIO*_IP_FEATURE[OPS<5>] */
4313 uint32_t atom_clr : 1; /**< PE can support Atomic clear operations.
4314 This is a RO copy of SRIO*_IP_FEATURE[OPS<4>] */
4315 uint32_t atom_swp : 1; /**< PE does not support Atomic Swap.
4316 This is a RO copy of SRIO*_IP_FEATURE[OPS<3>] */
4317 uint32_t port_wr : 1; /**< PE can Port Write operations.
4318 This is a RO copy of SRIO*_IP_FEATURE[OPS<2>] */
4319 uint32_t reserved_0_1 : 2;
4321 uint32_t reserved_0_1 : 2;
4322 uint32_t port_wr : 1;
4323 uint32_t atom_swp : 1;
4324 uint32_t atom_clr : 1;
4325 uint32_t atom_set : 1;
4326 uint32_t atom_dec : 1;
4327 uint32_t atom_inc : 1;
4328 uint32_t testswap : 1;
4329 uint32_t compswap : 1;
4330 uint32_t doorbell : 1;
4332 uint32_t write_r : 1;
4333 uint32_t swrite : 1;
4336 uint32_t reserved_16_21 : 6;
4337 uint32_t tlb_invs : 1;
4338 uint32_t tlb_inv : 1;
4339 uint32_t i_invald : 1;
4340 uint32_t io_read : 1;
4341 uint32_t d_flush : 1;
4342 uint32_t castout : 1;
4343 uint32_t d_invald : 1;
4344 uint32_t rd_own : 1;
4345 uint32_t i_read : 1;
4346 uint32_t gsm_read : 1;
4349 struct cvmx_sriomaintx_src_ops_s cn63xx;
4350 struct cvmx_sriomaintx_src_ops_s cn63xxp1;
4351 struct cvmx_sriomaintx_src_ops_s cn66xx;
4353 typedef union cvmx_sriomaintx_src_ops cvmx_sriomaintx_src_ops_t;
4356 * cvmx_sriomaint#_tx_drop
4358 * SRIOMAINT_TX_DROP = SRIO MAC Outgoing Packet Drop
4360 * Outging SRIO Packet Drop Control/Status
4363 * This register controls and provides status for dropping outgoing SRIO packets. The DROP bit
4364 * should only be cleared when no packets are currently being dropped. This can be guaranteed by
4365 * clearing the SRIOMAINT(0,2..3)_PORT_0_CTL.O_ENABLE bit before changing the DROP bit and restoring the
4366 * O_ENABLE afterwards.
4368 * Clk_Rst: SRIOMAINT(0,2..3)_MAC_CTRL hclk hrst_n
4370 union cvmx_sriomaintx_tx_drop {
4372 struct cvmx_sriomaintx_tx_drop_s {
4373 #ifdef __BIG_ENDIAN_BITFIELD
4374 uint32_t reserved_17_31 : 15;
4375 uint32_t drop : 1; /**< All outgoing packets are dropped. Any packets
4376 requiring a response will return 1's after the
4377 SRIOMAINT(0,2..3)_PORT_RT_CTL Timeout expires. This bit
4378 is set automatically when the TTL Timeout occurs
4379 or can be set by software and must always be
4380 cleared by software. */
4381 uint32_t drop_cnt : 16; /**< Number of packets dropped by transmit logic.
4382 Packets are dropped whenever a packet is ready to
4383 be transmitted and a TTL Timeouts occur, the DROP
4384 bit is set or the SRIOMAINT(0,2..3)_ERB_ERR_RATE_THR
4385 FAIL_TH has been reached and the DROP_PKT bit is
4386 set in SRIOMAINT(0,2..3)_PORT_0_CTL. This counter wraps
4387 on overflow and is cleared only on reset. */
4389 uint32_t drop_cnt : 16;
4391 uint32_t reserved_17_31 : 15;
4394 struct cvmx_sriomaintx_tx_drop_s cn63xx;
4395 struct cvmx_sriomaintx_tx_drop_s cn66xx;
4397 typedef union cvmx_sriomaintx_tx_drop cvmx_sriomaintx_tx_drop_t;