1 /***********************license start***************
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38 ***********************license end**************************************/
44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_SRIOX_DEFS_H__
53 #define __CVMX_SRIOX_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_SRIOX_ACC_CTRL(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
61 cvmx_warn("CVMX_SRIOX_ACC_CTRL(%lu) is invalid on this chip\n", block_id);
62 return CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull;
65 #define CVMX_SRIOX_ACC_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000148ull) + ((block_id) & 3) * 0x1000000ull)
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_SRIOX_ASMBLY_ID(unsigned long block_id)
71 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
73 cvmx_warn("CVMX_SRIOX_ASMBLY_ID(%lu) is invalid on this chip\n", block_id);
74 return CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull;
77 #define CVMX_SRIOX_ASMBLY_ID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000200ull) + ((block_id) & 3) * 0x1000000ull)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 static inline uint64_t CVMX_SRIOX_ASMBLY_INFO(unsigned long block_id)
83 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
85 cvmx_warn("CVMX_SRIOX_ASMBLY_INFO(%lu) is invalid on this chip\n", block_id);
86 return CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull;
89 #define CVMX_SRIOX_ASMBLY_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000208ull) + ((block_id) & 3) * 0x1000000ull)
91 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92 static inline uint64_t CVMX_SRIOX_BELL_RESP_CTRL(unsigned long block_id)
95 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
97 cvmx_warn("CVMX_SRIOX_BELL_RESP_CTRL(%lu) is invalid on this chip\n", block_id);
98 return CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull;
101 #define CVMX_SRIOX_BELL_RESP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000310ull) + ((block_id) & 3) * 0x1000000ull)
103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104 static inline uint64_t CVMX_SRIOX_BIST_STATUS(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
109 cvmx_warn("CVMX_SRIOX_BIST_STATUS(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull;
113 #define CVMX_SRIOX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000108ull) + ((block_id) & 3) * 0x1000000ull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_SRIOX_IMSG_CTRL(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
121 cvmx_warn("CVMX_SRIOX_IMSG_CTRL(%lu) is invalid on this chip\n", block_id);
122 return CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull;
125 #define CVMX_SRIOX_IMSG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000508ull) + ((block_id) & 3) * 0x1000000ull)
127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
128 static inline uint64_t CVMX_SRIOX_IMSG_INST_HDRX(unsigned long offset, unsigned long block_id)
131 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
132 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
133 cvmx_warn("CVMX_SRIOX_IMSG_INST_HDRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
134 return CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8;
137 #define CVMX_SRIOX_IMSG_INST_HDRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000510ull) + (((offset) & 1) + ((block_id) & 3) * 0x200000ull) * 8)
139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
140 static inline uint64_t CVMX_SRIOX_IMSG_QOS_GRPX(unsigned long offset, unsigned long block_id)
143 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 31)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
145 cvmx_warn("CVMX_SRIOX_IMSG_QOS_GRPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
146 return CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8;
149 #define CVMX_SRIOX_IMSG_QOS_GRPX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000600ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
152 static inline uint64_t CVMX_SRIOX_IMSG_STATUSX(unsigned long offset, unsigned long block_id)
155 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 23)) && ((block_id <= 1)))) ||
156 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 23)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
157 cvmx_warn("CVMX_SRIOX_IMSG_STATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
158 return CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8;
161 #define CVMX_SRIOX_IMSG_STATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000700ull) + (((offset) & 31) + ((block_id) & 3) * 0x200000ull) * 8)
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 static inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR(unsigned long block_id)
167 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
169 cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR(%lu) is invalid on this chip\n", block_id);
170 return CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull;
173 #define CVMX_SRIOX_IMSG_VPORT_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000500ull) + ((block_id) & 3) * 0x1000000ull)
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_SRIOX_IMSG_VPORT_THR2(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
180 cvmx_warn("CVMX_SRIOX_IMSG_VPORT_THR2(%lu) is invalid on this chip\n", block_id);
181 return CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull;
184 #define CVMX_SRIOX_IMSG_VPORT_THR2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000528ull) + ((block_id) & 3) * 0x1000000ull)
186 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
187 static inline uint64_t CVMX_SRIOX_INT2_ENABLE(unsigned long block_id)
190 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
191 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
192 cvmx_warn("CVMX_SRIOX_INT2_ENABLE(%lu) is invalid on this chip\n", block_id);
193 return CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull;
196 #define CVMX_SRIOX_INT2_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E0ull) + ((block_id) & 3) * 0x1000000ull)
198 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
199 static inline uint64_t CVMX_SRIOX_INT2_REG(unsigned long block_id)
202 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
204 cvmx_warn("CVMX_SRIOX_INT2_REG(%lu) is invalid on this chip\n", block_id);
205 return CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull;
208 #define CVMX_SRIOX_INT2_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003E8ull) + ((block_id) & 3) * 0x1000000ull)
210 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
211 static inline uint64_t CVMX_SRIOX_INT_ENABLE(unsigned long block_id)
214 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
215 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
216 cvmx_warn("CVMX_SRIOX_INT_ENABLE(%lu) is invalid on this chip\n", block_id);
217 return CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull;
220 #define CVMX_SRIOX_INT_ENABLE(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000110ull) + ((block_id) & 3) * 0x1000000ull)
222 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
223 static inline uint64_t CVMX_SRIOX_INT_INFO0(unsigned long block_id)
226 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
227 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
228 cvmx_warn("CVMX_SRIOX_INT_INFO0(%lu) is invalid on this chip\n", block_id);
229 return CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull;
232 #define CVMX_SRIOX_INT_INFO0(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000120ull) + ((block_id) & 3) * 0x1000000ull)
234 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
235 static inline uint64_t CVMX_SRIOX_INT_INFO1(unsigned long block_id)
238 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
239 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
240 cvmx_warn("CVMX_SRIOX_INT_INFO1(%lu) is invalid on this chip\n", block_id);
241 return CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull;
244 #define CVMX_SRIOX_INT_INFO1(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000128ull) + ((block_id) & 3) * 0x1000000ull)
246 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
247 static inline uint64_t CVMX_SRIOX_INT_INFO2(unsigned long block_id)
250 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
251 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
252 cvmx_warn("CVMX_SRIOX_INT_INFO2(%lu) is invalid on this chip\n", block_id);
253 return CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull;
256 #define CVMX_SRIOX_INT_INFO2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000130ull) + ((block_id) & 3) * 0x1000000ull)
258 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
259 static inline uint64_t CVMX_SRIOX_INT_INFO3(unsigned long block_id)
262 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
263 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
264 cvmx_warn("CVMX_SRIOX_INT_INFO3(%lu) is invalid on this chip\n", block_id);
265 return CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull;
268 #define CVMX_SRIOX_INT_INFO3(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000138ull) + ((block_id) & 3) * 0x1000000ull)
270 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
271 static inline uint64_t CVMX_SRIOX_INT_REG(unsigned long block_id)
274 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
275 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
276 cvmx_warn("CVMX_SRIOX_INT_REG(%lu) is invalid on this chip\n", block_id);
277 return CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull;
280 #define CVMX_SRIOX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000118ull) + ((block_id) & 3) * 0x1000000ull)
282 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
283 static inline uint64_t CVMX_SRIOX_IP_FEATURE(unsigned long block_id)
286 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
287 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
288 cvmx_warn("CVMX_SRIOX_IP_FEATURE(%lu) is invalid on this chip\n", block_id);
289 return CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull;
292 #define CVMX_SRIOX_IP_FEATURE(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F8ull) + ((block_id) & 3) * 0x1000000ull)
294 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
295 static inline uint64_t CVMX_SRIOX_MAC_BUFFERS(unsigned long block_id)
298 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
300 cvmx_warn("CVMX_SRIOX_MAC_BUFFERS(%lu) is invalid on this chip\n", block_id);
301 return CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull;
304 #define CVMX_SRIOX_MAC_BUFFERS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000390ull) + ((block_id) & 3) * 0x1000000ull)
306 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
307 static inline uint64_t CVMX_SRIOX_MAINT_OP(unsigned long block_id)
310 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
311 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
312 cvmx_warn("CVMX_SRIOX_MAINT_OP(%lu) is invalid on this chip\n", block_id);
313 return CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull;
316 #define CVMX_SRIOX_MAINT_OP(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000158ull) + ((block_id) & 3) * 0x1000000ull)
318 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
319 static inline uint64_t CVMX_SRIOX_MAINT_RD_DATA(unsigned long block_id)
322 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
323 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
324 cvmx_warn("CVMX_SRIOX_MAINT_RD_DATA(%lu) is invalid on this chip\n", block_id);
325 return CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull;
328 #define CVMX_SRIOX_MAINT_RD_DATA(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000160ull) + ((block_id) & 3) * 0x1000000ull)
330 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
331 static inline uint64_t CVMX_SRIOX_MCE_TX_CTL(unsigned long block_id)
334 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
335 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
336 cvmx_warn("CVMX_SRIOX_MCE_TX_CTL(%lu) is invalid on this chip\n", block_id);
337 return CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull;
340 #define CVMX_SRIOX_MCE_TX_CTL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000240ull) + ((block_id) & 3) * 0x1000000ull)
342 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
343 static inline uint64_t CVMX_SRIOX_MEM_OP_CTRL(unsigned long block_id)
346 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
347 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
348 cvmx_warn("CVMX_SRIOX_MEM_OP_CTRL(%lu) is invalid on this chip\n", block_id);
349 return CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull;
352 #define CVMX_SRIOX_MEM_OP_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000168ull) + ((block_id) & 3) * 0x1000000ull)
354 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
355 static inline uint64_t CVMX_SRIOX_OMSG_CTRLX(unsigned long offset, unsigned long block_id)
358 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
359 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
360 cvmx_warn("CVMX_SRIOX_OMSG_CTRLX(%lu,%lu) is invalid on this chip\n", offset, block_id);
361 return CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
364 #define CVMX_SRIOX_OMSG_CTRLX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000488ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
366 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
367 static inline uint64_t CVMX_SRIOX_OMSG_DONE_COUNTSX(unsigned long offset, unsigned long block_id)
370 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
371 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
372 cvmx_warn("CVMX_SRIOX_OMSG_DONE_COUNTSX(%lu,%lu) is invalid on this chip\n", offset, block_id);
373 return CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
376 #define CVMX_SRIOX_OMSG_DONE_COUNTSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004B0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
378 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
379 static inline uint64_t CVMX_SRIOX_OMSG_FMP_MRX(unsigned long offset, unsigned long block_id)
382 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
383 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
384 cvmx_warn("CVMX_SRIOX_OMSG_FMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
385 return CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
388 #define CVMX_SRIOX_OMSG_FMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000498ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
390 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
391 static inline uint64_t CVMX_SRIOX_OMSG_NMP_MRX(unsigned long offset, unsigned long block_id)
394 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
395 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
396 cvmx_warn("CVMX_SRIOX_OMSG_NMP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
397 return CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
400 #define CVMX_SRIOX_OMSG_NMP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80004A0ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
402 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
403 static inline uint64_t CVMX_SRIOX_OMSG_PORTX(unsigned long offset, unsigned long block_id)
406 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
407 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
408 cvmx_warn("CVMX_SRIOX_OMSG_PORTX(%lu,%lu) is invalid on this chip\n", offset, block_id);
409 return CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
412 #define CVMX_SRIOX_OMSG_PORTX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000480ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
414 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
415 static inline uint64_t CVMX_SRIOX_OMSG_SILO_THR(unsigned long block_id)
418 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
419 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
420 cvmx_warn("CVMX_SRIOX_OMSG_SILO_THR(%lu) is invalid on this chip\n", block_id);
421 return CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull;
424 #define CVMX_SRIOX_OMSG_SILO_THR(block_id) (CVMX_ADD_IO_SEG(0x00011800C80004F8ull) + ((block_id) & 3) * 0x1000000ull)
426 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
427 static inline uint64_t CVMX_SRIOX_OMSG_SP_MRX(unsigned long offset, unsigned long block_id)
430 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 1)) && ((block_id <= 1)))) ||
431 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 1)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
432 cvmx_warn("CVMX_SRIOX_OMSG_SP_MRX(%lu,%lu) is invalid on this chip\n", offset, block_id);
433 return CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64;
436 #define CVMX_SRIOX_OMSG_SP_MRX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000490ull) + (((offset) & 1) + ((block_id) & 3) * 0x40000ull) * 64)
438 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
439 static inline uint64_t CVMX_SRIOX_PRIOX_IN_USE(unsigned long offset, unsigned long block_id)
442 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
443 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 3)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
444 cvmx_warn("CVMX_SRIOX_PRIOX_IN_USE(%lu,%lu) is invalid on this chip\n", offset, block_id);
445 return CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8;
448 #define CVMX_SRIOX_PRIOX_IN_USE(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C80003C0ull) + (((offset) & 3) + ((block_id) & 3) * 0x200000ull) * 8)
450 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
451 static inline uint64_t CVMX_SRIOX_RX_BELL(unsigned long block_id)
454 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
455 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
456 cvmx_warn("CVMX_SRIOX_RX_BELL(%lu) is invalid on this chip\n", block_id);
457 return CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull;
460 #define CVMX_SRIOX_RX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000308ull) + ((block_id) & 3) * 0x1000000ull)
462 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
463 static inline uint64_t CVMX_SRIOX_RX_BELL_SEQ(unsigned long block_id)
466 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
467 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
468 cvmx_warn("CVMX_SRIOX_RX_BELL_SEQ(%lu) is invalid on this chip\n", block_id);
469 return CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull;
472 #define CVMX_SRIOX_RX_BELL_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000300ull) + ((block_id) & 3) * 0x1000000ull)
474 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
475 static inline uint64_t CVMX_SRIOX_RX_STATUS(unsigned long block_id)
478 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
479 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
480 cvmx_warn("CVMX_SRIOX_RX_STATUS(%lu) is invalid on this chip\n", block_id);
481 return CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull;
484 #define CVMX_SRIOX_RX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000380ull) + ((block_id) & 3) * 0x1000000ull)
486 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
487 static inline uint64_t CVMX_SRIOX_S2M_TYPEX(unsigned long offset, unsigned long block_id)
490 (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
491 (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset <= 15)) && ((block_id == 0) || (block_id == 2) || (block_id == 3))))))
492 cvmx_warn("CVMX_SRIOX_S2M_TYPEX(%lu,%lu) is invalid on this chip\n", offset, block_id);
493 return CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8;
496 #define CVMX_SRIOX_S2M_TYPEX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000180ull) + (((offset) & 15) + ((block_id) & 3) * 0x200000ull) * 8)
498 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
499 static inline uint64_t CVMX_SRIOX_SEQ(unsigned long block_id)
502 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
503 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
504 cvmx_warn("CVMX_SRIOX_SEQ(%lu) is invalid on this chip\n", block_id);
505 return CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull;
508 #define CVMX_SRIOX_SEQ(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000278ull) + ((block_id) & 3) * 0x1000000ull)
510 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
511 static inline uint64_t CVMX_SRIOX_STATUS_REG(unsigned long block_id)
514 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
515 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
516 cvmx_warn("CVMX_SRIOX_STATUS_REG(%lu) is invalid on this chip\n", block_id);
517 return CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull;
520 #define CVMX_SRIOX_STATUS_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000100ull) + ((block_id) & 3) * 0x1000000ull)
522 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
523 static inline uint64_t CVMX_SRIOX_TAG_CTRL(unsigned long block_id)
526 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
527 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
528 cvmx_warn("CVMX_SRIOX_TAG_CTRL(%lu) is invalid on this chip\n", block_id);
529 return CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull;
532 #define CVMX_SRIOX_TAG_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000178ull) + ((block_id) & 3) * 0x1000000ull)
534 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
535 static inline uint64_t CVMX_SRIOX_TLP_CREDITS(unsigned long block_id)
538 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
539 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
540 cvmx_warn("CVMX_SRIOX_TLP_CREDITS(%lu) is invalid on this chip\n", block_id);
541 return CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull;
544 #define CVMX_SRIOX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000150ull) + ((block_id) & 3) * 0x1000000ull)
546 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
547 static inline uint64_t CVMX_SRIOX_TX_BELL(unsigned long block_id)
550 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
551 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
552 cvmx_warn("CVMX_SRIOX_TX_BELL(%lu) is invalid on this chip\n", block_id);
553 return CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull;
556 #define CVMX_SRIOX_TX_BELL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000280ull) + ((block_id) & 3) * 0x1000000ull)
558 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
559 static inline uint64_t CVMX_SRIOX_TX_BELL_INFO(unsigned long block_id)
562 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
563 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
564 cvmx_warn("CVMX_SRIOX_TX_BELL_INFO(%lu) is invalid on this chip\n", block_id);
565 return CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull;
568 #define CVMX_SRIOX_TX_BELL_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000288ull) + ((block_id) & 3) * 0x1000000ull)
570 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
571 static inline uint64_t CVMX_SRIOX_TX_CTRL(unsigned long block_id)
574 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
575 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
576 cvmx_warn("CVMX_SRIOX_TX_CTRL(%lu) is invalid on this chip\n", block_id);
577 return CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull;
580 #define CVMX_SRIOX_TX_CTRL(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000170ull) + ((block_id) & 3) * 0x1000000ull)
582 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
583 static inline uint64_t CVMX_SRIOX_TX_EMPHASIS(unsigned long block_id)
586 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
587 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
588 cvmx_warn("CVMX_SRIOX_TX_EMPHASIS(%lu) is invalid on this chip\n", block_id);
589 return CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull;
592 #define CVMX_SRIOX_TX_EMPHASIS(block_id) (CVMX_ADD_IO_SEG(0x00011800C80003F0ull) + ((block_id) & 3) * 0x1000000ull)
594 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
595 static inline uint64_t CVMX_SRIOX_TX_STATUS(unsigned long block_id)
598 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
599 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
600 cvmx_warn("CVMX_SRIOX_TX_STATUS(%lu) is invalid on this chip\n", block_id);
601 return CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull;
604 #define CVMX_SRIOX_TX_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000388ull) + ((block_id) & 3) * 0x1000000ull)
606 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
607 static inline uint64_t CVMX_SRIOX_WR_DONE_COUNTS(unsigned long block_id)
610 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) ||
611 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0) || ((block_id >= 2) && (block_id <= 3))))))
612 cvmx_warn("CVMX_SRIOX_WR_DONE_COUNTS(%lu) is invalid on this chip\n", block_id);
613 return CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull;
616 #define CVMX_SRIOX_WR_DONE_COUNTS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000340ull) + ((block_id) & 3) * 0x1000000ull)
620 * cvmx_srio#_acc_ctrl
622 * SRIO_ACC_CTRL = SRIO Access Control
624 * General access control of the incoming BAR registers.
627 * This register controls write access to the BAR registers via SRIO Maintenance Operations. At
628 * powerup the BAR registers can be accessed via RSL and Maintenance Operations. If the DENY_BAR*
629 * bits or DENY_ADR* bits are set then Maintenance Writes to the corresponding BAR fields are
630 * ignored. Setting both the DENY_BAR and DENY_ADR for a corresponding BAR is compatable with the
631 * operation of the DENY_BAR bit found in 63xx Pass 2 and earlier. This register does not effect
632 * read operations. Reset values for DENY_BAR[2:0] are typically clear but they are set if
633 * the chip is operating in Authentik Mode.
635 * Clk_Rst: SRIO(0,2..3)_ACC_CTRL hclk hrst_n
637 union cvmx_sriox_acc_ctrl {
639 struct cvmx_sriox_acc_ctrl_s {
640 #ifdef __BIG_ENDIAN_BITFIELD
641 uint64_t reserved_7_63 : 57;
642 uint64_t deny_adr2 : 1; /**< Deny SRIO Write Access to SRIO Address Fields in
643 SRIOMAINT(0,2..3)_BAR2* Registers */
644 uint64_t deny_adr1 : 1; /**< Deny SRIO Write Access to SRIO Address Fields in
645 SRIOMAINT(0,2..3)_BAR1* Registers */
646 uint64_t deny_adr0 : 1; /**< Deny SRIO Write Access to SRIO Address Fields in
647 SRIOMAINT(0,2..3)_BAR0* Registers */
648 uint64_t reserved_3_3 : 1;
649 uint64_t deny_bar2 : 1; /**< Deny SRIO Write Access to non-SRIO Address Fields
650 in the SRIOMAINT_BAR2 Registers */
651 uint64_t deny_bar1 : 1; /**< Deny SRIO Write Access to non-SRIO Address Fields
652 in the SRIOMAINT_BAR1 Registers */
653 uint64_t deny_bar0 : 1; /**< Deny SRIO Write Access to non-SRIO Address Fields
654 in the SRIOMAINT_BAR0 Registers */
656 uint64_t deny_bar0 : 1;
657 uint64_t deny_bar1 : 1;
658 uint64_t deny_bar2 : 1;
659 uint64_t reserved_3_3 : 1;
660 uint64_t deny_adr0 : 1;
661 uint64_t deny_adr1 : 1;
662 uint64_t deny_adr2 : 1;
663 uint64_t reserved_7_63 : 57;
666 struct cvmx_sriox_acc_ctrl_cn63xx {
667 #ifdef __BIG_ENDIAN_BITFIELD
668 uint64_t reserved_3_63 : 61;
669 uint64_t deny_bar2 : 1; /**< Deny SRIO Write Access to BAR2 Registers */
670 uint64_t deny_bar1 : 1; /**< Deny SRIO Write Access to BAR1 Registers */
671 uint64_t deny_bar0 : 1; /**< Deny SRIO Write Access to BAR0 Registers */
673 uint64_t deny_bar0 : 1;
674 uint64_t deny_bar1 : 1;
675 uint64_t deny_bar2 : 1;
676 uint64_t reserved_3_63 : 61;
679 struct cvmx_sriox_acc_ctrl_cn63xx cn63xxp1;
680 struct cvmx_sriox_acc_ctrl_s cn66xx;
682 typedef union cvmx_sriox_acc_ctrl cvmx_sriox_acc_ctrl_t;
685 * cvmx_srio#_asmbly_id
687 * SRIO_ASMBLY_ID = SRIO Assembly ID
689 * The Assembly ID register controls the Assembly ID and Vendor
692 * This register specifies the Assembly ID and Vendor visible in SRIOMAINT(0,2..3)_ASMBLY_ID register. The
693 * Assembly Vendor ID is typically supplied by the RapidIO Trade Association. This register is only
694 * reset during COLD boot and may only be modified while SRIO(0,2..3)_STATUS_REG.ACCESS is zero.
696 * Clk_Rst: SRIO(0,2..3)_ASMBLY_ID sclk srst_cold_n
698 union cvmx_sriox_asmbly_id {
700 struct cvmx_sriox_asmbly_id_s {
701 #ifdef __BIG_ENDIAN_BITFIELD
702 uint64_t reserved_32_63 : 32;
703 uint64_t assy_id : 16; /**< Assembly Identifer */
704 uint64_t assy_ven : 16; /**< Assembly Vendor Identifer */
706 uint64_t assy_ven : 16;
707 uint64_t assy_id : 16;
708 uint64_t reserved_32_63 : 32;
711 struct cvmx_sriox_asmbly_id_s cn63xx;
712 struct cvmx_sriox_asmbly_id_s cn63xxp1;
713 struct cvmx_sriox_asmbly_id_s cn66xx;
715 typedef union cvmx_sriox_asmbly_id cvmx_sriox_asmbly_id_t;
718 * cvmx_srio#_asmbly_info
720 * SRIO_ASMBLY_INFO = SRIO Assembly Information
722 * The Assembly Info register controls the Assembly Revision
725 * The Assembly Info register controls the Assembly Revision visible in the ASSY_REV field of the
726 * SRIOMAINT(0,2..3)_ASMBLY_INFO register. This register is only reset during COLD boot and may only be
727 * modified while SRIO(0,2..3)_STATUS_REG.ACCESS is zero.
729 * Clk_Rst: SRIO(0,2..3)_ASMBLY_INFO sclk srst_cold_n
731 union cvmx_sriox_asmbly_info {
733 struct cvmx_sriox_asmbly_info_s {
734 #ifdef __BIG_ENDIAN_BITFIELD
735 uint64_t reserved_32_63 : 32;
736 uint64_t assy_rev : 16; /**< Assembly Revision */
737 uint64_t reserved_0_15 : 16;
739 uint64_t reserved_0_15 : 16;
740 uint64_t assy_rev : 16;
741 uint64_t reserved_32_63 : 32;
744 struct cvmx_sriox_asmbly_info_s cn63xx;
745 struct cvmx_sriox_asmbly_info_s cn63xxp1;
746 struct cvmx_sriox_asmbly_info_s cn66xx;
748 typedef union cvmx_sriox_asmbly_info cvmx_sriox_asmbly_info_t;
751 * cvmx_srio#_bell_resp_ctrl
753 * SRIO_BELL_RESP_CTRL = SRIO Doorbell Response Control
755 * The SRIO Doorbell Response Control Register
758 * This register is used to override the response priority of the outgoing doorbell responses.
760 * Clk_Rst: SRIO(0,2..3)_BELL_RESP_CTRL hclk hrst_n
762 union cvmx_sriox_bell_resp_ctrl {
764 struct cvmx_sriox_bell_resp_ctrl_s {
765 #ifdef __BIG_ENDIAN_BITFIELD
766 uint64_t reserved_6_63 : 58;
767 uint64_t rp1_sid : 1; /**< Sets response priority for incomimg doorbells
768 of priority 1 on the secondary ID (0=2, 1=3) */
769 uint64_t rp0_sid : 2; /**< Sets response priority for incomimg doorbells
770 of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */
771 uint64_t rp1_pid : 1; /**< Sets response priority for incomimg doorbells
772 of priority 1 on the primary ID (0=2, 1=3) */
773 uint64_t rp0_pid : 2; /**< Sets response priority for incomimg doorbells
774 of priority 0 on the primary ID (0,1=1 2=2, 3=3) */
776 uint64_t rp0_pid : 2;
777 uint64_t rp1_pid : 1;
778 uint64_t rp0_sid : 2;
779 uint64_t rp1_sid : 1;
780 uint64_t reserved_6_63 : 58;
783 struct cvmx_sriox_bell_resp_ctrl_s cn63xx;
784 struct cvmx_sriox_bell_resp_ctrl_s cn63xxp1;
785 struct cvmx_sriox_bell_resp_ctrl_s cn66xx;
787 typedef union cvmx_sriox_bell_resp_ctrl cvmx_sriox_bell_resp_ctrl_t;
790 * cvmx_srio#_bist_status
792 * SRIO_BIST_STATUS = SRIO Bist Status
794 * Results from BIST runs of SRIO's memories.
799 * Clk_Rst: SRIO(0,2..3)_BIST_STATUS hclk hrst_n
801 union cvmx_sriox_bist_status {
803 struct cvmx_sriox_bist_status_s {
804 #ifdef __BIG_ENDIAN_BITFIELD
805 uint64_t reserved_45_63 : 19;
806 uint64_t lram : 1; /**< Incoming Doorbell Lookup RAM. */
807 uint64_t mram : 2; /**< Incoming Message SLI FIFO. */
808 uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */
809 uint64_t bell : 2; /**< Incoming Doorbell FIFO. */
810 uint64_t otag : 2; /**< Outgoing Tag Data. */
811 uint64_t itag : 1; /**< Incoming TAG Data. */
812 uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */
813 uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */
814 uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */
815 uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */
816 uint64_t oarb2 : 2; /**< Additional Outgoing Priority RAMs. */
817 uint64_t rxbuf2 : 2; /**< Additional Incoming SRIO MAC Buffers. */
818 uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */
819 uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */
820 uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */
821 uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */
822 uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */
823 uint64_t imsg : 5; /**< Incoming Message RAMs. */
824 uint64_t omsg : 7; /**< Outgoing Message RAMs. */
845 uint64_t reserved_45_63 : 19;
848 struct cvmx_sriox_bist_status_cn63xx {
849 #ifdef __BIG_ENDIAN_BITFIELD
850 uint64_t reserved_44_63 : 20;
851 uint64_t mram : 2; /**< Incoming Message SLI FIFO. */
852 uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */
853 uint64_t bell : 2; /**< Incoming Doorbell FIFO. */
854 uint64_t otag : 2; /**< Outgoing Tag Data. */
855 uint64_t itag : 1; /**< Incoming TAG Data. */
856 uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */
857 uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */
858 uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */
859 uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */
860 uint64_t oarb2 : 2; /**< Additional Outgoing Priority RAMs (Pass 2). */
861 uint64_t rxbuf2 : 2; /**< Additional Incoming SRIO MAC Buffers (Pass 2). */
862 uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */
863 uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */
864 uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */
865 uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */
866 uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */
867 uint64_t imsg : 5; /**< Incoming Message RAMs.
868 IMSG<0> (i.e. <7>) unused in Pass 2 */
869 uint64_t omsg : 7; /**< Outgoing Message RAMs. */
889 uint64_t reserved_44_63 : 20;
892 struct cvmx_sriox_bist_status_cn63xxp1 {
893 #ifdef __BIG_ENDIAN_BITFIELD
894 uint64_t reserved_44_63 : 20;
895 uint64_t mram : 2; /**< Incoming Message SLI FIFO. */
896 uint64_t cram : 2; /**< Incoming Rd/Wr/Response Command FIFO. */
897 uint64_t bell : 2; /**< Incoming Doorbell FIFO. */
898 uint64_t otag : 2; /**< Outgoing Tag Data. */
899 uint64_t itag : 1; /**< Incoming TAG Data. */
900 uint64_t ofree : 1; /**< Outgoing Free Pointer RAM (OFIFO) */
901 uint64_t rtn : 2; /**< Outgoing Response Return FIFO. */
902 uint64_t obulk : 4; /**< Outgoing Bulk Data RAMs (OFIFO) */
903 uint64_t optrs : 4; /**< Outgoing Priority Pointer RAMs (OFIFO) */
904 uint64_t reserved_20_23 : 4;
905 uint64_t oarb : 2; /**< Outgoing Priority RAMs (OARB) */
906 uint64_t ispf : 1; /**< Incoming Soft Packet FIFO */
907 uint64_t ospf : 1; /**< Outgoing Soft Packet FIFO */
908 uint64_t txbuf : 2; /**< Outgoing SRIO MAC Buffer. */
909 uint64_t rxbuf : 2; /**< Incoming SRIO MAC Buffer. */
910 uint64_t imsg : 5; /**< Incoming Message RAMs. */
911 uint64_t omsg : 7; /**< Outgoing Message RAMs. */
920 uint64_t reserved_20_23 : 4;
930 uint64_t reserved_44_63 : 20;
933 struct cvmx_sriox_bist_status_s cn66xx;
935 typedef union cvmx_sriox_bist_status cvmx_sriox_bist_status_t;
938 * cvmx_srio#_imsg_ctrl
940 * SRIO_IMSG_CTRL = SRIO Incoming Message Control
942 * The SRIO Incoming Message Control Register
945 * RSP_THR should not typically be modified from reset value.
947 * Clk_Rst: SRIO(0,2..3)_IMSG_CTRL hclk hrst_n
949 union cvmx_sriox_imsg_ctrl {
951 struct cvmx_sriox_imsg_ctrl_s {
952 #ifdef __BIG_ENDIAN_BITFIELD
953 uint64_t reserved_32_63 : 32;
954 uint64_t to_mode : 1; /**< MP message timeout mode:
955 - 0: The timeout counter gets reset whenever the
956 next sequential segment is received, regardless
957 of whether it is accepted
958 - 1: The timeout counter gets reset only when the
959 next sequential segment is received and
961 uint64_t reserved_30_30 : 1;
962 uint64_t rsp_thr : 6; /**< Reserved */
963 uint64_t reserved_22_23 : 2;
964 uint64_t rp1_sid : 1; /**< Sets msg response priority for incomimg messages
965 of priority 1 on the secondary ID (0=2, 1=3) */
966 uint64_t rp0_sid : 2; /**< Sets msg response priority for incomimg messages
967 of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */
968 uint64_t rp1_pid : 1; /**< Sets msg response priority for incomimg messages
969 of priority 1 on the primary ID (0=2, 1=3) */
970 uint64_t rp0_pid : 2; /**< Sets msg response priority for incomimg messages
971 of priority 0 on the primary ID (0,1=1 2=2, 3=3) */
972 uint64_t reserved_15_15 : 1;
973 uint64_t prt_sel : 3; /**< Port/Controller selection method:
974 - 0: Table lookup based on mailbox
975 - 1: Table lookup based on priority
976 - 2: Table lookup based on letter
977 - 3: Size-based (SP to port 0, MP to port 1)
978 - 4: ID-based (pri ID to port 0, sec ID to port 1) */
979 uint64_t lttr : 4; /**< Port/Controller selection letter table */
980 uint64_t prio : 4; /**< Port/Controller selection priority table */
981 uint64_t mbox : 4; /**< Port/Controller selection mailbox table */
986 uint64_t prt_sel : 3;
987 uint64_t reserved_15_15 : 1;
988 uint64_t rp0_pid : 2;
989 uint64_t rp1_pid : 1;
990 uint64_t rp0_sid : 2;
991 uint64_t rp1_sid : 1;
992 uint64_t reserved_22_23 : 2;
993 uint64_t rsp_thr : 6;
994 uint64_t reserved_30_30 : 1;
995 uint64_t to_mode : 1;
996 uint64_t reserved_32_63 : 32;
999 struct cvmx_sriox_imsg_ctrl_s cn63xx;
1000 struct cvmx_sriox_imsg_ctrl_s cn63xxp1;
1001 struct cvmx_sriox_imsg_ctrl_s cn66xx;
1003 typedef union cvmx_sriox_imsg_ctrl cvmx_sriox_imsg_ctrl_t;
1006 * cvmx_srio#_imsg_inst_hdr#
1008 * SRIO_IMSG_INST_HDRX = SRIO Incoming Message Packet Instruction Header
1010 * The SRIO Port/Controller X Incoming Message Packet Instruction Header Register
1013 * SRIO HW generates most of the SRIO_WORD1 fields from these values. SRIO_WORD1 is the 2nd of two
1014 * header words that SRIO inserts in front of all received messages. SRIO_WORD1 may commonly be used
1015 * as a PIP/IPD PKT_INST_HDR. This CSR matches the PIP/IPD PKT_INST_HDR format except for the QOS
1016 * and GRP fields. SRIO*_IMSG_QOS_GRP*[QOS*,GRP*] supply the QOS and GRP fields.
1018 * Clk_Rst: SRIO(0,2..3)_IMSG_INST_HDR[0:1] hclk hrst_n
1020 union cvmx_sriox_imsg_inst_hdrx {
1022 struct cvmx_sriox_imsg_inst_hdrx_s {
1023 #ifdef __BIG_ENDIAN_BITFIELD
1024 uint64_t r : 1; /**< Port/Controller X R */
1025 uint64_t reserved_58_62 : 5;
1026 uint64_t pm : 2; /**< Port/Controller X PM */
1027 uint64_t reserved_55_55 : 1;
1028 uint64_t sl : 7; /**< Port/Controller X SL */
1029 uint64_t reserved_46_47 : 2;
1030 uint64_t nqos : 1; /**< Port/Controller X NQOS */
1031 uint64_t ngrp : 1; /**< Port/Controller X NGRP */
1032 uint64_t ntt : 1; /**< Port/Controller X NTT */
1033 uint64_t ntag : 1; /**< Port/Controller X NTAG */
1034 uint64_t reserved_35_41 : 7;
1035 uint64_t rs : 1; /**< Port/Controller X RS */
1036 uint64_t tt : 2; /**< Port/Controller X TT */
1037 uint64_t tag : 32; /**< Port/Controller X TAG */
1042 uint64_t reserved_35_41 : 7;
1047 uint64_t reserved_46_47 : 2;
1049 uint64_t reserved_55_55 : 1;
1051 uint64_t reserved_58_62 : 5;
1055 struct cvmx_sriox_imsg_inst_hdrx_s cn63xx;
1056 struct cvmx_sriox_imsg_inst_hdrx_s cn63xxp1;
1057 struct cvmx_sriox_imsg_inst_hdrx_s cn66xx;
1059 typedef union cvmx_sriox_imsg_inst_hdrx cvmx_sriox_imsg_inst_hdrx_t;
1062 * cvmx_srio#_imsg_qos_grp#
1064 * SRIO_IMSG_QOS_GRPX = SRIO Incoming Message QOS/GRP Table
1066 * The SRIO Incoming Message QOS/GRP Table Entry X
1069 * The QOS/GRP table contains 32 entries with 8 QOS/GRP pairs per entry - 256 pairs total. HW
1070 * selects the table entry by the concatenation of SRIO_WORD0[PRIO,DIS,MBOX], thus entry 0 is used
1071 * for messages with PRIO=0,DIS=0,MBOX=0, entry 1 is for PRIO=0,DIS=0,MBOX=1, etc. HW selects the
1072 * QOS/GRP pair from the table entry by the concatenation of SRIO_WORD0[ID,LETTER] as shown above. HW
1073 * then inserts the QOS/GRP pair into SRIO_WORD1[QOS,GRP], which may commonly be used for the PIP/IPD
1074 * PKT_INST_HDR[QOS,GRP] fields.
1076 * Clk_Rst: SRIO(0,2..3)_IMSG_QOS_GRP[0:1] hclk hrst_n
1078 union cvmx_sriox_imsg_qos_grpx {
1080 struct cvmx_sriox_imsg_qos_grpx_s {
1081 #ifdef __BIG_ENDIAN_BITFIELD
1082 uint64_t reserved_63_63 : 1;
1083 uint64_t qos7 : 3; /**< Entry X:7 QOS (ID=1, LETTER=3) */
1084 uint64_t grp7 : 4; /**< Entry X:7 GRP (ID=1, LETTER=3) */
1085 uint64_t reserved_55_55 : 1;
1086 uint64_t qos6 : 3; /**< Entry X:6 QOS (ID=1, LETTER=2) */
1087 uint64_t grp6 : 4; /**< Entry X:6 GRP (ID=1, LETTER=2) */
1088 uint64_t reserved_47_47 : 1;
1089 uint64_t qos5 : 3; /**< Entry X:5 QOS (ID=1, LETTER=1) */
1090 uint64_t grp5 : 4; /**< Entry X:5 GRP (ID=1, LETTER=1) */
1091 uint64_t reserved_39_39 : 1;
1092 uint64_t qos4 : 3; /**< Entry X:4 QOS (ID=1, LETTER=0) */
1093 uint64_t grp4 : 4; /**< Entry X:4 GRP (ID=1, LETTER=0) */
1094 uint64_t reserved_31_31 : 1;
1095 uint64_t qos3 : 3; /**< Entry X:3 QOS (ID=0, LETTER=3) */
1096 uint64_t grp3 : 4; /**< Entry X:3 GRP (ID=0, LETTER=3) */
1097 uint64_t reserved_23_23 : 1;
1098 uint64_t qos2 : 3; /**< Entry X:2 QOS (ID=0, LETTER=2) */
1099 uint64_t grp2 : 4; /**< Entry X:2 GRP (ID=0, LETTER=2) */
1100 uint64_t reserved_15_15 : 1;
1101 uint64_t qos1 : 3; /**< Entry X:1 QOS (ID=0, LETTER=1) */
1102 uint64_t grp1 : 4; /**< Entry X:1 GRP (ID=0, LETTER=1) */
1103 uint64_t reserved_7_7 : 1;
1104 uint64_t qos0 : 3; /**< Entry X:0 QOS (ID=0, LETTER=0) */
1105 uint64_t grp0 : 4; /**< Entry X:0 GRP (ID=0, LETTER=0) */
1109 uint64_t reserved_7_7 : 1;
1112 uint64_t reserved_15_15 : 1;
1115 uint64_t reserved_23_23 : 1;
1118 uint64_t reserved_31_31 : 1;
1121 uint64_t reserved_39_39 : 1;
1124 uint64_t reserved_47_47 : 1;
1127 uint64_t reserved_55_55 : 1;
1130 uint64_t reserved_63_63 : 1;
1133 struct cvmx_sriox_imsg_qos_grpx_s cn63xx;
1134 struct cvmx_sriox_imsg_qos_grpx_s cn63xxp1;
1135 struct cvmx_sriox_imsg_qos_grpx_s cn66xx;
1137 typedef union cvmx_sriox_imsg_qos_grpx cvmx_sriox_imsg_qos_grpx_t;
1140 * cvmx_srio#_imsg_status#
1142 * SRIO_IMSG_STATUSX = SRIO Incoming Message Status Table
1144 * The SRIO Incoming Message Status Table Entry X
1147 * Clk_Rst: SRIO(0,2..3)_IMSG_STATUS[0:1] hclk hrst_n
1150 union cvmx_sriox_imsg_statusx {
1152 struct cvmx_sriox_imsg_statusx_s {
1153 #ifdef __BIG_ENDIAN_BITFIELD
1154 uint64_t val1 : 1; /**< Entry X:1 Valid */
1155 uint64_t err1 : 1; /**< Entry X:1 Error */
1156 uint64_t toe1 : 1; /**< Entry X:1 Timeout Error */
1157 uint64_t toc1 : 1; /**< Entry X:1 Timeout Count */
1158 uint64_t prt1 : 1; /**< Entry X:1 Port */
1159 uint64_t reserved_58_58 : 1;
1160 uint64_t tt1 : 1; /**< Entry X:1 TT ID */
1161 uint64_t dis1 : 1; /**< Entry X:1 Dest ID */
1162 uint64_t seg1 : 4; /**< Entry X:1 Next Segment */
1163 uint64_t mbox1 : 2; /**< Entry X:1 Mailbox */
1164 uint64_t lttr1 : 2; /**< Entry X:1 Letter */
1165 uint64_t sid1 : 16; /**< Entry X:1 Source ID */
1166 uint64_t val0 : 1; /**< Entry X:0 Valid */
1167 uint64_t err0 : 1; /**< Entry X:0 Error */
1168 uint64_t toe0 : 1; /**< Entry X:0 Timeout Error */
1169 uint64_t toc0 : 1; /**< Entry X:0 Timeout Count */
1170 uint64_t prt0 : 1; /**< Entry X:0 Port */
1171 uint64_t reserved_26_26 : 1;
1172 uint64_t tt0 : 1; /**< Entry X:0 TT ID */
1173 uint64_t dis0 : 1; /**< Entry X:0 Dest ID */
1174 uint64_t seg0 : 4; /**< Entry X:0 Next Segment */
1175 uint64_t mbox0 : 2; /**< Entry X:0 Mailbox */
1176 uint64_t lttr0 : 2; /**< Entry X:0 Letter */
1177 uint64_t sid0 : 16; /**< Entry X:0 Source ID */
1185 uint64_t reserved_26_26 : 1;
1197 uint64_t reserved_58_58 : 1;
1205 struct cvmx_sriox_imsg_statusx_s cn63xx;
1206 struct cvmx_sriox_imsg_statusx_s cn63xxp1;
1207 struct cvmx_sriox_imsg_statusx_s cn66xx;
1209 typedef union cvmx_sriox_imsg_statusx cvmx_sriox_imsg_statusx_t;
1212 * cvmx_srio#_imsg_vport_thr
1214 * SRIO_IMSG_VPORT_THR = SRIO Incoming Message Virtual Port Threshold
1216 * The SRIO Incoming Message Virtual Port Threshold Register
1219 * SRIO0_IMSG_VPORT_THR.MAX_TOT must be >= SRIO0_IMSG_VPORT_THR.BUF_THR
1220 * + SRIO2_IMSG_VPORT_THR.BUF_THR + SRIO3_IMSG_VPORT_THR.BUF_THR. This register can be accessed
1221 * regardless of the value in SRIO(0,2..3)_STATUS_REG.ACCESS and is not effected by MAC reset. The maximum
1222 * number of VPORTs allocated to a MAC is limited to 46 if QLM0 is configured to x2 or x4 mode and 44
1223 * if configured in x1 mode.
1225 * Clk_Rst: SRIO(0,2..3)_IMSG_VPORT_THR sclk srst_n
1227 union cvmx_sriox_imsg_vport_thr {
1229 struct cvmx_sriox_imsg_vport_thr_s {
1230 #ifdef __BIG_ENDIAN_BITFIELD
1231 uint64_t reserved_54_63 : 10;
1232 uint64_t max_tot : 6; /**< Sets max number of vports available to the chip
1233 This field is only used in SRIO0. */
1234 uint64_t reserved_46_47 : 2;
1235 uint64_t max_s1 : 6; /**< Reserved
1236 This field is only used in SRIO0. */
1237 uint64_t reserved_38_39 : 2;
1238 uint64_t max_s0 : 6; /**< Sets max number of vports available to SRIO0
1239 This field is only used in SRIO0. */
1240 uint64_t sp_vport : 1; /**< Single-segment vport pre-allocation.
1241 When set, single-segment messages use pre-allocated
1242 vport slots (that do not count toward thresholds).
1243 When clear, single-segment messages must allocate
1244 vport slots just like multi-segment messages do. */
1245 uint64_t reserved_20_30 : 11;
1246 uint64_t buf_thr : 4; /**< Sets number of vports to be buffered by this
1247 interface. BUF_THR must not be zero when receiving
1248 messages. The max BUF_THR value is 8.
1249 Recommend BUF_THR values 1-4. If the 46 available
1250 vports are not statically-allocated across the two
1251 SRIO's, smaller BUF_THR values may leave more
1252 vports available for the other SRIO. Lack of a
1253 buffered vport can force a retry for a received
1254 first segment, so, particularly if SP_VPORT=0
1255 (which is not recommended) or the segment size is
1256 small, larger BUF_THR values may improve
1258 uint64_t reserved_14_15 : 2;
1259 uint64_t max_p1 : 6; /**< Sets max number of open vports in port 1 */
1260 uint64_t reserved_6_7 : 2;
1261 uint64_t max_p0 : 6; /**< Sets max number of open vports in port 0 */
1263 uint64_t max_p0 : 6;
1264 uint64_t reserved_6_7 : 2;
1265 uint64_t max_p1 : 6;
1266 uint64_t reserved_14_15 : 2;
1267 uint64_t buf_thr : 4;
1268 uint64_t reserved_20_30 : 11;
1269 uint64_t sp_vport : 1;
1270 uint64_t max_s0 : 6;
1271 uint64_t reserved_38_39 : 2;
1272 uint64_t max_s1 : 6;
1273 uint64_t reserved_46_47 : 2;
1274 uint64_t max_tot : 6;
1275 uint64_t reserved_54_63 : 10;
1278 struct cvmx_sriox_imsg_vport_thr_s cn63xx;
1279 struct cvmx_sriox_imsg_vport_thr_s cn63xxp1;
1280 struct cvmx_sriox_imsg_vport_thr_s cn66xx;
1282 typedef union cvmx_sriox_imsg_vport_thr cvmx_sriox_imsg_vport_thr_t;
1285 * cvmx_srio#_imsg_vport_thr2
1287 * SRIO_IMSG_VPORT_THR2 = SRIO Incoming Message Virtual Port Additional Threshold
1289 * The SRIO Incoming Message Virtual Port Additional Threshold Register
1292 * Additional vport thresholds for SRIO MACs 2 and 3. This register is only used in SRIO0 and is only
1293 * used when the QLM0 is configured as x1 lanes or x2 lanes. In the x1 case the maximum number of
1294 * VPORTs is limited to 44. In the x2 case the maximum number of VPORTs is limited to 46. These
1295 * values are ignored in the x4 configuration. This register can be accessed regardless of the value
1296 * in SRIO(0,2..3)_STATUS_REG.ACCESS and is not effected by MAC reset.
1298 * Clk_Rst: SRIO(0,2..3)_IMSG_VPORT_THR sclk srst_n
1300 union cvmx_sriox_imsg_vport_thr2 {
1302 struct cvmx_sriox_imsg_vport_thr2_s {
1303 #ifdef __BIG_ENDIAN_BITFIELD
1304 uint64_t reserved_46_63 : 18;
1305 uint64_t max_s3 : 6; /**< Sets max number of vports available to SRIO3
1306 This field is only used in SRIO0. */
1307 uint64_t reserved_38_39 : 2;
1308 uint64_t max_s2 : 6; /**< Sets max number of vports available to SRIO2
1309 This field is only used in SRIO0. */
1310 uint64_t reserved_0_31 : 32;
1312 uint64_t reserved_0_31 : 32;
1313 uint64_t max_s2 : 6;
1314 uint64_t reserved_38_39 : 2;
1315 uint64_t max_s3 : 6;
1316 uint64_t reserved_46_63 : 18;
1319 struct cvmx_sriox_imsg_vport_thr2_s cn66xx;
1321 typedef union cvmx_sriox_imsg_vport_thr2 cvmx_sriox_imsg_vport_thr2_t;
1324 * cvmx_srio#_int2_enable
1326 * SRIO_INT2_ENABLE = SRIO Interrupt 2 Enable
1328 * Allows SRIO to generate additional interrupts when corresponding enable bit is set.
1331 * This register enables interrupts in SRIO(0,2..3)_INT2_REG that can be asserted while the MAC is in reset.
1332 * The register can be accessed/modified regardless of the value of SRIO(0,2..3)_STATUS_REG.ACCESS.
1334 * Clk_Rst: SRIO(0,2..3)_INT2_ENABLE sclk srst_n
1336 union cvmx_sriox_int2_enable {
1338 struct cvmx_sriox_int2_enable_s {
1339 #ifdef __BIG_ENDIAN_BITFIELD
1340 uint64_t reserved_1_63 : 63;
1341 uint64_t pko_rst : 1; /**< PKO Reset Error Enable */
1343 uint64_t pko_rst : 1;
1344 uint64_t reserved_1_63 : 63;
1347 struct cvmx_sriox_int2_enable_s cn63xx;
1348 struct cvmx_sriox_int2_enable_s cn66xx;
1350 typedef union cvmx_sriox_int2_enable cvmx_sriox_int2_enable_t;
1353 * cvmx_srio#_int2_reg
1355 * SRIO_INT2_REG = SRIO Interrupt 2 Register
1357 * Displays and clears which enabled interrupts have occured
1360 * This register provides interrupt status. Unlike SRIO*_INT_REG, SRIO*_INT2_REG can be accessed
1361 * whenever the SRIO is present, regardless of whether the corresponding SRIO is in reset or not.
1362 * INT_SUM shows the status of the interrupts in SRIO(0,2..3)_INT_REG. Any set bits written to this
1363 * register clear the corresponding interrupt. The register can be accessed/modified regardless of
1364 * the value of SRIO(0,2..3)_STATUS_REG.ACCESS and probably should be the first register read when an SRIO
1367 * Clk_Rst: SRIO(0,2..3)_INT2_REG sclk srst_n
1369 union cvmx_sriox_int2_reg {
1371 struct cvmx_sriox_int2_reg_s {
1372 #ifdef __BIG_ENDIAN_BITFIELD
1373 uint64_t reserved_32_63 : 32;
1374 uint64_t int_sum : 1; /**< Interrupt Set and Enabled in SRIO(0,2..3)_INT_REG */
1375 uint64_t reserved_1_30 : 30;
1376 uint64_t pko_rst : 1; /**< PKO Reset Error - Message Received from PKO while
1379 uint64_t pko_rst : 1;
1380 uint64_t reserved_1_30 : 30;
1381 uint64_t int_sum : 1;
1382 uint64_t reserved_32_63 : 32;
1385 struct cvmx_sriox_int2_reg_s cn63xx;
1386 struct cvmx_sriox_int2_reg_s cn66xx;
1388 typedef union cvmx_sriox_int2_reg cvmx_sriox_int2_reg_t;
1391 * cvmx_srio#_int_enable
1393 * SRIO_INT_ENABLE = SRIO Interrupt Enable
1395 * Allows SRIO to generate interrupts when corresponding enable bit is set.
1398 * This register enables interrupts.
1400 * Clk_Rst: SRIO(0,2..3)_INT_ENABLE hclk hrst_n
1402 union cvmx_sriox_int_enable {
1404 struct cvmx_sriox_int_enable_s {
1405 #ifdef __BIG_ENDIAN_BITFIELD
1406 uint64_t reserved_27_63 : 37;
1407 uint64_t zero_pkt : 1; /**< Received Incoming SRIO Zero byte packet */
1408 uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout */
1409 uint64_t fail : 1; /**< ERB Error Rate reached Fail Count */
1410 uint64_t degrade : 1; /**< ERB Error Rate reached Degrade Count */
1411 uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error */
1412 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */
1413 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */
1414 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */
1415 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */
1416 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */
1417 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */
1418 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */
1419 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */
1420 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */
1421 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */
1422 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */
1423 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */
1424 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */
1425 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */
1426 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */
1427 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */
1428 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */
1429 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */
1430 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */
1431 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */
1432 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */
1433 uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */
1435 uint64_t txbell : 1;
1436 uint64_t bell_err : 1;
1437 uint64_t rxbell : 1;
1438 uint64_t maint_op : 1;
1439 uint64_t bar_err : 1;
1440 uint64_t deny_wr : 1;
1441 uint64_t sli_err : 1;
1442 uint64_t wr_done : 1;
1443 uint64_t mce_tx : 1;
1444 uint64_t mce_rx : 1;
1445 uint64_t soft_tx : 1;
1446 uint64_t soft_rx : 1;
1447 uint64_t log_erb : 1;
1448 uint64_t phy_erb : 1;
1449 uint64_t link_dwn : 1;
1450 uint64_t link_up : 1;
1453 uint64_t omsg_err : 1;
1454 uint64_t pko_err : 1;
1455 uint64_t rtry_err : 1;
1456 uint64_t f_error : 1;
1457 uint64_t mac_buf : 1;
1458 uint64_t degrade : 1;
1460 uint64_t ttl_tout : 1;
1461 uint64_t zero_pkt : 1;
1462 uint64_t reserved_27_63 : 37;
1465 struct cvmx_sriox_int_enable_s cn63xx;
1466 struct cvmx_sriox_int_enable_cn63xxp1 {
1467 #ifdef __BIG_ENDIAN_BITFIELD
1468 uint64_t reserved_22_63 : 42;
1469 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */
1470 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded */
1471 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */
1472 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error */
1473 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */
1474 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */
1475 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */
1476 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */
1477 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB */
1478 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB */
1479 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */
1480 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */
1481 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */
1482 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */
1483 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */
1484 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received. */
1485 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */
1486 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */
1487 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete. */
1488 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received. */
1489 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error. */
1490 uint64_t txbell : 1; /**< Outgoing Doorbell Complete. */
1492 uint64_t txbell : 1;
1493 uint64_t bell_err : 1;
1494 uint64_t rxbell : 1;
1495 uint64_t maint_op : 1;
1496 uint64_t bar_err : 1;
1497 uint64_t deny_wr : 1;
1498 uint64_t sli_err : 1;
1499 uint64_t wr_done : 1;
1500 uint64_t mce_tx : 1;
1501 uint64_t mce_rx : 1;
1502 uint64_t soft_tx : 1;
1503 uint64_t soft_rx : 1;
1504 uint64_t log_erb : 1;
1505 uint64_t phy_erb : 1;
1506 uint64_t link_dwn : 1;
1507 uint64_t link_up : 1;
1510 uint64_t omsg_err : 1;
1511 uint64_t pko_err : 1;
1512 uint64_t rtry_err : 1;
1513 uint64_t f_error : 1;
1514 uint64_t reserved_22_63 : 42;
1517 struct cvmx_sriox_int_enable_s cn66xx;
1519 typedef union cvmx_sriox_int_enable cvmx_sriox_int_enable_t;
1522 * cvmx_srio#_int_info0
1524 * SRIO_INT_INFO0 = SRIO Interrupt Information
1526 * The SRIO Interrupt Information
1529 * This register contains the first header word of the illegal s2m transaction associated with the
1530 * SLI_ERR interrupt. The remaining information is located in SRIO(0,2..3)_INT_INFO1. This register is
1531 * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then
1532 * additional information can be captured.
1533 * Common Errors Include:
1534 * 1. Load/Stores with Length over 32
1535 * 2. Load/Stores that translate to Maintenance Ops with a length over 8
1536 * 3. Load Ops that translate to Atomic Ops with other than 1, 2 and 4 byte accesses
1537 * 4. Load/Store Ops with a Length 0
1538 * 5. Unexpected Responses
1540 * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n
1542 union cvmx_sriox_int_info0 {
1544 struct cvmx_sriox_int_info0_s {
1545 #ifdef __BIG_ENDIAN_BITFIELD
1546 uint64_t cmd : 4; /**< Command
1547 0 = Load, Outgoing Read Request
1548 4 = Store, Outgoing Write Request
1549 8 = Response, Outgoing Read Response
1550 All Others are reserved and generate errors */
1551 uint64_t type : 4; /**< Command Type
1552 Load/Store SRIO_S2M_TYPE used
1553 Response (Reserved) */
1554 uint64_t tag : 8; /**< Internal Transaction Number */
1555 uint64_t reserved_42_47 : 6;
1556 uint64_t length : 10; /**< Data Length in 64-bit Words (Load/Store Only) */
1557 uint64_t status : 3; /**< Response Status
1560 All others reserved */
1561 uint64_t reserved_16_28 : 13;
1562 uint64_t be0 : 8; /**< First 64-bit Word Byte Enables (Load/Store Only) */
1563 uint64_t be1 : 8; /**< Last 64-bit Word Byte Enables (Load/Store Only) */
1567 uint64_t reserved_16_28 : 13;
1568 uint64_t status : 3;
1569 uint64_t length : 10;
1570 uint64_t reserved_42_47 : 6;
1576 struct cvmx_sriox_int_info0_s cn63xx;
1577 struct cvmx_sriox_int_info0_s cn63xxp1;
1578 struct cvmx_sriox_int_info0_s cn66xx;
1580 typedef union cvmx_sriox_int_info0 cvmx_sriox_int_info0_t;
1583 * cvmx_srio#_int_info1
1585 * SRIO_INT_INFO1 = SRIO Interrupt Information
1587 * The SRIO Interrupt Information
1590 * This register contains the second header word of the illegal s2m transaction associated with the
1591 * SLI_ERR interrupt. The remaining information is located in SRIO(0,2..3)_INT_INFO0. This register is
1592 * only updated when the SLI_ERR is initially detected. Once the interrupt is cleared then
1593 * additional information can be captured.
1595 * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n
1597 union cvmx_sriox_int_info1 {
1599 struct cvmx_sriox_int_info1_s {
1600 #ifdef __BIG_ENDIAN_BITFIELD
1601 uint64_t info1 : 64; /**< Address (Load/Store) or First 64-bit Word of
1602 Response Data Associated with Interrupt */
1604 uint64_t info1 : 64;
1607 struct cvmx_sriox_int_info1_s cn63xx;
1608 struct cvmx_sriox_int_info1_s cn63xxp1;
1609 struct cvmx_sriox_int_info1_s cn66xx;
1611 typedef union cvmx_sriox_int_info1 cvmx_sriox_int_info1_t;
1614 * cvmx_srio#_int_info2
1616 * SRIO_INT_INFO2 = SRIO Interrupt Information
1618 * The SRIO Interrupt Information
1621 * This register contains the invalid outbound message descriptor associated with the OMSG_ERR
1622 * interrupt. This register is only updated when the OMSG_ERR is initially detected. Once the
1623 * interrupt is cleared then additional information can be captured.
1625 * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n
1627 union cvmx_sriox_int_info2 {
1629 struct cvmx_sriox_int_info2_s {
1630 #ifdef __BIG_ENDIAN_BITFIELD
1631 uint64_t prio : 2; /**< PRIO field of outbound message descriptor
1632 associated with the OMSG_ERR interrupt */
1633 uint64_t tt : 1; /**< TT field of outbound message descriptor
1634 associated with the OMSG_ERR interrupt */
1635 uint64_t sis : 1; /**< SIS field of outbound message descriptor
1636 associated with the OMSG_ERR interrupt */
1637 uint64_t ssize : 4; /**< SSIZE field of outbound message descriptor
1638 associated with the OMSG_ERR interrupt */
1639 uint64_t did : 16; /**< DID field of outbound message descriptor
1640 associated with the OMSG_ERR interrupt */
1641 uint64_t xmbox : 4; /**< XMBOX field of outbound message descriptor
1642 associated with the OMSG_ERR interrupt */
1643 uint64_t mbox : 2; /**< MBOX field of outbound message descriptor
1644 associated with the OMSG_ERR interrupt */
1645 uint64_t letter : 2; /**< LETTER field of outbound message descriptor
1646 associated with the OMSG_ERR interrupt */
1647 uint64_t rsrvd : 30; /**< RSRVD field of outbound message descriptor
1648 associated with the OMSG_ERR interrupt */
1649 uint64_t lns : 1; /**< LNS field of outbound message descriptor
1650 associated with the OMSG_ERR interrupt */
1651 uint64_t intr : 1; /**< INT field of outbound message descriptor
1652 associated with the OMSG_ERR interrupt */
1656 uint64_t rsrvd : 30;
1657 uint64_t letter : 2;
1667 struct cvmx_sriox_int_info2_s cn63xx;
1668 struct cvmx_sriox_int_info2_s cn63xxp1;
1669 struct cvmx_sriox_int_info2_s cn66xx;
1671 typedef union cvmx_sriox_int_info2 cvmx_sriox_int_info2_t;
1674 * cvmx_srio#_int_info3
1676 * SRIO_INT_INFO3 = SRIO Interrupt Information
1678 * The SRIO Interrupt Information
1681 * This register contains the retry response associated with the RTRY_ERR interrupt. This register
1682 * is only updated when the RTRY_ERR is initially detected. Once the interrupt is cleared then
1683 * additional information can be captured.
1685 * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n
1687 union cvmx_sriox_int_info3 {
1689 struct cvmx_sriox_int_info3_s {
1690 #ifdef __BIG_ENDIAN_BITFIELD
1691 uint64_t prio : 2; /**< Priority of received retry response message */
1692 uint64_t tt : 2; /**< TT of received retry response message */
1693 uint64_t type : 4; /**< Type of received retry response message
1695 uint64_t other : 48; /**< Other fields of received retry response message
1696 If TT==0 (8-bit ID's)
1697 OTHER<47:40> => destination ID
1698 OTHER<39:32> => source ID
1699 OTHER<31:28> => transaction (should be 1 - msg)
1700 OTHER<27:24> => status (should be 3 - retry)
1701 OTHER<23:22> => letter
1702 OTHER<21:20> => mbox
1703 OTHER<19:16> => msgseg
1704 OTHER<15:0> => unused
1705 If TT==1 (16-bit ID's)
1706 OTHER<47:32> => destination ID
1707 OTHER<31:16> => source ID
1708 OTHER<15:12> => transaction (should be 1 - msg)
1709 OTHER<11:8> => status (should be 3 - retry)
1710 OTHER<7:6> => letter
1712 OTHER<3:0> => msgseg */
1713 uint64_t reserved_0_7 : 8;
1715 uint64_t reserved_0_7 : 8;
1716 uint64_t other : 48;
1722 struct cvmx_sriox_int_info3_s cn63xx;
1723 struct cvmx_sriox_int_info3_s cn63xxp1;
1724 struct cvmx_sriox_int_info3_s cn66xx;
1726 typedef union cvmx_sriox_int_info3 cvmx_sriox_int_info3_t;
1729 * cvmx_srio#_int_reg
1731 * SRIO_INT_REG = SRIO Interrupt Register
1733 * Displays and clears which enabled interrupts have occured
1736 * This register provides interrupt status. Like most SRIO CSRs, this register can only
1737 * be read/written when the corresponding SRIO is both present and not in reset. (SRIO*_INT2_REG
1738 * can be accessed when SRIO is in reset.) Any set bits written to this register clear the
1739 * corresponding interrupt. The RXBELL interrupt is cleared by reading all the entries in the
1740 * incoming Doorbell FIFO. The LOG_ERB interrupt must be cleared before writing zeroes
1741 * to clear the bits in the SRIOMAINT*_ERB_LT_ERR_DET register. Otherwise a new interrupt may be
1742 * lost. The PHY_ERB interrupt must be cleared before writing a zero to
1743 * SRIOMAINT*_ERB_ATTR_CAPT[VALID]. Otherwise, a new interrupt may be lost. OMSG_ERR is set when an
1744 * invalid outbound message descriptor is received. The descriptor is deemed to be invalid if the
1745 * SSIZE field is set to a reserved value, the SSIZE field combined with the packet length would
1746 * result in more than 16 message segments, or the packet only contains a descriptor (no data).
1748 * Clk_Rst: SRIO(0,2..3)_INT_REG hclk hrst_n
1750 union cvmx_sriox_int_reg {
1752 struct cvmx_sriox_int_reg_s {
1753 #ifdef __BIG_ENDIAN_BITFIELD
1754 uint64_t reserved_32_63 : 32;
1755 uint64_t int2_sum : 1; /**< Interrupt Set and Enabled in SRIO(0,2..3)_INT2_REG */
1756 uint64_t reserved_27_30 : 4;
1757 uint64_t zero_pkt : 1; /**< Received Incoming SRIO Zero byte packet */
1758 uint64_t ttl_tout : 1; /**< Outgoing Packet Time to Live Timeout
1759 See SRIOMAINT(0,2..3)_DROP_PACKET */
1760 uint64_t fail : 1; /**< ERB Error Rate reached Fail Count
1761 See SRIOMAINT(0,2..3)_ERB_ERR_RATE */
1762 uint64_t degrad : 1; /**< ERB Error Rate reached Degrade Count
1763 See SRIOMAINT(0,2..3)_ERB_ERR_RATE */
1764 uint64_t mac_buf : 1; /**< SRIO MAC Buffer CRC Error
1765 See SRIO(0,2..3)_MAC_BUFFERS */
1766 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */
1767 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded
1768 See SRIO(0,2..3)_INT_INFO3
1769 When one or more of the segments in an outgoing
1770 message have a RTRY_ERR, SRIO will not set
1771 OMSG* after the message "transfer". */
1772 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */
1773 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error
1774 See SRIO(0,2..3)_INT_INFO2 */
1775 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete
1776 See SRIO(0,2..3)_OMSG_DONE_COUNTS1 */
1777 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete
1778 See SRIO(0,2..3)_OMSG_DONE_COUNTS0 */
1779 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */
1780 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */
1781 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB
1782 See SRIOMAINT*_ERB_ATTR_CAPT */
1783 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB
1784 See SRIOMAINT(0,2..3)_ERB_LT_ERR_DET */
1785 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */
1786 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */
1787 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */
1788 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */
1789 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received.
1790 See SRIO(0,2..3)_WR_DONE_COUNTS */
1791 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received.
1792 See SRIO(0,2..3)_INT_INFO[1:0] */
1793 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */
1794 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */
1795 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete.
1796 See SRIO(0,2..3)_MAINT_OP and SRIO(0,2..3)_MAINT_RD_DATA */
1797 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received.
1798 Read SRIO(0,2..3)_RX_BELL to empty FIFO */
1799 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error.
1800 See SRIO(0,2..3)_TX_BELL_INFO */
1801 uint64_t txbell : 1; /**< Outgoing Doorbell Complete.
1802 TXBELL will not be asserted if a Timeout, Retry or
1805 uint64_t txbell : 1;
1806 uint64_t bell_err : 1;
1807 uint64_t rxbell : 1;
1808 uint64_t maint_op : 1;
1809 uint64_t bar_err : 1;
1810 uint64_t deny_wr : 1;
1811 uint64_t sli_err : 1;
1812 uint64_t wr_done : 1;
1813 uint64_t mce_tx : 1;
1814 uint64_t mce_rx : 1;
1815 uint64_t soft_tx : 1;
1816 uint64_t soft_rx : 1;
1817 uint64_t log_erb : 1;
1818 uint64_t phy_erb : 1;
1819 uint64_t link_dwn : 1;
1820 uint64_t link_up : 1;
1823 uint64_t omsg_err : 1;
1824 uint64_t pko_err : 1;
1825 uint64_t rtry_err : 1;
1826 uint64_t f_error : 1;
1827 uint64_t mac_buf : 1;
1828 uint64_t degrad : 1;
1830 uint64_t ttl_tout : 1;
1831 uint64_t zero_pkt : 1;
1832 uint64_t reserved_27_30 : 4;
1833 uint64_t int2_sum : 1;
1834 uint64_t reserved_32_63 : 32;
1837 struct cvmx_sriox_int_reg_s cn63xx;
1838 struct cvmx_sriox_int_reg_cn63xxp1 {
1839 #ifdef __BIG_ENDIAN_BITFIELD
1840 uint64_t reserved_22_63 : 42;
1841 uint64_t f_error : 1; /**< SRIO Fatal Port Error (MAC reset required) */
1842 uint64_t rtry_err : 1; /**< Outbound Message Retry Threshold Exceeded
1843 See SRIO(0..1)_INT_INFO3
1844 When one or more of the segments in an outgoing
1845 message have a RTRY_ERR, SRIO will not set
1846 OMSG* after the message "transfer". */
1847 uint64_t pko_err : 1; /**< Outbound Message Received PKO Error */
1848 uint64_t omsg_err : 1; /**< Outbound Message Invalid Descriptor Error
1849 See SRIO(0..1)_INT_INFO2 */
1850 uint64_t omsg1 : 1; /**< Controller 1 Outbound Message Complete */
1851 uint64_t omsg0 : 1; /**< Controller 0 Outbound Message Complete */
1852 uint64_t link_up : 1; /**< Serial Link going from Inactive to Active */
1853 uint64_t link_dwn : 1; /**< Serial Link going from Active to Inactive */
1854 uint64_t phy_erb : 1; /**< Physical Layer Error detected in ERB
1855 See SRIOMAINT*_ERB_ATTR_CAPT */
1856 uint64_t log_erb : 1; /**< Logical/Transport Layer Error detected in ERB
1857 See SRIOMAINT(0..1)_ERB_LT_ERR_DET */
1858 uint64_t soft_rx : 1; /**< Incoming Packet received by Soft Packet FIFO */
1859 uint64_t soft_tx : 1; /**< Outgoing Packet sent by Soft Packet FIFO */
1860 uint64_t mce_rx : 1; /**< Incoming Multicast Event Symbol */
1861 uint64_t mce_tx : 1; /**< Outgoing Multicast Event Transmit Complete */
1862 uint64_t wr_done : 1; /**< Outgoing Last Nwrite_R DONE Response Received. */
1863 uint64_t sli_err : 1; /**< Unsupported S2M Transaction Received.
1864 See SRIO(0..1)_INT_INFO[1:0] */
1865 uint64_t deny_wr : 1; /**< Incoming Maint_Wr Access to Denied Bar Registers. */
1866 uint64_t bar_err : 1; /**< Incoming Access Crossing/Missing BAR Address */
1867 uint64_t maint_op : 1; /**< Internal Maintenance Operation Complete.
1868 See SRIO(0..1)_MAINT_OP and SRIO(0..1)_MAINT_RD_DATA */
1869 uint64_t rxbell : 1; /**< One or more Incoming Doorbells Received.
1870 Read SRIO(0..1)_RX_BELL to empty FIFO */
1871 uint64_t bell_err : 1; /**< Outgoing Doorbell Timeout, Retry or Error.
1872 See SRIO(0..1)_TX_BELL_INFO */
1873 uint64_t txbell : 1; /**< Outgoing Doorbell Complete.
1874 TXBELL will not be asserted if a Timeout, Retry or
1877 uint64_t txbell : 1;
1878 uint64_t bell_err : 1;
1879 uint64_t rxbell : 1;
1880 uint64_t maint_op : 1;
1881 uint64_t bar_err : 1;
1882 uint64_t deny_wr : 1;
1883 uint64_t sli_err : 1;
1884 uint64_t wr_done : 1;
1885 uint64_t mce_tx : 1;
1886 uint64_t mce_rx : 1;
1887 uint64_t soft_tx : 1;
1888 uint64_t soft_rx : 1;
1889 uint64_t log_erb : 1;
1890 uint64_t phy_erb : 1;
1891 uint64_t link_dwn : 1;
1892 uint64_t link_up : 1;
1895 uint64_t omsg_err : 1;
1896 uint64_t pko_err : 1;
1897 uint64_t rtry_err : 1;
1898 uint64_t f_error : 1;
1899 uint64_t reserved_22_63 : 42;
1902 struct cvmx_sriox_int_reg_s cn66xx;
1904 typedef union cvmx_sriox_int_reg cvmx_sriox_int_reg_t;
1907 * cvmx_srio#_ip_feature
1909 * SRIO_IP_FEATURE = SRIO IP Feature Select
1911 * Debug Register used to enable IP Core Features
1914 * This register is used to override powerup values used by the SRIOMAINT Registers and QLM
1915 * configuration. The register is only reset during COLD boot. It should only be modified only
1916 * while SRIO(0,2..3)_STATUS_REG.ACCESS is zero.
1918 * Clk_Rst: SRIO(0,2..3)_IP_FEATURE sclk srst_cold_n
1920 union cvmx_sriox_ip_feature {
1922 struct cvmx_sriox_ip_feature_s {
1923 #ifdef __BIG_ENDIAN_BITFIELD
1924 uint64_t ops : 32; /**< Reset Value for the OPs fields in both the
1925 SRIOMAINT(0,2..3)_SRC_OPS and SRIOMAINT(0,2..3)_DST_OPS
1927 uint64_t reserved_15_31 : 17;
1928 uint64_t no_vmin : 1; /**< Lane Sync Valid Minimum Count Disable. (Pass 3)
1929 0 = Wait for 2^12 valid codewords and at least
1930 127 comma characters before starting
1932 1 = Wait only for 127 comma characters before
1933 starting alignment. (SRIO V1.3 Compatable) */
1934 uint64_t a66 : 1; /**< 66-bit Address Support. Value for bit 2 of the
1935 EX_ADDR field in the SRIOMAINT(0,2..3)_PE_FEAT register. */
1936 uint64_t a50 : 1; /**< 50-bit Address Support. Value for bit 1 of the
1937 EX_ADDR field in the SRIOMAINT(0,2..3)_PE_FEAT register. */
1938 uint64_t reserved_11_11 : 1;
1939 uint64_t tx_flow : 1; /**< Reset Value for the TX_FLOW field in the
1940 SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG register. */
1941 uint64_t pt_width : 2; /**< Value for the PT_WIDTH field in the
1942 SRIOMAINT(0,2..3)_PORT_0_CTL register. */
1943 uint64_t tx_pol : 4; /**< TX Serdes Polarity Lanes 3-0
1944 0 = Normal Operation
1945 1 = Invert, Swap +/- Tx SERDES Pins */
1946 uint64_t rx_pol : 4; /**< RX Serdes Polarity Lanes 3-0
1947 0 = Normal Operation
1948 1 = Invert, Swap +/- Rx SERDES Pins */
1950 uint64_t rx_pol : 4;
1951 uint64_t tx_pol : 4;
1952 uint64_t pt_width : 2;
1953 uint64_t tx_flow : 1;
1954 uint64_t reserved_11_11 : 1;
1957 uint64_t no_vmin : 1;
1958 uint64_t reserved_15_31 : 17;
1962 struct cvmx_sriox_ip_feature_cn63xx {
1963 #ifdef __BIG_ENDIAN_BITFIELD
1964 uint64_t ops : 32; /**< Reset Value for the OPs fields in both the
1965 SRIOMAINT(0..1)_SRC_OPS and SRIOMAINT(0..1)_DST_OPS
1967 uint64_t reserved_14_31 : 18;
1968 uint64_t a66 : 1; /**< 66-bit Address Support. Value for bit 2 of the
1969 EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */
1970 uint64_t a50 : 1; /**< 50-bit Address Support. Value for bit 1 of the
1971 EX_ADDR field in the SRIOMAINT(0..1)_PE_FEAT register. */
1972 uint64_t reserved_11_11 : 1;
1973 uint64_t tx_flow : 1; /**< Reset Value for the TX_FLOW field in the
1974 SRIOMAINT(0..1)_IR_BUFFER_CONFIG register.
1975 Pass 2 will Reset to 1 when RTL ready.
1976 (TX flow control not supported in pass 1) */
1977 uint64_t pt_width : 2; /**< Value for the PT_WIDTH field in the
1978 SRIOMAINT(0..1)_PORT_0_CTL register.
1979 Reset to 0x2 rather than 0x3 in pass 1 (2 lane
1980 interface supported in pass 1). */
1981 uint64_t tx_pol : 4; /**< TX Serdes Polarity Lanes 3-0
1982 0 = Normal Operation
1983 1 = Invert, Swap +/- Tx SERDES Pins */
1984 uint64_t rx_pol : 4; /**< RX Serdes Polarity Lanes 3-0
1985 0 = Normal Operation
1986 1 = Invert, Swap +/- Rx SERDES Pins */
1988 uint64_t rx_pol : 4;
1989 uint64_t tx_pol : 4;
1990 uint64_t pt_width : 2;
1991 uint64_t tx_flow : 1;
1992 uint64_t reserved_11_11 : 1;
1995 uint64_t reserved_14_31 : 18;
1999 struct cvmx_sriox_ip_feature_cn63xx cn63xxp1;
2000 struct cvmx_sriox_ip_feature_s cn66xx;
2002 typedef union cvmx_sriox_ip_feature cvmx_sriox_ip_feature_t;
2005 * cvmx_srio#_mac_buffers
2007 * SRIO_MAC_BUFFERS = SRIO MAC Buffer Control
2009 * Reports errors and controls buffer usage on the main MAC buffers
2012 * Register displays errors status for each of the eight RX and TX buffers and controls use of the
2013 * buffer in future operations. It also displays the number of RX and TX buffers currently used by
2016 * Clk_Rst: SRIO(0,2..3)_MAC_BUFFERS hclk hrst_n
2018 union cvmx_sriox_mac_buffers {
2020 struct cvmx_sriox_mac_buffers_s {
2021 #ifdef __BIG_ENDIAN_BITFIELD
2022 uint64_t reserved_56_63 : 8;
2023 uint64_t tx_enb : 8; /**< TX Buffer Enable. Each bit enables a specific TX
2024 Buffer. At least 2 of these bits must be set for
2025 proper operation. These bits must be cleared to
2026 and then set again to reuese the buffer after an
2028 uint64_t reserved_44_47 : 4;
2029 uint64_t tx_inuse : 4; /**< Number of TX buffers containing packets waiting
2030 to be transmitted or to be acknowledged. */
2031 uint64_t tx_stat : 8; /**< Errors detected in main SRIO Transmit Buffers.
2032 CRC error detected in buffer sets bit of buffer \#
2033 until the corresponding TX_ENB is disabled. Each
2034 bit set causes the SRIO(0,2..3)_INT_REG.MAC_BUF
2036 uint64_t reserved_24_31 : 8;
2037 uint64_t rx_enb : 8; /**< RX Buffer Enable. Each bit enables a specific RX
2038 Buffer. At least 2 of these bits must be set for
2039 proper operation. These bits must be cleared to
2040 and then set again to reuese the buffer after an
2042 uint64_t reserved_12_15 : 4;
2043 uint64_t rx_inuse : 4; /**< Number of RX buffers containing valid packets
2044 waiting to be processed by the logical layer. */
2045 uint64_t rx_stat : 8; /**< Errors detected in main SRIO Receive Buffers. CRC
2046 error detected in buffer sets bit of buffer \#
2047 until the corresponding RX_ENB is disabled. Each
2048 bit set causes the SRIO(0,2..3)_INT_REG.MAC_BUF
2051 uint64_t rx_stat : 8;
2052 uint64_t rx_inuse : 4;
2053 uint64_t reserved_12_15 : 4;
2054 uint64_t rx_enb : 8;
2055 uint64_t reserved_24_31 : 8;
2056 uint64_t tx_stat : 8;
2057 uint64_t tx_inuse : 4;
2058 uint64_t reserved_44_47 : 4;
2059 uint64_t tx_enb : 8;
2060 uint64_t reserved_56_63 : 8;
2063 struct cvmx_sriox_mac_buffers_s cn63xx;
2064 struct cvmx_sriox_mac_buffers_s cn66xx;
2066 typedef union cvmx_sriox_mac_buffers cvmx_sriox_mac_buffers_t;
2069 * cvmx_srio#_maint_op
2071 * SRIO_MAINT_OP = SRIO Maintenance Operation
2073 * Allows access to maintenance registers.
2076 * This register allows write access to the local SRIOMAINT registers. A write to this register
2077 * posts a read or write operation selected by the OP bit to the local SRIOMAINT register selected by
2078 * ADDR. This write also sets the PENDING bit. The PENDING bit is cleared by hardware when the
2079 * operation is complete. The MAINT_OP Interrupt is also set as the PENDING bit is cleared. While
2080 * this bit is set, additional writes to this register stall the RSL. The FAIL bit is set with the
2081 * clearing of the PENDING bit when an illegal address is selected. WR_DATA is used only during write
2082 * operations. Only 32-bit Maintenance Operations are supported.
2084 * Clk_Rst: SRIO(0,2..3)_MAINT_OP hclk hrst_n
2086 union cvmx_sriox_maint_op {
2088 struct cvmx_sriox_maint_op_s {
2089 #ifdef __BIG_ENDIAN_BITFIELD
2090 uint64_t wr_data : 32; /**< Write Data[31:0]. */
2091 uint64_t reserved_27_31 : 5;
2092 uint64_t fail : 1; /**< Maintenance Operation Address Error */
2093 uint64_t pending : 1; /**< Maintenance Operation Pending */
2094 uint64_t op : 1; /**< Operation. 0=Read, 1=Write */
2095 uint64_t addr : 24; /**< Address. Addr[1:0] are ignored. */
2099 uint64_t pending : 1;
2101 uint64_t reserved_27_31 : 5;
2102 uint64_t wr_data : 32;
2105 struct cvmx_sriox_maint_op_s cn63xx;
2106 struct cvmx_sriox_maint_op_s cn63xxp1;
2107 struct cvmx_sriox_maint_op_s cn66xx;
2109 typedef union cvmx_sriox_maint_op cvmx_sriox_maint_op_t;
2112 * cvmx_srio#_maint_rd_data
2114 * SRIO_MAINT_RD_DATA = SRIO Maintenance Read Data
2116 * Allows read access of maintenance registers.
2119 * This register allows read access of the local SRIOMAINT registers. A write to the SRIO(0,2..3)_MAINT_OP
2120 * register with the OP bit set to zero initiates a read request and clears the VALID bit. The
2121 * resulting read is returned here and the VALID bit is set. Access to the register will not stall
2122 * the RSL but the VALID bit should be read.
2124 * Clk_Rst: SRIO(0,2..3)_MAINT_RD_DATA hclk hrst_n
2126 union cvmx_sriox_maint_rd_data {
2128 struct cvmx_sriox_maint_rd_data_s {
2129 #ifdef __BIG_ENDIAN_BITFIELD
2130 uint64_t reserved_33_63 : 31;
2131 uint64_t valid : 1; /**< Read Data Valid. */
2132 uint64_t rd_data : 32; /**< Read Data[31:0]. */
2134 uint64_t rd_data : 32;
2136 uint64_t reserved_33_63 : 31;
2139 struct cvmx_sriox_maint_rd_data_s cn63xx;
2140 struct cvmx_sriox_maint_rd_data_s cn63xxp1;
2141 struct cvmx_sriox_maint_rd_data_s cn66xx;
2143 typedef union cvmx_sriox_maint_rd_data cvmx_sriox_maint_rd_data_t;
2146 * cvmx_srio#_mce_tx_ctl
2148 * SRIO_MCE_TX_CTL = SRIO Multicast Event Transmit Control
2150 * Multicast Event TX Control
2153 * Writes to this register cause the SRIO device to generate a Multicast Event. Setting the MCE bit
2154 * requests the logic to generate the Multicast Event Symbol. Reading the MCS bit shows the status
2155 * of the transmit event. The hardware will clear the bit when the event has been transmitted and
2156 * set the MCS_TX Interrupt.
2158 * Clk_Rst: SRIO(0,2..3)_MCE_TX_CTL hclk hrst_n
2160 union cvmx_sriox_mce_tx_ctl {
2162 struct cvmx_sriox_mce_tx_ctl_s {
2163 #ifdef __BIG_ENDIAN_BITFIELD
2164 uint64_t reserved_1_63 : 63;
2165 uint64_t mce : 1; /**< Multicast Event Transmit. */
2168 uint64_t reserved_1_63 : 63;
2171 struct cvmx_sriox_mce_tx_ctl_s cn63xx;
2172 struct cvmx_sriox_mce_tx_ctl_s cn63xxp1;
2173 struct cvmx_sriox_mce_tx_ctl_s cn66xx;
2175 typedef union cvmx_sriox_mce_tx_ctl cvmx_sriox_mce_tx_ctl_t;
2178 * cvmx_srio#_mem_op_ctrl
2180 * SRIO_MEM_OP_CTRL = SRIO Memory Operation Control
2182 * The SRIO Memory Operation Control
2185 * This register is used to control memory operations. Bits are provided to override the priority of
2186 * the outgoing responses to memory operations. The memory operations with responses include NREAD,
2187 * NWRITE_R, ATOMIC_INC, ATOMIC_DEC, ATOMIC_SET and ATOMIC_CLR.
2189 * Clk_Rst: SRIO(0,2..3)_MEM_OP_CTRL hclk hrst_n
2191 union cvmx_sriox_mem_op_ctrl {
2193 struct cvmx_sriox_mem_op_ctrl_s {
2194 #ifdef __BIG_ENDIAN_BITFIELD
2195 uint64_t reserved_10_63 : 54;
2196 uint64_t rr_ro : 1; /**< Read Response Relaxed Ordering. Controls ordering
2197 rules for incoming memory operations
2199 1 = Relaxed Ordering */
2200 uint64_t w_ro : 1; /**< Write Relaxed Ordering. Controls ordering rules
2201 for incoming memory operations
2203 1 = Relaxed Ordering */
2204 uint64_t reserved_6_7 : 2;
2205 uint64_t rp1_sid : 1; /**< Sets response priority for incomimg memory ops
2206 of priority 1 on the secondary ID (0=2, 1=3) */
2207 uint64_t rp0_sid : 2; /**< Sets response priority for incomimg memory ops
2208 of priority 0 on the secondary ID (0,1=1 2=2, 3=3) */
2209 uint64_t rp1_pid : 1; /**< Sets response priority for incomimg memory ops
2210 of priority 1 on the primary ID (0=2, 1=3) */
2211 uint64_t rp0_pid : 2; /**< Sets response priority for incomimg memory ops
2212 of priority 0 on the primary ID (0,1=1 2=2, 3=3) */
2214 uint64_t rp0_pid : 2;
2215 uint64_t rp1_pid : 1;
2216 uint64_t rp0_sid : 2;
2217 uint64_t rp1_sid : 1;
2218 uint64_t reserved_6_7 : 2;
2221 uint64_t reserved_10_63 : 54;
2224 struct cvmx_sriox_mem_op_ctrl_s cn63xx;
2225 struct cvmx_sriox_mem_op_ctrl_s cn63xxp1;
2226 struct cvmx_sriox_mem_op_ctrl_s cn66xx;
2228 typedef union cvmx_sriox_mem_op_ctrl cvmx_sriox_mem_op_ctrl_t;
2231 * cvmx_srio#_omsg_ctrl#
2233 * SRIO_OMSG_CTRLX = SRIO Outbound Message Control
2235 * The SRIO Controller X Outbound Message Control Register
2238 * 1) If IDM_TT, IDM_SIS, and IDM_DID are all clear, then the "ID match" will always be false.
2239 * 2) LTTR_SP and LTTR_MP must be non-zero at all times, otherwise the message output queue can
2241 * 3) TESTMODE has no function on controller 1
2242 * 4) When IDM_TT=0, it is possible for an ID match to match an 8-bit DID with a 16-bit DID - SRIO
2243 * zero-extends all 8-bit DID's, and the DID comparisons are always 16-bits.
2245 * Clk_Rst: SRIO(0,2..3)_OMSG_CTRL[0:1] hclk hrst_n
2247 union cvmx_sriox_omsg_ctrlx {
2249 struct cvmx_sriox_omsg_ctrlx_s {
2250 #ifdef __BIG_ENDIAN_BITFIELD
2251 uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */
2252 uint64_t reserved_37_62 : 26;
2253 uint64_t silo_max : 5; /**< Sets max number outgoing segments for controller X
2254 Valid range is 0x01 .. 0x10 Note that lower
2255 values will reduce bandwidth. */
2256 uint64_t rtry_thr : 16; /**< Controller X Retry threshold */
2257 uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */
2258 uint64_t reserved_11_14 : 4;
2259 uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */
2260 uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */
2261 uint64_t idm_did : 1; /**< Controller X ID match includes DID */
2262 uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic
2263 letter select mode (LNS) */
2264 uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic
2265 letter select mode (LNS) */
2267 uint64_t lttr_mp : 4;
2268 uint64_t lttr_sp : 4;
2269 uint64_t idm_did : 1;
2270 uint64_t idm_sis : 1;
2271 uint64_t idm_tt : 1;
2272 uint64_t reserved_11_14 : 4;
2273 uint64_t rtry_en : 1;
2274 uint64_t rtry_thr : 16;
2275 uint64_t silo_max : 5;
2276 uint64_t reserved_37_62 : 26;
2277 uint64_t testmode : 1;
2280 struct cvmx_sriox_omsg_ctrlx_s cn63xx;
2281 struct cvmx_sriox_omsg_ctrlx_cn63xxp1 {
2282 #ifdef __BIG_ENDIAN_BITFIELD
2283 uint64_t testmode : 1; /**< Controller X test mode (keep as RSVD in HRM) */
2284 uint64_t reserved_32_62 : 31;
2285 uint64_t rtry_thr : 16; /**< Controller X Retry threshold */
2286 uint64_t rtry_en : 1; /**< Controller X Retry threshold enable */
2287 uint64_t reserved_11_14 : 4;
2288 uint64_t idm_tt : 1; /**< Controller X ID match includes TT ID */
2289 uint64_t idm_sis : 1; /**< Controller X ID match includes SIS */
2290 uint64_t idm_did : 1; /**< Controller X ID match includes DID */
2291 uint64_t lttr_sp : 4; /**< Controller X SP allowable letters in dynamic
2292 letter select mode (LNS) */
2293 uint64_t lttr_mp : 4; /**< Controller X MP allowable letters in dynamic
2294 letter select mode (LNS) */
2296 uint64_t lttr_mp : 4;
2297 uint64_t lttr_sp : 4;
2298 uint64_t idm_did : 1;
2299 uint64_t idm_sis : 1;
2300 uint64_t idm_tt : 1;
2301 uint64_t reserved_11_14 : 4;
2302 uint64_t rtry_en : 1;
2303 uint64_t rtry_thr : 16;
2304 uint64_t reserved_32_62 : 31;
2305 uint64_t testmode : 1;
2308 struct cvmx_sriox_omsg_ctrlx_s cn66xx;
2310 typedef union cvmx_sriox_omsg_ctrlx cvmx_sriox_omsg_ctrlx_t;
2313 * cvmx_srio#_omsg_done_counts#
2315 * SRIO_OMSG_DONE_COUNTSX = SRIO Outbound Message Complete Counts
2317 * The SRIO Controller X Outbound Message Complete Counts Register
2320 * This register shows the number of successful and unsuccessful Outgoing Messages issued through
2321 * this controller. The only messages considered are the ones with the INT field set in the PKO
2322 * message header. This register is typically not written while Outbound SRIO Memory traffic is
2323 * enabled. The sum of the GOOD and BAD counts should equal the number of messages sent unless
2324 * the MAC has been reset.
2326 * Clk_Rst: SRIO(0,2..3)_OMSG_DONE_COUNTS[0:1] hclk hrst_n
2328 union cvmx_sriox_omsg_done_countsx {
2330 struct cvmx_sriox_omsg_done_countsx_s {
2331 #ifdef __BIG_ENDIAN_BITFIELD
2332 uint64_t reserved_32_63 : 32;
2333 uint64_t bad : 16; /**< Number of Outbound Messages requesting an INT that
2334 did not increment GOOD. (One or more segment of the
2335 message either timed out, reached the retry limit,
2336 or received an ERROR response.) */
2337 uint64_t good : 16; /**< Number of Outbound Messages requesting an INT that
2338 received a DONE response for every segment. */
2342 uint64_t reserved_32_63 : 32;
2345 struct cvmx_sriox_omsg_done_countsx_s cn63xx;
2346 struct cvmx_sriox_omsg_done_countsx_s cn66xx;
2348 typedef union cvmx_sriox_omsg_done_countsx cvmx_sriox_omsg_done_countsx_t;
2351 * cvmx_srio#_omsg_fmp_mr#
2353 * SRIO_OMSG_FMP_MRX = SRIO Outbound Message FIRSTMP Message Restriction
2355 * The SRIO Controller X Outbound Message FIRSTMP Message Restriction Register
2358 * This CSR controls when FMP candidate message segments (from the two different controllers) can enter
2359 * the message segment silo to be sent out. A segment remains in the silo until after is has
2360 * been transmitted and either acknowledged or errored out.
2362 * Candidates and silo entries are one of 4 types:
2363 * SP - a single-segment message
2364 * FMP - the first segment of a multi-segment message
2365 * NMP - the other segments in a multi-segment message
2366 * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing
2367 * a multi-segment message into the silo and can match against segments generated by
2368 * the other controller
2370 * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo.
2371 * By default (i.e. zeroes in this CSR), the FMP candidate matches against all entries in the
2372 * silo. When fields in this CSR are set, FMP candidate segments will match fewer silo entries and
2373 * can enter the silo more freely, probably providing better performance.
2375 * Clk_Rst: SRIO(0,2..3)_OMSG_FMP_MR[0:1] hclk hrst_n
2377 union cvmx_sriox_omsg_fmp_mrx {
2379 struct cvmx_sriox_omsg_fmp_mrx_s {
2380 #ifdef __BIG_ENDIAN_BITFIELD
2381 uint64_t reserved_15_63 : 49;
2382 uint64_t ctlr_sp : 1; /**< Controller X FIRSTMP enable controller SP
2383 When set, the FMP candidate message segment can
2384 only match siloed SP segments that were created
2385 by the same controller. When clear, this FMP-SP
2386 match can also occur when the segments were
2387 created by the other controller.
2388 Not used by the hardware when ALL_SP is set. */
2389 uint64_t ctlr_fmp : 1; /**< Controller X FIRSTMP enable controller FIRSTMP
2390 When set, the FMP candidate message segment can
2391 only match siloed FMP segments that were created
2392 by the same controller. When clear, this FMP-FMP
2393 match can also occur when the segments were
2394 created by the other controller.
2395 Not used by the hardware when ALL_FMP is set. */
2396 uint64_t ctlr_nmp : 1; /**< Controller X FIRSTMP enable controller NFIRSTMP
2397 When set, the FMP candidate message segment can
2398 only match siloed NMP segments that were created
2399 by the same controller. When clear, this FMP-NMP
2400 match can also occur when the segments were
2401 created by the other controller.
2402 Not used by the hardware when ALL_NMP is set. */
2403 uint64_t id_sp : 1; /**< Controller X FIRSTMP enable ID SP
2404 When set, the FMP candidate message segment can
2405 only match siloed SP segments that "ID match" the
2406 candidate. When clear, this FMP-SP match can occur
2408 Not used by the hardware when ALL_SP is set. */
2409 uint64_t id_fmp : 1; /**< Controller X FIRSTMP enable ID FIRSTMP
2410 When set, the FMP candidate message segment can
2411 only match siloed FMP segments that "ID match" the
2412 candidate. When clear, this FMP-FMP match can occur
2414 Not used by the hardware when ALL_FMP is set. */
2415 uint64_t id_nmp : 1; /**< Controller X FIRSTMP enable ID NFIRSTMP
2416 When set, the FMP candidate message segment can
2417 only match siloed NMP segments that "ID match" the
2418 candidate. When clear, this FMP-NMP match can occur
2420 Not used by the hardware when ALL_NMP is set. */
2421 uint64_t id_psd : 1; /**< Controller X FIRSTMP enable ID PSEUDO
2422 When set, the FMP candidate message segment can
2423 only match the silo pseudo (for the other
2424 controller) when it is an "ID match". When clear,
2425 this FMP-PSD match can occur with any ID values.
2426 Not used by the hardware when ALL_PSD is set. */
2427 uint64_t mbox_sp : 1; /**< Controller X FIRSTMP enable MBOX SP
2428 When set, the FMP candidate message segment can
2429 only match siloed SP segments with the same 2-bit
2430 mbox value as the candidate. When clear, this
2431 FMP-SP match can occur with any mbox values.
2432 Not used by the hardware when ALL_SP is set. */
2433 uint64_t mbox_fmp : 1; /**< Controller X FIRSTMP enable MBOX FIRSTMP
2434 When set, the FMP candidate message segment can
2435 only match siloed FMP segments with the same 2-bit
2436 mbox value as the candidate. When clear, this
2437 FMP-FMP match can occur with any mbox values.
2438 Not used by the hardware when ALL_FMP is set. */
2439 uint64_t mbox_nmp : 1; /**< Controller X FIRSTMP enable MBOX NFIRSTMP
2440 When set, the FMP candidate message segment can
2441 only match siloed NMP segments with the same 2-bit
2442 mbox value as the candidate. When clear, this
2443 FMP-NMP match can occur with any mbox values.
2444 Not used by the hardware when ALL_NMP is set. */
2445 uint64_t mbox_psd : 1; /**< Controller X FIRSTMP enable MBOX PSEUDO
2446 When set, the FMP candidate message segment can
2447 only match the silo pseudo (for the other
2448 controller) if the pseudo has the same 2-bit mbox
2449 value as the candidate. When clear, this FMP-PSD
2450 match can occur with any mbox values.
2451 Not used by the hardware when ALL_PSD is set. */
2452 uint64_t all_sp : 1; /**< Controller X FIRSTMP enable all SP
2453 When set, no FMP candidate message segments ever
2454 match siloed SP segments and ID_SP
2455 and MBOX_SP are not used. When clear, FMP-SP
2456 matches can occur. */
2457 uint64_t all_fmp : 1; /**< Controller X FIRSTMP enable all FIRSTMP
2458 When set, no FMP candidate message segments ever
2459 match siloed FMP segments and ID_FMP and MBOX_FMP
2460 are not used. When clear, FMP-FMP matches can
2462 uint64_t all_nmp : 1; /**< Controller X FIRSTMP enable all NFIRSTMP
2463 When set, no FMP candidate message segments ever
2464 match siloed NMP segments and ID_NMP and MBOX_NMP
2465 are not used. When clear, FMP-NMP matches can
2467 uint64_t all_psd : 1; /**< Controller X FIRSTMP enable all PSEUDO
2468 When set, no FMP candidate message segments ever
2469 match the silo pseudo (for the other controller)
2470 and ID_PSD and MBOX_PSD are not used. When clear,
2471 FMP-PSD matches can occur. */
2473 uint64_t all_psd : 1;
2474 uint64_t all_nmp : 1;
2475 uint64_t all_fmp : 1;
2476 uint64_t all_sp : 1;
2477 uint64_t mbox_psd : 1;
2478 uint64_t mbox_nmp : 1;
2479 uint64_t mbox_fmp : 1;
2480 uint64_t mbox_sp : 1;
2481 uint64_t id_psd : 1;
2482 uint64_t id_nmp : 1;
2483 uint64_t id_fmp : 1;
2485 uint64_t ctlr_nmp : 1;
2486 uint64_t ctlr_fmp : 1;
2487 uint64_t ctlr_sp : 1;
2488 uint64_t reserved_15_63 : 49;
2491 struct cvmx_sriox_omsg_fmp_mrx_s cn63xx;
2492 struct cvmx_sriox_omsg_fmp_mrx_s cn63xxp1;
2493 struct cvmx_sriox_omsg_fmp_mrx_s cn66xx;
2495 typedef union cvmx_sriox_omsg_fmp_mrx cvmx_sriox_omsg_fmp_mrx_t;
2498 * cvmx_srio#_omsg_nmp_mr#
2500 * SRIO_OMSG_NMP_MRX = SRIO Outbound Message NFIRSTMP Message Restriction
2502 * The SRIO Controller X Outbound Message NFIRSTMP Message Restriction Register
2505 * This CSR controls when NMP candidate message segments (from the two different controllers) can enter
2506 * the message segment silo to be sent out. A segment remains in the silo until after is has
2507 * been transmitted and either acknowledged or errored out.
2509 * Candidates and silo entries are one of 4 types:
2510 * SP - a single-segment message
2511 * FMP - the first segment of a multi-segment message
2512 * NMP - the other segments in a multi-segment message
2513 * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing
2514 * a multi-segment message into the silo and can match against segments generated by
2515 * the other controller
2517 * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo.
2518 * By default (i.e. zeroes in this CSR), the NMP candidate matches against all entries in the
2519 * silo. When fields in this CSR are set, NMP candidate segments will match fewer silo entries and
2520 * can enter the silo more freely, probably providing better performance.
2522 * Clk_Rst: SRIO(0,2..3)_OMSG_NMP_MR[0:1] hclk hrst_n
2524 union cvmx_sriox_omsg_nmp_mrx {
2526 struct cvmx_sriox_omsg_nmp_mrx_s {
2527 #ifdef __BIG_ENDIAN_BITFIELD
2528 uint64_t reserved_15_63 : 49;
2529 uint64_t ctlr_sp : 1; /**< Controller X NFIRSTMP enable controller SP
2530 When set, the NMP candidate message segment can
2531 only match siloed SP segments that were created
2532 by the same controller. When clear, this NMP-SP
2533 match can also occur when the segments were
2534 created by the other controller.
2535 Not used by the hardware when ALL_SP is set. */
2536 uint64_t ctlr_fmp : 1; /**< Controller X NFIRSTMP enable controller FIRSTMP
2537 When set, the NMP candidate message segment can
2538 only match siloed FMP segments that were created
2539 by the same controller. When clear, this NMP-FMP
2540 match can also occur when the segments were
2541 created by the other controller.
2542 Not used by the hardware when ALL_FMP is set. */
2543 uint64_t ctlr_nmp : 1; /**< Controller X NFIRSTMP enable controller NFIRSTMP
2544 When set, the NMP candidate message segment can
2545 only match siloed NMP segments that were created
2546 by the same controller. When clear, this NMP-NMP
2547 match can also occur when the segments were
2548 created by the other controller.
2549 Not used by the hardware when ALL_NMP is set. */
2550 uint64_t id_sp : 1; /**< Controller X NFIRSTMP enable ID SP
2551 When set, the NMP candidate message segment can
2552 only match siloed SP segments that "ID match" the
2553 candidate. When clear, this NMP-SP match can occur
2555 Not used by the hardware when ALL_SP is set. */
2556 uint64_t id_fmp : 1; /**< Controller X NFIRSTMP enable ID FIRSTMP
2557 When set, the NMP candidate message segment can
2558 only match siloed FMP segments that "ID match" the
2559 candidate. When clear, this NMP-FMP match can occur
2561 Not used by the hardware when ALL_FMP is set. */
2562 uint64_t id_nmp : 1; /**< Controller X NFIRSTMP enable ID NFIRSTMP
2563 When set, the NMP candidate message segment can
2564 only match siloed NMP segments that "ID match" the
2565 candidate. When clear, this NMP-NMP match can occur
2567 Not used by the hardware when ALL_NMP is set. */
2568 uint64_t reserved_8_8 : 1;
2569 uint64_t mbox_sp : 1; /**< Controller X NFIRSTMP enable MBOX SP
2570 When set, the NMP candidate message segment can
2571 only match siloed SP segments with the same 2-bit
2572 mbox value as the candidate. When clear, this
2573 NMP-SP match can occur with any mbox values.
2574 Not used by the hardware when ALL_SP is set. */
2575 uint64_t mbox_fmp : 1; /**< Controller X NFIRSTMP enable MBOX FIRSTMP
2576 When set, the NMP candidate message segment can
2577 only match siloed FMP segments with the same 2-bit
2578 mbox value as the candidate. When clear, this
2579 NMP-FMP match can occur with any mbox values.
2580 Not used by the hardware when ALL_FMP is set. */
2581 uint64_t mbox_nmp : 1; /**< Controller X NFIRSTMP enable MBOX NFIRSTMP
2582 When set, the NMP candidate message segment can
2583 only match siloed NMP segments with the same 2-bit
2584 mbox value as the candidate. When clear, this
2585 NMP-NMP match can occur with any mbox values.
2586 Not used by the hardware when ALL_NMP is set. */
2587 uint64_t reserved_4_4 : 1;
2588 uint64_t all_sp : 1; /**< Controller X NFIRSTMP enable all SP
2589 When set, no NMP candidate message segments ever
2590 match siloed SP segments and ID_SP
2591 and MBOX_SP are not used. When clear, NMP-SP
2592 matches can occur. */
2593 uint64_t all_fmp : 1; /**< Controller X NFIRSTMP enable all FIRSTMP
2594 When set, no NMP candidate message segments ever
2595 match siloed FMP segments and ID_FMP and MBOX_FMP
2596 are not used. When clear, NMP-FMP matches can
2598 uint64_t all_nmp : 1; /**< Controller X NFIRSTMP enable all NFIRSTMP
2599 When set, no NMP candidate message segments ever
2600 match siloed NMP segments and ID_NMP and MBOX_NMP
2601 are not used. When clear, NMP-NMP matches can
2603 uint64_t reserved_0_0 : 1;
2605 uint64_t reserved_0_0 : 1;
2606 uint64_t all_nmp : 1;
2607 uint64_t all_fmp : 1;
2608 uint64_t all_sp : 1;
2609 uint64_t reserved_4_4 : 1;
2610 uint64_t mbox_nmp : 1;
2611 uint64_t mbox_fmp : 1;
2612 uint64_t mbox_sp : 1;
2613 uint64_t reserved_8_8 : 1;
2614 uint64_t id_nmp : 1;
2615 uint64_t id_fmp : 1;
2617 uint64_t ctlr_nmp : 1;
2618 uint64_t ctlr_fmp : 1;
2619 uint64_t ctlr_sp : 1;
2620 uint64_t reserved_15_63 : 49;
2623 struct cvmx_sriox_omsg_nmp_mrx_s cn63xx;
2624 struct cvmx_sriox_omsg_nmp_mrx_s cn63xxp1;
2625 struct cvmx_sriox_omsg_nmp_mrx_s cn66xx;
2627 typedef union cvmx_sriox_omsg_nmp_mrx cvmx_sriox_omsg_nmp_mrx_t;
2630 * cvmx_srio#_omsg_port#
2632 * SRIO_OMSG_PORTX = SRIO Outbound Message Port
2634 * The SRIO Controller X Outbound Message Port Register
2637 * PORT maps the PKO port to SRIO interface \# / controller X as follows:
2639 * 000 == PKO port 40
2640 * 001 == PKO port 41
2641 * 010 == PKO port 42
2642 * 011 == PKO port 43
2643 * 100 == PKO port 44
2644 * 101 == PKO port 45
2645 * 110 == PKO port 46
2646 * 111 == PKO port 47
2648 * No two PORT fields among the enabled controllers (ENABLE == 1) may be set to the same value.
2649 * The register is only reset during COLD boot. The register can be accessed/modified regardless of
2650 * the value in SRIO(0,2..3)_STATUS_REG.ACCESS.
2652 * Clk_Rst: SRIO(0,2..3)_OMSG_PORT[0:1] sclk srst_n
2654 union cvmx_sriox_omsg_portx {
2656 struct cvmx_sriox_omsg_portx_s {
2657 #ifdef __BIG_ENDIAN_BITFIELD
2658 uint64_t reserved_32_63 : 32;
2659 uint64_t enable : 1; /**< Controller X enable */
2660 uint64_t reserved_3_30 : 28;
2661 uint64_t port : 3; /**< Controller X PKO port */
2664 uint64_t reserved_3_30 : 28;
2665 uint64_t enable : 1;
2666 uint64_t reserved_32_63 : 32;
2669 struct cvmx_sriox_omsg_portx_cn63xx {
2670 #ifdef __BIG_ENDIAN_BITFIELD
2671 uint64_t reserved_32_63 : 32;
2672 uint64_t enable : 1; /**< Controller X enable */
2673 uint64_t reserved_2_30 : 29;
2674 uint64_t port : 2; /**< Controller X PKO port */
2677 uint64_t reserved_2_30 : 29;
2678 uint64_t enable : 1;
2679 uint64_t reserved_32_63 : 32;
2682 struct cvmx_sriox_omsg_portx_cn63xx cn63xxp1;
2683 struct cvmx_sriox_omsg_portx_s cn66xx;
2685 typedef union cvmx_sriox_omsg_portx cvmx_sriox_omsg_portx_t;
2688 * cvmx_srio#_omsg_silo_thr
2690 * SRIO_OMSG_SILO_THR = SRIO Outgoing Message SILO Thresholds
2692 * The SRIO Outgoing Message SILO Thresholds
2695 * Limits the number of Outgoing Message Segments in flight at a time.
2697 * Clk_Rst: SRIO(0,2..3)_OMSG_SILO_THR hclk hrst_n
2699 union cvmx_sriox_omsg_silo_thr {
2701 struct cvmx_sriox_omsg_silo_thr_s {
2702 #ifdef __BIG_ENDIAN_BITFIELD
2703 uint64_t reserved_5_63 : 59;
2704 uint64_t tot_silo : 5; /**< Sets max number segments in flight for all
2705 controllers. Valid range is 0x01 .. 0x10 but
2706 lower values reduce bandwidth. */
2708 uint64_t tot_silo : 5;
2709 uint64_t reserved_5_63 : 59;
2712 struct cvmx_sriox_omsg_silo_thr_s cn63xx;
2713 struct cvmx_sriox_omsg_silo_thr_s cn66xx;
2715 typedef union cvmx_sriox_omsg_silo_thr cvmx_sriox_omsg_silo_thr_t;
2718 * cvmx_srio#_omsg_sp_mr#
2720 * SRIO_OMSG_SP_MRX = SRIO Outbound Message SP Message Restriction
2722 * The SRIO Controller X Outbound Message SP Message Restriction Register
2725 * This CSR controls when SP candidate message segments (from the two different controllers) can enter
2726 * the message segment silo to be sent out. A segment remains in the silo until after is has
2727 * been transmitted and either acknowledged or errored out.
2729 * Candidates and silo entries are one of 4 types:
2730 * SP - a single-segment message
2731 * FMP - the first segment of a multi-segment message
2732 * NMP - the other segments in a multi-segment message
2733 * PSD - the silo psuedo-entry that is valid only while a controller is in the middle of pushing
2734 * a multi-segment message into the silo and can match against segments generated by
2735 * the other controller
2737 * When a candidate "matches" against a silo entry or pseudo entry, it cannot enter the silo.
2738 * By default (i.e. zeroes in this CSR), the SP candidate matches against all entries in the
2739 * silo. When fields in this CSR are set, SP candidate segments will match fewer silo entries and
2740 * can enter the silo more freely, probably providing better performance.
2742 * Clk_Rst: SRIO(0,2..3)_OMSG_SP_MR[0:1] hclk hrst_n
2744 union cvmx_sriox_omsg_sp_mrx {
2746 struct cvmx_sriox_omsg_sp_mrx_s {
2747 #ifdef __BIG_ENDIAN_BITFIELD
2748 uint64_t reserved_16_63 : 48;
2749 uint64_t xmbox_sp : 1; /**< Controller X SP enable XMBOX SP
2750 When set, the SP candidate message can only
2751 match siloed SP segments with the same 4-bit xmbox
2752 value as the candidate. When clear, this SP-SP
2753 match can occur with any xmbox values.
2754 When XMBOX_SP is set, MBOX_SP will commonly be set.
2755 Not used by the hardware when ALL_SP is set. */
2756 uint64_t ctlr_sp : 1; /**< Controller X SP enable controller SP
2757 When set, the SP candidate message can
2758 only match siloed SP segments that were created
2759 by the same controller. When clear, this SP-SP
2760 match can also occur when the segments were
2761 created by the other controller.
2762 Not used by the hardware when ALL_SP is set. */
2763 uint64_t ctlr_fmp : 1; /**< Controller X SP enable controller FIRSTMP
2764 When set, the SP candidate message can
2765 only match siloed FMP segments that were created
2766 by the same controller. When clear, this SP-FMP
2767 match can also occur when the segments were
2768 created by the other controller.
2769 Not used by the hardware when ALL_FMP is set. */
2770 uint64_t ctlr_nmp : 1; /**< Controller X SP enable controller NFIRSTMP
2771 When set, the SP candidate message can
2772 only match siloed NMP segments that were created
2773 by the same controller. When clear, this SP-NMP
2774 match can also occur when the segments were
2775 created by the other controller.
2776 Not used by the hardware when ALL_NMP is set. */
2777 uint64_t id_sp : 1; /**< Controller X SP enable ID SP
2778 When set, the SP candidate message can
2779 only match siloed SP segments that "ID match" the
2780 candidate. When clear, this SP-SP match can occur
2782 Not used by the hardware when ALL_SP is set. */
2783 uint64_t id_fmp : 1; /**< Controller X SP enable ID FIRSTMP
2784 When set, the SP candidate message can
2785 only match siloed FMP segments that "ID match" the
2786 candidate. When clear, this SP-FMP match can occur
2788 Not used by the hardware when ALL_FMP is set. */
2789 uint64_t id_nmp : 1; /**< Controller X SP enable ID NFIRSTMP
2790 When set, the SP candidate message can
2791 only match siloed NMP segments that "ID match" the
2792 candidate. When clear, this SP-NMP match can occur
2794 Not used by the hardware when ALL_NMP is set. */
2795 uint64_t id_psd : 1; /**< Controller X SP enable ID PSEUDO
2796 When set, the SP candidate message can
2797 only match the silo pseudo (for the other
2798 controller) when it is an "ID match". When clear,
2799 this SP-PSD match can occur with any ID values.
2800 Not used by the hardware when ALL_PSD is set. */
2801 uint64_t mbox_sp : 1; /**< Controller X SP enable MBOX SP
2802 When set, the SP candidate message can only
2803 match siloed SP segments with the same 2-bit mbox
2804 value as the candidate. When clear, this SP-SP
2805 match can occur with any mbox values.
2806 Not used by the hardware when ALL_SP is set. */
2807 uint64_t mbox_fmp : 1; /**< Controller X SP enable MBOX FIRSTMP
2808 When set, the SP candidate message can only
2809 match siloed FMP segments with the same 2-bit mbox
2810 value as the candidate. When clear, this SP-FMP
2811 match can occur with any mbox values.
2812 Not used by the hardware when ALL_FMP is set. */
2813 uint64_t mbox_nmp : 1; /**< Controller X SP enable MBOX NFIRSTMP
2814 When set, the SP candidate message can only
2815 match siloed NMP segments with the same 2-bit mbox
2816 value as the candidate. When clear, this SP-NMP
2817 match can occur with any mbox values.
2818 Not used by the hardware when ALL_NMP is set. */
2819 uint64_t mbox_psd : 1; /**< Controller X SP enable MBOX PSEUDO
2820 When set, the SP candidate message can only
2821 match the silo pseudo (for the other controller)
2822 if the pseudo has the same 2-bit mbox value as the
2823 candidate. When clear, this SP-PSD match can occur
2824 with any mbox values.
2825 Not used by the hardware when ALL_PSD is set. */
2826 uint64_t all_sp : 1; /**< Controller X SP enable all SP
2827 When set, no SP candidate messages ever
2828 match siloed SP segments, and XMBOX_SP, ID_SP,
2829 and MBOX_SP are not used. When clear, SP-SP
2830 matches can occur. */
2831 uint64_t all_fmp : 1; /**< Controller X SP enable all FIRSTMP
2832 When set, no SP candidate messages ever
2833 match siloed FMP segments and ID_FMP and MBOX_FMP
2834 are not used. When clear, SP-FMP matches can
2836 uint64_t all_nmp : 1; /**< Controller X SP enable all NFIRSTMP
2837 When set, no SP candidate messages ever
2838 match siloed NMP segments and ID_NMP and MBOX_NMP
2839 are not used. When clear, SP-NMP matches can
2841 uint64_t all_psd : 1; /**< Controller X SP enable all PSEUDO
2842 When set, no SP candidate messages ever
2843 match the silo pseudo (for the other controller)
2844 and ID_PSD and MBOX_PSD are not used. When clear,
2845 SP-PSD matches can occur. */
2847 uint64_t all_psd : 1;
2848 uint64_t all_nmp : 1;
2849 uint64_t all_fmp : 1;
2850 uint64_t all_sp : 1;
2851 uint64_t mbox_psd : 1;
2852 uint64_t mbox_nmp : 1;
2853 uint64_t mbox_fmp : 1;
2854 uint64_t mbox_sp : 1;
2855 uint64_t id_psd : 1;
2856 uint64_t id_nmp : 1;
2857 uint64_t id_fmp : 1;
2859 uint64_t ctlr_nmp : 1;
2860 uint64_t ctlr_fmp : 1;
2861 uint64_t ctlr_sp : 1;
2862 uint64_t xmbox_sp : 1;
2863 uint64_t reserved_16_63 : 48;
2866 struct cvmx_sriox_omsg_sp_mrx_s cn63xx;
2867 struct cvmx_sriox_omsg_sp_mrx_s cn63xxp1;
2868 struct cvmx_sriox_omsg_sp_mrx_s cn66xx;
2870 typedef union cvmx_sriox_omsg_sp_mrx cvmx_sriox_omsg_sp_mrx_t;
2873 * cvmx_srio#_prio#_in_use
2875 * SRIO_PRIO[0:3]_IN_USE = S2M PRIORITY FIFO IN USE COUNTS
2877 * SRIO S2M Priority X FIFO Inuse counts
2880 * These registers provide status information on the number of read/write requests pending in the S2M
2881 * Priority FIFOs. The information can be used to help determine when an S2M_TYPE register can be
2882 * reallocated. For example, if an S2M_TYPE is used N times in a DMA write operation and the DMA has
2883 * completed. The register corresponding to the RD/WR_PRIOR of the S2M_TYPE can be read to determine
2884 * the START_CNT and then can be polled to see if the END_CNT equals the START_CNT or at least
2885 * START_CNT+N. These registers can be accessed regardless of the value of SRIO(0,2..3)_STATUS_REG.ACCESS
2886 * but are reset by either the MAC or Core being reset.
2888 * Clk_Rst: SRIO(0,2..3)_PRIO[0:3]_IN_USE sclk srst_n, hrst_n
2890 union cvmx_sriox_priox_in_use {
2892 struct cvmx_sriox_priox_in_use_s {
2893 #ifdef __BIG_ENDIAN_BITFIELD
2894 uint64_t reserved_32_63 : 32;
2895 uint64_t end_cnt : 16; /**< Count of Packets with S2M_TYPES completed for this
2897 uint64_t start_cnt : 16; /**< Count of Packets with S2M_TYPES started for this
2900 uint64_t start_cnt : 16;
2901 uint64_t end_cnt : 16;
2902 uint64_t reserved_32_63 : 32;
2905 struct cvmx_sriox_priox_in_use_s cn63xx;
2906 struct cvmx_sriox_priox_in_use_s cn66xx;
2908 typedef union cvmx_sriox_priox_in_use cvmx_sriox_priox_in_use_t;
2911 * cvmx_srio#_rx_bell
2913 * SRIO_RX_BELL = SRIO Receive Doorbell
2915 * The SRIO Incoming (RX) Doorbell
2918 * This register contains the SRIO Information, Device ID, Transaction Type and Priority of the
2919 * incoming Doorbell Transaction as well as the number of transactions waiting to be read. Reading
2920 * this register causes a Doorbell to be removed from the RX Bell FIFO and the COUNT to be
2921 * decremented. If the COUNT is zero then the FIFO is empty and the other fields should be
2922 * considered invalid. When the FIFO is full an ERROR is automatically issued. The RXBELL Interrupt
2923 * can be used to detect posts to this FIFO.
2925 * Clk_Rst: SRIO(0,2..3)_RX_BELL hclk hrst_n
2927 union cvmx_sriox_rx_bell {
2929 struct cvmx_sriox_rx_bell_s {
2930 #ifdef __BIG_ENDIAN_BITFIELD
2931 uint64_t reserved_48_63 : 16;
2932 uint64_t data : 16; /**< Information field from received doorbell */
2933 uint64_t src_id : 16; /**< Doorbell Source Device ID[15:0] */
2934 uint64_t count : 8; /**< RX Bell FIFO Count
2935 Note: Count must be > 0 for entry to be valid. */
2936 uint64_t reserved_5_7 : 3;
2937 uint64_t dest_id : 1; /**< Destination Device ID 0=Primary, 1=Secondary */
2938 uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */
2939 uint64_t reserved_2_2 : 1;
2940 uint64_t priority : 2; /**< Doorbell Priority */
2942 uint64_t priority : 2;
2943 uint64_t reserved_2_2 : 1;
2945 uint64_t dest_id : 1;
2946 uint64_t reserved_5_7 : 3;
2948 uint64_t src_id : 16;
2950 uint64_t reserved_48_63 : 16;
2953 struct cvmx_sriox_rx_bell_s cn63xx;
2954 struct cvmx_sriox_rx_bell_s cn63xxp1;
2955 struct cvmx_sriox_rx_bell_s cn66xx;
2957 typedef union cvmx_sriox_rx_bell cvmx_sriox_rx_bell_t;
2960 * cvmx_srio#_rx_bell_seq
2962 * SRIO_RX_BELL_SEQ = SRIO Receive Doorbell Sequence Count
2964 * The SRIO Incoming (RX) Doorbell Sequence Count
2967 * This register contains the value of the sequence counter when the doorbell was received and a
2968 * shadow copy of the Bell FIFO Count that can be read without emptying the FIFO. This register must
2969 * be read prior to SRIO(0,2..3)_RX_BELL to guarantee that the information corresponds to the correct
2972 * Clk_Rst: SRIO(0,2..3)_RX_BELL_SEQ hclk hrst_n
2974 union cvmx_sriox_rx_bell_seq {
2976 struct cvmx_sriox_rx_bell_seq_s {
2977 #ifdef __BIG_ENDIAN_BITFIELD
2978 uint64_t reserved_40_63 : 24;
2979 uint64_t count : 8; /**< RX Bell FIFO Count
2980 Note: Count must be > 0 for entry to be valid. */
2981 uint64_t seq : 32; /**< 32-bit Sequence \# associated with Doorbell Message */
2985 uint64_t reserved_40_63 : 24;
2988 struct cvmx_sriox_rx_bell_seq_s cn63xx;
2989 struct cvmx_sriox_rx_bell_seq_s cn63xxp1;
2990 struct cvmx_sriox_rx_bell_seq_s cn66xx;
2992 typedef union cvmx_sriox_rx_bell_seq cvmx_sriox_rx_bell_seq_t;
2995 * cvmx_srio#_rx_status
2997 * SRIO_RX_STATUS = SRIO Inbound Credits/Response Status
2999 * Specifies the current number of credits/responses by SRIO for Inbound Traffic
3002 * Debug Register specifying the number of credits/responses currently in use for Inbound Traffic.
3003 * The maximum value for COMP, N_POST and POST is set in SRIO(0,2..3)_TLP_CREDITS. When all inbound traffic
3004 * has stopped the values should eventually return to the maximum values. The RTN_PR[3:1] entry
3005 * counts should eventually return to the reset values.
3007 * Clk_Rst: SRIO(0,2..3)_RX_STATUS hclk hrst_n
3009 union cvmx_sriox_rx_status {
3011 struct cvmx_sriox_rx_status_s {
3012 #ifdef __BIG_ENDIAN_BITFIELD
3013 uint64_t rtn_pr3 : 8; /**< Number of pending Priority 3 Response Entries. */
3014 uint64_t rtn_pr2 : 8; /**< Number of pending Priority 2 Response Entries. */
3015 uint64_t rtn_pr1 : 8; /**< Number of pending Priority 1 Response Entries. */
3016 uint64_t reserved_28_39 : 12;
3017 uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S. */
3018 uint64_t comp : 8; /**< Credits for Read Completions used in M2S. */
3019 uint64_t reserved_13_15 : 3;
3020 uint64_t n_post : 5; /**< Credits for Read Requests used in M2S. */
3021 uint64_t post : 8; /**< Credits for Write Request Postings used in M2S. */
3024 uint64_t n_post : 5;
3025 uint64_t reserved_13_15 : 3;
3028 uint64_t reserved_28_39 : 12;
3029 uint64_t rtn_pr1 : 8;
3030 uint64_t rtn_pr2 : 8;
3031 uint64_t rtn_pr3 : 8;
3034 struct cvmx_sriox_rx_status_s cn63xx;
3035 struct cvmx_sriox_rx_status_s cn63xxp1;
3036 struct cvmx_sriox_rx_status_s cn66xx;
3038 typedef union cvmx_sriox_rx_status cvmx_sriox_rx_status_t;
3041 * cvmx_srio#_s2m_type#
3043 * SRIO_S2M_TYPE[0:15] = SLI to SRIO MAC Operation Type
3045 * SRIO Operation Type selected by PP or DMA Accesses
3048 * This CSR table specifies how to convert a SLI/DPI MAC read or write into sRIO operations.
3049 * Each SLI/DPI read or write access supplies a 64-bit address (MACADD[63:0]), 2-bit ADDRTYPE, and
3050 * 2-bit endian-swap. This SRIO*_S2M_TYPE* CSR description specifies a table with 16 CSRs. SRIO
3051 * selects one of the table entries with TYPEIDX[3:0], which it creates from the SLI/DPI MAC memory
3052 * space read or write as follows:
3053 * TYPEIDX[1:0] = ADDRTYPE[1:0] (ADDRTYPE[1] is no-snoop to the PCIe MAC,
3054 * ADDRTYPE[0] is relaxed-ordering to the PCIe MAC)
3055 * TYPEIDX[2] = MACADD[50]
3056 * TYPEIDX[3] = MACADD[59]
3058 * Clk_Rst: SRIO(0,2..3)_S2M_TYPE[0:15] hclk hrst_n
3060 union cvmx_sriox_s2m_typex {
3062 struct cvmx_sriox_s2m_typex_s {
3063 #ifdef __BIG_ENDIAN_BITFIELD
3064 uint64_t reserved_19_63 : 45;
3065 uint64_t wr_op : 3; /**< sRIO operation for SLI/DPI writes
3067 SLI/DPI hardware break MAC memory space writes
3068 that they generate into pieces of maximum size
3069 256B. For NWRITE/NWRITE_R/SWRITE WR_OP variants
3070 below, SRIO will, if necessary to obey sRIO
3071 requirements, automatically break the write into
3072 even smaller writes. The same is not true for
3073 MAINTENANCE writes and port-writes. Additional
3074 SW/usage restrictions are required for these
3075 MAINTENANCE WR_OP's to work correctly. SW must
3076 restrict the alignment and length of DPI pointers,
3077 limit the store sizes that the cores issue, and
3078 possibly also set SLI_MEM_ACCESS_SUBID*[NMERGE]
3079 so that all MAC memory space writes with
3080 MAINTENANCE write and port-write WR_OP's can be
3081 serviced in a single sRIO operation.
3083 SRIO always sends the write data (64-bit) words
3086 WR_OP = 0 = Normal Write (NWRITE)
3087 SRIO breaks a MAC memory space write into
3088 the minimum number of required sRIO NWRITE
3089 operations. This will be 1-5 total NWRITEs,
3090 depending on endian-swap, alignment, and
3093 WR_OP = 1 = Normal Write w/Response (NWRITE_R)
3094 SRIO breaks a MAC memory space write into
3095 the minimum number of required sRIO
3096 NWRITE_R operations. This will be 1-5 total
3097 NWRITE_R's, depending on endian-swap,
3098 alignment, and length.
3100 SRIO sets SRIO*_INT_REG[WR_DONE] after it
3101 receives the DONE response for the last
3104 WR_OP = 2 = NWRITE, Streaming write (SWRITE),
3106 SRIO attempts to turn the MAC memory space
3107 write into an SWRITE operation. There will
3108 be 1-5 total sRIO operations (0-2 NWRITE's
3109 followed by 0-1 SWRITE's followed by 0-2
3110 NWRITE's) generated to complete the MAC
3111 memory space write, depending on
3112 endian-swap, alignment, and length.
3114 If the starting address is not 64-bit
3115 aligned, SRIO first creates 1-4 NWRITE's to
3116 either align it or complete the write. Then
3117 SRIO creates a SWRITE including all aligned
3118 64-bit words. (SRIO won't create an SWRITE
3119 when there are none.) If store data
3120 remains, SRIO finally creates another 1 or
3123 WR_OP = 3 = NWRITE, SWRITE, NWRITE_R
3124 SRIO attempts to turn the MAC memory space
3125 write into an SWRITE operation followed by
3126 a NWRITE_R operation. The last operation
3127 is always NWRITE_R. There will be 1-5
3128 total sRIO operations (0-2 NWRITE's,
3129 followed by 0-1 SWRITE, followed by 1-4
3130 NWRITE_R's) generated to service the MAC
3131 memory space write, depending on
3132 endian-swap, alignment, and length.
3134 If the write is contained in one aligned
3135 64-bit word, SRIO will completely service
3136 the MAC memory space write with 1-4
3139 Otherwise, if the write spans multiple
3140 words, SRIO services the write as follows.
3141 First, if the start of the write is not
3142 word-aligned, SRIO creates 1 or 2 NWRITE's
3143 to align it. Then SRIO creates an SWRITE
3144 that includes all aligned 64-bit words,
3145 leaving data for the final NWRITE_R(s).
3146 (SRIO won't create the SWRITE when there is
3147 no data for it.) Then SRIO finally creates
3150 In any case, SRIO sets
3151 SRIO*_INT_REG[WR_DONE] after it receives
3152 the DONE response for the last NWRITE_R
3155 WR_OP = 4 = NWRITE, NWRITE_R
3156 SRIO attempts to turn the MAC memory space
3157 write into an NWRITE operation followed by
3158 a NWRITE_R operation. The last operation
3159 is always NWRITE_R. There will be 1-5
3160 total sRIO operations (0-3 NWRITE's
3161 followed by 1-4 NWRITE_R's) generated to
3162 service the MAC memory space write,
3163 depending on endian-swap, alignment, and
3166 If the write is contained in one aligned
3167 64-bit word, SRIO will completely service
3168 the MAC memory space write with 1-4
3171 Otherwise, if the write spans multiple
3172 words, SRIO services the write as follows.
3173 First, if the start of the write is not
3174 word-aligned, SRIO creates 1 or 2 NWRITE's
3175 to align it. Then SRIO creates an NWRITE
3176 that includes all aligned 64-bit words,
3177 leaving data for the final NWRITE_R(s).
3178 (SRIO won't create this NWRITE when there
3179 is no data for it.) Then SRIO finally
3180 creates 1 or 2 NWRITE_R's.
3182 In any case, SRIO sets
3183 SRIO*_INT_REG[WR_DONE] after it receives
3184 the DONE response for the last NWRITE_R
3187 WR_OP = 5 = Reserved
3189 WR_OP = 6 = Maintenance Write
3190 - SRIO will create one sRIO MAINTENANCE write
3191 operation to service the MAC memory space
3193 - IAOW_SEL must be zero. (see description
3195 - MDS must be zero. (MDS is MACADD[63:62] -
3196 see IAOW_SEL description below.)
3197 - Hop Cnt is MACADD[31:24]/SRIOAddress[31:24]
3198 - MACADD[23:0]/SRIOAddress[23:0] selects
3199 maintenance register (i.e. config_offset)
3200 - sRIODestID[15:0] is MACADD[49:34].
3201 (MACADD[49:42] unused when ID16=0)
3202 - Write size/alignment must obey sRIO rules
3203 (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte
3206 WR_OP = 7 = Maintenance Port Write
3207 - SRIO will create one sRIO MAINTENANCE port
3208 write operation to service the MAC memory
3210 - IAOW_SEL must be zero. (see description
3212 - MDS must be zero. (MDS is MACADD[63:62] -
3213 see IAOW_SEL description below.)
3214 - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24]
3215 - MACADD[23:0]/sRIOAddress[23:0] MBZ
3216 (config_offset field reserved by sRIO)
3217 - sRIODestID[15:0] is MACADD[49:34].
3218 (MACADD[49:42] unused when ID16=0)
3219 - Write size/alignment must obey sRIO rules
3220 (4, 8, 16, 24, 32, 40, 48, 56 and 64 byte
3222 uint64_t reserved_15_15 : 1;
3223 uint64_t rd_op : 3; /**< sRIO operation for SLI/DPI reads
3225 SLI/DPI hardware and sRIO configuration
3226 restrictions guarantee that SRIO can service any
3227 MAC memory space read that it receives from SLI/DPI
3228 with a single NREAD, assuming that RD_OP selects
3229 NREAD. DPI will break a read into multiple MAC
3230 memory space reads to ensure this holds. The same
3231 is not true for the ATOMIC and MAINTENANCE RD_OP
3232 values. Additional SW/usage restrictions are
3233 required for ATOMIC and MAINTENANCE RD_OP to work
3234 correctly. SW must restrict the alignment and
3235 length of DPI pointers and limit the load sizes
3236 that the cores issue such that all MAC memory space
3237 reads with ATOMIC and MAINTENANCE RD_OP's can be
3238 serviced in a single sRIO operation.
3240 RD_OP = 0 = Normal Read (NREAD)
3241 - SRIO will create one sRIO NREAD
3242 operation to service the MAC memory
3244 - Read size/alignment must obey sRIO rules
3245 (up to 256 byte lengths). (This requirement
3246 is guaranteed by SLI/DPI usage restrictions
3249 RD_OP = 1 = Reserved
3251 RD_OP = 2 = Atomic Set
3252 - SRIO will create one sRIO ATOMIC set
3253 operation to service the MAC memory
3255 - Read size/alignment must obey sRIO rules
3256 (1, 2, and 4 byte lengths allowed)
3258 RD_OP = 3 = Atomic Clear
3259 - SRIO will create one sRIO ATOMIC clr
3260 operation to service the MAC memory
3262 - Read size/alignment must obey sRIO rules
3263 (1, 2, and 4 byte lengths allowed)
3265 RD_OP = 4 = Atomic Increment
3266 - SRIO will create one sRIO ATOMIC inc
3267 operation to service the MAC memory
3269 - Read size/alignment must obey sRIO rules
3270 (1, 2, and 4 byte lengths allowed)
3272 RD_OP = 5 = Atomic Decrement
3273 - SRIO will create one sRIO ATOMIC dec
3274 operation to service the MAC memory
3276 - Read size/alignment must obey sRIO rules
3277 (1, 2, and 4 byte lengths allowed)
3279 RD_OP = 6 = Maintenance Read
3280 - SRIO will create one sRIO MAINTENANCE read
3281 operation to service the MAC memory
3283 - IAOW_SEL must be zero. (see description
3285 - MDS must be zero. (MDS is MACADD[63:62] -
3286 see IAOW_SEL description below.)
3287 - Hop Cnt is MACADD[31:24]/sRIOAddress[31:24]
3288 - MACADD[23:0]/sRIOAddress[23:0] selects
3289 maintenance register (i.e. config_offset)
3290 - sRIODestID[15:0] is MACADD[49:34].
3291 (MACADD[49:42] unused when ID16=0)
3292 - Read size/alignment must obey sRIO rules
3293 (4, 8, 16, 32 and 64 byte lengths allowed)
3295 RD_OP = 7 = Reserved */
3296 uint64_t wr_prior : 2; /**< Transaction Priority 0-3 used for writes */
3297 uint64_t rd_prior : 2; /**< Transaction Priority 0-3 used for reads/ATOMICs */
3298 uint64_t reserved_6_7 : 2;
3299 uint64_t src_id : 1; /**< Source ID
3301 0 = Use Primary ID as Source ID
3302 (SRIOMAINT*_PRI_DEV_ID[ID16 or ID8], depending
3303 on SRIO TT ID (i.e. ID16 below))
3305 1 = Use Secondary ID as Source ID
3306 (SRIOMAINT*_SEC_DEV_ID[ID16 or ID8], depending
3307 on SRIO TT ID (i.e. ID16 below)) */
3308 uint64_t id16 : 1; /**< SRIO TT ID 0=8bit, 1=16-bit
3309 IAOW_SEL must not be 2 when ID16=1. */
3310 uint64_t reserved_2_3 : 2;
3311 uint64_t iaow_sel : 2; /**< Internal Address Offset Width Select
3313 IAOW_SEL determines how to convert the
3314 MACADD[63:62,58:51,49:0] recieved from SLI/DPI with
3315 read/write into an sRIO address (sRIOAddress[...])
3316 and sRIO destination ID (sRIODestID[...]). The sRIO
3317 address width mode (SRIOMAINT_PE_LLC[EX_ADDR]) and
3318 ID16, determine the width of the sRIO address and
3319 ID in the outgoing request(s), respectively.
3321 MACADD[61:60] is always unused.
3323 MACADD[59] is always TYPEIDX[3]
3324 MACADD[50] is always TYPEIDX[2]
3325 (TYPEIDX[3:0] selects one of these
3326 SRIO*_S2M_TYPE* table entries.)
3328 MACADD[17:0] always becomes sRIOAddress[17:0].
3330 IAOW_SEL = 0 = 34-bit Address Offset
3332 Must be used when sRIO link is in 34-bit
3334 When sRIO is in 50-bit address width mode,
3335 sRIOAddress[49:34]=0 in the outgoing request.
3336 When sRIO is in 66-bit address width mode,
3337 sRIOAddress[65:34]=0 in the outgoing request.
3339 Usage of the SLI/DPI MAC address when
3341 MACADD[63:62] = Multi-Device Swap (MDS)
3342 MDS value affects MACADD[49:18] usage
3343 MACADD[58:51] => unused
3344 MACADD[49:18] usage depends on MDS value
3346 MACADD[49:34] => sRIODestID[15:0]
3347 (MACADD[49:42] unused when ID16=0)
3348 MACADD[33:18] => sRIOAddress[33:18]
3350 MACADD[49:42] => sRIODestID[15:8]
3351 (MACADD[49:42] unused when ID16 = 0)
3352 MACADD[41:34] => sRIOAddress[33:26]
3353 MACADD[33:26] => sRIODestID[7:0]
3354 MACADD[25:18] => sRIOAddress[25:18]
3357 MACADD[49:34] => sRIOAddress[33:18]
3358 MACADD[33:18] => sRIODestID[15:0]
3361 IAOW_SEL = 1 = 42-bit Address Offset
3363 Must not be used when sRIO link is in 34-bit
3365 When sRIO is in 50-bit address width mode,
3366 sRIOAddress[49:42]=0 in the outgoing request.
3367 When sRIO is in 66-bit address width mode,
3368 sRIOAddress[65:42]=0 in the outgoing request.
3370 Usage of the SLI/DPI MAC address when
3372 MACADD[63:62] => Multi-Device Swap (MDS)
3373 MDS value affects MACADD[58:51,49:42,33:18]
3375 MACADD[41:34] => sRIOAddress[41:34]
3376 MACADD[58:51,49:42,33:18] usage depends on
3379 MACADD[58:51] => sRIODestID[15:8]
3380 MACADD[49:42] => sRIODestID[7:0]
3381 (MACADD[58:51] unused when ID16=0)
3382 MACADD[33:18] => sRIOAddress[33:18]
3384 MACADD[58:51] => sRIODestID[15:8]
3385 (MACADD[58:51] unused when ID16 = 0)
3386 MACADD[49:42] => sRIOAddress[33:26]
3387 MACADD[33:26] => sRIODestID[7:0]
3388 MACADD[25:18] => sRIOAddress[25:18]
3391 MACADD[58:51] => sRIOAddress[33:26]
3392 MACADD[49:42] => sRIOAddress[25:18]
3393 MACADD[33:18] => sRIODestID[15:0]
3396 IAOW_SEL = 2 = 50-bit Address Offset
3398 Must not be used when sRIO link is in 34-bit
3400 Must not be used when ID16=1.
3401 When sRIO is in 66-bit address width mode,
3402 sRIOAddress[65:50]=0 in the outgoing request.
3404 Usage of the SLI/DPI MAC address when
3406 MACADD[63:62] => Multi-Device Swap (MDS)
3407 MDS value affects MACADD[58:51,33:26] use
3408 MDS value 3 is reserved
3409 MACADD[49:34] => sRIOAddress[49:34]
3410 MACADD[25:18] => sRIOAddress[25:18]
3411 MACADD[58:51,33:26] usage depends on
3414 MACADD[58:51] => sRIODestID[7:0]
3415 MACADD[33:26] => sRIOAddress[33:26]
3417 MACADD[58:51] => sRIOAddress[33:26]
3418 MACADD[33:26] => sRIODestID[7:0]
3422 IAOW_SEL = 3 = Reserved */
3424 uint64_t iaow_sel : 2;
3425 uint64_t reserved_2_3 : 2;
3427 uint64_t src_id : 1;
3428 uint64_t reserved_6_7 : 2;
3429 uint64_t rd_prior : 2;
3430 uint64_t wr_prior : 2;
3432 uint64_t reserved_15_15 : 1;
3434 uint64_t reserved_19_63 : 45;
3437 struct cvmx_sriox_s2m_typex_s cn63xx;
3438 struct cvmx_sriox_s2m_typex_s cn63xxp1;
3439 struct cvmx_sriox_s2m_typex_s cn66xx;
3441 typedef union cvmx_sriox_s2m_typex cvmx_sriox_s2m_typex_t;
3446 * SRIO_SEQ = SRIO Sequence Count
3448 * The SRIO Sequence Count
3451 * This register contains the current value of the sequence counter. This counter increments every
3452 * time a doorbell or the first segment of a message is accepted.
3454 * Clk_Rst: SRIO(0,2..3)_SEQ hclk hrst_n
3456 union cvmx_sriox_seq {
3458 struct cvmx_sriox_seq_s {
3459 #ifdef __BIG_ENDIAN_BITFIELD
3460 uint64_t reserved_32_63 : 32;
3461 uint64_t seq : 32; /**< 32-bit Sequence \# */
3464 uint64_t reserved_32_63 : 32;
3467 struct cvmx_sriox_seq_s cn63xx;
3468 struct cvmx_sriox_seq_s cn63xxp1;
3469 struct cvmx_sriox_seq_s cn66xx;
3471 typedef union cvmx_sriox_seq cvmx_sriox_seq_t;
3474 * cvmx_srio#_status_reg
3479 * SRIO_STATUS_REG = SRIO Status Register
3481 * General status of the SRIO.
3484 * The SRIO field displays if the port has been configured for SRIO operation. This register can be
3485 * read regardless of whether the SRIO is selected or being reset. Although some other registers can
3486 * be accessed while the ACCESS bit is zero (see individual registers for details), the majority of
3487 * SRIO registers and all the SRIOMAINT registers can be used only when the ACCESS bit is asserted.
3489 * Clk_Rst: SRIO(0,2..3)_STATUS_REG sclk srst_n
3491 union cvmx_sriox_status_reg {
3493 struct cvmx_sriox_status_reg_s {
3494 #ifdef __BIG_ENDIAN_BITFIELD
3495 uint64_t reserved_2_63 : 62;
3496 uint64_t access : 1; /**< SRIO and SRIOMAINT Register Access.
3497 0 - Register Access Disabled.
3498 1 - Register Access Enabled. */
3499 uint64_t srio : 1; /**< SRIO Port Enabled.
3500 0 - All SRIO functions disabled.
3501 1 - All SRIO Operations permitted. */
3504 uint64_t access : 1;
3505 uint64_t reserved_2_63 : 62;
3508 struct cvmx_sriox_status_reg_s cn63xx;
3509 struct cvmx_sriox_status_reg_s cn63xxp1;
3510 struct cvmx_sriox_status_reg_s cn66xx;
3512 typedef union cvmx_sriox_status_reg cvmx_sriox_status_reg_t;
3515 * cvmx_srio#_tag_ctrl
3517 * SRIO_TAG_CTRL = SRIO TAG Control
3519 * The SRIO TAG Control
3522 * This register is used to show the state of the internal transaction tags and provides a manual
3523 * reset of the outgoing tags.
3525 * Clk_Rst: SRIO(0,2..3)_TAG_CTRL hclk hrst_n
3527 union cvmx_sriox_tag_ctrl {
3529 struct cvmx_sriox_tag_ctrl_s {
3530 #ifdef __BIG_ENDIAN_BITFIELD
3531 uint64_t reserved_17_63 : 47;
3532 uint64_t o_clr : 1; /**< Manual OTAG Clear. This bit manually resets the
3533 number of OTAGs back to 16 and loses track of any
3534 outgoing packets. This function is automatically
3535 performed when the SRIO MAC is reset but it may be
3536 necessary after a chip reset while the MAC is in
3537 operation. This bit must be set then cleared to
3538 return to normal operation. Typically, Outgoing
3539 SRIO packets must be halted 6 seconds prior to
3540 this bit is set to avoid generating duplicate tags
3541 and unexpected response errors. */
3542 uint64_t reserved_13_15 : 3;
3543 uint64_t otag : 5; /**< Number of Available Outbound Tags. Tags are
3544 required for all outgoing memory and maintenance
3545 operations that require a response. (Max 16) */
3546 uint64_t reserved_5_7 : 3;
3547 uint64_t itag : 5; /**< Number of Available Inbound Tags. Tags are
3548 required for all incoming memory operations that
3549 require a response. (Max 16) */
3552 uint64_t reserved_5_7 : 3;
3554 uint64_t reserved_13_15 : 3;
3556 uint64_t reserved_17_63 : 47;
3559 struct cvmx_sriox_tag_ctrl_s cn63xx;
3560 struct cvmx_sriox_tag_ctrl_s cn63xxp1;
3561 struct cvmx_sriox_tag_ctrl_s cn66xx;
3563 typedef union cvmx_sriox_tag_ctrl cvmx_sriox_tag_ctrl_t;
3566 * cvmx_srio#_tlp_credits
3568 * SRIO_TLP_CREDITS = SRIO TLP Credits
3570 * Specifies the number of credits the SRIO can use for incoming Commands and Messages.
3573 * Specifies the number of maximum credits the SRIO can use for incoming Commands and Messages.
3574 * Reset values for COMP, N_POST and POST credits are based on the number of lanes allocated by the
3575 * QLM Configuration to the SRIO MAC and whether QLM1 is used by PCIe. If SRIO MACs are unused then
3576 * credits may be allocated to other MACs under some circumstances. The following table shows the
3577 * reset values for COMP/N_POST/POST:
3578 * QLM0_CFG QLM1_CFG SRIO0 SRIO2 SRIO3
3579 * ======================================================
3580 * PEM Any 0/0/0 0/0/0 0/0/0
3581 * SRIO x4 Any 128/16/128 0/0/0 0/0/0
3582 * SRIO x2 PEM 64/8/64 64/8/64 0/0/0
3583 * SRIO x2 non-PEM 128/16/128 128/16/128 0/0/0
3584 * SRIO x1 PEM 42/5/42 42/5/42 42/5/42
3585 * SRIO x1 non-PEM 64/8/64 64/8/64 64/8/64
3587 * Clk_Rst: SRIO(0,2..3)_TLP_CREDITS hclk hrst_n
3589 union cvmx_sriox_tlp_credits {
3591 struct cvmx_sriox_tlp_credits_s {
3592 #ifdef __BIG_ENDIAN_BITFIELD
3593 uint64_t reserved_28_63 : 36;
3594 uint64_t mbox : 4; /**< Credits for Mailbox Data used in M2S.
3595 Legal values are 0x2 to 0x8. */
3596 uint64_t comp : 8; /**< Credits for Read Completions used in M2S.
3597 Legal values are 0x22 to 0x80. */
3598 uint64_t reserved_13_15 : 3;
3599 uint64_t n_post : 5; /**< Credits for Read Requests used in M2S.
3600 Legal values are 0x4 to 0x10. */
3601 uint64_t post : 8; /**< Credits for Write Request Postings used in M2S.
3602 Legal values are 0x22 to 0x80. */
3605 uint64_t n_post : 5;
3606 uint64_t reserved_13_15 : 3;
3609 uint64_t reserved_28_63 : 36;
3612 struct cvmx_sriox_tlp_credits_s cn63xx;
3613 struct cvmx_sriox_tlp_credits_s cn63xxp1;
3614 struct cvmx_sriox_tlp_credits_s cn66xx;
3616 typedef union cvmx_sriox_tlp_credits cvmx_sriox_tlp_credits_t;
3619 * cvmx_srio#_tx_bell
3621 * SRIO_TX_BELL = SRIO Transmit Doorbell
3623 * The SRIO Outgoing (TX) Doorbell
3626 * This register specifies SRIO Information, Device ID, Transaction Type and Priority of the outgoing
3627 * Doorbell Transaction. Writes to this register causes the Doorbell to be issued using these bits.
3628 * The write also causes the PENDING bit to be set. The hardware automatically clears bit when the
3629 * Doorbell operation has been acknowledged. A write to this register while the PENDING bit is set
3630 * should be avoided as it will stall the RSL until the first Doorbell has completed.
3632 * Clk_Rst: SRIO(0,2..3)_TX_BELL hclk hrst_n
3634 union cvmx_sriox_tx_bell {
3636 struct cvmx_sriox_tx_bell_s {
3637 #ifdef __BIG_ENDIAN_BITFIELD
3638 uint64_t reserved_48_63 : 16;
3639 uint64_t data : 16; /**< Information field for next doorbell operation */
3640 uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */
3641 uint64_t reserved_9_15 : 7;
3642 uint64_t pending : 1; /**< Doorbell Transmit in Progress */
3643 uint64_t reserved_5_7 : 3;
3644 uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */
3645 uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */
3646 uint64_t reserved_2_2 : 1;
3647 uint64_t priority : 2; /**< Doorbell Priority */
3649 uint64_t priority : 2;
3650 uint64_t reserved_2_2 : 1;
3652 uint64_t src_id : 1;
3653 uint64_t reserved_5_7 : 3;
3654 uint64_t pending : 1;
3655 uint64_t reserved_9_15 : 7;
3656 uint64_t dest_id : 16;
3658 uint64_t reserved_48_63 : 16;
3661 struct cvmx_sriox_tx_bell_s cn63xx;
3662 struct cvmx_sriox_tx_bell_s cn63xxp1;
3663 struct cvmx_sriox_tx_bell_s cn66xx;
3665 typedef union cvmx_sriox_tx_bell cvmx_sriox_tx_bell_t;
3668 * cvmx_srio#_tx_bell_info
3670 * SRIO_TX_BELL_INFO = SRIO Transmit Doorbell Interrupt Information
3672 * The SRIO Outgoing (TX) Doorbell Interrupt Information
3675 * This register is only updated if the BELL_ERR bit is clear in SRIO(0,2..3)_INT_REG. This register
3676 * displays SRIO Information, Device ID, Transaction Type and Priority of the Doorbell Transaction
3677 * that generated the BELL_ERR Interrupt. The register includes either a RETRY, ERROR or TIMEOUT
3680 * Clk_Rst: SRIO(0,2..3)_TX_BELL_INFO hclk hrst_n
3682 union cvmx_sriox_tx_bell_info {
3684 struct cvmx_sriox_tx_bell_info_s {
3685 #ifdef __BIG_ENDIAN_BITFIELD
3686 uint64_t reserved_48_63 : 16;
3687 uint64_t data : 16; /**< Information field from last doorbell operation */
3688 uint64_t dest_id : 16; /**< Doorbell Destination Device ID[15:0] */
3689 uint64_t reserved_8_15 : 8;
3690 uint64_t timeout : 1; /**< Transmit Doorbell Failed with Timeout. */
3691 uint64_t error : 1; /**< Transmit Doorbell Destination returned Error. */
3692 uint64_t retry : 1; /**< Transmit Doorbell Requests a retransmission. */
3693 uint64_t src_id : 1; /**< Source Device ID 0=Primary, 1=Secondary */
3694 uint64_t id16 : 1; /**< Transaction Type, 0=use ID[7:0], 1=use ID[15:0] */
3695 uint64_t reserved_2_2 : 1;
3696 uint64_t priority : 2; /**< Doorbell Priority */
3698 uint64_t priority : 2;
3699 uint64_t reserved_2_2 : 1;
3701 uint64_t src_id : 1;
3704 uint64_t timeout : 1;
3705 uint64_t reserved_8_15 : 8;
3706 uint64_t dest_id : 16;
3708 uint64_t reserved_48_63 : 16;
3711 struct cvmx_sriox_tx_bell_info_s cn63xx;
3712 struct cvmx_sriox_tx_bell_info_s cn63xxp1;
3713 struct cvmx_sriox_tx_bell_info_s cn66xx;
3715 typedef union cvmx_sriox_tx_bell_info cvmx_sriox_tx_bell_info_t;
3718 * cvmx_srio#_tx_ctrl
3720 * SRIO_TX_CTRL = SRIO Transmit Control
3722 * The SRIO Transmit Control
3725 * This register is used to control SRIO Outgoing Packet Allocation. TAG_TH[2:0] set the thresholds
3726 * to allow priority traffic requiring responses to be queued based on the number of outgoing tags
3727 * (TIDs) available. 16 Tags are available. If a priority is blocked for lack of tags then all
3728 * lower priority packets are also blocked irregardless of whether they require tags.
3730 * Clk_Rst: SRIO(0,2..3)_TX_CTRL hclk hrst_n
3732 union cvmx_sriox_tx_ctrl {
3734 struct cvmx_sriox_tx_ctrl_s {
3735 #ifdef __BIG_ENDIAN_BITFIELD
3736 uint64_t reserved_53_63 : 11;
3737 uint64_t tag_th2 : 5; /**< Sets threshold for minimum number of OTAGs
3738 required before a packet of priority 2 requiring a
3739 response will be queued for transmission. (Max 16)
3740 There generally should be no priority 3 request
3741 packets which require a response/tag, so a TAG_THR
3742 value as low as 0 is allowed. */
3743 uint64_t reserved_45_47 : 3;
3744 uint64_t tag_th1 : 5; /**< Sets threshold for minimum number of OTAGs
3745 required before a packet of priority 1 requiring a
3746 response will be queued for transmission. (Max 16)
3747 Generally, TAG_TH1 must be > TAG_TH2 to leave OTAGs
3748 for outgoing priority 2 (or 3) requests. */
3749 uint64_t reserved_37_39 : 3;
3750 uint64_t tag_th0 : 5; /**< Sets threshold for minimum number of OTAGs
3751 required before a packet of priority 0 requiring a
3752 response will be queued for transmission. (Max 16)
3753 Generally, TAG_TH0 must be > TAG_TH1 to leave OTAGs
3754 for outgoing priority 1 or 2 (or 3) requests. */
3755 uint64_t reserved_20_31 : 12;
3756 uint64_t tx_th2 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
3757 uint64_t reserved_12_15 : 4;
3758 uint64_t tx_th1 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
3759 uint64_t reserved_4_7 : 4;
3760 uint64_t tx_th0 : 4; /**< Reserved. (See SRIOMAINT(0,2..3)_IR_BUFFER_CONFIG2) */
3762 uint64_t tx_th0 : 4;
3763 uint64_t reserved_4_7 : 4;
3764 uint64_t tx_th1 : 4;
3765 uint64_t reserved_12_15 : 4;
3766 uint64_t tx_th2 : 4;
3767 uint64_t reserved_20_31 : 12;
3768 uint64_t tag_th0 : 5;
3769 uint64_t reserved_37_39 : 3;
3770 uint64_t tag_th1 : 5;
3771 uint64_t reserved_45_47 : 3;
3772 uint64_t tag_th2 : 5;
3773 uint64_t reserved_53_63 : 11;
3776 struct cvmx_sriox_tx_ctrl_s cn63xx;
3777 struct cvmx_sriox_tx_ctrl_s cn63xxp1;
3778 struct cvmx_sriox_tx_ctrl_s cn66xx;
3780 typedef union cvmx_sriox_tx_ctrl cvmx_sriox_tx_ctrl_t;
3783 * cvmx_srio#_tx_emphasis
3785 * SRIO_TX_EMPHASIS = SRIO TX Lane Emphasis
3787 * Controls TX Emphasis used by the SRIO SERDES
3790 * This controls the emphasis value used by the SRIO SERDES. This register is only reset during COLD
3791 * boot and may be modified regardless of the value in SRIO(0,2..3)_STATUS_REG.ACCESS. This register is not
3792 * connected to the QLM and thus has no effect. It should not be included in the documentation.
3794 * Clk_Rst: SRIO(0,2..3)_TX_EMPHASIS sclk srst_cold_n
3796 union cvmx_sriox_tx_emphasis {
3798 struct cvmx_sriox_tx_emphasis_s {
3799 #ifdef __BIG_ENDIAN_BITFIELD
3800 uint64_t reserved_4_63 : 60;
3801 uint64_t emph : 4; /**< Emphasis Value used for all lanes. Default value
3802 is 0x0 for 1.25G b/s and 0xA for all other rates. */
3805 uint64_t reserved_4_63 : 60;
3808 struct cvmx_sriox_tx_emphasis_s cn63xx;
3809 struct cvmx_sriox_tx_emphasis_s cn66xx;
3811 typedef union cvmx_sriox_tx_emphasis cvmx_sriox_tx_emphasis_t;
3814 * cvmx_srio#_tx_status
3816 * SRIO_TX_STATUS = SRIO Outbound Credits/Ops Status
3818 * Specifies the current number of credits/ops by SRIO for Outbound Traffic
3821 * Debug Register specifying the number of credits/ops currently in use for Outbound Traffic.
3822 * When all outbound traffic has stopped the values should eventually return to the reset values.
3824 * Clk_Rst: SRIO(0,2..3)_TX_STATUS hclk hrst_n
3826 union cvmx_sriox_tx_status {
3828 struct cvmx_sriox_tx_status_s {
3829 #ifdef __BIG_ENDIAN_BITFIELD
3830 uint64_t reserved_32_63 : 32;
3831 uint64_t s2m_pr3 : 8; /**< Number of pending S2M Priority 3 Entries. */
3832 uint64_t s2m_pr2 : 8; /**< Number of pending S2M Priority 2 Entries. */
3833 uint64_t s2m_pr1 : 8; /**< Number of pending S2M Priority 1 Entries. */
3834 uint64_t s2m_pr0 : 8; /**< Number of pending S2M Priority 0 Entries. */
3836 uint64_t s2m_pr0 : 8;
3837 uint64_t s2m_pr1 : 8;
3838 uint64_t s2m_pr2 : 8;
3839 uint64_t s2m_pr3 : 8;
3840 uint64_t reserved_32_63 : 32;
3843 struct cvmx_sriox_tx_status_s cn63xx;
3844 struct cvmx_sriox_tx_status_s cn63xxp1;
3845 struct cvmx_sriox_tx_status_s cn66xx;
3847 typedef union cvmx_sriox_tx_status cvmx_sriox_tx_status_t;
3850 * cvmx_srio#_wr_done_counts
3852 * SRIO_WR_DONE_COUNTS = SRIO Outgoing Write Done Counts
3854 * The SRIO Outbound Write Done Counts
3857 * This register shows the number of successful and unsuccessful NwriteRs issued through this MAC.
3858 * These count only considers the last NwriteR generated by each Store Instruction. If any NwriteR
3859 * in the series receives an ERROR Status then it is reported in SRIOMAINT(0,2..3)_ERB_LT_ERR_DET.IO_ERR.
3860 * If any NwriteR does not receive a response within the timeout period then it is reported in
3861 * SRIOMAINT(0,2..3)_ERB_LT_ERR_DET.PKT_TOUT. Only errors on the last NwriteR's are counted as BAD. This
3862 * register is typically not written while Outbound SRIO Memory traffic is enabled.
3864 * Clk_Rst: SRIO(0,2..3)_WR_DONE_COUNTS hclk hrst_n
3866 union cvmx_sriox_wr_done_counts {
3868 struct cvmx_sriox_wr_done_counts_s {
3869 #ifdef __BIG_ENDIAN_BITFIELD
3870 uint64_t reserved_32_63 : 32;
3871 uint64_t bad : 16; /**< Count of the final outbound NwriteR in the series
3872 associated with a Store Operation that have timed
3873 out or received a response with an ERROR status. */
3874 uint64_t good : 16; /**< Count of the final outbound NwriteR in the series
3875 associated with a Store operation that has
3876 received a response with a DONE status. */
3880 uint64_t reserved_32_63 : 32;
3883 struct cvmx_sriox_wr_done_counts_s cn63xx;
3884 struct cvmx_sriox_wr_done_counts_s cn66xx;
3886 typedef union cvmx_sriox_wr_done_counts cvmx_sriox_wr_done_counts_t;