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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_STXX_DEFS_H__
53 #define __CVMX_STXX_DEFS_H__
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 static inline uint64_t CVMX_STXX_ARB_CTL(unsigned long block_id)
59 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
60 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
61 cvmx_warn("CVMX_STXX_ARB_CTL(%lu) is invalid on this chip\n", block_id);
62 return CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull;
65 #define CVMX_STXX_ARB_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000608ull) + ((block_id) & 1) * 0x8000000ull)
67 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
68 static inline uint64_t CVMX_STXX_BCKPRS_CNT(unsigned long block_id)
71 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
73 cvmx_warn("CVMX_STXX_BCKPRS_CNT(%lu) is invalid on this chip\n", block_id);
74 return CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull;
77 #define CVMX_STXX_BCKPRS_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000688ull) + ((block_id) & 1) * 0x8000000ull)
79 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
80 static inline uint64_t CVMX_STXX_COM_CTL(unsigned long block_id)
83 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
84 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
85 cvmx_warn("CVMX_STXX_COM_CTL(%lu) is invalid on this chip\n", block_id);
86 return CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull;
89 #define CVMX_STXX_COM_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000600ull) + ((block_id) & 1) * 0x8000000ull)
91 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
92 static inline uint64_t CVMX_STXX_DIP_CNT(unsigned long block_id)
95 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
96 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
97 cvmx_warn("CVMX_STXX_DIP_CNT(%lu) is invalid on this chip\n", block_id);
98 return CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull;
101 #define CVMX_STXX_DIP_CNT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000690ull) + ((block_id) & 1) * 0x8000000ull)
103 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
104 static inline uint64_t CVMX_STXX_IGN_CAL(unsigned long block_id)
107 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
109 cvmx_warn("CVMX_STXX_IGN_CAL(%lu) is invalid on this chip\n", block_id);
110 return CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull;
113 #define CVMX_STXX_IGN_CAL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000610ull) + ((block_id) & 1) * 0x8000000ull)
115 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
116 static inline uint64_t CVMX_STXX_INT_MSK(unsigned long block_id)
119 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
120 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
121 cvmx_warn("CVMX_STXX_INT_MSK(%lu) is invalid on this chip\n", block_id);
122 return CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull;
125 #define CVMX_STXX_INT_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A0ull) + ((block_id) & 1) * 0x8000000ull)
127 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
128 static inline uint64_t CVMX_STXX_INT_REG(unsigned long block_id)
131 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
132 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
133 cvmx_warn("CVMX_STXX_INT_REG(%lu) is invalid on this chip\n", block_id);
134 return CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull;
137 #define CVMX_STXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x0001180090000698ull) + ((block_id) & 1) * 0x8000000ull)
139 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
140 static inline uint64_t CVMX_STXX_INT_SYNC(unsigned long block_id)
143 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
145 cvmx_warn("CVMX_STXX_INT_SYNC(%lu) is invalid on this chip\n", block_id);
146 return CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull;
149 #define CVMX_STXX_INT_SYNC(block_id) (CVMX_ADD_IO_SEG(0x00011800900006A8ull) + ((block_id) & 1) * 0x8000000ull)
151 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
152 static inline uint64_t CVMX_STXX_MIN_BST(unsigned long block_id)
155 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
156 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
157 cvmx_warn("CVMX_STXX_MIN_BST(%lu) is invalid on this chip\n", block_id);
158 return CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull;
161 #define CVMX_STXX_MIN_BST(block_id) (CVMX_ADD_IO_SEG(0x0001180090000618ull) + ((block_id) & 1) * 0x8000000ull)
163 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
164 static inline uint64_t CVMX_STXX_SPI4_CALX(unsigned long offset, unsigned long block_id)
167 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 31)) && ((block_id <= 1)))) ||
168 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
169 cvmx_warn("CVMX_STXX_SPI4_CALX(%lu,%lu) is invalid on this chip\n", offset, block_id);
170 return CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
173 #define CVMX_STXX_SPI4_CALX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180090000400ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)
175 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
176 static inline uint64_t CVMX_STXX_SPI4_DAT(unsigned long block_id)
179 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
181 cvmx_warn("CVMX_STXX_SPI4_DAT(%lu) is invalid on this chip\n", block_id);
182 return CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull;
185 #define CVMX_STXX_SPI4_DAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000628ull) + ((block_id) & 1) * 0x8000000ull)
187 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
188 static inline uint64_t CVMX_STXX_SPI4_STAT(unsigned long block_id)
191 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
192 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
193 cvmx_warn("CVMX_STXX_SPI4_STAT(%lu) is invalid on this chip\n", block_id);
194 return CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull;
197 #define CVMX_STXX_SPI4_STAT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000630ull) + ((block_id) & 1) * 0x8000000ull)
199 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
200 static inline uint64_t CVMX_STXX_STAT_BYTES_HI(unsigned long block_id)
203 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
205 cvmx_warn("CVMX_STXX_STAT_BYTES_HI(%lu) is invalid on this chip\n", block_id);
206 return CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull;
209 #define CVMX_STXX_STAT_BYTES_HI(block_id) (CVMX_ADD_IO_SEG(0x0001180090000648ull) + ((block_id) & 1) * 0x8000000ull)
211 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
212 static inline uint64_t CVMX_STXX_STAT_BYTES_LO(unsigned long block_id)
215 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
216 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
217 cvmx_warn("CVMX_STXX_STAT_BYTES_LO(%lu) is invalid on this chip\n", block_id);
218 return CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull;
221 #define CVMX_STXX_STAT_BYTES_LO(block_id) (CVMX_ADD_IO_SEG(0x0001180090000680ull) + ((block_id) & 1) * 0x8000000ull)
223 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
224 static inline uint64_t CVMX_STXX_STAT_CTL(unsigned long block_id)
227 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
229 cvmx_warn("CVMX_STXX_STAT_CTL(%lu) is invalid on this chip\n", block_id);
230 return CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull;
233 #define CVMX_STXX_STAT_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180090000638ull) + ((block_id) & 1) * 0x8000000ull)
235 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
236 static inline uint64_t CVMX_STXX_STAT_PKT_XMT(unsigned long block_id)
239 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
240 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
241 cvmx_warn("CVMX_STXX_STAT_PKT_XMT(%lu) is invalid on this chip\n", block_id);
242 return CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull;
245 #define CVMX_STXX_STAT_PKT_XMT(block_id) (CVMX_ADD_IO_SEG(0x0001180090000640ull) + ((block_id) & 1) * 0x8000000ull)
251 * STX_ARB_CTL - Spi transmit arbitration control
255 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
256 * parameter will have to be adjusted. Please see the
257 * STX_SPI4_DAT[MAX_T] section for additional information. In
258 * addition, the min_burst can only be guaranteed on the initial data
259 * burst of a given packet (i.e. the first data burst which contains
260 * the SOP tick). All subsequent bursts could be truncated by training
261 * sequences at any point during transmission and could be arbitrarily
262 * small. This mode is only for use in Spi4 mode.
264 union cvmx_stxx_arb_ctl {
266 struct cvmx_stxx_arb_ctl_s {
267 #ifdef __BIG_ENDIAN_BITFIELD
268 uint64_t reserved_6_63 : 58;
269 uint64_t mintrn : 1; /**< Hold off training cycles until STX_MIN_BST[MINB]
271 uint64_t reserved_4_4 : 1;
272 uint64_t igntpa : 1; /**< User switch to ignore any TPA information from the
273 Spi interface. This CSR forces all TPA terms to
274 be masked out. It is only intended as backdoor
276 uint64_t reserved_0_2 : 3;
278 uint64_t reserved_0_2 : 3;
280 uint64_t reserved_4_4 : 1;
282 uint64_t reserved_6_63 : 58;
285 struct cvmx_stxx_arb_ctl_s cn38xx;
286 struct cvmx_stxx_arb_ctl_s cn38xxp2;
287 struct cvmx_stxx_arb_ctl_s cn58xx;
288 struct cvmx_stxx_arb_ctl_s cn58xxp1;
290 typedef union cvmx_stxx_arb_ctl cvmx_stxx_arb_ctl_t;
293 * cvmx_stx#_bckprs_cnt
296 * This register reports the total number of cycles (STX data clks -
297 * stx_clk) in which the port defined in STX_STAT_CTL[BCKPRS] has lost TPA
298 * or is otherwise receiving backpressure.
300 * In Spi4 mode, this is defined as a loss of TPA which is indicated when
301 * the receiving device reports SATISFIED for the given port. The calendar
302 * status is brought into N2 on the spi4_tx*_sclk and synchronized into the
303 * N2 Spi TX clock domain which is 1/2 the frequency of the spi4_tx*_dclk
304 * clock (internally, this the stx_clk). The counter will update on the
305 * rising edge in which backpressure is reported.
307 * This register will be cleared when software writes all '1's to
308 * the STX_BCKPRS_CNT.
310 union cvmx_stxx_bckprs_cnt {
312 struct cvmx_stxx_bckprs_cnt_s {
313 #ifdef __BIG_ENDIAN_BITFIELD
314 uint64_t reserved_32_63 : 32;
315 uint64_t cnt : 32; /**< Number of cycles when back-pressure is received
316 for port defined in STX_STAT_CTL[BCKPRS] */
319 uint64_t reserved_32_63 : 32;
322 struct cvmx_stxx_bckprs_cnt_s cn38xx;
323 struct cvmx_stxx_bckprs_cnt_s cn38xxp2;
324 struct cvmx_stxx_bckprs_cnt_s cn58xx;
325 struct cvmx_stxx_bckprs_cnt_s cn58xxp1;
327 typedef union cvmx_stxx_bckprs_cnt cvmx_stxx_bckprs_cnt_t;
332 * STX_COM_CTL - TX Common Control Register
337 * Both the calendar table and the LEN and M parameters must be
338 * completely setup before writing the Interface enable (INF_EN) and
339 * Status channel enabled (ST_EN) asserted.
341 union cvmx_stxx_com_ctl {
343 struct cvmx_stxx_com_ctl_s {
344 #ifdef __BIG_ENDIAN_BITFIELD
345 uint64_t reserved_4_63 : 60;
346 uint64_t st_en : 1; /**< Status channel enabled */
347 uint64_t reserved_1_2 : 2;
348 uint64_t inf_en : 1; /**< Interface enable */
351 uint64_t reserved_1_2 : 2;
353 uint64_t reserved_4_63 : 60;
356 struct cvmx_stxx_com_ctl_s cn38xx;
357 struct cvmx_stxx_com_ctl_s cn38xxp2;
358 struct cvmx_stxx_com_ctl_s cn58xx;
359 struct cvmx_stxx_com_ctl_s cn58xxp1;
361 typedef union cvmx_stxx_com_ctl cvmx_stxx_com_ctl_t;
368 * This counts the number of consecutive DIP2 states in which the the
369 * received DIP2 is bad. The expected range is 1-15 cycles with the
370 * value of 0 meaning disabled.
373 * This counts the number of consecutive unexpected framing patterns (11)
374 * states. The expected range is 1-15 cycles with the value of 0 meaning
377 union cvmx_stxx_dip_cnt {
379 struct cvmx_stxx_dip_cnt_s {
380 #ifdef __BIG_ENDIAN_BITFIELD
381 uint64_t reserved_8_63 : 56;
382 uint64_t frmmax : 4; /**< Number of consecutive unexpected framing patterns
383 before loss of sync */
384 uint64_t dipmax : 4; /**< Number of consecutive DIP2 error before loss
389 uint64_t reserved_8_63 : 56;
392 struct cvmx_stxx_dip_cnt_s cn38xx;
393 struct cvmx_stxx_dip_cnt_s cn38xxp2;
394 struct cvmx_stxx_dip_cnt_s cn58xx;
395 struct cvmx_stxx_dip_cnt_s cn58xxp1;
397 typedef union cvmx_stxx_dip_cnt cvmx_stxx_dip_cnt_t;
402 * STX_IGN_CAL - Ignore Calendar Status from Spi4 Status Channel
405 union cvmx_stxx_ign_cal {
407 struct cvmx_stxx_ign_cal_s {
408 #ifdef __BIG_ENDIAN_BITFIELD
409 uint64_t reserved_16_63 : 48;
410 uint64_t igntpa : 16; /**< Ignore Calendar Status from Spi4 Status Channel
412 - 0: Use the status channel info
413 - 1: Grant the given port MAX_BURST1 credits */
415 uint64_t igntpa : 16;
416 uint64_t reserved_16_63 : 48;
419 struct cvmx_stxx_ign_cal_s cn38xx;
420 struct cvmx_stxx_ign_cal_s cn38xxp2;
421 struct cvmx_stxx_ign_cal_s cn58xx;
422 struct cvmx_stxx_ign_cal_s cn58xxp1;
424 typedef union cvmx_stxx_ign_cal cvmx_stxx_ign_cal_t;
430 * If the bit is enabled, then the coresponding exception condition will
431 * result in an interrupt to the system.
433 union cvmx_stxx_int_msk {
435 struct cvmx_stxx_int_msk_s {
436 #ifdef __BIG_ENDIAN_BITFIELD
437 uint64_t reserved_8_63 : 56;
438 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
439 uint64_t unxfrm : 1; /**< Unexpected framing sequence */
440 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
441 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */
442 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */
443 uint64_t ovrbst : 1; /**< Transmit packet burst too big */
444 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */
445 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */
447 uint64_t calpar0 : 1;
448 uint64_t calpar1 : 1;
455 uint64_t reserved_8_63 : 56;
458 struct cvmx_stxx_int_msk_s cn38xx;
459 struct cvmx_stxx_int_msk_s cn38xxp2;
460 struct cvmx_stxx_int_msk_s cn58xx;
461 struct cvmx_stxx_int_msk_s cn58xxp1;
463 typedef union cvmx_stxx_int_msk cvmx_stxx_int_msk_t;
470 * This bit indicates that the Spi4 calendar table encountered a parity
471 * error on bank0 of the calendar table memory. This error bit is
472 * associated with the calendar table on the TX interface - the interface
473 * that drives the Spi databus. The calendar table is used in Spi4 mode
474 * when using the status channel. Parity errors can occur during normal
475 * operation when the calendar table is constantly being read for the port
476 * information, or during initialization time, when the user has access.
477 * This errors will force the the status channel to the reset state and
478 * begin driving training sequences. The status channel will also reset.
479 * Software must follow the init sequence to resynch the interface. This
480 * includes toggling INF_EN which will cancel all outstanding accumulated
484 * Identical to CALPAR0 except that it indicates that the error occured
485 * on bank1 (instead of bank0).
488 * STX can track upto a 512KB data burst. Any packet larger than that is
489 * illegal and will cause confusion in the STX state machine. BMI is
490 * responsible for throwing away these out of control packets from the
491 * input and the Execs should never generate them on the output. This is
492 * a fatal error and should have STX_INT_SYNC[OVRBST] set.
495 * FIFO where the Spi4 data ramps upto its transmit frequency has
496 * overflowed. This is a fatal error and should have
497 * STX_INT_SYNC[DATOVR] set.
500 * This bit will fire if any DIP2 error is caught by the Spi4 status
504 * This bit indicates that the number of consecutive DIP2 errors exceeds
505 * STX_DIP_CNT[MAXDIP] and that the interface should be taken down. The
506 * datapath will be notified and send continuous training sequences until
507 * software resynchronizes the interface. This error condition should
508 * have STX_INT_SYNC[NOSYNC] set.
511 * Unexpected framing data was seen on the status channel.
514 * This bit indicates that the number of consecutive unexpected framing
515 * sequences STX_DIP_CNT[MAXFRM] and that the interface should be taken
516 * down. The datapath will be notified and send continuous training
517 * sequences until software resynchronizes the interface. This error
518 * condition should have STX_INT_SYNC[FRMERR] set.
521 * Indicates that an exception marked in STX_INT_SYNC has occured and the
522 * TX datapath is disabled. It is recommended that the OVRBST, DATOVR,
523 * NOSYNC, and FRMERR error conditions all have their bits set in the
524 * STX_INT_SYNC register.
526 union cvmx_stxx_int_reg {
528 struct cvmx_stxx_int_reg_s {
529 #ifdef __BIG_ENDIAN_BITFIELD
530 uint64_t reserved_9_63 : 55;
531 uint64_t syncerr : 1; /**< Interface encountered a fatal error */
532 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
533 uint64_t unxfrm : 1; /**< Unexpected framing sequence */
534 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
535 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */
536 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */
537 uint64_t ovrbst : 1; /**< Transmit packet burst too big */
538 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */
539 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */
541 uint64_t calpar0 : 1;
542 uint64_t calpar1 : 1;
549 uint64_t syncerr : 1;
550 uint64_t reserved_9_63 : 55;
553 struct cvmx_stxx_int_reg_s cn38xx;
554 struct cvmx_stxx_int_reg_s cn38xxp2;
555 struct cvmx_stxx_int_reg_s cn58xx;
556 struct cvmx_stxx_int_reg_s cn58xxp1;
558 typedef union cvmx_stxx_int_reg cvmx_stxx_int_reg_t;
564 * If the bit is enabled, then the coresponding exception condition is flagged
565 * to be fatal. In Spi4 mode, the exception condition will result in a loss
566 * of sync condition on the Spi4 interface and the datapath will send
567 * continuous traing sequences.
569 * It is recommended that software set the OVRBST, DATOVR, NOSYNC, and
570 * FRMERR errors as synchronization events. Software is free to
571 * synchronize the bus on other conditions, but this is the minimum
574 union cvmx_stxx_int_sync {
576 struct cvmx_stxx_int_sync_s {
577 #ifdef __BIG_ENDIAN_BITFIELD
578 uint64_t reserved_8_63 : 56;
579 uint64_t frmerr : 1; /**< FRMCNT has exceeded STX_DIP_CNT[MAXFRM] */
580 uint64_t unxfrm : 1; /**< Unexpected framing sequence */
581 uint64_t nosync : 1; /**< ERRCNT has exceeded STX_DIP_CNT[MAXDIP] */
582 uint64_t diperr : 1; /**< DIP2 error on the Spi4 Status channel */
583 uint64_t datovr : 1; /**< Spi4 FIFO overflow error */
584 uint64_t ovrbst : 1; /**< Transmit packet burst too big */
585 uint64_t calpar1 : 1; /**< STX Calendar Table Parity Error Bank1 */
586 uint64_t calpar0 : 1; /**< STX Calendar Table Parity Error Bank0 */
588 uint64_t calpar0 : 1;
589 uint64_t calpar1 : 1;
596 uint64_t reserved_8_63 : 56;
599 struct cvmx_stxx_int_sync_s cn38xx;
600 struct cvmx_stxx_int_sync_s cn38xxp2;
601 struct cvmx_stxx_int_sync_s cn58xx;
602 struct cvmx_stxx_int_sync_s cn58xxp1;
604 typedef union cvmx_stxx_int_sync cvmx_stxx_int_sync_t;
609 * STX_MIN_BST - Min Burst to enforce when inserting training sequence
612 union cvmx_stxx_min_bst {
614 struct cvmx_stxx_min_bst_s {
615 #ifdef __BIG_ENDIAN_BITFIELD
616 uint64_t reserved_9_63 : 55;
617 uint64_t minb : 9; /**< When STX_ARB_CTL[MINTRN] is set, MINB indicates
618 the number of 8B blocks to send before inserting
619 a training sequence. Normally MINB will be set
620 to GMX_TX_SPI_THRESH[THRESH]. MINB should always
621 be set to an even number (ie. multiple of 16B) */
624 uint64_t reserved_9_63 : 55;
627 struct cvmx_stxx_min_bst_s cn38xx;
628 struct cvmx_stxx_min_bst_s cn38xxp2;
629 struct cvmx_stxx_min_bst_s cn58xx;
630 struct cvmx_stxx_min_bst_s cn58xxp1;
632 typedef union cvmx_stxx_min_bst cvmx_stxx_min_bst_t;
635 * cvmx_stx#_spi4_cal#
637 * specify the RSL base addresses for the block
638 * STX_SPI4_CAL - Spi4 Calender table
639 * direct_calendar_write / direct_calendar_read
642 * There are 32 calendar table CSR's, each containing 4 entries for a
643 * total of 128 entries. In the above definition...
645 * n = calendar table offset * 4
647 * Example, offset 0x00 contains the calendar table entries 0, 1, 2, 3
648 * (with n == 0). Offset 0x10 is the 16th entry in the calendar table
649 * and would contain entries (16*4) = 64, 65, 66, and 67.
652 * Calendar table entry accesses (read or write) can only occur
653 * if the interface is disabled. All other accesses will be
656 * Both the calendar table and the LEN and M parameters must be
657 * completely setup before writing the Interface enable (INF_EN) and
658 * Status channel enabled (ST_EN) asserted.
660 union cvmx_stxx_spi4_calx {
662 struct cvmx_stxx_spi4_calx_s {
663 #ifdef __BIG_ENDIAN_BITFIELD
664 uint64_t reserved_17_63 : 47;
665 uint64_t oddpar : 1; /**< Odd parity over STX_SPI4_CAL[15:0]
666 (^STX_SPI4_CAL[16:0] === 1'b1) | $NS NS */
667 uint64_t prt3 : 4; /**< Status for port n+3 */
668 uint64_t prt2 : 4; /**< Status for port n+2 */
669 uint64_t prt1 : 4; /**< Status for port n+1 */
670 uint64_t prt0 : 4; /**< Status for port n+0 */
677 uint64_t reserved_17_63 : 47;
680 struct cvmx_stxx_spi4_calx_s cn38xx;
681 struct cvmx_stxx_spi4_calx_s cn38xxp2;
682 struct cvmx_stxx_spi4_calx_s cn58xx;
683 struct cvmx_stxx_spi4_calx_s cn58xxp1;
685 typedef union cvmx_stxx_spi4_calx cvmx_stxx_spi4_calx_t;
690 * STX_SPI4_DAT - Spi4 datapath channel control register
695 * * DATA_MAX_T must be in MOD 4 cycles
697 * * DATA_MAX_T must at least 0x20
699 * * DATA_MAX_T == 0 or ALPHA == 0 will disable the training sequnce
701 * * If STX_ARB_CTL[MINTRN] is set, then training cycles will stall
702 * waiting for min bursts to complete. In the worst case, this will
703 * add the entire min burst transmission time to the interval between
704 * trainging sequence. The observed MAX_T on the Spi4 bus will be...
706 * STX_SPI4_DAT[MAX_T] + (STX_MIN_BST[MINB] * 4)
708 * If STX_ARB_CTL[MINTRN] is set in Spi4 mode, then the data_max_t
709 * parameter will have to be adjusted. Please see the
710 * STX_SPI4_DAT[MAX_T] section for additional information. In
711 * addition, the min_burst can only be guaranteed on the initial data
712 * burst of a given packet (i.e. the first data burst which contains
713 * the SOP tick). All subsequent bursts could be truncated by training
714 * sequences at any point during transmission and could be arbitrarily
715 * small. This mode is only for use in Spi4 mode.
717 union cvmx_stxx_spi4_dat {
719 struct cvmx_stxx_spi4_dat_s {
720 #ifdef __BIG_ENDIAN_BITFIELD
721 uint64_t reserved_32_63 : 32;
722 uint64_t alpha : 16; /**< alpha (from spi4.2 spec) */
723 uint64_t max_t : 16; /**< DATA_MAX_T (from spi4.2 spec) */
727 uint64_t reserved_32_63 : 32;
730 struct cvmx_stxx_spi4_dat_s cn38xx;
731 struct cvmx_stxx_spi4_dat_s cn38xxp2;
732 struct cvmx_stxx_spi4_dat_s cn58xx;
733 struct cvmx_stxx_spi4_dat_s cn58xxp1;
735 typedef union cvmx_stxx_spi4_dat cvmx_stxx_spi4_dat_t;
738 * cvmx_stx#_spi4_stat
740 * STX_SPI4_STAT - Spi4 status channel control register
745 * Both the calendar table and the LEN and M parameters must be
746 * completely setup before writing the Interface enable (INF_EN) and
747 * Status channel enabled (ST_EN) asserted.
749 * The calendar table will only be enabled when LEN > 0.
751 * Current rev will only support LVTTL status IO.
753 union cvmx_stxx_spi4_stat {
755 struct cvmx_stxx_spi4_stat_s {
756 #ifdef __BIG_ENDIAN_BITFIELD
757 uint64_t reserved_16_63 : 48;
758 uint64_t m : 8; /**< CALENDAR_M (from spi4.2 spec) */
759 uint64_t reserved_7_7 : 1;
760 uint64_t len : 7; /**< CALENDAR_LEN (from spi4.2 spec) */
763 uint64_t reserved_7_7 : 1;
765 uint64_t reserved_16_63 : 48;
768 struct cvmx_stxx_spi4_stat_s cn38xx;
769 struct cvmx_stxx_spi4_stat_s cn38xxp2;
770 struct cvmx_stxx_spi4_stat_s cn58xx;
771 struct cvmx_stxx_spi4_stat_s cn58xxp1;
773 typedef union cvmx_stxx_spi4_stat cvmx_stxx_spi4_stat_t;
776 * cvmx_stx#_stat_bytes_hi
778 union cvmx_stxx_stat_bytes_hi {
780 struct cvmx_stxx_stat_bytes_hi_s {
781 #ifdef __BIG_ENDIAN_BITFIELD
782 uint64_t reserved_32_63 : 32;
783 uint64_t cnt : 32; /**< Number of bytes sent (CNT[63:32]) */
786 uint64_t reserved_32_63 : 32;
789 struct cvmx_stxx_stat_bytes_hi_s cn38xx;
790 struct cvmx_stxx_stat_bytes_hi_s cn38xxp2;
791 struct cvmx_stxx_stat_bytes_hi_s cn58xx;
792 struct cvmx_stxx_stat_bytes_hi_s cn58xxp1;
794 typedef union cvmx_stxx_stat_bytes_hi cvmx_stxx_stat_bytes_hi_t;
797 * cvmx_stx#_stat_bytes_lo
799 union cvmx_stxx_stat_bytes_lo {
801 struct cvmx_stxx_stat_bytes_lo_s {
802 #ifdef __BIG_ENDIAN_BITFIELD
803 uint64_t reserved_32_63 : 32;
804 uint64_t cnt : 32; /**< Number of bytes sent (CNT[31:0]) */
807 uint64_t reserved_32_63 : 32;
810 struct cvmx_stxx_stat_bytes_lo_s cn38xx;
811 struct cvmx_stxx_stat_bytes_lo_s cn38xxp2;
812 struct cvmx_stxx_stat_bytes_lo_s cn58xx;
813 struct cvmx_stxx_stat_bytes_lo_s cn58xxp1;
815 typedef union cvmx_stxx_stat_bytes_lo cvmx_stxx_stat_bytes_lo_t;
820 union cvmx_stxx_stat_ctl {
822 struct cvmx_stxx_stat_ctl_s {
823 #ifdef __BIG_ENDIAN_BITFIELD
824 uint64_t reserved_5_63 : 59;
825 uint64_t clr : 1; /**< Clear all statistics counters
828 - STX_STAT_BYTES_LO */
829 uint64_t bckprs : 4; /**< The selected port for STX_BCKPRS_CNT */
833 uint64_t reserved_5_63 : 59;
836 struct cvmx_stxx_stat_ctl_s cn38xx;
837 struct cvmx_stxx_stat_ctl_s cn38xxp2;
838 struct cvmx_stxx_stat_ctl_s cn58xx;
839 struct cvmx_stxx_stat_ctl_s cn58xxp1;
841 typedef union cvmx_stxx_stat_ctl cvmx_stxx_stat_ctl_t;
844 * cvmx_stx#_stat_pkt_xmt
846 union cvmx_stxx_stat_pkt_xmt {
848 struct cvmx_stxx_stat_pkt_xmt_s {
849 #ifdef __BIG_ENDIAN_BITFIELD
850 uint64_t reserved_32_63 : 32;
851 uint64_t cnt : 32; /**< Number of packets sent */
854 uint64_t reserved_32_63 : 32;
857 struct cvmx_stxx_stat_pkt_xmt_s cn38xx;
858 struct cvmx_stxx_stat_pkt_xmt_s cn38xxp2;
859 struct cvmx_stxx_stat_pkt_xmt_s cn58xx;
860 struct cvmx_stxx_stat_pkt_xmt_s cn58xxp1;
862 typedef union cvmx_stxx_stat_pkt_xmt cvmx_stxx_stat_pkt_xmt_t;