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49 * Support library for the hardware work queue timers.
51 * <hr>$Revision: 70030 $<hr>
53 #include "executive-config.h"
54 #include "cvmx-config.h"
56 #include "cvmx-sysinfo.h"
58 #include "cvmx-bootmem.h"
60 /* CSR typedefs have been moved to cvmx-tim-defs.h */
63 * Global structure holding the state of all timers.
65 CVMX_SHARED cvmx_tim_t cvmx_tim;
68 #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
70 * Setup a timer for use. Must be called before the timer
73 * @param tick Time between each bucket in microseconds. This must not be
74 * smaller than 1024/(clock frequency in MHz).
75 * @param max_ticks The maximum number of ticks the timer must be able
76 * to schedule in the future. There are guaranteed to be enough
77 * timer buckets such that:
78 * number of buckets >= max_ticks.
79 * @return Zero on success. Negative on error. Failures are possible
80 * if the number of buckets needed is too large or memory
81 * allocation fails for creating the buckets.
83 int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
87 uint64_t tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM);
89 uint64_t hw_tick_ns_allowed;
90 uint64_t tick_ns = 1000 * tick;
95 /* for the simulator */
96 if (tim_clock_hz == 0)
97 tim_clock_hz = 800000000;
99 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
101 cvmx_tim_fr_rn_tt_t fr_tt;
102 fr_tt.u64 = cvmx_read_csr(CVMX_TIM_FR_RN_TT);
103 timer_thr = fr_tt.s.fr_rn_tt;
106 hw_tick_ns = timer_thr * 1000000000ull / tim_clock_hz;
108 * Double the minimal allowed tick to 2 * HW tick. tick between
109 * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval
110 * to zero, or 1024 cycles. This is not enough time for the timer unit
111 * to fetch the bucket data, Resulting in timer ring error interrupt
112 * be always generated. Avoid such setting in software.
114 hw_tick_ns_allowed = hw_tick_ns * 2;
116 /* Make sure the timers are stopped */
119 /* Reinitialize out timer state */
120 memset(&cvmx_tim, 0, sizeof(cvmx_tim));
122 if (tick_ns < hw_tick_ns_allowed)
124 cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than"
125 " the minimal ticks allowed by hardware %lu(ns)\n",
126 tick_ns, hw_tick_ns_allowed);
129 else if (tick_ns > 4194304 * hw_tick_ns)
131 cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than"
132 " the max ticks %lu(ns)\n", tick_ns, hw_tick_ns);
138 if (tick_ns < (hw_tick_ns << i))
142 cvmx_tim.max_ticks = (uint32_t)max_ticks;
143 cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10);
144 cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000;
146 temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift;
148 /* round up to nearest power of 2 */
150 temp = temp | (temp >> 1);
151 temp = temp | (temp >> 2);
152 temp = temp | (temp >> 4);
153 temp = temp | (temp >> 8);
154 temp = temp | (temp >> 16);
155 cvmx_tim.num_buckets = temp + 1;
157 /* ensure input params fall into permitted ranges */
158 if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576)
160 cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n");
164 /* Allocate the timer buckets from hardware addressable memory */
165 cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets
166 * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE);
167 if (cvmx_tim.bucket == NULL)
169 cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n");
172 memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t));
174 cvmx_tim.start_time = 0;
176 /* Loop through all timers */
177 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
179 int interval = ((1 << (cvmx_tim.bucket_shift - 10)) - 1);
180 cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets;
181 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
183 cvmx_tim_ringx_ctl0_t ring_ctl0;
184 cvmx_tim_ringx_ctl1_t ring_ctl1;
185 cvmx_tim_ringx_ctl2_t ring_ctl2;
186 cvmx_tim_reg_flags_t reg_flags;
188 /* Tell the hardware where about the bucket array */
190 ring_ctl2.s.csize = CVMX_FPA_TIMER_POOL_SIZE / 8;
191 ring_ctl2.s.base = cvmx_ptr_to_phys(bucket) >> 5;
192 cvmx_write_csr(CVMX_TIM_RINGX_CTL2(timer_id), ring_ctl2.u64);
194 reg_flags.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
196 ring_ctl1.s.cpool = ((reg_flags.s.ena_dfb == 0) ? CVMX_FPA_TIMER_POOL : 0);
197 ring_ctl1.s.bsize = cvmx_tim.num_buckets - 1;
198 cvmx_write_csr(CVMX_TIM_RINGX_CTL1(timer_id), ring_ctl1.u64);
201 ring_ctl0.s.timercount = interval + timer_id * interval / CVMX_TIM_NUM_TIMERS;
202 cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64);
204 ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id));
206 ring_ctl0.s.interval = interval;
207 cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64);
208 ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id));
212 cvmx_tim_mem_ring0_t config_ring0;
213 cvmx_tim_mem_ring1_t config_ring1;
214 /* Tell the hardware where about the bucket array */
215 config_ring0.u64 = 0;
216 config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
217 config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
218 config_ring0.s.ring = timer_id;
219 cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
221 /* Tell the hardware the size of each chunk block in pointers */
222 config_ring1.u64 = 0;
223 config_ring1.s.enable = 1;
224 config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
225 config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
226 config_ring1.s.interval = interval;
227 config_ring1.s.ring = timer_id;
228 cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
237 * Start the hardware timer processing
239 void cvmx_tim_start(void)
241 cvmx_tim_control_t control;
243 control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
244 control.s.enable_dwb = 1;
245 control.s.enable_timers = 1;
247 /* Remember when we started the timers */
248 cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM);
249 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
254 * Stop the hardware timer processing. Timers stay configured.
256 void cvmx_tim_stop(void)
258 cvmx_tim_control_t control;
259 control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
260 control.s.enable_dwb = 0;
261 control.s.enable_timers = 0;
262 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
267 * Stop the timer. After this the timer must be setup again
270 #ifdef CVMX_ENABLE_TIMER_FUNCTIONS
271 void cvmx_tim_shutdown(void)
275 uint64_t entries_per_chunk;
277 /* Make sure the timers are stopped */
280 entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1;
282 /* Now walk all buckets freeing the chunks */
283 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
285 for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++)
288 uint64_t next_chunk_addr;
289 cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket;
290 CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */
292 /* Each bucket contains a list of chunks */
293 chunk_addr = bucket_ptr->first_chunk_addr;
294 while (bucket_ptr->num_entries)
297 cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr));
299 /* Read next chunk pointer from end of the current chunk */
300 next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8));
302 cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0);
303 chunk_addr = next_chunk_addr;
304 if (bucket_ptr->num_entries > entries_per_chunk)
305 bucket_ptr->num_entries -= entries_per_chunk;
307 bucket_ptr->num_entries = 0;