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168 * Copyright (c) 2003-2007, Cavium Networks. All rights reserved.
172 * OCTEON SDK License Type 4:
174 * Author: Cavium Networks
176 * Contact: support@caviumnetworks.com
177 * This file is part of the OCTEON SDK
179 * Copyright (c) 2007 Cavium Networks
181 * This file is free software; you can redistribute it and/or modify
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190 * the Free Software Foundation.
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197 * This file may also be available under a different license from Cavium.
198 * Contact Cavium Networks for more information
199 ***********************license end**************************************/
203 * This code is an example of using twsi core in raw mode, bypasing High
204 * Level Controller (HLC). It is recommended to use HLC if only possible as
205 * it is more efficient and robust mechanism.
206 * The example code shows use of twsi for generating long (more that 8 bytes HLC limit)
207 * read - write transactions using 7-bit addressing. Different types of
208 * transactions can be generated if needed. Make sure that commands written to twsi core
209 * follow core state transitions outlinged in OCTEON documentation. The core state is
210 * reported in stat register after the command colpletion. In each state core will accept
211 * only the allowed commands.
216 #include <cvmx-csr-typedefs.h>
217 #include "cvmx-twsi-raw.h"
220 * uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
221 * twsi core register read
222 * twsi_id - twsi core index
223 * reg 0 - 8-bit register
224 * returns 8-bit register contetn
226 uint8_t cvmx_twsix_read_ctr(int twsi_id, uint8_t reg)
228 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
232 sw_twsi_val.s.op = 6;
233 sw_twsi_val.s.eop_ia = reg;
235 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
236 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
238 return sw_twsi_val.s.d ;
242 * uint8_t cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
244 * twsi core register write
245 * twsi_id - twsi core index
246 * reg 0 - 8-bit register
247 * data - data to write
251 int cvmx_twsix_write_ctr(int twsi_id, uint8_t reg, uint8_t data)
253 cvmx_mio_twsx_sw_twsi_t sw_twsi_val;
257 sw_twsi_val.s.op = 6;
258 sw_twsi_val.s.eop_ia = reg;
259 sw_twsi_val.s.d = data;
260 cvmx_write_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id), sw_twsi_val.u64);
261 while (((cvmx_mio_twsx_sw_twsi_t)(sw_twsi_val.u64 = cvmx_read_csr(CVMX_MIO_TWSX_SW_TWSI(twsi_id)))).s.v)
268 * cvmx_twsi_wait_iflg(int twsi_id)
269 * cvmx_twsi_wait_stop(int twsi_id)
272 * Busy wait for interrupt flag or stop bit on control register. This implementation is for OS-less
273 * application. With OS services available it could be implemented with semaphore
274 * block and interrupt wake up.
275 * TWSI_WAIT for loop must be defined large enough to allow on-wire transaction to finish - that is
276 * about 10 twsi clocks
278 #define TWSI_WAIT 10000000
279 static inline int cvmx_twsi_wait_iflg(int twsi_id)
281 octeon_twsi_ctl_t ctl_reg;
282 int wait = TWSI_WAIT;
284 ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
285 } while((ctl_reg.s.iflg ==0) && (wait-- >0));
286 if(wait == 0) return -1;
290 static inline int cvmx_twsi_wait_stop(int twsi_id)
292 octeon_twsi_ctl_t ctl_reg;
293 int wait = TWSI_WAIT;
295 ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
296 } while((ctl_reg.s.stp ==1) && (wait-- >0));
297 if(wait == 0) return -1;
303 * uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
304 * uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
306 * helper functions - read or write byte to data reg and reads the TWSI core status
308 static uint8_t octeon_twsi_read_byte(int twsi_id, uint8_t* byte, int ack)
310 octeon_twsi_ctl_t ctl_reg;
311 octeon_twsi_data_t data;
312 octeon_twsi_stat_t stat;
314 /* clear interrupt flag, set aak for requested ACK signal level */
316 ctl_reg.s.aak = (ack==0) ?0:1;
318 cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
320 /* wait for twsi_ctl[iflg] to be set */
321 if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
324 data.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_DATA_REG);
327 /* read the status */
328 stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
332 static uint8_t octeon_twsi_write_byte(int twsi_id, uint8_t byte)
334 octeon_twsi_ctl_t ctl_reg;
335 octeon_twsi_data_t data;
336 octeon_twsi_stat_t stat;
338 /* tx data byte - write to twsi_data reg, then clear twsi_ctl[iflg] */
340 cvmx_twsix_write_ctr(twsi_id, TWSI_DATA_REG, data.u8);
342 ctl_reg.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
344 cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
346 /* wait for twsi_ctl[iflg] to be set */
347 if(cvmx_twsi_wait_iflg(twsi_id)) goto error;
349 /* read the status */
350 stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
355 * int octeon_i2c_xfer_msg_raw(struct i2c_msg *msg)
357 * Send (read or write) a message with 7-bit address device over direct control of
358 * TWSI core, bypassind HLC. Will try to finish the transaction on failure, so core state
359 * expected to be idle with HLC enabled on exit.
361 * dev - TWSI controller index (0 for cores with single controler)
362 * msg - message to transfer
363 * returns 0 on success, TWSI core state on error. Will try to finish the transaction on failure, so core state expected to be idle
365 int octeon_i2c_xfer_msg_raw(int twsi_id, struct i2c_msg *msg)
368 octeon_twsi_ctl_t ctl_reg;
369 octeon_twsi_addr_t addr;
370 octeon_twsi_stat_t stat;
371 int is_read = msg->flags & I2C_M_RD;
374 /* check the core state, quit if not idle */
375 stat.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
376 if(stat.s.stat != TWSI_IDLE) {
377 msg->len =0; return stat.s.stat;
380 /* first send start - set twsi_ctl[sta] to 1 */
385 cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
386 /* wait for twsi_ctl[iflg] to be set */
387 if(cvmx_twsi_wait_iflg(twsi_id)) goto stop;
389 /* Write 7-bit addr to twsi_data; set read bit */
390 addr.s.slave_addr7 = msg->addr;
391 if(is_read) addr.s.r =1;
393 stat.s.stat =octeon_twsi_write_byte(twsi_id, addr.u8);
397 /* any status but ACK_RXED means failure - we try to send stop and go idle */
398 if(!(stat.s.stat == TWSI_ADDR_R_TX_ACK_RXED)) {
403 /* We read data from the buffer and send ACK back.
404 The last byte we read with negative ACK */
405 for(i =0; i<msg->len-1; i++)
407 stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 1);
408 if(stat.s.stat != TWSI_DATA_RX_ACK_TXED)
411 /* last read we send negACK */
412 stat.s.stat =octeon_twsi_read_byte(twsi_id, &msg->buf[i], 0);
413 if(stat.s.stat != TWSI_DATA_RX_NACK_TXED)
417 /* Data write loop */
419 /* any status but ACK_RXED means failure - we try to send stop and go idle */
420 if(stat.s.stat != TWSI_ADDR_W_TX_ACK_RXED) {
425 /* We write data to the buffer and check for ACK. */
426 for(i =0; i<msg->len; i++)
428 stat.s.stat =octeon_twsi_write_byte(twsi_id, msg->buf[i]);
429 if(stat.s.stat == TWSI_DATA_TX_NACK_RXED) {
430 /* Negative ACK means slave can not RX more */
434 else if(stat.s.stat != TWSI_DATA_TX_ACK_RXED) {
435 /* lost arbitration? try to send stop and go idle. This current byte likely was not written */
436 msg->len = (i-2) >0? (i-2):0;
443 ctl_reg.u8 =cvmx_twsix_read_ctr(twsi_id, TWSI_CTL_REG);
446 cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);
447 /* wait for twsi_ctl[stp] to clear */
448 cvmx_twsi_wait_stop(twsi_id);
450 stat.u8 = cvmx_twsix_read_ctr(twsi_id, TWSI_STAT_REG);
451 if(stat.s.stat == TWSI_IDLE)
453 /* Leave TWSI core with HLC eabled */
459 cvmx_twsix_write_ctr(twsi_id, TWSI_CTL_REG, ctl_reg.u8);