1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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11 * notice, this list of conditions and the following disclaimer.
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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38 ***********************license end**************************************/
46 #define CVMX_USE_1_TO_1_TLB_MAPPINGS 0
47 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
48 #include <linux/kernel.h>
49 #include <asm/octeon/cvmx.h>
50 #include <asm/octeon/cvmx-spinlock.h>
51 #include <asm/octeon/octeon-pci-console.h>
53 #define MIN(a,b) min((a),(b))
56 #include "cvmx-platform.h"
59 #include "cvmx-spinlock.h"
61 # define MIN(a,b) (((a)<(b))?(a):(b))
64 #include "cvmx-bootmem.h"
65 #include "octeon-pci-console.h"
71 #if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
72 #include "octeon-pci.h"
76 /* The following code is only used in standalone CVMX applications. It does
77 not apply for kernel or Linux programming */
78 #if defined(OCTEON_TARGET) && !defined(__linux__) && !defined(CVMX_BUILD_FOR_LINUX_KERNEL)
80 static int cvmx_pci_console_num = 0;
81 static int per_core_pci_consoles = 0;
82 static uint64_t pci_console_desc_addr = 0;
83 /* This function for simple executive internal use only - do not use in any application */
84 int __cvmx_pci_console_write (int fd, char *buf, int nbytes)
89 console_num = fd & 0xFFFF;
91 else if (per_core_pci_consoles)
93 console_num = cvmx_get_core_num();
96 console_num = cvmx_pci_console_num;
98 if (!pci_console_desc_addr)
100 const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
101 pci_console_desc_addr = block_desc->base_addr;
105 return octeon_pci_console_write(pci_console_desc_addr, console_num, buf, nbytes, 0);
112 #if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE)))
113 static int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
115 if (rd_idx >= buffer_size || wr_idx >= buffer_size)
118 return (((buffer_size -1) - (wr_idx - rd_idx))%buffer_size);
120 static int octeon_pci_console_buffer_avail_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
122 if (rd_idx >= buffer_size || wr_idx >= buffer_size)
125 return (buffer_size - 1 - octeon_pci_console_buffer_free_bytes(buffer_size, wr_idx, rd_idx));
131 /* The following code is only used under Linux userspace when you are using
133 #if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
134 int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags)
136 if (!console_desc_addr)
139 /* Get global pci console information and look up specific console structure. */
140 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
141 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
142 if (console_num >= num_consoles)
144 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
147 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
148 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
150 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
151 /* Check to see if any data is available */
152 uint32_t rd_idx, wr_idx;
155 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
156 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
157 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
159 // printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
160 int bytes_to_write = octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
161 if (bytes_to_write <= 0)
162 return bytes_to_write;
163 bytes_to_write = MIN(bytes_to_write, write_reqest_size);
164 /* Check to see if what we want to write is not contiguous, and limit ourselves to the contiguous block*/
165 if (wr_idx + bytes_to_write >= console_buffer_size)
166 bytes_to_write = console_buffer_size - wr_idx;
168 // printf("Attempting to write %d bytes, (buf size: %d)\n", bytes_to_write, write_reqest_size);
170 octeon_pci_write_mem(base_addr + wr_idx, buffer, bytes_to_write, OCTEON_PCI_ENDIAN_64BIT_SWAP);
171 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index), (wr_idx + bytes_to_write)%console_buffer_size);
173 return bytes_to_write;
177 int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags)
179 if (!console_desc_addr)
182 /* Get global pci console information and look up specific console structure. */
183 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
184 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
185 if (console_num >= num_consoles)
187 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
190 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
191 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
192 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
194 /* Check to see if any data is available */
195 uint32_t rd_idx, wr_idx;
198 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
199 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
200 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
202 // printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
203 int bytes_to_read = octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
204 if (bytes_to_read <= 0)
205 return bytes_to_read;
208 bytes_to_read = MIN(bytes_to_read, buf_size);
209 /* Check to see if what we want to read is not contiguous, and limit ourselves to the contiguous block*/
210 if (rd_idx + bytes_to_read >= console_buffer_size)
211 bytes_to_read = console_buffer_size - rd_idx;
214 octeon_pci_read_mem(buffer, base_addr + rd_idx, bytes_to_read,OCTEON_PCI_ENDIAN_64BIT_SWAP);
215 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index), (rd_idx + bytes_to_read)%console_buffer_size);
217 return bytes_to_read;
221 int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num)
223 if (!console_desc_addr)
226 /* Get global pci console information and look up specific console structure. */
227 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
228 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
229 if (console_num >= num_consoles)
231 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
234 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
235 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
237 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
238 /* Check to see if any data is available */
239 uint32_t rd_idx, wr_idx;
242 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
243 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
244 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
246 // printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
247 return octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
251 int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num)
253 if (!console_desc_addr)
256 /* Get global pci console information and look up specific console structure. */
257 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
258 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
259 if (console_num >= num_consoles)
261 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
264 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
265 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
266 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
268 /* Check to see if any data is available */
269 uint32_t rd_idx, wr_idx;
272 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
273 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
274 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
276 // printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
277 return octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
281 #endif /* TARGET_HOST */
288 /* This code is only available in a kernel or CVMX standalone. It can't be used
290 #if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE))) || defined(CVMX_BUILD_FOR_LINUX_KERNEL)
292 static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num)
294 octeon_pci_console_desc_t *cons_desc_ptr;
296 if (!console_desc_addr)
299 cons_desc_ptr = (octeon_pci_console_desc_t *)cvmx_phys_to_ptr(console_desc_addr);
300 if (console_num >= cons_desc_ptr->num_consoles)
303 return (octeon_pci_console_t *)cvmx_phys_to_ptr(cons_desc_ptr->console_addr_array[console_num]);
307 int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags)
309 octeon_pci_console_t *cons_ptr;
310 cvmx_spinlock_t *lock;
315 cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
319 lock = (cvmx_spinlock_t *)&cons_ptr->lock;
321 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
323 cvmx_spinlock_lock(lock);
324 while (bytes_to_write > 0)
326 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->output_write_index, cons_ptr->output_read_index);
327 // printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
328 if (bytes_available > 0)
330 int write_size = MIN(bytes_available, bytes_to_write);
331 /* Limit ourselves to what we can output in a contiguous block */
332 if (cons_ptr->output_write_index + write_size >= cons_ptr->buf_size)
333 write_size = cons_ptr->buf_size - cons_ptr->output_write_index;
335 memcpy(buf_ptr + cons_ptr->output_write_index, buffer + bytes_written, write_size);
336 CVMX_SYNCW; /* Make sure data is visible before changing write index */
337 cons_ptr->output_write_index = (cons_ptr->output_write_index + write_size)%cons_ptr->buf_size;
338 bytes_to_write -= write_size;
339 bytes_written += write_size;
341 else if (bytes_available == 0)
343 /* Check to see if we should wait for room, or return after a partial write */
344 if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
350 cvmx_wait(1000000); /* Delay if we are spinning */
360 cvmx_spinlock_unlock(lock);
361 return(bytes_written);
364 int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags)
368 cvmx_spinlock_t *lock;
371 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
375 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
377 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
378 if (bytes_available < 0)
379 return bytes_available;
381 lock = (cvmx_spinlock_t *)&cons_ptr->lock;
382 cvmx_spinlock_lock(lock);
384 if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK))
386 /* Wait for some data to be available */
387 while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index)))
397 // printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
399 /* Don't overflow the buffer passed to us */
400 read_size = MIN(bytes_available, buffer_size);
402 /* Limit ourselves to what we can input in a contiguous block */
403 if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
404 read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
406 memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
407 cons_ptr->input_read_index = (cons_ptr->input_read_index + read_size)%cons_ptr->buf_size;
408 bytes_read += read_size;
410 cvmx_spinlock_unlock(lock);
415 int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num)
418 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
422 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
423 if (bytes_available >= 0)
424 return(bytes_available);
430 int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num)
433 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
437 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
438 if (bytes_available >= 0)
439 return(bytes_available);
447 /* This code can only be used in the bootloader */
448 #if defined(CONFIG_OCTEON_U_BOOT) && (defined(CFG_PCI_CONSOLE) || defined(CONFIG_SYS_PCI_CONSOLE))
449 uint64_t octeon_pci_console_init(int num_consoles, int buffer_size)
451 octeon_pci_console_desc_t *cons_desc_ptr;
452 octeon_pci_console_t *cons_ptr;
454 /* Compute size required for pci console structure */
455 int alloc_size = num_consoles * (buffer_size * 2 + sizeof(octeon_pci_console_t) + sizeof(uint64_t)) + sizeof(octeon_pci_console_desc_t);
457 /* Allocate memory for the consoles. This must be in the range addresssible by the bootloader.
458 ** Try to do so in a manner which minimizes fragmentation. We try to put it at the top of DDR0 or bottom of
459 ** DDR2 first, and only do generic allocation if those fail */
460 int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR0_SIZE - alloc_size - 128, OCTEON_DDR0_SIZE, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
461 if (console_block_addr < 0)
462 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, OCTEON_DDR2_BASE + 1, OCTEON_DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
463 if (console_block_addr < 0)
464 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
465 if (console_block_addr < 0)
468 cons_desc_ptr = (void *)(uint32_t)console_block_addr;
470 memset(cons_desc_ptr, 0, alloc_size); /* Clear entire alloc'ed memory */
472 cons_desc_ptr->lock = 1; /* initialize as locked until we are done */
474 cons_desc_ptr->num_consoles = num_consoles;
475 cons_desc_ptr->flags = 0;
476 cons_desc_ptr->major_version = OCTEON_PCI_CONSOLE_MAJOR_VERSION;
477 cons_desc_ptr->minor_version = OCTEON_PCI_CONSOLE_MINOR_VERSION;
480 uint64_t avail_addr = console_block_addr + sizeof(octeon_pci_console_desc_t) + num_consoles * sizeof(uint64_t);
481 for (i = 0; i < num_consoles;i++)
483 cons_desc_ptr->console_addr_array[i] = avail_addr;
484 cons_ptr = (void *)(uint32_t)cons_desc_ptr->console_addr_array[i];
485 avail_addr += sizeof(octeon_pci_console_t);
486 cons_ptr->input_base_addr = avail_addr;
487 avail_addr += buffer_size;
488 cons_ptr->output_base_addr = avail_addr;
489 avail_addr += buffer_size;
490 cons_ptr->buf_size = buffer_size;
493 cons_desc_ptr->lock = 0;
495 return console_block_addr;