1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
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11 * notice, this list of conditions and the following disclaimer.
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14 * copyright notice, this list of conditions and the following
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16 * with the distribution.
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38 ***********************license end**************************************/
46 #define CVMX_USE_1_TO_1_TLB_MAPPINGS 0
47 #ifdef CVMX_BUILD_FOR_LINUX_KERNEL
48 #include <linux/kernel.h>
49 #include <asm/octeon/cvmx.h>
50 #include <asm/octeon/cvmx-spinlock.h>
51 #include <asm/octeon/octeon-pci-console.h>
53 #define MIN(a,b) min((a),(b))
56 #include "cvmx-platform.h"
59 #include "cvmx-spinlock.h"
60 #define MIN(a,b) (((a)<(b))?(a):(b))
62 #include "cvmx-bootmem.h"
63 #include "octeon-pci-console.h"
67 #if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
68 #include "octeon-pci.h"
72 /* The following code is only used in standalone CVMX applications. It does
73 not apply for kernel or Linux programming */
74 #if defined(OCTEON_TARGET) && !defined(__linux__)
76 static int cvmx_pci_console_num = 0;
77 static int per_core_pci_consoles = 0;
78 static uint64_t pci_console_desc_addr = 0;
79 /* This function for simple executive internal use only - do not use in any application */
80 int __cvmx_pci_console_write (int fd, char *buf, int nbytes)
85 console_num = fd & 0xFFFF;
87 else if (per_core_pci_consoles)
89 console_num = cvmx_get_core_num();
92 console_num = cvmx_pci_console_num;
94 if (!pci_console_desc_addr)
96 const cvmx_bootmem_named_block_desc_t *block_desc = cvmx_bootmem_find_named_block(OCTEON_PCI_CONSOLE_BLOCK_NAME);
97 pci_console_desc_addr = block_desc->base_addr;
101 return octeon_pci_console_write(pci_console_desc_addr, console_num, buf, nbytes, 0);
108 #if !defined(CONFIG_OCTEON_U_BOOT) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE))
109 int octeon_pci_console_buffer_free_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
111 if (rd_idx >= buffer_size || wr_idx >= buffer_size)
114 return (((buffer_size -1) - (wr_idx - rd_idx))%buffer_size);
116 int octeon_pci_console_buffer_avail_bytes(uint32_t buffer_size, uint32_t wr_idx, uint32_t rd_idx)
118 if (rd_idx >= buffer_size || wr_idx >= buffer_size)
121 return (buffer_size - 1 - octeon_pci_console_buffer_free_bytes(buffer_size, wr_idx, rd_idx));
127 /* The following code is only used under Linux userspace when you are using
129 #if defined(__linux__) && !defined(__KERNEL__) && !defined(OCTEON_TARGET)
130 int octeon_pci_console_host_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int write_reqest_size, uint32_t flags)
132 if (!console_desc_addr)
135 /* Get global pci console information and look up specific console structure. */
136 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
137 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
138 if (console_num >= num_consoles)
140 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
143 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
144 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
146 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
147 /* Check to see if any data is available */
148 uint32_t rd_idx, wr_idx;
151 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
152 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
153 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
155 // printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
156 int bytes_to_write = octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
157 if (bytes_to_write <= 0)
158 return bytes_to_write;
159 bytes_to_write = MIN(bytes_to_write, write_reqest_size);
160 /* Check to see if what we want to write is not contiguous, and limit ourselves to the contiguous block*/
161 if (wr_idx + bytes_to_write >= console_buffer_size)
162 bytes_to_write = console_buffer_size - wr_idx;
164 // printf("Attempting to write %d bytes, (buf size: %d)\n", bytes_to_write, write_reqest_size);
166 octeon_pci_write_mem(base_addr + wr_idx, buffer, bytes_to_write, OCTEON_PCI_ENDIAN_64BIT_SWAP);
167 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index), (wr_idx + bytes_to_write)%console_buffer_size);
169 return bytes_to_write;
173 int octeon_pci_console_host_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buf_size, uint32_t flags)
175 if (!console_desc_addr)
178 /* Get global pci console information and look up specific console structure. */
179 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
180 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
181 if (console_num >= num_consoles)
183 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
186 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
187 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
188 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
190 /* Check to see if any data is available */
191 uint32_t rd_idx, wr_idx;
194 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
195 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
196 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
198 // printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
199 int bytes_to_read = octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
200 if (bytes_to_read <= 0)
201 return bytes_to_read;
204 bytes_to_read = MIN(bytes_to_read, buf_size);
205 /* Check to see if what we want to read is not contiguous, and limit ourselves to the contiguous block*/
206 if (rd_idx + bytes_to_read >= console_buffer_size)
207 bytes_to_read = console_buffer_size - rd_idx;
210 octeon_pci_read_mem(buffer, base_addr + rd_idx, bytes_to_read,OCTEON_PCI_ENDIAN_64BIT_SWAP);
211 octeon_write_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index), (rd_idx + bytes_to_read)%console_buffer_size);
213 return bytes_to_read;
217 int octeon_pci_console_host_write_avail(uint64_t console_desc_addr, unsigned int console_num)
219 if (!console_desc_addr)
222 /* Get global pci console information and look up specific console structure. */
223 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
224 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
225 if (console_num >= num_consoles)
227 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
230 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
231 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
233 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
234 /* Check to see if any data is available */
235 uint32_t rd_idx, wr_idx;
238 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, input_base_addr));
239 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_read_index));
240 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, input_write_index));
242 // printf("Input base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
243 return octeon_pci_console_buffer_free_bytes(console_buffer_size, wr_idx, rd_idx);
247 int octeon_pci_console_host_read_avail(uint64_t console_desc_addr, unsigned int console_num)
249 if (!console_desc_addr)
252 /* Get global pci console information and look up specific console structure. */
253 uint32_t num_consoles = octeon_read_mem32(console_desc_addr + offsetof(octeon_pci_console_desc_t, num_consoles));
254 // printf("Num consoles: %d, buf size: %d\n", num_consoles, console_buffer_size);
255 if (console_num >= num_consoles)
257 printf("ERROR: attempting to read non-existant console: %d\n", console_num);
260 uint64_t console_addr = octeon_read_mem64(console_desc_addr + offsetof(octeon_pci_console_desc_t, console_addr_array) + console_num *8);
261 uint32_t console_buffer_size = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, buf_size));
262 // printf("Console %d is at 0x%llx\n", console_num, (long long)console_addr);
264 /* Check to see if any data is available */
265 uint32_t rd_idx, wr_idx;
268 base_addr = octeon_read_mem64(console_addr + offsetof(octeon_pci_console_t, output_base_addr));
269 rd_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_read_index));
270 wr_idx = octeon_read_mem32(console_addr + offsetof(octeon_pci_console_t, output_write_index));
272 // printf("Read buffer base: 0x%llx, rd: %d(0x%x), wr: %d(0x%x)\n", (long long)base_addr, rd_idx, rd_idx, wr_idx, wr_idx);
273 return octeon_pci_console_buffer_avail_bytes(console_buffer_size, wr_idx, rd_idx);
277 #endif /* TARGET_HOST */
284 /* This code is only available in a kernel or CVMX standalone. It can't be used
286 #if (!defined(CONFIG_OCTEON_U_BOOT) && (!defined(__linux__) || defined(__KERNEL__))) || (defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE))
288 static octeon_pci_console_t *octeon_pci_console_get_ptr(uint64_t console_desc_addr, unsigned int console_num)
290 octeon_pci_console_desc_t *cons_desc_ptr;
292 if (!console_desc_addr)
295 cons_desc_ptr = (octeon_pci_console_desc_t *)cvmx_phys_to_ptr(console_desc_addr);
296 if (console_num >= cons_desc_ptr->num_consoles)
299 return (octeon_pci_console_t *)cvmx_phys_to_ptr(cons_desc_ptr->console_addr_array[console_num]);
303 int octeon_pci_console_write(uint64_t console_desc_addr, unsigned int console_num, const char * buffer, int bytes_to_write, uint32_t flags)
305 octeon_pci_console_t *cons_ptr;
306 cvmx_spinlock_t *lock;
311 cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
315 lock = (cvmx_spinlock_t *)&cons_ptr->lock;
317 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
319 cvmx_spinlock_lock(lock);
320 while (bytes_to_write > 0)
322 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->output_write_index, cons_ptr->output_read_index);
323 // printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
324 if (bytes_available > 0)
326 int write_size = MIN(bytes_available, bytes_to_write);
327 /* Limit ourselves to what we can output in a contiguous block */
328 if (cons_ptr->output_write_index + write_size >= cons_ptr->buf_size)
329 write_size = cons_ptr->buf_size - cons_ptr->output_write_index;
331 memcpy(buf_ptr + cons_ptr->output_write_index, buffer + bytes_written, write_size);
332 CVMX_SYNCW; /* Make sure data is visible before changing write index */
333 cons_ptr->output_write_index = (cons_ptr->output_write_index + write_size)%cons_ptr->buf_size;
334 bytes_to_write -= write_size;
335 bytes_written += write_size;
337 else if (bytes_available == 0)
339 /* Check to see if we should wait for room, or return after a partial write */
340 if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
343 cvmx_wait(1000000); /* Delay if we are spinning */
353 cvmx_spinlock_unlock(lock);
354 return(bytes_written);
357 int octeon_pci_console_read(uint64_t console_desc_addr, unsigned int console_num, char * buffer, int buffer_size, uint32_t flags)
361 cvmx_spinlock_t *lock;
364 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
368 buf_ptr = (char*)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
370 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
371 if (bytes_available < 0)
372 return bytes_available;
374 lock = (cvmx_spinlock_t *)&cons_ptr->lock;
375 cvmx_spinlock_lock(lock);
377 if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK))
379 /* Wait for some data to be available */
380 while (0 == (bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index)))
385 // printf("Console %d has %d bytes available for writes\n", console_num, bytes_available);
387 /* Don't overflow the buffer passed to us */
388 read_size = MIN(bytes_available, buffer_size);
390 /* Limit ourselves to what we can input in a contiguous block */
391 if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
392 read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
394 memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
395 cons_ptr->input_read_index = (cons_ptr->input_read_index + read_size)%cons_ptr->buf_size;
396 bytes_read += read_size;
398 cvmx_spinlock_unlock(lock);
403 int octeon_pci_console_write_avail(uint64_t console_desc_addr, unsigned int console_num)
406 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
410 bytes_available = octeon_pci_console_buffer_free_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
411 if (bytes_available >= 0)
412 return(bytes_available);
418 int octeon_pci_console_read_avail(uint64_t console_desc_addr, unsigned int console_num)
421 octeon_pci_console_t *cons_ptr = octeon_pci_console_get_ptr(console_desc_addr, console_num);
425 bytes_available = octeon_pci_console_buffer_avail_bytes(cons_ptr->buf_size, cons_ptr->input_write_index, cons_ptr->input_read_index);
426 if (bytes_available >= 0)
427 return(bytes_available);
435 /* This code can only be used in the bootloader */
436 #if defined(CONFIG_OCTEON_U_BOOT) && defined(CFG_PCI_CONSOLE)
437 #define DDR0_TOP 0x10000000
438 #define DDR2_BASE 0x20000000
439 uint64_t octeon_pci_console_init(int num_consoles, int buffer_size)
441 octeon_pci_console_desc_t *cons_desc_ptr;
442 octeon_pci_console_t *cons_ptr;
444 /* Compute size required for pci console structure */
445 int alloc_size = num_consoles * (buffer_size * 2 + sizeof(octeon_pci_console_t) + sizeof(uint64_t)) + sizeof(octeon_pci_console_desc_t);
447 /* Allocate memory for the consoles. This must be in the range addresssible by the bootloader.
448 ** Try to do so in a manner which minimizes fragmentation. We try to put it at the top of DDR0 or bottom of
449 ** DDR2 first, and only do generic allocation if those fail */
450 int64_t console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR0_TOP - alloc_size - 128, DDR0_TOP, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
451 if (console_block_addr < 0)
452 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, DDR2_BASE + 1, DDR2_BASE + alloc_size + 128, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
453 if (console_block_addr < 0)
454 console_block_addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0, 0x7fffffff, 128, OCTEON_PCI_CONSOLE_BLOCK_NAME, CVMX_BOOTMEM_FLAG_END_ALLOC);
455 if (console_block_addr < 0)
458 cons_desc_ptr = (void *)(uint32_t)console_block_addr;
460 memset(cons_desc_ptr, 0, alloc_size); /* Clear entire alloc'ed memory */
462 cons_desc_ptr->lock = 1; /* initialize as locked until we are done */
464 cons_desc_ptr->num_consoles = num_consoles;
465 cons_desc_ptr->flags = 0;
466 cons_desc_ptr->major_version = OCTEON_PCI_CONSOLE_MAJOR_VERSION;
467 cons_desc_ptr->minor_version = OCTEON_PCI_CONSOLE_MINOR_VERSION;
470 uint64_t avail_addr = console_block_addr + sizeof(octeon_pci_console_desc_t) + num_consoles * sizeof(uint64_t);
471 for (i = 0; i < num_consoles;i++)
473 cons_desc_ptr->console_addr_array[i] = avail_addr;
474 cons_ptr = (void *)(uint32_t)cons_desc_ptr->console_addr_array[i];
475 avail_addr += sizeof(octeon_pci_console_t);
476 cons_ptr->input_base_addr = avail_addr;
477 avail_addr += buffer_size;
478 cons_ptr->output_base_addr = avail_addr;
479 avail_addr += buffer_size;
480 cons_ptr->buf_size = buffer_size;
483 cons_desc_ptr->lock = 0;
485 return console_block_addr;