2 * Copyright (c) 2005-2008 Pawel Jakub Dawidek <pjd@FreeBSD.org>
3 * Copyright (c) 2010 Konstantin Belousov <kib@FreeBSD.org>
4 * Copyright (c) 2014 The FreeBSD Foundation
5 * Copyright (c) 2017 Conrad Meyer <cem@FreeBSD.org>
8 * Portions of this software were developed by John-Mark Gurney
9 * under sponsorship of the FreeBSD Foundation and
10 * Rubicon Communications, LLC (Netgate).
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/kernel.h>
41 #include <sys/libkern.h>
43 #include <sys/module.h>
44 #include <sys/malloc.h>
45 #include <sys/rwlock.h>
51 #include <crypto/aesni/aesni.h>
52 #include <crypto/aesni/sha_sse.h>
53 #include <crypto/sha1.h>
54 #include <crypto/sha2/sha256.h>
56 #include <opencrypto/cryptodev.h>
57 #include <opencrypto/gmac.h>
58 #include <cryptodev_if.h>
60 #include <machine/md_var.h>
61 #include <machine/specialreg.h>
63 #include <machine/npx.h>
64 #elif defined(__amd64__)
65 #include <machine/fpu.h>
68 static struct mtx_padalign *ctx_mtx;
69 static struct fpu_kern_ctx **ctx_fpu;
77 TAILQ_HEAD(aesni_sessions_head, aesni_session) sessions;
81 #define ACQUIRE_CTX(i, ctx) \
83 (i) = PCPU_GET(cpuid); \
84 mtx_lock(&ctx_mtx[(i)]); \
85 (ctx) = ctx_fpu[(i)]; \
87 #define RELEASE_CTX(i, ctx) \
89 mtx_unlock(&ctx_mtx[(i)]); \
94 static int aesni_newsession(device_t, uint32_t *sidp, struct cryptoini *cri);
95 static int aesni_freesession(device_t, uint64_t tid);
96 static void aesni_freesession_locked(struct aesni_softc *sc,
97 struct aesni_session *ses);
98 static int aesni_cipher_setup(struct aesni_session *ses,
99 struct cryptoini *encini, struct cryptoini *authini);
100 static int aesni_cipher_process(struct aesni_session *ses,
101 struct cryptodesc *enccrd, struct cryptodesc *authcrd, struct cryptop *crp);
102 static int aesni_cipher_crypt(struct aesni_session *ses,
103 struct cryptodesc *enccrd, struct cryptodesc *authcrd, struct cryptop *crp);
104 static int aesni_cipher_mac(struct aesni_session *ses, struct cryptodesc *crd,
105 struct cryptop *crp);
107 MALLOC_DEFINE(M_AESNI, "aesni_data", "AESNI Data");
110 aesni_identify(driver_t *drv, device_t parent)
113 /* NB: order 10 is so we get attached after h/w devices */
114 if (device_find_child(parent, "aesni", -1) == NULL &&
115 BUS_ADD_CHILD(parent, 10, "aesni", -1) == 0)
116 panic("aesni: could not attach");
120 detect_cpu_features(bool *has_aes, bool *has_sha)
123 *has_aes = ((cpu_feature2 & CPUID2_AESNI) != 0 &&
124 (cpu_feature2 & CPUID2_SSE41) != 0);
125 *has_sha = ((cpu_stdext_feature & CPUID_STDEXT_SHA) != 0 &&
126 (cpu_feature2 & CPUID2_SSSE3) != 0);
130 aesni_probe(device_t dev)
132 bool has_aes, has_sha;
134 detect_cpu_features(&has_aes, &has_sha);
135 if (!has_aes && !has_sha) {
136 device_printf(dev, "No AES or SHA support.\n");
138 } else if (has_aes && has_sha)
140 "AES-CBC,AES-XTS,AES-GCM,AES-ICM,SHA1,SHA256");
142 device_set_desc(dev, "AES-CBC,AES-XTS,AES-GCM,AES-ICM");
144 device_set_desc(dev, "SHA1,SHA256");
154 /* XXX - no way to return driverid */
156 if (ctx_fpu[i] != NULL) {
157 mtx_destroy(&ctx_mtx[i]);
158 fpu_kern_free_ctx(ctx_fpu[i]);
162 free(ctx_mtx, M_AESNI);
164 free(ctx_fpu, M_AESNI);
169 aesni_attach(device_t dev)
171 struct aesni_softc *sc;
174 sc = device_get_softc(dev);
176 TAILQ_INIT(&sc->sessions);
179 sc->cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE |
182 device_printf(dev, "Could not get crypto driver id.\n");
186 ctx_mtx = malloc(sizeof *ctx_mtx * (mp_maxid + 1), M_AESNI,
188 ctx_fpu = malloc(sizeof *ctx_fpu * (mp_maxid + 1), M_AESNI,
192 ctx_fpu[i] = fpu_kern_alloc_ctx(0);
193 mtx_init(&ctx_mtx[i], "anifpumtx", NULL, MTX_DEF|MTX_NEW);
196 rw_init(&sc->lock, "aesni_lock");
198 detect_cpu_features(&sc->has_aes, &sc->has_sha);
200 crypto_register(sc->cid, CRYPTO_AES_CBC, 0, 0);
201 crypto_register(sc->cid, CRYPTO_AES_ICM, 0, 0);
202 crypto_register(sc->cid, CRYPTO_AES_NIST_GCM_16, 0, 0);
203 crypto_register(sc->cid, CRYPTO_AES_128_NIST_GMAC, 0, 0);
204 crypto_register(sc->cid, CRYPTO_AES_192_NIST_GMAC, 0, 0);
205 crypto_register(sc->cid, CRYPTO_AES_256_NIST_GMAC, 0, 0);
206 crypto_register(sc->cid, CRYPTO_AES_XTS, 0, 0);
209 crypto_register(sc->cid, CRYPTO_SHA1, 0, 0);
210 crypto_register(sc->cid, CRYPTO_SHA1_HMAC, 0, 0);
211 crypto_register(sc->cid, CRYPTO_SHA2_256_HMAC, 0, 0);
217 aesni_detach(device_t dev)
219 struct aesni_softc *sc;
220 struct aesni_session *ses;
222 sc = device_get_softc(dev);
225 TAILQ_FOREACH(ses, &sc->sessions, next) {
227 rw_wunlock(&sc->lock);
229 "Cannot detach, sessions still active.\n");
234 while ((ses = TAILQ_FIRST(&sc->sessions)) != NULL) {
235 TAILQ_REMOVE(&sc->sessions, ses, next);
238 rw_wunlock(&sc->lock);
239 crypto_unregister_all(sc->cid);
241 rw_destroy(&sc->lock);
249 aesni_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri)
251 struct aesni_softc *sc;
252 struct aesni_session *ses;
253 struct cryptoini *encini, *authini;
257 if (sidp == NULL || cri == NULL) {
258 CRYPTDEB("no sidp or cri");
262 sc = device_get_softc(dev);
271 for (; cri != NULL; cri = cri->cri_next) {
272 switch (cri->cri_alg) {
273 case CRYPTO_AES_NIST_GCM_16:
281 if (encini != NULL) {
282 CRYPTDEB("encini already set");
287 case CRYPTO_AES_128_NIST_GMAC:
288 case CRYPTO_AES_192_NIST_GMAC:
289 case CRYPTO_AES_256_NIST_GMAC:
291 * nothing to do here, maybe in the future cache some
297 case CRYPTO_SHA1_HMAC:
298 case CRYPTO_SHA2_256_HMAC:
301 if (authini != NULL) {
302 CRYPTDEB("authini already set");
309 CRYPTDEB("unhandled algorithm");
313 if (encini == NULL && authini == NULL) {
314 CRYPTDEB("no cipher");
318 * GMAC algorithms are only supported with simultaneous GCM. Likewise
319 * GCM is not supported without GMAC.
326 rw_wunlock(&sc->lock);
330 * Free sessions goes first, so if first session is used, we need to
333 ses = TAILQ_FIRST(&sc->sessions);
334 if (ses == NULL || ses->used) {
335 ses = malloc(sizeof(*ses), M_AESNI, M_NOWAIT | M_ZERO);
337 rw_wunlock(&sc->lock);
342 TAILQ_REMOVE(&sc->sessions, ses, next);
345 TAILQ_INSERT_TAIL(&sc->sessions, ses, next);
346 rw_wunlock(&sc->lock);
349 ses->algo = encini->cri_alg;
351 ses->auth_algo = authini->cri_alg;
353 error = aesni_cipher_setup(ses, encini, authini);
355 CRYPTDEB("setup failed");
357 aesni_freesession_locked(sc, ses);
358 rw_wunlock(&sc->lock);
367 aesni_freesession_locked(struct aesni_softc *sc, struct aesni_session *ses)
371 rw_assert(&sc->lock, RA_WLOCKED);
374 TAILQ_REMOVE(&sc->sessions, ses, next);
375 explicit_bzero(ses, sizeof(*ses));
377 TAILQ_INSERT_HEAD(&sc->sessions, ses, next);
381 aesni_freesession(device_t dev, uint64_t tid)
383 struct aesni_softc *sc;
384 struct aesni_session *ses;
387 sc = device_get_softc(dev);
388 sid = ((uint32_t)tid) & 0xffffffff;
390 TAILQ_FOREACH_REVERSE(ses, &sc->sessions, aesni_sessions_head, next) {
395 rw_wunlock(&sc->lock);
398 aesni_freesession_locked(sc, ses);
399 rw_wunlock(&sc->lock);
404 aesni_process(device_t dev, struct cryptop *crp, int hint __unused)
406 struct aesni_softc *sc = device_get_softc(dev);
407 struct aesni_session *ses = NULL;
408 struct cryptodesc *crd, *enccrd, *authcrd;
420 if (crp->crp_callback == NULL || crp->crp_desc == NULL) {
425 for (crd = crp->crp_desc; crd != NULL; crd = crd->crd_next) {
426 switch (crd->crd_alg) {
427 case CRYPTO_AES_NIST_GCM_16:
433 if (enccrd != NULL) {
440 case CRYPTO_AES_128_NIST_GMAC:
441 case CRYPTO_AES_192_NIST_GMAC:
442 case CRYPTO_AES_256_NIST_GMAC:
444 case CRYPTO_SHA1_HMAC:
445 case CRYPTO_SHA2_256_HMAC:
446 if (authcrd != NULL) {
459 if ((enccrd == NULL && authcrd == NULL) ||
460 (needauth && authcrd == NULL)) {
465 /* CBC & XTS can only handle full blocks for now */
466 if (enccrd != NULL && (enccrd->crd_alg == CRYPTO_AES_CBC ||
467 enccrd->crd_alg == CRYPTO_AES_XTS) &&
468 (enccrd->crd_len % AES_BLOCK_LEN) != 0) {
474 TAILQ_FOREACH_REVERSE(ses, &sc->sessions, aesni_sessions_head, next) {
475 if (ses->id == (crp->crp_sid & 0xffffffff))
478 rw_runlock(&sc->lock);
484 error = aesni_cipher_process(ses, enccrd, authcrd, crp);
489 crp->crp_etype = error;
495 aesni_cipher_alloc(struct cryptodesc *enccrd, struct cryptop *crp,
503 if (crp->crp_flags & CRYPTO_F_IMBUF) {
504 m = (struct mbuf *)crp->crp_buf;
505 if (m->m_next != NULL)
507 addr = mtod(m, uint8_t *);
508 } else if (crp->crp_flags & CRYPTO_F_IOV) {
509 uio = (struct uio *)crp->crp_buf;
510 if (uio->uio_iovcnt != 1)
513 addr = (uint8_t *)iov->iov_base;
515 addr = (uint8_t *)crp->crp_buf;
517 addr += enccrd->crd_skip;
521 addr = malloc(enccrd->crd_len, M_AESNI, M_NOWAIT);
524 crypto_copydata(crp->crp_flags, crp->crp_buf, enccrd->crd_skip,
525 enccrd->crd_len, addr);
531 static device_method_t aesni_methods[] = {
532 DEVMETHOD(device_identify, aesni_identify),
533 DEVMETHOD(device_probe, aesni_probe),
534 DEVMETHOD(device_attach, aesni_attach),
535 DEVMETHOD(device_detach, aesni_detach),
537 DEVMETHOD(cryptodev_newsession, aesni_newsession),
538 DEVMETHOD(cryptodev_freesession, aesni_freesession),
539 DEVMETHOD(cryptodev_process, aesni_process),
544 static driver_t aesni_driver = {
547 sizeof(struct aesni_softc),
549 static devclass_t aesni_devclass;
551 DRIVER_MODULE(aesni, nexus, aesni_driver, aesni_devclass, 0, 0);
552 MODULE_VERSION(aesni, 1);
553 MODULE_DEPEND(aesni, crypto, 1, 1, 1);
556 aesni_cipher_setup(struct aesni_session *ses, struct cryptoini *encini,
557 struct cryptoini *authini)
559 struct fpu_kern_ctx *ctx;
560 int kt, ctxidx, keylen, error;
562 switch (ses->auth_algo) {
564 case CRYPTO_SHA1_HMAC:
565 case CRYPTO_SHA2_256_HMAC:
566 if (authini->cri_klen % 8 != 0)
568 keylen = authini->cri_klen / 8;
569 if (keylen > sizeof(ses->hmac_key))
571 if (ses->auth_algo == CRYPTO_SHA1 && keylen > 0)
573 memcpy(ses->hmac_key, authini->cri_key, keylen);
574 ses->mlen = authini->cri_mlen;
577 kt = is_fpu_kern_thread(0) || (encini == NULL);
579 ACQUIRE_CTX(ctxidx, ctx);
580 error = fpu_kern_enter(curthread, ctx,
581 FPU_KERN_NORMAL | FPU_KERN_KTHR);
588 error = aesni_cipher_setup_common(ses, encini->cri_key,
592 fpu_kern_leave(curthread, ctx);
594 RELEASE_CTX(ctxidx, ctx);
600 intel_sha1_update(void *vctx, const void *vdata, u_int datalen)
602 struct sha1_ctxt *ctx = vctx;
603 const char *data = vdata;
611 /* Do any aligned blocks without redundant copying. */
612 if (datalen >= 64 && ctx->count % 64 == 0) {
613 blocks = datalen / 64;
614 ctx->c.b64[0] += blocks * 64 * 8;
615 intel_sha1_step(ctx->h.b32, data + off, blocks);
619 while (off < datalen) {
620 gapstart = ctx->count % 64;
621 gaplen = 64 - gapstart;
623 copysiz = (gaplen < datalen - off) ? gaplen : datalen - off;
624 bcopy(&data[off], &ctx->m.b8[gapstart], copysiz);
625 ctx->count += copysiz;
627 ctx->c.b64[0] += copysiz * 8;
628 if (ctx->count % 64 == 0)
629 intel_sha1_step(ctx->h.b32, (void *)ctx->m.b8, 1);
636 SHA1_Finalize_fn(void *digest, void *ctx)
638 sha1_result(ctx, digest);
642 intel_sha256_update(void *vctx, const void *vdata, u_int len)
644 SHA256_CTX *ctx = vctx;
648 const unsigned char *src = vdata;
650 /* Number of bytes left in the buffer from previous updates */
651 r = (ctx->count >> 3) & 0x3f;
653 /* Convert the length into a number of bits */
656 /* Update number of bits */
657 ctx->count += bitlen;
659 /* Handle the case where we don't need to perform any transforms */
661 memcpy(&ctx->buf[r], src, len);
665 /* Finish the current block */
666 memcpy(&ctx->buf[r], src, 64 - r);
667 intel_sha256_step(ctx->state, ctx->buf, 1);
671 /* Perform complete blocks */
674 intel_sha256_step(ctx->state, src, blocks);
679 /* Copy left over data into buffer */
680 memcpy(ctx->buf, src, len);
685 SHA256_Finalize_fn(void *digest, void *ctx)
687 SHA256_Final(digest, ctx);
691 * Compute the HASH( (key ^ xorbyte) || buf )
694 hmac_internal(void *ctx, uint32_t *res,
695 int (*update)(void *, const void *, u_int),
696 void (*finalize)(void *, void *), uint8_t *key, uint8_t xorbyte,
697 const void *buf, size_t off, size_t buflen, int crpflags)
701 for (i = 0; i < 64; i++)
703 update(ctx, key, 64);
704 for (i = 0; i < 64; i++)
707 crypto_apply(crpflags, __DECONST(void *, buf), off, buflen,
708 __DECONST(int (*)(void *, void *, u_int), update), ctx);
713 aesni_cipher_process(struct aesni_session *ses, struct cryptodesc *enccrd,
714 struct cryptodesc *authcrd, struct cryptop *crp)
716 struct fpu_kern_ctx *ctx;
720 if (enccrd != NULL) {
721 if ((enccrd->crd_alg == CRYPTO_AES_ICM ||
722 enccrd->crd_alg == CRYPTO_AES_NIST_GCM_16) &&
723 (enccrd->crd_flags & CRD_F_IV_EXPLICIT) == 0)
730 kt = is_fpu_kern_thread(0);
732 ACQUIRE_CTX(ctxidx, ctx);
733 error = fpu_kern_enter(curthread, ctx,
734 FPU_KERN_NORMAL | FPU_KERN_KTHR);
740 if (enccrd != NULL && authcrd != NULL) {
741 /* Perform the first operation */
742 if (crp->crp_desc == enccrd)
743 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp);
745 error = aesni_cipher_mac(ses, authcrd, crp);
748 /* Perform the second operation */
749 if (crp->crp_desc == enccrd)
750 error = aesni_cipher_mac(ses, authcrd, crp);
752 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp);
753 } else if (enccrd != NULL)
754 error = aesni_cipher_crypt(ses, enccrd, authcrd, crp);
756 error = aesni_cipher_mac(ses, authcrd, crp);
763 fpu_kern_leave(curthread, ctx);
765 RELEASE_CTX(ctxidx, ctx);
771 aesni_cipher_crypt(struct aesni_session *ses, struct cryptodesc *enccrd,
772 struct cryptodesc *authcrd, struct cryptop *crp)
774 uint8_t iv[AES_BLOCK_LEN], tag[GMAC_DIGEST_LEN], *buf, *authbuf;
776 bool encflag, allocated, authallocated;
778 KASSERT(ses->algo != CRYPTO_AES_NIST_GCM_16 || authcrd != NULL,
779 ("AES_NIST_GCM_16 must include MAC descriptor"));
784 buf = aesni_cipher_alloc(enccrd, crp, &allocated);
788 authallocated = false;
789 if (ses->algo == CRYPTO_AES_NIST_GCM_16) {
790 authbuf = aesni_cipher_alloc(authcrd, crp, &authallocated);
791 if (authbuf == NULL) {
798 encflag = (enccrd->crd_flags & CRD_F_ENCRYPT) == CRD_F_ENCRYPT;
799 if ((enccrd->crd_flags & CRD_F_KEY_EXPLICIT) != 0) {
800 error = aesni_cipher_setup_common(ses, enccrd->crd_key,
806 switch (enccrd->crd_alg) {
809 ivlen = AES_BLOCK_LEN;
814 case CRYPTO_AES_NIST_GCM_16:
815 ivlen = 12; /* should support arbitarily larger */
821 if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT) != 0)
822 bcopy(enccrd->crd_iv, iv, ivlen);
824 arc4rand(iv, ivlen, 0);
826 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0)
827 crypto_copyback(crp->crp_flags, crp->crp_buf,
828 enccrd->crd_inject, ivlen, iv);
830 if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT) != 0)
831 bcopy(enccrd->crd_iv, iv, ivlen);
833 crypto_copydata(crp->crp_flags, crp->crp_buf,
834 enccrd->crd_inject, ivlen, iv);
840 aesni_encrypt_cbc(ses->rounds, ses->enc_schedule,
841 enccrd->crd_len, buf, buf, iv);
843 aesni_decrypt_cbc(ses->rounds, ses->dec_schedule,
844 enccrd->crd_len, buf, iv);
847 /* encryption & decryption are the same */
848 aesni_encrypt_icm(ses->rounds, ses->enc_schedule,
849 enccrd->crd_len, buf, buf, iv);
853 aesni_encrypt_xts(ses->rounds, ses->enc_schedule,
854 ses->xts_schedule, enccrd->crd_len, buf, buf,
857 aesni_decrypt_xts(ses->rounds, ses->dec_schedule,
858 ses->xts_schedule, enccrd->crd_len, buf, buf,
861 case CRYPTO_AES_NIST_GCM_16:
863 crypto_copydata(crp->crp_flags, crp->crp_buf,
864 authcrd->crd_inject, GMAC_DIGEST_LEN, tag);
866 bzero(tag, sizeof tag);
869 AES_GCM_encrypt(buf, buf, authbuf, iv, tag,
870 enccrd->crd_len, authcrd->crd_len, ivlen,
871 ses->enc_schedule, ses->rounds);
874 crypto_copyback(crp->crp_flags, crp->crp_buf,
875 authcrd->crd_inject, GMAC_DIGEST_LEN, tag);
877 if (!AES_GCM_decrypt(buf, buf, authbuf, iv, tag,
878 enccrd->crd_len, authcrd->crd_len, ivlen,
879 ses->enc_schedule, ses->rounds))
887 explicit_bzero(buf, enccrd->crd_len);
891 explicit_bzero(authbuf, authcrd->crd_len);
892 free(authbuf, M_AESNI);
898 aesni_cipher_mac(struct aesni_session *ses, struct cryptodesc *crd,
902 struct SHA256Context sha2 __aligned(16);
903 struct sha1_ctxt sha1 __aligned(16);
905 uint32_t res[SHA2_256_HASH_LEN / sizeof(uint32_t)];
908 if (crd->crd_flags != 0)
911 switch (ses->auth_algo) {
912 case CRYPTO_SHA1_HMAC:
913 hashlen = SHA1_HASH_LEN;
914 /* Inner hash: (K ^ IPAD) || data */
915 sha1_init(&sctx.sha1);
916 hmac_internal(&sctx.sha1, res, intel_sha1_update,
917 SHA1_Finalize_fn, ses->hmac_key, 0x36, crp->crp_buf,
918 crd->crd_skip, crd->crd_len, crp->crp_flags);
919 /* Outer hash: (K ^ OPAD) || inner hash */
920 sha1_init(&sctx.sha1);
921 hmac_internal(&sctx.sha1, res, intel_sha1_update,
922 SHA1_Finalize_fn, ses->hmac_key, 0x5C, res, 0, hashlen, 0);
925 hashlen = SHA1_HASH_LEN;
926 sha1_init(&sctx.sha1);
927 crypto_apply(crp->crp_flags, crp->crp_buf, crd->crd_skip,
928 crd->crd_len, __DECONST(int (*)(void *, void *, u_int),
929 intel_sha1_update), &sctx.sha1);
930 sha1_result(&sctx.sha1, (void *)res);
932 case CRYPTO_SHA2_256_HMAC:
933 hashlen = SHA2_256_HASH_LEN;
934 /* Inner hash: (K ^ IPAD) || data */
935 SHA256_Init(&sctx.sha2);
936 hmac_internal(&sctx.sha2, res, intel_sha256_update,
937 SHA256_Finalize_fn, ses->hmac_key, 0x36, crp->crp_buf,
938 crd->crd_skip, crd->crd_len, crp->crp_flags);
939 /* Outer hash: (K ^ OPAD) || inner hash */
940 SHA256_Init(&sctx.sha2);
941 hmac_internal(&sctx.sha2, res, intel_sha256_update,
942 SHA256_Finalize_fn, ses->hmac_key, 0x5C, res, 0, hashlen,
947 * AES-GMAC authentication is verified while processing the
953 if (ses->mlen != 0 && ses->mlen < hashlen)
956 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, hashlen,