2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2017 Conrad Meyer <cem@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Keccak SHAKE128 (if supported by the device?) uses a 1344 bit block.
35 * SHA3-224 is the next largest block size, at 1152 bits. However, crypto(4)
36 * doesn't support any SHA3 hash, so SHA2 is the constraint:
38 #define CCP_HASH_MAX_BLOCK_SIZE (SHA2_512_BLOCK_LEN)
40 #define CCP_AES_MAX_KEY_LEN (AES_XTS_MAX_KEY)
41 #define CCP_MAX_CRYPTO_IV_LEN 32 /* GCM IV + GHASH context */
43 #define MAX_HW_QUEUES 5
44 #define MAX_LSB_REGIONS 8
47 #define __must_check __attribute__((__warn_unused_result__))
51 * Internal data structures.
58 SHA2_256, SHA2_384, SHA2_512
61 struct ccp_session_hmac {
62 struct auth_hash *auth_hash;
64 unsigned int partial_digest_len;
65 unsigned int auth_mode;
67 char ipad[CCP_HASH_MAX_BLOCK_SIZE];
68 char opad[CCP_HASH_MAX_BLOCK_SIZE];
71 struct ccp_session_gmac {
73 char final_block[GMAC_BLOCK_LEN];
76 struct ccp_session_blkcipher {
81 char enckey[CCP_AES_MAX_KEY_LEN];
82 char iv[CCP_MAX_CRYPTO_IV_LEN];
87 bool cipher_first : 1;
89 enum { HMAC, BLKCIPHER, AUTHENC, GCM } mode;
92 struct ccp_session_hmac hmac;
93 struct ccp_session_gmac gmac;
95 struct ccp_session_blkcipher blkcipher;
102 struct ccp_softc *cq_softc;
104 /* Host memory and tracking structures for descriptor ring. */
105 bus_dma_tag_t ring_desc_tag;
106 bus_dmamap_t ring_desc_map;
107 struct ccp_desc *desc_ring;
108 bus_addr_t desc_ring_bus_addr;
109 /* Callbacks and arguments ring; indices correspond to above ring. */
110 struct ccp_completion_ctx *completions_ring;
112 uint32_t qcontrol; /* Cached register value */
113 unsigned lsb_mask; /* LSBs available to queue */
114 int private_lsb; /* Reserved LSB #, or -1 */
118 unsigned cq_acq_tail;
120 bool cq_waiting; /* Thread waiting for space */
122 struct sglist *cq_sg_crp;
123 struct sglist *cq_sg_ulptx;
124 struct sglist *cq_sg_dst;
127 struct ccp_completion_ctx {
128 void (*callback_fn)(struct ccp_queue *qp, struct ccp_session *s,
129 void *arg, int error);
131 struct ccp_session *session;
140 unsigned ring_size_order;
143 * Each command queue is either public or private. "Private"
144 * (PSP-only) by default. PSP grants access to some queues to host via
145 * QMR (Queue Mask Register). Set bits are host accessible.
147 uint8_t valid_queues;
151 uint16_t hw_features;
152 uint16_t num_lsb_entries;
154 /* Primary BAR (RID 2) used for register access */
155 bus_space_tag_t pci_bus_tag;
156 bus_space_handle_t pci_bus_handle;
158 struct resource *pci_resource;
160 /* Secondary BAR (RID 5) apparently used for MSI-X */
161 int pci_resource_id_msix;
162 struct resource *pci_resource_msix;
164 /* Interrupt resources */
166 struct resource *intr_res[2];
169 struct ccp_queue queues[MAX_HW_QUEUES];
172 /* Internal globals */
173 SYSCTL_DECL(_hw_ccp);
174 MALLOC_DECLARE(M_CCP);
175 extern bool g_debug_print;
176 extern struct ccp_softc *g_ccp_softc;
181 #define DPRINTF(dev, ...) do { \
182 if (!g_debug_print) \
185 device_printf((dev), "XXX " __VA_ARGS__); \
187 printf("ccpXXX: " __VA_ARGS__); \
191 #define INSECURE_DEBUG(dev, ...) do { \
192 if (!g_debug_print) \
195 device_printf((dev), "XXX " __VA_ARGS__); \
197 printf("ccpXXX: " __VA_ARGS__); \
200 #define INSECURE_DEBUG(dev, ...)
204 * Internal hardware manipulation routines.
206 int ccp_hw_attach(device_t dev);
207 void ccp_hw_detach(device_t dev);
209 void ccp_queue_write_tail(struct ccp_queue *qp);
212 void db_ccp_show_hw(struct ccp_softc *sc);
213 void db_ccp_show_queue_hw(struct ccp_queue *qp);
217 * Internal hardware crypt-op submission routines.
219 int ccp_authenc(struct ccp_queue *sc, struct ccp_session *s,
220 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde)
222 int ccp_blkcipher(struct ccp_queue *sc, struct ccp_session *s,
223 struct cryptop *crp) __must_check;
224 int ccp_gcm(struct ccp_queue *sc, struct ccp_session *s, struct cryptop *crp,
225 struct cryptodesc *crda, struct cryptodesc *crde) __must_check;
226 int ccp_hmac(struct ccp_queue *sc, struct ccp_session *s, struct cryptop *crp)
230 * Internal hardware TRNG read routine.
232 u_int random_ccp_read(void *v, u_int c);
235 int ccp_queue_acquire_reserve(struct ccp_queue *qp, unsigned n, int mflags)
237 void ccp_queue_abort(struct ccp_queue *qp);
238 void ccp_queue_release(struct ccp_queue *qp);
241 * Internal inline routines.
243 static inline unsigned
244 ccp_queue_get_active(struct ccp_queue *qp)
246 struct ccp_softc *sc;
249 return ((qp->cq_tail - qp->cq_head) & ((1 << sc->ring_size_order) - 1));
252 static inline unsigned
253 ccp_queue_get_ring_space(struct ccp_queue *qp)
255 struct ccp_softc *sc;
258 return ((1 << sc->ring_size_order) - ccp_queue_get_active(qp) - 1);