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33 #include <sys/types.h>
34 #include <sys/systm.h>
36 #include <machine/cpufunc.h>
37 #include <machine/md_var.h>
38 #include <x86/cputypes.h>
39 #include <x86/specialreg.h>
41 #include <crypto/openssl/ossl.h>
42 #include <crypto/openssl/ossl_cipher.h>
45 * See OPENSSL_ia32cap(3).
47 * [0] = cpu_feature but with a few custom bits
48 * [1] = cpu_feature2 but with AMD XOP in bit 11
49 * [2] = cpu_stdext_feature
52 unsigned int OPENSSL_ia32cap_P[4];
53 #define AESNI_CAPABLE (OPENSSL_ia32cap_P[1]&(1<<(57-32)))
55 ossl_cipher_setkey_t aesni_set_encrypt_key;
56 ossl_cipher_setkey_t aesni_set_decrypt_key;
59 ossl_cpuid(struct ossl_softc *sc)
65 /* Derived from OpenSSL_ia32_cpuid. */
67 OPENSSL_ia32cap_P[0] = cpu_feature & ~(CPUID_B20 | CPUID_IA64);
68 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
69 OPENSSL_ia32cap_P[0] |= CPUID_IA64;
70 if ((cpu_id & 0xf00) != 0xf00)
71 OPENSSL_ia32cap_P[0] |= CPUID_B20;
74 /* Only leave CPUID_HTT on if HTT is present. */
75 if (cpu_vendor_id == CPU_VENDOR_AMD && cpu_exthigh >= 0x80000008) {
76 max_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
77 if (cpu_feature & CPUID_HTT) {
78 if ((cpu_procinfo & CPUID_HTT_CORES) >> 16 <= max_cores)
79 OPENSSL_ia32cap_P[0] &= ~CPUID_HTT;
83 cpuid_count(4, 0, regs);
84 max_cores = (regs[0] >> 26) & 0xfff;
89 OPENSSL_ia32cap_P[0] &= ~CPUID_HTT;
90 else if ((cpu_procinfo & CPUID_HTT_CORES) >> 16 == 0)
91 OPENSSL_ia32cap_P[0] &= ~CPUID_HTT;
93 OPENSSL_ia32cap_P[1] = cpu_feature2 & ~AMDID2_XOP;
94 if (cpu_vendor_id == CPU_VENDOR_AMD)
95 OPENSSL_ia32cap_P[1] |= amd_feature2 & AMDID2_XOP;
97 OPENSSL_ia32cap_P[2] = cpu_stdext_feature;
98 if ((OPENSSL_ia32cap_P[1] & CPUID2_XSAVE) == 0)
99 OPENSSL_ia32cap_P[2] &= ~(CPUID_STDEXT_AVX512F |
100 CPUID_STDEXT_AVX512DQ);
102 /* Disable AVX512F on Skylake-X. */
103 if ((cpu_id & 0x0fff0ff0) == 0x00050650)
104 OPENSSL_ia32cap_P[2] &= ~(CPUID_STDEXT_AVX512F);
106 if (cpu_feature2 & CPUID2_OSXSAVE)
111 if ((xcr0 & (XFEATURE_AVX512 | XFEATURE_AVX)) !=
112 (XFEATURE_AVX512 | XFEATURE_AVX))
113 OPENSSL_ia32cap_P[2] &= ~(CPUID_STDEXT_AVX512VL |
114 CPUID_STDEXT_AVX512BW | CPUID_STDEXT_AVX512IFMA |
115 CPUID_STDEXT_AVX512F);
116 if ((xcr0 & XFEATURE_AVX) != XFEATURE_AVX) {
117 OPENSSL_ia32cap_P[1] &= ~(CPUID2_AVX | AMDID2_XOP | CPUID2_FMA);
118 OPENSSL_ia32cap_P[2] &= ~CPUID_STDEXT_AVX2;
121 if (!AESNI_CAPABLE) {
126 ossl_cipher_aes_cbc.set_encrypt_key = aesni_set_encrypt_key;
127 ossl_cipher_aes_cbc.set_decrypt_key = aesni_set_decrypt_key;