2 * Copyright (c) 2003-2005 Nate Lawson (SDG)
3 * Copyright (c) 2001 Michael Smith
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
39 #include <sys/power.h>
41 #include <sys/sched.h>
45 #include <dev/pci/pcivar.h>
46 #include <machine/atomic.h>
47 #include <machine/bus.h>
48 #if defined(__amd64__) || defined(__i386__)
49 #include <machine/clock.h>
53 #include <contrib/dev/acpica/include/acpi.h>
54 #include <contrib/dev/acpica/include/accommon.h>
56 #include <dev/acpica/acpivar.h>
59 * Support for ACPI Processor devices, including C[1-3] sleep states.
62 /* Hooks for the ACPI CA debugging infrastructure */
63 #define _COMPONENT ACPI_PROCESSOR
64 ACPI_MODULE_NAME("PROCESSOR")
67 struct resource *p_lvlx; /* Register to read to enter state. */
68 uint32_t type; /* C1-3 (C4 and up treated as C3). */
69 uint32_t trans_lat; /* Transition latency (usec). */
70 uint32_t power; /* Power consumed (mW). */
71 int res_type; /* Resource type for p_lvlx. */
72 int res_rid; /* Resource ID for p_lvlx. */
74 #define MAX_CX_STATES 8
76 struct acpi_cpu_softc {
78 ACPI_HANDLE cpu_handle;
79 struct pcpu *cpu_pcpu;
80 uint32_t cpu_acpi_id; /* ACPI processor id */
81 uint32_t cpu_p_blk; /* ACPI P_BLK location */
82 uint32_t cpu_p_blk_len; /* P_BLK length (must be 6). */
83 struct acpi_cx cpu_cx_states[MAX_CX_STATES];
84 int cpu_cx_count; /* Number of valid Cx states. */
85 int cpu_prev_sleep;/* Last idle sleep duration. */
86 int cpu_features; /* Child driver supported features. */
88 int cpu_non_c3; /* Index of lowest non-C3 state. */
89 u_int cpu_cx_stats[MAX_CX_STATES];/* Cx usage history. */
90 /* Values for sysctl. */
91 struct sysctl_ctx_list cpu_sysctl_ctx;
92 struct sysctl_oid *cpu_sysctl_tree;
94 int cpu_cx_lowest_lim;
95 int cpu_disable_idle; /* Disable entry to idle function */
96 char cpu_cx_supported[64];
99 struct acpi_cpu_device {
100 struct resource_list ad_rl;
103 #define CPU_GET_REG(reg, width) \
104 (bus_space_read_ ## width(rman_get_bustag((reg)), \
105 rman_get_bushandle((reg)), 0))
106 #define CPU_SET_REG(reg, width, val) \
107 (bus_space_write_ ## width(rman_get_bustag((reg)), \
108 rman_get_bushandle((reg)), 0, (val)))
110 #define PM_USEC(x) ((x) >> 2) /* ~4 clocks per usec (3.57955 Mhz) */
112 #define ACPI_NOTIFY_CX_STATES 0x81 /* _CST changed. */
114 #define CPU_QUIRK_NO_C3 (1<<0) /* C3-type states are not usable. */
115 #define CPU_QUIRK_NO_BM_CTRL (1<<2) /* No bus mastering control. */
117 #define PCI_VENDOR_INTEL 0x8086
118 #define PCI_DEVICE_82371AB_3 0x7113 /* PIIX4 chipset for quirks. */
119 #define PCI_REVISION_A_STEP 0
120 #define PCI_REVISION_B_STEP 1
121 #define PCI_REVISION_4E 2
122 #define PCI_REVISION_4M 3
123 #define PIIX4_DEVACTB_REG 0x58
124 #define PIIX4_BRLD_EN_IRQ0 (1<<0)
125 #define PIIX4_BRLD_EN_IRQ (1<<1)
126 #define PIIX4_BRLD_EN_IRQ8 (1<<5)
127 #define PIIX4_STOP_BREAK_MASK (PIIX4_BRLD_EN_IRQ0 | PIIX4_BRLD_EN_IRQ | PIIX4_BRLD_EN_IRQ8)
128 #define PIIX4_PCNTRL_BST_EN (1<<10)
130 /* Allow users to ignore processor orders in MADT. */
131 static int cpu_unordered;
132 TUNABLE_INT("debug.acpi.cpu_unordered", &cpu_unordered);
133 SYSCTL_INT(_debug_acpi, OID_AUTO, cpu_unordered, CTLFLAG_RDTUN,
135 "Do not use the MADT to match ACPI Processor objects to CPUs.");
137 /* Platform hardware resource information. */
138 static uint32_t cpu_smi_cmd; /* Value to write to SMI_CMD. */
139 static uint8_t cpu_cst_cnt; /* Indicate we are _CST aware. */
140 static int cpu_quirks; /* Indicate any hardware bugs. */
142 /* Values for sysctl. */
143 static struct sysctl_ctx_list cpu_sysctl_ctx;
144 static struct sysctl_oid *cpu_sysctl_tree;
145 static int cpu_cx_generic;
146 static int cpu_cx_lowest_lim;
148 static device_t *cpu_devices;
149 static int cpu_ndevices;
150 static struct acpi_cpu_softc **cpu_softc;
151 ACPI_SERIAL_DECL(cpu, "ACPI CPU");
153 static int acpi_cpu_probe(device_t dev);
154 static int acpi_cpu_attach(device_t dev);
155 static int acpi_cpu_suspend(device_t dev);
156 static int acpi_cpu_resume(device_t dev);
157 static int acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id,
159 static struct resource_list *acpi_cpu_get_rlist(device_t dev, device_t child);
160 static device_t acpi_cpu_add_child(device_t dev, u_int order, const char *name,
162 static int acpi_cpu_read_ivar(device_t dev, device_t child, int index,
164 static int acpi_cpu_shutdown(device_t dev);
165 static void acpi_cpu_cx_probe(struct acpi_cpu_softc *sc);
166 static void acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc);
167 static int acpi_cpu_cx_cst(struct acpi_cpu_softc *sc);
168 static void acpi_cpu_startup(void *arg);
169 static void acpi_cpu_startup_cx(struct acpi_cpu_softc *sc);
170 static void acpi_cpu_cx_list(struct acpi_cpu_softc *sc);
171 static void acpi_cpu_idle(sbintime_t sbt);
172 static void acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context);
173 static int acpi_cpu_quirks(void);
174 static int acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS);
175 static int acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS);
176 static int acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc);
177 static int acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
178 static int acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS);
180 static device_method_t acpi_cpu_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, acpi_cpu_probe),
183 DEVMETHOD(device_attach, acpi_cpu_attach),
184 DEVMETHOD(device_detach, bus_generic_detach),
185 DEVMETHOD(device_shutdown, acpi_cpu_shutdown),
186 DEVMETHOD(device_suspend, acpi_cpu_suspend),
187 DEVMETHOD(device_resume, acpi_cpu_resume),
190 DEVMETHOD(bus_add_child, acpi_cpu_add_child),
191 DEVMETHOD(bus_read_ivar, acpi_cpu_read_ivar),
192 DEVMETHOD(bus_get_resource_list, acpi_cpu_get_rlist),
193 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
194 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
195 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource),
196 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
197 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
198 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
199 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
200 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
205 static driver_t acpi_cpu_driver = {
208 sizeof(struct acpi_cpu_softc),
211 static devclass_t acpi_cpu_devclass;
212 DRIVER_MODULE(cpu, acpi, acpi_cpu_driver, acpi_cpu_devclass, 0, 0);
213 MODULE_DEPEND(cpu, acpi, 1, 1, 1);
216 acpi_cpu_probe(device_t dev)
224 if (acpi_disabled("cpu") || acpi_get_type(dev) != ACPI_TYPE_PROCESSOR)
227 handle = acpi_get_handle(dev);
228 if (cpu_softc == NULL)
229 cpu_softc = malloc(sizeof(struct acpi_cpu_softc *) *
230 (mp_maxid + 1), M_TEMP /* XXX */, M_WAITOK | M_ZERO);
232 /* Get our Processor object. */
234 buf.Length = ACPI_ALLOCATE_BUFFER;
235 status = AcpiEvaluateObject(handle, NULL, NULL, &buf);
236 if (ACPI_FAILURE(status)) {
237 device_printf(dev, "probe failed to get Processor obj - %s\n",
238 AcpiFormatException(status));
241 obj = (ACPI_OBJECT *)buf.Pointer;
242 if (obj->Type != ACPI_TYPE_PROCESSOR) {
243 device_printf(dev, "Processor object has bad type %d\n", obj->Type);
249 * Find the processor associated with our unit. We could use the
250 * ProcId as a key, however, some boxes do not have the same values
251 * in their Processor object as the ProcId values in the MADT.
253 acpi_id = obj->Processor.ProcId;
255 if (acpi_pcpu_get_id(dev, &acpi_id, &cpu_id) != 0)
259 * Check if we already probed this processor. We scan the bus twice
260 * so it's possible we've already seen this one.
262 if (cpu_softc[cpu_id] != NULL)
265 /* Mark this processor as in-use and save our derived id for attach. */
266 cpu_softc[cpu_id] = (void *)1;
267 acpi_set_private(dev, (void*)(intptr_t)cpu_id);
268 device_set_desc(dev, "ACPI CPU");
274 acpi_cpu_attach(device_t dev)
277 ACPI_OBJECT arg[4], *obj;
278 ACPI_OBJECT_LIST arglist;
279 struct pcpu *pcpu_data;
280 struct acpi_cpu_softc *sc;
281 struct acpi_softc *acpi_sc;
284 int cpu_id, drv_count, i;
288 /* UUID needed by _OSC evaluation */
289 static uint8_t cpu_oscuuid[16] = { 0x16, 0xA6, 0x77, 0x40, 0x0C, 0x29,
290 0xBE, 0x47, 0x9E, 0xBD, 0xD8, 0x70,
291 0x58, 0x71, 0x39, 0x53 };
293 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
295 sc = device_get_softc(dev);
297 sc->cpu_handle = acpi_get_handle(dev);
298 cpu_id = (int)(intptr_t)acpi_get_private(dev);
299 cpu_softc[cpu_id] = sc;
300 pcpu_data = pcpu_find(cpu_id);
301 pcpu_data->pc_device = dev;
302 sc->cpu_pcpu = pcpu_data;
303 cpu_smi_cmd = AcpiGbl_FADT.SmiCommand;
304 cpu_cst_cnt = AcpiGbl_FADT.CstControl;
307 buf.Length = ACPI_ALLOCATE_BUFFER;
308 status = AcpiEvaluateObject(sc->cpu_handle, NULL, NULL, &buf);
309 if (ACPI_FAILURE(status)) {
310 device_printf(dev, "attach failed to get Processor obj - %s\n",
311 AcpiFormatException(status));
314 obj = (ACPI_OBJECT *)buf.Pointer;
315 sc->cpu_p_blk = obj->Processor.PblkAddress;
316 sc->cpu_p_blk_len = obj->Processor.PblkLength;
317 sc->cpu_acpi_id = obj->Processor.ProcId;
319 ACPI_DEBUG_PRINT((ACPI_DB_INFO, "acpi_cpu%d: P_BLK at %#x/%d\n",
320 device_get_unit(dev), sc->cpu_p_blk, sc->cpu_p_blk_len));
323 * If this is the first cpu we attach, create and initialize the generic
324 * resources that will be used by all acpi cpu devices.
326 if (device_get_unit(dev) == 0) {
327 /* Assume we won't be using generic Cx mode by default */
328 cpu_cx_generic = FALSE;
330 /* Install hw.acpi.cpu sysctl tree */
331 acpi_sc = acpi_device_get_parent_softc(dev);
332 sysctl_ctx_init(&cpu_sysctl_ctx);
333 cpu_sysctl_tree = SYSCTL_ADD_NODE(&cpu_sysctl_ctx,
334 SYSCTL_CHILDREN(acpi_sc->acpi_sysctl_tree), OID_AUTO, "cpu",
335 CTLFLAG_RD, 0, "node for CPU children");
337 /* Queue post cpu-probing task handler */
338 AcpiOsExecute(OSL_NOTIFY_HANDLER, acpi_cpu_startup, NULL);
342 * Before calling any CPU methods, collect child driver feature hints
343 * and notify ACPI of them. We support unified SMP power control
344 * so advertise this ourselves. Note this is not the same as independent
345 * SMP control where each CPU can have different settings.
347 sc->cpu_features = ACPI_CAP_SMP_SAME | ACPI_CAP_SMP_SAME_C3;
348 if (devclass_get_drivers(acpi_cpu_devclass, &drivers, &drv_count) == 0) {
349 for (i = 0; i < drv_count; i++) {
350 if (ACPI_GET_FEATURES(drivers[i], &features) == 0)
351 sc->cpu_features |= features;
353 free(drivers, M_TEMP);
357 * CPU capabilities are specified in
358 * Intel Processor Vendor-Specific ACPI Interface Specification.
360 if (sc->cpu_features) {
361 arglist.Pointer = arg;
363 arg[0].Type = ACPI_TYPE_BUFFER;
364 arg[0].Buffer.Length = sizeof(cpu_oscuuid);
365 arg[0].Buffer.Pointer = cpu_oscuuid; /* UUID */
366 arg[1].Type = ACPI_TYPE_INTEGER;
367 arg[1].Integer.Value = 1; /* revision */
368 arg[2].Type = ACPI_TYPE_INTEGER;
369 arg[2].Integer.Value = 1; /* count */
370 arg[3].Type = ACPI_TYPE_BUFFER;
371 arg[3].Buffer.Length = sizeof(cap_set); /* Capabilities buffer */
372 arg[3].Buffer.Pointer = (uint8_t *)cap_set;
373 cap_set[0] = 0; /* status */
374 cap_set[1] = sc->cpu_features;
375 status = AcpiEvaluateObject(sc->cpu_handle, "_OSC", &arglist, NULL);
376 if (ACPI_SUCCESS(status)) {
378 device_printf(dev, "_OSC returned status %#x\n", cap_set[0]);
381 arglist.Pointer = arg;
383 arg[0].Type = ACPI_TYPE_BUFFER;
384 arg[0].Buffer.Length = sizeof(cap_set);
385 arg[0].Buffer.Pointer = (uint8_t *)cap_set;
386 cap_set[0] = 1; /* revision */
387 cap_set[1] = 1; /* number of capabilities integers */
388 cap_set[2] = sc->cpu_features;
389 AcpiEvaluateObject(sc->cpu_handle, "_PDC", &arglist, NULL);
393 /* Probe for Cx state support. */
394 acpi_cpu_cx_probe(sc);
400 acpi_cpu_postattach(void *unused __unused)
406 err = devclass_get_devices(acpi_cpu_devclass, &devices, &n);
408 printf("devclass_get_devices(acpi_cpu_devclass) failed\n");
411 for (i = 0; i < n; i++)
412 bus_generic_probe(devices[i]);
413 for (i = 0; i < n; i++)
414 bus_generic_attach(devices[i]);
415 free(devices, M_TEMP);
418 SYSINIT(acpi_cpu, SI_SUB_CONFIGURE, SI_ORDER_MIDDLE,
419 acpi_cpu_postattach, NULL);
422 disable_idle(struct acpi_cpu_softc *sc)
426 CPU_SETOF(sc->cpu_pcpu->pc_cpuid, &cpuset);
427 sc->cpu_disable_idle = TRUE;
430 * Ensure that the CPU is not in idle state or in acpi_cpu_idle().
431 * Note that this code depends on the fact that the rendezvous IPI
432 * can not penetrate context where interrupts are disabled and acpi_cpu_idle
433 * is called and executed in such a context with interrupts being re-enabled
434 * right before return.
436 smp_rendezvous_cpus(cpuset, smp_no_rendevous_barrier, NULL,
437 smp_no_rendevous_barrier, NULL);
441 enable_idle(struct acpi_cpu_softc *sc)
444 sc->cpu_disable_idle = FALSE;
448 is_idle_disabled(struct acpi_cpu_softc *sc)
451 return (sc->cpu_disable_idle);
455 * Disable any entry to the idle function during suspend and re-enable it
459 acpi_cpu_suspend(device_t dev)
463 error = bus_generic_suspend(dev);
466 disable_idle(device_get_softc(dev));
471 acpi_cpu_resume(device_t dev)
474 enable_idle(device_get_softc(dev));
475 return (bus_generic_resume(dev));
479 * Find the processor associated with a given ACPI ID. By default,
480 * use the MADT to map ACPI IDs to APIC IDs and use that to locate a
481 * processor. Some systems have inconsistent ASL and MADT however.
482 * For these systems the cpu_unordered tunable can be set in which
483 * case we assume that Processor objects are listed in the same order
484 * in both the MADT and ASL.
487 acpi_pcpu_get_id(device_t dev, uint32_t *acpi_id, uint32_t *cpu_id)
492 KASSERT(acpi_id != NULL, ("Null acpi_id"));
493 KASSERT(cpu_id != NULL, ("Null cpu_id"));
494 idx = device_get_unit(dev);
497 * If pc_acpi_id for CPU 0 is not initialized (e.g. a non-APIC
498 * UP box) use the ACPI ID from the first processor we find.
500 if (idx == 0 && mp_ncpus == 1) {
502 if (pc->pc_acpi_id == 0xffffffff)
503 pc->pc_acpi_id = *acpi_id;
510 KASSERT(pc != NULL, ("no pcpu data for %d", i));
514 * If pc_acpi_id doesn't match the ACPI ID from the
515 * ASL, prefer the MADT-derived value.
517 if (pc->pc_acpi_id != *acpi_id)
518 *acpi_id = pc->pc_acpi_id;
519 *cpu_id = pc->pc_cpuid;
523 if (pc->pc_acpi_id == *acpi_id) {
526 "Processor %s (ACPI ID %u) -> APIC ID %d\n",
527 acpi_name(acpi_get_handle(dev)), *acpi_id,
529 *cpu_id = pc->pc_cpuid;
536 printf("ACPI: Processor %s (ACPI ID %u) ignored\n",
537 acpi_name(acpi_get_handle(dev)), *acpi_id);
542 static struct resource_list *
543 acpi_cpu_get_rlist(device_t dev, device_t child)
545 struct acpi_cpu_device *ad;
547 ad = device_get_ivars(child);
554 acpi_cpu_add_child(device_t dev, u_int order, const char *name, int unit)
556 struct acpi_cpu_device *ad;
559 if ((ad = malloc(sizeof(*ad), M_TEMP, M_NOWAIT | M_ZERO)) == NULL)
562 resource_list_init(&ad->ad_rl);
564 child = device_add_child_ordered(dev, order, name, unit);
566 device_set_ivars(child, ad);
573 acpi_cpu_read_ivar(device_t dev, device_t child, int index, uintptr_t *result)
575 struct acpi_cpu_softc *sc;
577 sc = device_get_softc(dev);
579 case ACPI_IVAR_HANDLE:
580 *result = (uintptr_t)sc->cpu_handle;
583 *result = (uintptr_t)sc->cpu_pcpu;
585 #if defined(__amd64__) || defined(__i386__)
586 case CPU_IVAR_NOMINAL_MHZ:
587 if (tsc_is_invariant) {
588 *result = (uintptr_t)(atomic_load_acq_64(&tsc_freq) / 1000000);
600 acpi_cpu_shutdown(device_t dev)
602 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
604 /* Allow children to shutdown first. */
605 bus_generic_shutdown(dev);
608 * Disable any entry to the idle function.
610 disable_idle(device_get_softc(dev));
613 * CPU devices are not truely detached and remain referenced,
614 * so their resources are not freed.
621 acpi_cpu_cx_probe(struct acpi_cpu_softc *sc)
623 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
625 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
626 sc->cpu_prev_sleep = 1000000;
627 sc->cpu_cx_lowest = 0;
628 sc->cpu_cx_lowest_lim = 0;
631 * Check for the ACPI 2.0 _CST sleep states object. If we can't find
632 * any, we'll revert to generic FADT/P_BLK Cx control method which will
633 * be handled by acpi_cpu_startup. We need to defer to after having
634 * probed all the cpus in the system before probing for generic Cx
635 * states as we may already have found cpus with valid _CST packages
637 if (!cpu_cx_generic && acpi_cpu_cx_cst(sc) != 0) {
639 * We were unable to find a _CST package for this cpu or there
640 * was an error parsing it. Switch back to generic mode.
642 cpu_cx_generic = TRUE;
644 device_printf(sc->cpu_dev, "switching to generic Cx mode\n");
648 * TODO: _CSD Package should be checked here.
653 acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc)
655 ACPI_GENERIC_ADDRESS gas;
656 struct acpi_cx *cx_ptr;
658 sc->cpu_cx_count = 0;
659 cx_ptr = sc->cpu_cx_states;
661 /* Use initial sleep value of 1 sec. to start with lowest idle state. */
662 sc->cpu_prev_sleep = 1000000;
664 /* C1 has been required since just after ACPI 1.0 */
665 cx_ptr->type = ACPI_STATE_C1;
666 cx_ptr->trans_lat = 0;
668 sc->cpu_non_c3 = sc->cpu_cx_count;
672 * The spec says P_BLK must be 6 bytes long. However, some systems
673 * use it to indicate a fractional set of features present so we
674 * take 5 as C2. Some may also have a value of 7 to indicate
675 * another C3 but most use _CST for this (as required) and having
676 * "only" C1-C3 is not a hardship.
678 if (sc->cpu_p_blk_len < 5)
681 /* Validate and allocate resources for C2 (P_LVL2). */
682 gas.SpaceId = ACPI_ADR_SPACE_SYSTEM_IO;
684 if (AcpiGbl_FADT.C2Latency <= 100) {
685 gas.Address = sc->cpu_p_blk + 4;
687 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
688 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
689 if (cx_ptr->p_lvlx != NULL) {
690 cx_ptr->type = ACPI_STATE_C2;
691 cx_ptr->trans_lat = AcpiGbl_FADT.C2Latency;
693 sc->cpu_non_c3 = sc->cpu_cx_count;
697 if (sc->cpu_p_blk_len < 6)
700 /* Validate and allocate resources for C3 (P_LVL3). */
701 if (AcpiGbl_FADT.C3Latency <= 1000 && !(cpu_quirks & CPU_QUIRK_NO_C3)) {
702 gas.Address = sc->cpu_p_blk + 5;
704 acpi_bus_alloc_gas(sc->cpu_dev, &cx_ptr->res_type, &cx_ptr->res_rid,
705 &gas, &cx_ptr->p_lvlx, RF_SHAREABLE);
706 if (cx_ptr->p_lvlx != NULL) {
707 cx_ptr->type = ACPI_STATE_C3;
708 cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency;
711 cpu_can_deep_sleep = 1;
717 * Parse a _CST package and set up its Cx states. Since the _CST object
718 * can change dynamically, our notify handler may call this function
719 * to clean up and probe the new _CST package.
722 acpi_cpu_cx_cst(struct acpi_cpu_softc *sc)
724 struct acpi_cx *cx_ptr;
732 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
735 buf.Length = ACPI_ALLOCATE_BUFFER;
736 status = AcpiEvaluateObject(sc->cpu_handle, "_CST", NULL, &buf);
737 if (ACPI_FAILURE(status))
740 /* _CST is a package with a count and at least one Cx package. */
741 top = (ACPI_OBJECT *)buf.Pointer;
742 if (!ACPI_PKG_VALID(top, 2) || acpi_PkgInt32(top, 0, &count) != 0) {
743 device_printf(sc->cpu_dev, "invalid _CST package\n");
744 AcpiOsFree(buf.Pointer);
747 if (count != top->Package.Count - 1) {
748 device_printf(sc->cpu_dev, "invalid _CST state count (%d != %d)\n",
749 count, top->Package.Count - 1);
750 count = top->Package.Count - 1;
752 if (count > MAX_CX_STATES) {
753 device_printf(sc->cpu_dev, "_CST has too many states (%d)\n", count);
754 count = MAX_CX_STATES;
758 sc->cpu_cx_count = 0;
759 cx_ptr = sc->cpu_cx_states;
762 * C1 has been required since just after ACPI 1.0.
763 * Reserve the first slot for it.
765 cx_ptr->type = ACPI_STATE_C0;
769 /* Set up all valid states. */
770 for (i = 0; i < count; i++) {
771 pkg = &top->Package.Elements[i + 1];
772 if (!ACPI_PKG_VALID(pkg, 4) ||
773 acpi_PkgInt32(pkg, 1, &cx_ptr->type) != 0 ||
774 acpi_PkgInt32(pkg, 2, &cx_ptr->trans_lat) != 0 ||
775 acpi_PkgInt32(pkg, 3, &cx_ptr->power) != 0) {
777 device_printf(sc->cpu_dev, "skipping invalid Cx state package\n");
781 /* Validate the state to see if we should use it. */
782 switch (cx_ptr->type) {
784 if (sc->cpu_cx_states[0].type == ACPI_STATE_C0) {
785 /* This is the first C1 state. Use the reserved slot. */
786 sc->cpu_cx_states[0] = *cx_ptr;
788 sc->cpu_non_c3 = sc->cpu_cx_count;
794 sc->cpu_non_c3 = sc->cpu_cx_count;
798 if ((cpu_quirks & CPU_QUIRK_NO_C3) != 0) {
799 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
800 "acpi_cpu%d: C3[%d] not available.\n",
801 device_get_unit(sc->cpu_dev), i));
804 cpu_can_deep_sleep = 1;
808 /* Free up any previous register. */
809 if (cx_ptr->p_lvlx != NULL) {
810 bus_release_resource(sc->cpu_dev, cx_ptr->res_type, cx_ptr->res_rid,
812 cx_ptr->p_lvlx = NULL;
815 /* Allocate the control register for C2 or C3. */
816 cx_ptr->res_rid = sc->cpu_cx_count;
817 acpi_PkgGas(sc->cpu_dev, pkg, 0, &cx_ptr->res_type, &cx_ptr->res_rid,
818 &cx_ptr->p_lvlx, RF_SHAREABLE);
819 if (cx_ptr->p_lvlx) {
820 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
821 "acpi_cpu%d: Got C%d - %d latency\n",
822 device_get_unit(sc->cpu_dev), cx_ptr->type,
828 AcpiOsFree(buf.Pointer);
830 /* If C1 state was not found, we need one now. */
831 cx_ptr = sc->cpu_cx_states;
832 if (cx_ptr->type == ACPI_STATE_C0) {
833 cx_ptr->type = ACPI_STATE_C1;
834 cx_ptr->trans_lat = 0;
841 * Call this *after* all CPUs have been attached.
844 acpi_cpu_startup(void *arg)
846 struct acpi_cpu_softc *sc;
849 /* Get set of CPU devices */
850 devclass_get_devices(acpi_cpu_devclass, &cpu_devices, &cpu_ndevices);
853 * Setup any quirks that might necessary now that we have probed
858 if (cpu_cx_generic) {
860 * We are using generic Cx mode, probe for available Cx states
861 * for all processors.
863 for (i = 0; i < cpu_ndevices; i++) {
864 sc = device_get_softc(cpu_devices[i]);
865 acpi_cpu_generic_cx_probe(sc);
869 * We are using _CST mode, remove C3 state if necessary.
870 * As we now know for sure that we will be using _CST mode
871 * install our notify handler.
873 for (i = 0; i < cpu_ndevices; i++) {
874 sc = device_get_softc(cpu_devices[i]);
875 if (cpu_quirks & CPU_QUIRK_NO_C3) {
876 sc->cpu_cx_count = sc->cpu_non_c3 + 1;
878 AcpiInstallNotifyHandler(sc->cpu_handle, ACPI_DEVICE_NOTIFY,
879 acpi_cpu_notify, sc);
883 /* Perform Cx final initialization. */
884 for (i = 0; i < cpu_ndevices; i++) {
885 sc = device_get_softc(cpu_devices[i]);
886 acpi_cpu_startup_cx(sc);
889 /* Add a sysctl handler to handle global Cx lowest setting */
890 SYSCTL_ADD_PROC(&cpu_sysctl_ctx, SYSCTL_CHILDREN(cpu_sysctl_tree),
891 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
892 NULL, 0, acpi_cpu_global_cx_lowest_sysctl, "A",
893 "Global lowest Cx sleep state to use");
895 /* Take over idling from cpu_idle_default(). */
896 cpu_cx_lowest_lim = 0;
897 for (i = 0; i < cpu_ndevices; i++) {
898 sc = device_get_softc(cpu_devices[i]);
901 cpu_idle_hook = acpi_cpu_idle;
905 acpi_cpu_cx_list(struct acpi_cpu_softc *sc)
911 * Set up the list of Cx states
913 sbuf_new(&sb, sc->cpu_cx_supported, sizeof(sc->cpu_cx_supported),
915 for (i = 0; i < sc->cpu_cx_count; i++)
916 sbuf_printf(&sb, "C%d/%d/%d ", i + 1, sc->cpu_cx_states[i].type,
917 sc->cpu_cx_states[i].trans_lat);
923 acpi_cpu_startup_cx(struct acpi_cpu_softc *sc)
925 acpi_cpu_cx_list(sc);
927 SYSCTL_ADD_STRING(&sc->cpu_sysctl_ctx,
928 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
929 OID_AUTO, "cx_supported", CTLFLAG_RD,
930 sc->cpu_cx_supported, 0,
931 "Cx/microsecond values for supported Cx states");
932 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
933 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
934 OID_AUTO, "cx_lowest", CTLTYPE_STRING | CTLFLAG_RW,
935 (void *)sc, 0, acpi_cpu_cx_lowest_sysctl, "A",
936 "lowest Cx sleep state to use");
937 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
938 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
939 OID_AUTO, "cx_usage", CTLTYPE_STRING | CTLFLAG_RD,
940 (void *)sc, 0, acpi_cpu_usage_sysctl, "A",
941 "percent usage for each Cx state");
942 SYSCTL_ADD_PROC(&sc->cpu_sysctl_ctx,
943 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->cpu_dev)),
944 OID_AUTO, "cx_usage_counters", CTLTYPE_STRING | CTLFLAG_RD,
945 (void *)sc, 0, acpi_cpu_usage_counters_sysctl, "A",
946 "Cx sleep state counters");
948 /* Signal platform that we can handle _CST notification. */
949 if (!cpu_cx_generic && cpu_cst_cnt != 0) {
951 AcpiOsWritePort(cpu_smi_cmd, cpu_cst_cnt, 8);
957 * Idle the CPU in the lowest state possible. This function is called with
958 * interrupts disabled. Note that once it re-enables interrupts, a task
959 * switch can occur so do not access shared data (i.e. the softc) after
960 * interrupts are re-enabled.
963 acpi_cpu_idle(sbintime_t sbt)
965 struct acpi_cpu_softc *sc;
966 struct acpi_cx *cx_next;
968 uint32_t start_time, end_time;
969 int bm_active, cx_next_idx, i, us;
972 * Look up our CPU id to get our softc. If it's NULL, we'll use C1
973 * since there is no ACPI processor object for this CPU. This occurs
974 * for logical CPUs in the HTT case.
976 sc = cpu_softc[PCPU_GET(cpuid)];
982 /* If disabled, take the safe path. */
983 if (is_idle_disabled(sc)) {
988 /* Find the lowest state that has small enough latency. */
989 us = sc->cpu_prev_sleep;
990 if (sbt >= 0 && us > (sbt >> 12))
993 if (cpu_disable_deep_sleep)
994 i = min(sc->cpu_cx_lowest, sc->cpu_non_c3);
996 i = sc->cpu_cx_lowest;
997 for (; i >= 0; i--) {
998 if (sc->cpu_cx_states[i].trans_lat * 3 <= us) {
1005 * Check for bus master activity. If there was activity, clear
1006 * the bit and use the lowest non-C3 state. Note that the USB
1007 * driver polling for new devices keeps this bit set all the
1008 * time if USB is loaded.
1010 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0 &&
1011 cx_next_idx > sc->cpu_non_c3) {
1012 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, &bm_active);
1013 if (bm_active != 0) {
1014 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_STATUS, 1);
1015 cx_next_idx = sc->cpu_non_c3;
1019 /* Select the next state and update statistics. */
1020 cx_next = &sc->cpu_cx_states[cx_next_idx];
1021 sc->cpu_cx_stats[cx_next_idx]++;
1022 KASSERT(cx_next->type != ACPI_STATE_C0, ("acpi_cpu_idle: C0 sleep"));
1025 * Execute HLT (or equivalent) and wait for an interrupt. We can't
1026 * precisely calculate the time spent in C1 since the place we wake up
1027 * is an ISR. Assume we slept no more then half of quantum, unless
1028 * we are called inside critical section, delaying context switch.
1030 if (cx_next->type == ACPI_STATE_C1) {
1031 cputicks = cpu_ticks();
1033 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate();
1034 if (curthread->td_critnest == 0)
1035 end_time = min(end_time, 500000 / hz);
1036 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + end_time) / 4;
1041 * For C3, disable bus master arbitration and enable bus master wake
1042 * if BM control is available, otherwise flush the CPU cache.
1044 if (cx_next->type == ACPI_STATE_C3) {
1045 if ((cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
1046 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 1);
1047 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 1);
1049 ACPI_FLUSH_CPU_CACHE();
1053 * Read from P_LVLx to enter C2(+), checking time spent asleep.
1054 * Use the ACPI timer for measuring sleep time. Since we need to
1055 * get the time very close to the CPU start/stop clock logic, this
1056 * is the only reliable time source.
1058 if (cx_next->type == ACPI_STATE_C3) {
1059 AcpiHwRead(&start_time, &AcpiGbl_FADT.XPmTimerBlock);
1063 cputicks = cpu_ticks();
1065 CPU_GET_REG(cx_next->p_lvlx, 1);
1068 * Read the end time twice. Since it may take an arbitrary time
1069 * to enter the idle state, the first read may be executed before
1070 * the processor has stopped. Doing it again provides enough
1071 * margin that we are certain to have a correct value.
1073 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
1074 if (cx_next->type == ACPI_STATE_C3) {
1075 AcpiHwRead(&end_time, &AcpiGbl_FADT.XPmTimerBlock);
1076 end_time = acpi_TimerDelta(end_time, start_time);
1078 end_time = ((cpu_ticks() - cputicks) << 20) / cpu_tickrate();
1080 /* Enable bus master arbitration and disable bus master wakeup. */
1081 if (cx_next->type == ACPI_STATE_C3 &&
1082 (cpu_quirks & CPU_QUIRK_NO_BM_CTRL) == 0) {
1083 AcpiWriteBitRegister(ACPI_BITREG_ARB_DISABLE, 0);
1084 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1088 sc->cpu_prev_sleep = (sc->cpu_prev_sleep * 3 + PM_USEC(end_time)) / 4;
1092 * Re-evaluate the _CST object when we are notified that it changed.
1095 acpi_cpu_notify(ACPI_HANDLE h, UINT32 notify, void *context)
1097 struct acpi_cpu_softc *sc = (struct acpi_cpu_softc *)context;
1099 if (notify != ACPI_NOTIFY_CX_STATES)
1103 * C-state data for target CPU is going to be in flux while we execute
1104 * acpi_cpu_cx_cst, so disable entering acpi_cpu_idle.
1105 * Also, it may happen that multiple ACPI taskqueues may concurrently
1106 * execute notifications for the same CPU. ACPI_SERIAL is used to
1107 * protect against that.
1109 ACPI_SERIAL_BEGIN(cpu);
1112 /* Update the list of Cx states. */
1113 acpi_cpu_cx_cst(sc);
1114 acpi_cpu_cx_list(sc);
1115 acpi_cpu_set_cx_lowest(sc);
1118 ACPI_SERIAL_END(cpu);
1120 acpi_UserNotify("PROCESSOR", sc->cpu_handle, notify);
1124 acpi_cpu_quirks(void)
1129 ACPI_FUNCTION_TRACE((char *)(uintptr_t)__func__);
1132 * Bus mastering arbitration control is needed to keep caches coherent
1133 * while sleeping in C3. If it's not present but a working flush cache
1134 * instruction is present, flush the caches before entering C3 instead.
1135 * Otherwise, just disable C3 completely.
1137 if (AcpiGbl_FADT.Pm2ControlBlock == 0 ||
1138 AcpiGbl_FADT.Pm2ControlLength == 0) {
1139 if ((AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD) &&
1140 (AcpiGbl_FADT.Flags & ACPI_FADT_WBINVD_FLUSH) == 0) {
1141 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1142 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1143 "acpi_cpu: no BM control, using flush cache method\n"));
1145 cpu_quirks |= CPU_QUIRK_NO_C3;
1146 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1147 "acpi_cpu: no BM control, C3 not available\n"));
1152 * If we are using generic Cx mode, C3 on multiple CPUs requires using
1153 * the expensive flush cache instruction.
1155 if (cpu_cx_generic && mp_ncpus > 1) {
1156 cpu_quirks |= CPU_QUIRK_NO_BM_CTRL;
1157 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1158 "acpi_cpu: SMP, using flush cache mode for C3\n"));
1161 /* Look for various quirks of the PIIX4 part. */
1162 acpi_dev = pci_find_device(PCI_VENDOR_INTEL, PCI_DEVICE_82371AB_3);
1163 if (acpi_dev != NULL) {
1164 switch (pci_get_revid(acpi_dev)) {
1166 * Disable C3 support for all PIIX4 chipsets. Some of these parts
1167 * do not report the BMIDE status to the BM status register and
1168 * others have a livelock bug if Type-F DMA is enabled. Linux
1169 * works around the BMIDE bug by reading the BM status directly
1170 * but we take the simpler approach of disabling C3 for these
1173 * See erratum #18 ("C3 Power State/BMIDE and Type-F DMA
1174 * Livelock") from the January 2002 PIIX4 specification update.
1175 * Applies to all PIIX4 models.
1177 * Also, make sure that all interrupts cause a "Stop Break"
1178 * event to exit from C2 state.
1179 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
1180 * should be set to zero, otherwise it causes C2 to short-sleep.
1181 * PIIX4 doesn't properly support C3 and bus master activity
1182 * need not break out of C2.
1184 case PCI_REVISION_A_STEP:
1185 case PCI_REVISION_B_STEP:
1186 case PCI_REVISION_4E:
1187 case PCI_REVISION_4M:
1188 cpu_quirks |= CPU_QUIRK_NO_C3;
1189 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1190 "acpi_cpu: working around PIIX4 bug, disabling C3\n"));
1192 val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
1193 if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
1194 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1195 "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
1196 val |= PIIX4_STOP_BREAK_MASK;
1197 pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
1199 AcpiReadBitRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
1201 ACPI_DEBUG_PRINT((ACPI_DB_INFO,
1202 "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
1203 AcpiWriteBitRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
1215 acpi_cpu_usage_sysctl(SYSCTL_HANDLER_ARGS)
1217 struct acpi_cpu_softc *sc;
1221 uintmax_t fract, sum, whole;
1223 sc = (struct acpi_cpu_softc *) arg1;
1225 for (i = 0; i < sc->cpu_cx_count; i++)
1226 sum += sc->cpu_cx_stats[i];
1227 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1228 for (i = 0; i < sc->cpu_cx_count; i++) {
1230 whole = (uintmax_t)sc->cpu_cx_stats[i] * 100;
1231 fract = (whole % sum) * 100;
1232 sbuf_printf(&sb, "%u.%02u%% ", (u_int)(whole / sum),
1233 (u_int)(fract / sum));
1235 sbuf_printf(&sb, "0.00%% ");
1237 sbuf_printf(&sb, "last %dus", sc->cpu_prev_sleep);
1240 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1247 * XXX TODO: actually add support to count each entry/exit
1248 * from the Cx states.
1251 acpi_cpu_usage_counters_sysctl(SYSCTL_HANDLER_ARGS)
1253 struct acpi_cpu_softc *sc;
1258 sc = (struct acpi_cpu_softc *) arg1;
1260 /* Print out the raw counters */
1261 sbuf_new(&sb, buf, sizeof(buf), SBUF_FIXEDLEN);
1263 for (i = 0; i < sc->cpu_cx_count; i++) {
1264 sbuf_printf(&sb, "%u ", sc->cpu_cx_stats[i]);
1269 sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
1276 acpi_cpu_set_cx_lowest(struct acpi_cpu_softc *sc)
1280 ACPI_SERIAL_ASSERT(cpu);
1281 sc->cpu_cx_lowest = min(sc->cpu_cx_lowest_lim, sc->cpu_cx_count - 1);
1283 /* If not disabling, cache the new lowest non-C3 state. */
1285 for (i = sc->cpu_cx_lowest; i >= 0; i--) {
1286 if (sc->cpu_cx_states[i].type < ACPI_STATE_C3) {
1292 /* Reset the statistics counters. */
1293 bzero(sc->cpu_cx_stats, sizeof(sc->cpu_cx_stats));
1298 acpi_cpu_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1300 struct acpi_cpu_softc *sc;
1304 sc = (struct acpi_cpu_softc *) arg1;
1305 snprintf(state, sizeof(state), "C%d", sc->cpu_cx_lowest_lim + 1);
1306 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1307 if (error != 0 || req->newptr == NULL)
1309 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1311 if (strcasecmp(state, "Cmax") == 0)
1312 val = MAX_CX_STATES;
1314 val = (int) strtol(state + 1, NULL, 10);
1315 if (val < 1 || val > MAX_CX_STATES)
1319 ACPI_SERIAL_BEGIN(cpu);
1320 sc->cpu_cx_lowest_lim = val - 1;
1321 acpi_cpu_set_cx_lowest(sc);
1322 ACPI_SERIAL_END(cpu);
1328 acpi_cpu_global_cx_lowest_sysctl(SYSCTL_HANDLER_ARGS)
1330 struct acpi_cpu_softc *sc;
1334 snprintf(state, sizeof(state), "C%d", cpu_cx_lowest_lim + 1);
1335 error = sysctl_handle_string(oidp, state, sizeof(state), req);
1336 if (error != 0 || req->newptr == NULL)
1338 if (strlen(state) < 2 || toupper(state[0]) != 'C')
1340 if (strcasecmp(state, "Cmax") == 0)
1341 val = MAX_CX_STATES;
1343 val = (int) strtol(state + 1, NULL, 10);
1344 if (val < 1 || val > MAX_CX_STATES)
1348 /* Update the new lowest useable Cx state for all CPUs. */
1349 ACPI_SERIAL_BEGIN(cpu);
1350 cpu_cx_lowest_lim = val - 1;
1351 for (i = 0; i < cpu_ndevices; i++) {
1352 sc = device_get_softc(cpu_devices[i]);
1353 sc->cpu_cx_lowest_lim = cpu_cx_lowest_lim;
1354 acpi_cpu_set_cx_lowest(sc);
1356 ACPI_SERIAL_END(cpu);