sys/dev/acpica/acpi_hpet.c

   1 /*-
   2  * Copyright (c) 2005 Poul-Henning Kamp
   3  * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_acpi.h"
  32 #if defined(__amd64__) || defined(__ia64__)
  33 #define DEV_APIC
  34 #else
  35 #include "opt_apic.h"
  36 #endif
  37 #include <sys/param.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/module.h>
  41 #include <sys/proc.h>
  42 #include <sys/rman.h>
  43 #include <sys/time.h>
  44 #include <sys/smp.h>
  45 #include <sys/sysctl.h>
  46 #include <sys/timeet.h>
  47 #include <sys/timetc.h>
  48
  49 #include <contrib/dev/acpica/include/acpi.h>
  50 #include <contrib/dev/acpica/include/accommon.h>
  51
  52 #include <dev/acpica/acpivar.h>
  53 #include <dev/acpica/acpi_hpet.h>
  54
  55 #ifdef DEV_APIC
  56 #include "pcib_if.h"
  57 #endif
  58
  59 #define HPET_VENDID_AMD         0x4353
  60 #define HPET_VENDID_INTEL       0x8086
  61 #define HPET_VENDID_NVIDIA      0x10de
  62 #define HPET_VENDID_SW          0x1166
  63
  64 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
  65
  66 static devclass_t hpet_devclass;
  67
  68 /* ACPI CA debugging */
  69 #define _COMPONENT      ACPI_TIMER
  70 ACPI_MODULE_NAME("HPET")
  71
  72 struct hpet_softc {
  73         device_t                dev;
  74         int                     mem_rid;
  75         int                     intr_rid;
  76         int                     irq;
  77         int                     useirq;
  78         int                     legacy_route;
  79         int                     per_cpu;
  80         uint32_t                allowed_irqs;
  81         struct resource         *mem_res;
  82         struct resource         *intr_res;
  83         void                    *intr_handle;
  84         ACPI_HANDLE             handle;
  85         uint64_t                freq;
  86         uint32_t                caps;
  87         struct timecounter      tc;
  88         struct hpet_timer {
  89                 struct eventtimer       et;
  90                 struct hpet_softc       *sc;
  91                 int                     num;
  92                 int                     mode;
  93                 int                     intr_rid;
  94                 int                     irq;
  95                 int                     pcpu_cpu;
  96                 int                     pcpu_misrouted;
  97                 int                     pcpu_master;
  98                 int                     pcpu_slaves[MAXCPU];
  99                 struct resource         *intr_res;
 100                 void                    *intr_handle;
 101                 uint32_t                caps;
 102                 uint32_t                vectors;
 103                 uint32_t                div;
 104                 uint32_t                next;
 105                 char                    name[8];
 106         }                       t[32];
 107         int                     num_timers;
 108 };
 109
 110 static u_int hpet_get_timecount(struct timecounter *tc);
 111 static void hpet_test(struct hpet_softc *sc);
 112
 113 static char *hpet_ids[] = { "PNP0103", NULL };
 114
 115 static u_int
 116 hpet_get_timecount(struct timecounter *tc)
 117 {
 118         struct hpet_softc *sc;
 119
 120         sc = tc->tc_priv;
 121         return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
 122 }
 123
 124 static void
 125 hpet_enable(struct hpet_softc *sc)
 126 {
 127         uint32_t val;
 128
 129         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 130         if (sc->legacy_route)
 131                 val |= HPET_CNF_LEG_RT;
 132         else
 133                 val &= ~HPET_CNF_LEG_RT;
 134         val |= HPET_CNF_ENABLE;
 135         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 136 }
 137
 138 static void
 139 hpet_disable(struct hpet_softc *sc)
 140 {
 141         uint32_t val;
 142
 143         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 144         val &= ~HPET_CNF_ENABLE;
 145         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 146 }
 147
 148 static int
 149 hpet_start(struct eventtimer *et,
 150     struct bintime *first, struct bintime *period)
 151 {
 152         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 153         struct hpet_timer *t;
 154         struct hpet_softc *sc = mt->sc;
 155         uint32_t fdiv, now;
 156
 157         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 158         if (period != NULL) {
 159                 t->mode = 1;
 160                 t->div = (sc->freq * (period->frac >> 32)) >> 32;
 161                 if (period->sec != 0)
 162                         t->div += sc->freq * period->sec;
 163         } else {
 164                 t->mode = 2;
 165                 t->div = 0;
 166         }
 167         if (first != NULL) {
 168                 fdiv = (sc->freq * (first->frac >> 32)) >> 32;
 169                 if (first->sec != 0)
 170                         fdiv += sc->freq * first->sec;
 171         } else
 172                 fdiv = t->div;
 173         if (t->irq < 0)
 174                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 175         t->caps |= HPET_TCNF_INT_ENB;
 176         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 177 restart:
 178         t->next = now + fdiv;
 179         if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 180                 t->caps |= HPET_TCNF_TYPE;
 181                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 182                     t->caps | HPET_TCNF_VAL_SET);
 183                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 184                     t->next);
 185                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 186                     t->div);
 187         } else {
 188                 t->caps &= ~HPET_TCNF_TYPE;
 189                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 190                     t->caps);
 191                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 192                     t->next);
 193         }
 194         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 195         if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
 196                 fdiv *= 2;
 197                 goto restart;
 198         }
 199         return (0);
 200 }
 201
 202 static int
 203 hpet_stop(struct eventtimer *et)
 204 {
 205         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 206         struct hpet_timer *t;
 207         struct hpet_softc *sc = mt->sc;
 208
 209         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 210         t->mode = 0;
 211         t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
 212         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 213         return (0);
 214 }
 215
 216 static int
 217 hpet_intr_single(void *arg)
 218 {
 219         struct hpet_timer *t = (struct hpet_timer *)arg;
 220         struct hpet_timer *mt;
 221         struct hpet_softc *sc = t->sc;
 222         uint32_t now;
 223
 224         if (t->mode == 0)
 225                 return (FILTER_STRAY);
 226         /* Check that per-CPU timer interrupt reached right CPU. */
 227         if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
 228                 if ((++t->pcpu_misrouted) % 32 == 0) {
 229                         printf("HPET interrupt routed to the wrong CPU"
 230                             " (timer %d CPU %d -> %d)!\n",
 231                             t->num, t->pcpu_cpu, curcpu);
 232                 }
 233
 234                 /*
 235                  * Reload timer, hoping that next time may be more lucky
 236                  * (system will manage proper interrupt binding).
 237                  */
 238                 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
 239                     t->mode == 2) {
 240                         t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
 241                             sc->freq / 8;
 242                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 243                             t->next);
 244                 }
 245                 return (FILTER_HANDLED);
 246         }
 247         if (t->mode == 1 &&
 248             (t->caps & HPET_TCAP_PER_INT) == 0) {
 249                 t->next += t->div;
 250                 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 251                 if ((int32_t)((now + t->div / 2) - t->next) > 0)
 252                         t->next = now + t->div / 2;
 253                 bus_write_4(sc->mem_res,
 254                     HPET_TIMER_COMPARATOR(t->num), t->next);
 255         } else if (t->mode == 2)
 256                 t->mode = 0;
 257         mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
 258         if (mt->et.et_active)
 259                 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
 260         return (FILTER_HANDLED);
 261 }
 262
 263 static int
 264 hpet_intr(void *arg)
 265 {
 266         struct hpet_softc *sc = (struct hpet_softc *)arg;
 267         int i;
 268         uint32_t val;
 269
 270         val = bus_read_4(sc->mem_res, HPET_ISR);
 271         if (val) {
 272                 bus_write_4(sc->mem_res, HPET_ISR, val);
 273                 val &= sc->useirq;
 274                 for (i = 0; i < sc->num_timers; i++) {
 275                         if ((val & (1 << i)) == 0)
 276                                 continue;
 277                         hpet_intr_single(&sc->t[i]);
 278                 }
 279                 return (FILTER_HANDLED);
 280         }
 281         return (FILTER_STRAY);
 282 }
 283
 284 static ACPI_STATUS
 285 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
 286     void **status)
 287 {
 288         char            **ids;
 289         uint32_t        id = (uint32_t)(uintptr_t)context;
 290         uint32_t        uid = 0;
 291
 292         for (ids = hpet_ids; *ids != NULL; ids++) {
 293                 if (acpi_MatchHid(handle, *ids))
 294                         break;
 295         }
 296         if (*ids == NULL)
 297                 return (AE_OK);
 298         if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
 299             id == uid)
 300                 *((int *)status) = 1;
 301         return (AE_OK);
 302 }
 303
 304 /*
 305  * Find an existing IRQ resource that matches the requested IRQ range
 306  * and return its RID.  If one is not found, use a new RID.
 307  */
 308 static int
 309 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
 310 {
 311         u_long irq;
 312         int error, rid;
 313
 314         for (rid = 0;; rid++) {
 315                 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
 316                 if (error != 0 || (start <= irq && irq <= end))
 317                         return (rid);
 318         }
 319 }
 320
 321 /* Discover the HPET via the ACPI table of the same name. */
 322 static void
 323 hpet_identify(driver_t *driver, device_t parent)
 324 {
 325         ACPI_TABLE_HPET *hpet;
 326         ACPI_STATUS     status;
 327         device_t        child;
 328         int             i, found;
 329
 330         /* Only one HPET device can be added. */
 331         if (devclass_get_device(hpet_devclass, 0))
 332                 return;
 333         for (i = 1; ; i++) {
 334                 /* Search for HPET table. */
 335                 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
 336                 if (ACPI_FAILURE(status))
 337                         return;
 338                 /* Search for HPET device with same ID. */
 339                 found = 0;
 340                 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
 341                     100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence, (void *)&found);
 342                 /* If found - let it be probed in normal way. */
 343                 if (found)
 344                         continue;
 345                 /* If not - create it from table info. */
 346                 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
 347                 if (child == NULL) {
 348                         printf("%s: can't add child\n", __func__);
 349                         continue;
 350                 }
 351                 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
 352                     HPET_MEM_WIDTH);
 353         }
 354 }
 355
 356 static int
 357 hpet_probe(device_t dev)
 358 {
 359         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 360
 361         if (acpi_disabled("hpet"))
 362                 return (ENXIO);
 363         if (acpi_get_handle(dev) != NULL &&
 364             ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
 365                 return (ENXIO);
 366
 367         device_set_desc(dev, "High Precision Event Timer");
 368         return (0);
 369 }
 370
 371 static int
 372 hpet_attach(device_t dev)
 373 {
 374         struct hpet_softc *sc;
 375         struct hpet_timer *t;
 376         int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
 377         int pcpu_master;
 378         static int maxhpetet = 0;
 379         uint32_t val, val2, cvectors, dvectors;
 380         uint16_t vendor, rev;
 381
 382         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 383
 384         sc = device_get_softc(dev);
 385         sc->dev = dev;
 386         sc->handle = acpi_get_handle(dev);
 387
 388         sc->mem_rid = 0;
 389         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 390             RF_ACTIVE);
 391         if (sc->mem_res == NULL)
 392                 return (ENOMEM);
 393
 394         /* Validate that we can access the whole region. */
 395         if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
 396                 device_printf(dev, "memory region width %ld too small\n",
 397                     rman_get_size(sc->mem_res));
 398                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 399                 return (ENXIO);
 400         }
 401
 402         /* Be sure timer is enabled. */
 403         hpet_enable(sc);
 404
 405         /* Read basic statistics about the timer. */
 406         val = bus_read_4(sc->mem_res, HPET_PERIOD);
 407         if (val == 0) {
 408                 device_printf(dev, "invalid period\n");
 409                 hpet_disable(sc);
 410                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 411                 return (ENXIO);
 412         }
 413
 414         sc->freq = (1000000000000000LL + val / 2) / val;
 415         sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
 416         vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
 417         rev = sc->caps & HPET_CAP_REV_ID;
 418         num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
 419         /*
 420          * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
 421          * Specification and provides an off by one number
 422          * of timers/comparators.
 423          * Additionally, they use unregistered value in VENDOR_ID field.
 424          */
 425         if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
 426                 num_timers--;
 427         sc->num_timers = num_timers;
 428         if (bootverbose) {
 429                 device_printf(dev,
 430                     "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
 431                     vendor, rev, sc->freq,
 432                     (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
 433                     num_timers,
 434                     (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
 435         }
 436         for (i = 0; i < num_timers; i++) {
 437                 t = &sc->t[i];
 438                 t->sc = sc;
 439                 t->num = i;
 440                 t->mode = 0;
 441                 t->intr_rid = -1;
 442                 t->irq = -1;
 443                 t->pcpu_cpu = -1;
 444                 t->pcpu_misrouted = 0;
 445                 t->pcpu_master = -1;
 446                 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
 447                 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
 448                 if (bootverbose) {
 449                         device_printf(dev,
 450                             " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
 451                             t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
 452                             (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
 453                             (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
 454                             (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
 455                 }
 456         }
 457         if (testenv("debug.acpi.hpet_test"))
 458                 hpet_test(sc);
 459         /*
 460          * Don't attach if the timer never increments.  Since the spec
 461          * requires it to be at least 10 MHz, it has to change in 1 us.
 462          */
 463         val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 464         DELAY(1);
 465         val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 466         if (val == val2) {
 467                 device_printf(dev, "HPET never increments, disabling\n");
 468                 hpet_disable(sc);
 469                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 470                 return (ENXIO);
 471         }
 472         /* Announce first HPET as timecounter. */
 473         if (device_get_unit(dev) == 0) {
 474                 sc->tc.tc_get_timecount = hpet_get_timecount,
 475                 sc->tc.tc_counter_mask = ~0u,
 476                 sc->tc.tc_name = "HPET",
 477                 sc->tc.tc_quality = 950,
 478                 sc->tc.tc_frequency = sc->freq;
 479                 sc->tc.tc_priv = sc;
 480                 tc_init(&sc->tc);
 481         }
 482         /* If not disabled - setup and announce event timers. */
 483         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 484              "clock", &i) == 0 && i == 0)
 485                 return (0);
 486
 487         /* Check whether we can and want legacy routing. */
 488         sc->legacy_route = 0;
 489         resource_int_value(device_get_name(dev), device_get_unit(dev),
 490              "legacy_route", &sc->legacy_route);
 491         if ((sc->caps & HPET_CAP_LEG_RT) == 0)
 492                 sc->legacy_route = 0;
 493         if (sc->legacy_route) {
 494                 sc->t[0].vectors = 0;
 495                 sc->t[1].vectors = 0;
 496         }
 497
 498         /* Check what IRQs we want use. */
 499         /* By default allow any PCI IRQs. */
 500         sc->allowed_irqs = 0xffff0000;
 501         /*
 502          * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
 503          * Lower are also not always working for different reasons.
 504          * SB800 fixed it, but seems do not implements level triggering
 505          * properly, that makes it very unreliable - it freezes after any
 506          * interrupt loss. Avoid legacy IRQs for AMD.
 507          */
 508         if (vendor == HPET_VENDID_AMD)
 509                 sc->allowed_irqs = 0x00000000;
 510         /*
 511          * NVidia MCP5x chipsets have number of unexplained interrupt
 512          * problems. For some reason, using HPET interrupts breaks HDA sound.
 513          */
 514         if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
 515                 sc->allowed_irqs = 0x00000000;
 516         /*
 517          * ServerWorks HT1000 reported to have problems with IRQs >= 16.
 518          * Lower IRQs are working, but allowed mask is not set correctly.
 519          * Legacy_route mode works fine.
 520          */
 521         if (vendor == HPET_VENDID_SW && rev <= 0x01)
 522                 sc->allowed_irqs = 0x00000000;
 523         /*
 524          * Neither QEMU nor VirtualBox report supported IRQs correctly.
 525          * The only way to use HPET there is to specify IRQs manually
 526          * and/or use legacy_route. Legacy_route mode works on both.
 527          */
 528         if (vm_guest)
 529                 sc->allowed_irqs = 0x00000000;
 530         /* Let user override. */
 531         resource_int_value(device_get_name(dev), device_get_unit(dev),
 532              "allowed_irqs", &sc->allowed_irqs);
 533
 534         /* Get how much per-CPU timers we should try to provide. */
 535         sc->per_cpu = 1;
 536         resource_int_value(device_get_name(dev), device_get_unit(dev),
 537              "per_cpu", &sc->per_cpu);
 538
 539         num_msi = 0;
 540         sc->useirq = 0;
 541         /* Find IRQ vectors for all timers. */
 542         cvectors = sc->allowed_irqs & 0xffff0000;
 543         dvectors = sc->allowed_irqs & 0x0000ffff;
 544         if (sc->legacy_route)
 545                 dvectors &= 0x0000fefe;
 546         for (i = 0; i < num_timers; i++) {
 547                 t = &sc->t[i];
 548                 if (sc->legacy_route && i < 2)
 549                         t->irq = (i == 0) ? 0 : 8;
 550 #ifdef DEV_APIC
 551                 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
 552                         if ((j = PCIB_ALLOC_MSIX(
 553                             device_get_parent(device_get_parent(dev)), dev,
 554                             &t->irq))) {
 555                                 device_printf(dev,
 556                                     "Can't allocate interrupt for t%d.\n", j);
 557                         }
 558                 }
 559 #endif
 560                 else if (dvectors & t->vectors) {
 561                         t->irq = ffs(dvectors & t->vectors) - 1;
 562                         dvectors &= ~(1 << t->irq);
 563                 }
 564                 if (t->irq >= 0) {
 565                         t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
 566                         t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 567                             &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
 568                         if (t->intr_res == NULL) {
 569                                 t->irq = -1;
 570                                 device_printf(dev,
 571                                     "Can't map interrupt for t%d.\n", i);
 572                         } else if (bus_setup_intr(dev, t->intr_res,
 573                             INTR_TYPE_CLK, hpet_intr_single, NULL, t,
 574                             &t->intr_handle) != 0) {
 575                                 t->irq = -1;
 576                                 device_printf(dev,
 577                                     "Can't setup interrupt for t%d.\n", i);
 578                         } else {
 579                                 bus_describe_intr(dev, t->intr_res,
 580                                     t->intr_handle, "t%d", i);
 581                                 num_msi++;
 582                         }
 583                 }
 584                 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
 585                         cvectors &= t->vectors;
 586                         sc->useirq |= (1 << i);
 587                 }
 588         }
 589         if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
 590                 sc->legacy_route = 0;
 591         if (sc->legacy_route)
 592                 hpet_enable(sc);
 593         /* Group timers for per-CPU operation. */
 594         num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
 595         num_percpu_t = num_percpu_et * mp_ncpus;
 596         pcpu_master = 0;
 597         cur_cpu = CPU_FIRST();
 598         for (i = 0; i < num_timers; i++) {
 599                 t = &sc->t[i];
 600                 if (t->irq >= 0 && num_percpu_t > 0) {
 601                         if (cur_cpu == CPU_FIRST())
 602                                 pcpu_master = i;
 603                         t->pcpu_cpu = cur_cpu;
 604                         t->pcpu_master = pcpu_master;
 605                         sc->t[pcpu_master].
 606                             pcpu_slaves[cur_cpu] = i;
 607                         bus_bind_intr(dev, t->intr_res, cur_cpu);
 608                         cur_cpu = CPU_NEXT(cur_cpu);
 609                         num_percpu_t--;
 610                 } else if (t->irq >= 0)
 611                         bus_bind_intr(dev, t->intr_res, CPU_FIRST());
 612         }
 613         bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
 614         sc->irq = -1;
 615         /* If at least one timer needs legacy IRQ - set it up. */
 616         if (sc->useirq) {
 617                 j = i = fls(cvectors) - 1;
 618                 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
 619                         j--;
 620                 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
 621                 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 622                     &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
 623                 if (sc->intr_res == NULL)
 624                         device_printf(dev, "Can't map interrupt.\n");
 625                 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
 626                     hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
 627                         device_printf(dev, "Can't setup interrupt.\n");
 628                 } else {
 629                         sc->irq = rman_get_start(sc->intr_res);
 630                         /* Bind IRQ to BSP to avoid live migration. */
 631                         bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
 632                 }
 633         }
 634         /* Program and announce event timers. */
 635         for (i = 0; i < num_timers; i++) {
 636                 t = &sc->t[i];
 637                 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
 638                 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
 639                 t->caps &= ~(HPET_TCNF_INT_TYPE);
 640                 t->caps |= HPET_TCNF_32MODE;
 641                 if (t->irq >= 0 && sc->legacy_route && i < 2) {
 642                         /* Legacy route doesn't need more configuration. */
 643                 } else
 644 #ifdef DEV_APIC
 645                 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
 646                         uint64_t addr;
 647                         uint32_t data;
 648
 649                         if (PCIB_MAP_MSI(
 650                             device_get_parent(device_get_parent(dev)), dev,
 651                             t->irq, &addr, &data) == 0) {
 652                                 bus_write_4(sc->mem_res,
 653                                     HPET_TIMER_FSB_ADDR(i), addr);
 654                                 bus_write_4(sc->mem_res,
 655                                     HPET_TIMER_FSB_VAL(i), data);
 656                                 t->caps |= HPET_TCNF_FSB_EN;
 657                         } else
 658                                 t->irq = -2;
 659                 } else
 660 #endif
 661                 if (t->irq >= 0)
 662                         t->caps |= (t->irq << 9);
 663                 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
 664                         t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
 665                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
 666                 /* Skip event timers without set up IRQ. */
 667                 if (t->irq < 0 &&
 668                     (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
 669                         continue;
 670                 /* Announce the reset. */
 671                 if (maxhpetet == 0)
 672                         t->et.et_name = "HPET";
 673                 else {
 674                         sprintf(t->name, "HPET%d", maxhpetet);
 675                         t->et.et_name = t->name;
 676                 }
 677                 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 678                 t->et.et_quality = 450;
 679                 if (t->pcpu_master >= 0) {
 680                         t->et.et_flags |= ET_FLAGS_PERCPU;
 681                         t->et.et_quality += 100;
 682                 }
 683                 if ((t->caps & HPET_TCAP_PER_INT) == 0)
 684                         t->et.et_quality -= 10;
 685                 t->et.et_frequency = sc->freq;
 686                 t->et.et_min_period.sec = 0;
 687                 t->et.et_min_period.frac =
 688                     (((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq) << 32;
 689                 t->et.et_max_period.sec = 0xfffffffeLLU / sc->freq;
 690                 t->et.et_max_period.frac =
 691                     ((0xfffffffeLLU << 32) / sc->freq) << 32;
 692                 t->et.et_start = hpet_start;
 693                 t->et.et_stop = hpet_stop;
 694                 t->et.et_priv = &sc->t[i];
 695                 if (t->pcpu_master < 0 || t->pcpu_master == i) {
 696                         et_register(&t->et);
 697                         maxhpetet++;
 698                 }
 699         }
 700         return (0);
 701 }
 702
 703 static int
 704 hpet_detach(device_t dev)
 705 {
 706         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 707
 708         /* XXX Without a tc_remove() function, we can't detach. */
 709         return (EBUSY);
 710 }
 711
 712 static int
 713 hpet_suspend(device_t dev)
 714 {
 715 //      struct hpet_softc *sc;
 716
 717         /*
 718          * Disable the timer during suspend.  The timer will not lose
 719          * its state in S1 or S2, but we are required to disable
 720          * it.
 721          */
 722 //      sc = device_get_softc(dev);
 723 //      hpet_disable(sc);
 724
 725         return (0);
 726 }
 727
 728 static int
 729 hpet_resume(device_t dev)
 730 {
 731         struct hpet_softc *sc;
 732         struct hpet_timer *t;
 733         int i;
 734
 735         /* Re-enable the timer after a resume to keep the clock advancing. */
 736         sc = device_get_softc(dev);
 737         hpet_enable(sc);
 738         /* Restart event timers that were running on suspend. */
 739         for (i = 0; i < sc->num_timers; i++) {
 740                 t = &sc->t[i];
 741 #ifdef DEV_APIC
 742                 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
 743                         uint64_t addr;
 744                         uint32_t data;
 745
 746                         if (PCIB_MAP_MSI(
 747                             device_get_parent(device_get_parent(dev)), dev,
 748                             t->irq, &addr, &data) == 0) {
 749                                 bus_write_4(sc->mem_res,
 750                                     HPET_TIMER_FSB_ADDR(i), addr);
 751                                 bus_write_4(sc->mem_res,
 752                                     HPET_TIMER_FSB_VAL(i), data);
 753                         }
 754                 }
 755 #endif
 756                 if (t->mode == 0)
 757                         continue;
 758                 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 759                 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 760                         t->caps |= HPET_TCNF_TYPE;
 761                         t->next += t->div;
 762                         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 763                             t->caps | HPET_TCNF_VAL_SET);
 764                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 765                             t->next);
 766                         bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
 767                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 768                             t->div);
 769                 } else {
 770                         t->next += sc->freq / 1024;
 771                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 772                             t->next);
 773                 }
 774                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 775                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 776         }
 777         return (0);
 778 }
 779
 780 /* Print some basic latency/rate information to assist in debugging. */
 781 static void
 782 hpet_test(struct hpet_softc *sc)
 783 {
 784         int i;
 785         uint32_t u1, u2;
 786         struct bintime b0, b1, b2;
 787         struct timespec ts;
 788
 789         binuptime(&b0);
 790         binuptime(&b0);
 791         binuptime(&b1);
 792         u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 793         for (i = 1; i < 1000; i++)
 794                 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 795         binuptime(&b2);
 796         u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 797
 798         bintime_sub(&b2, &b1);
 799         bintime_sub(&b1, &b0);
 800         bintime_sub(&b2, &b1);
 801         bintime2timespec(&b2, &ts);
 802
 803         device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
 804             (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
 805
 806         device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
 807 }
 808
 809 #ifdef DEV_APIC
 810 static int
 811 hpet_remap_intr(device_t dev, device_t child, u_int irq)
 812 {
 813         struct hpet_softc *sc = device_get_softc(dev);
 814         struct hpet_timer *t;
 815         uint64_t addr;
 816         uint32_t data;
 817         int error, i;
 818
 819         for (i = 0; i < sc->num_timers; i++) {
 820                 t = &sc->t[i];
 821                 if (t->irq != irq)
 822                         continue;
 823                 error = PCIB_MAP_MSI(
 824                     device_get_parent(device_get_parent(dev)), dev,
 825                     irq, &addr, &data);
 826                 if (error)
 827                         return (error);
 828                 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
 829                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
 830                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
 831                 hpet_enable(sc);
 832                 return (0);
 833         }
 834         return (ENOENT);
 835 }
 836 #endif
 837
 838 static device_method_t hpet_methods[] = {
 839         /* Device interface */
 840         DEVMETHOD(device_identify, hpet_identify),
 841         DEVMETHOD(device_probe, hpet_probe),
 842         DEVMETHOD(device_attach, hpet_attach),
 843         DEVMETHOD(device_detach, hpet_detach),
 844         DEVMETHOD(device_suspend, hpet_suspend),
 845         DEVMETHOD(device_resume, hpet_resume),
 846
 847 #ifdef DEV_APIC
 848         DEVMETHOD(bus_remap_intr, hpet_remap_intr),
 849 #endif
 850
 851         {0, 0}
 852 };
 853
 854 static driver_t hpet_driver = {
 855         "hpet",
 856         hpet_methods,
 857         sizeof(struct hpet_softc),
 858 };
 859
 860 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
 861 MODULE_DEPEND(hpet, acpi, 1, 1, 1);