2 * Copyright (c) 2005 Poul-Henning Kamp
3 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #if defined(__amd64__)
38 #include <sys/param.h>
41 #include <sys/kernel.h>
42 #include <sys/module.h>
48 #include <sys/sysctl.h>
49 #include <sys/timeet.h>
50 #include <sys/timetc.h>
53 #include <contrib/dev/acpica/include/acpi.h>
54 #include <contrib/dev/acpica/include/accommon.h>
56 #include <dev/acpica/acpivar.h>
57 #include <dev/acpica/acpi_hpet.h>
63 #define HPET_VENDID_AMD 0x4353
64 #define HPET_VENDID_AMD2 0x1022
65 #define HPET_VENDID_HYGON 0x1d94
66 #define HPET_VENDID_INTEL 0x8086
67 #define HPET_VENDID_NVIDIA 0x10de
68 #define HPET_VENDID_SW 0x1166
70 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
72 static devclass_t hpet_devclass;
74 /* ACPI CA debugging */
75 #define _COMPONENT ACPI_TIMER
76 ACPI_MODULE_NAME("HPET")
86 uint32_t allowed_irqs;
87 struct resource *mem_res;
88 struct resource *intr_res;
94 struct timecounter tc;
97 struct hpet_softc *sc;
100 #define TIMER_STOPPED 0
101 #define TIMER_PERIODIC 1
102 #define TIMER_ONESHOT 2
108 int pcpu_slaves[MAXCPU];
109 struct resource *intr_res;
120 int mmap_allow_write;
123 static d_open_t hpet_open;
124 static d_mmap_t hpet_mmap;
126 static struct cdevsw hpet_cdevsw = {
127 .d_version = D_VERSION,
133 static u_int hpet_get_timecount(struct timecounter *tc);
134 static void hpet_test(struct hpet_softc *sc);
136 static char *hpet_ids[] = { "PNP0103", NULL };
138 /* Knob to disable acpi_hpet device */
139 bool acpi_hpet_disabled = false;
142 hpet_get_timecount(struct timecounter *tc)
144 struct hpet_softc *sc;
147 return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
151 hpet_vdso_timehands(struct vdso_timehands *vdso_th, struct timecounter *tc)
153 struct hpet_softc *sc;
156 vdso_th->th_algo = VDSO_TH_ALGO_X86_HPET;
157 vdso_th->th_x86_shift = 0;
158 vdso_th->th_x86_hpet_idx = device_get_unit(sc->dev);
159 bzero(vdso_th->th_res, sizeof(vdso_th->th_res));
160 return (sc->mmap_allow != 0);
163 #ifdef COMPAT_FREEBSD32
165 hpet_vdso_timehands32(struct vdso_timehands32 *vdso_th32,
166 struct timecounter *tc)
168 struct hpet_softc *sc;
171 vdso_th32->th_algo = VDSO_TH_ALGO_X86_HPET;
172 vdso_th32->th_x86_shift = 0;
173 vdso_th32->th_x86_hpet_idx = device_get_unit(sc->dev);
174 bzero(vdso_th32->th_res, sizeof(vdso_th32->th_res));
175 return (sc->mmap_allow != 0);
180 hpet_enable(struct hpet_softc *sc)
184 val = bus_read_4(sc->mem_res, HPET_CONFIG);
185 if (sc->legacy_route)
186 val |= HPET_CNF_LEG_RT;
188 val &= ~HPET_CNF_LEG_RT;
189 val |= HPET_CNF_ENABLE;
190 bus_write_4(sc->mem_res, HPET_CONFIG, val);
194 hpet_disable(struct hpet_softc *sc)
198 val = bus_read_4(sc->mem_res, HPET_CONFIG);
199 val &= ~HPET_CNF_ENABLE;
200 bus_write_4(sc->mem_res, HPET_CONFIG, val);
204 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
206 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
207 struct hpet_timer *t;
208 struct hpet_softc *sc = mt->sc;
211 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
213 t->mode = TIMER_PERIODIC;
214 t->div = (sc->freq * period) >> 32;
216 t->mode = TIMER_ONESHOT;
220 fdiv = (sc->freq * first) >> 32;
224 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
225 t->caps |= HPET_TCNF_INT_ENB;
226 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
228 t->next = now + fdiv;
229 if (t->mode == TIMER_PERIODIC && (t->caps & HPET_TCAP_PER_INT)) {
230 t->caps |= HPET_TCNF_TYPE;
231 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
232 t->caps | HPET_TCNF_VAL_SET);
233 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
235 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
238 t->caps &= ~HPET_TCNF_TYPE;
239 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
241 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
244 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
245 if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
253 hpet_stop(struct eventtimer *et)
255 struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
256 struct hpet_timer *t;
257 struct hpet_softc *sc = mt->sc;
259 t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
260 t->mode = TIMER_STOPPED;
261 t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
262 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
267 hpet_intr_single(void *arg)
269 struct hpet_timer *t = (struct hpet_timer *)arg;
270 struct hpet_timer *mt;
271 struct hpet_softc *sc = t->sc;
274 if (t->mode == TIMER_STOPPED)
275 return (FILTER_STRAY);
276 /* Check that per-CPU timer interrupt reached right CPU. */
277 if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
278 if ((++t->pcpu_misrouted) % 32 == 0) {
279 printf("HPET interrupt routed to the wrong CPU"
280 " (timer %d CPU %d -> %d)!\n",
281 t->num, t->pcpu_cpu, curcpu);
285 * Reload timer, hoping that next time may be more lucky
286 * (system will manage proper interrupt binding).
288 if ((t->mode == TIMER_PERIODIC &&
289 (t->caps & HPET_TCAP_PER_INT) == 0) ||
290 t->mode == TIMER_ONESHOT) {
291 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
293 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
296 return (FILTER_HANDLED);
298 if (t->mode == TIMER_PERIODIC &&
299 (t->caps & HPET_TCAP_PER_INT) == 0) {
301 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
302 if ((int32_t)((now + t->div / 2) - t->next) > 0)
303 t->next = now + t->div / 2;
304 bus_write_4(sc->mem_res,
305 HPET_TIMER_COMPARATOR(t->num), t->next);
306 } else if (t->mode == TIMER_ONESHOT)
307 t->mode = TIMER_STOPPED;
308 mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
309 if (mt->et.et_active)
310 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
311 return (FILTER_HANDLED);
317 struct hpet_softc *sc = (struct hpet_softc *)arg;
321 val = bus_read_4(sc->mem_res, HPET_ISR);
323 bus_write_4(sc->mem_res, HPET_ISR, val);
325 for (i = 0; i < sc->num_timers; i++) {
326 if ((val & (1 << i)) == 0)
328 hpet_intr_single(&sc->t[i]);
330 return (FILTER_HANDLED);
332 return (FILTER_STRAY);
336 hpet_get_uid(device_t dev)
338 struct hpet_softc *sc;
340 sc = device_get_softc(dev);
341 return (sc->acpi_uid);
345 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
349 uint32_t id = (uint32_t)(uintptr_t)context;
352 for (ids = hpet_ids; *ids != NULL; ids++) {
353 if (acpi_MatchHid(handle, *ids))
358 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
360 *status = acpi_get_device(handle);
365 * Find an existing IRQ resource that matches the requested IRQ range
366 * and return its RID. If one is not found, use a new RID.
369 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
374 for (rid = 0;; rid++) {
375 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
376 if (error != 0 || (start <= irq && irq <= end))
382 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td)
384 struct hpet_softc *sc;
394 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,
395 int nprot, vm_memattr_t *memattr)
397 struct hpet_softc *sc;
400 if (offset >= rman_get_size(sc->mem_res))
402 if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
404 *paddr = rman_get_start(sc->mem_res) + offset;
405 *memattr = VM_MEMATTR_UNCACHEABLE;
410 /* Discover the HPET via the ACPI table of the same name. */
412 hpet_identify(driver_t *driver, device_t parent)
414 ACPI_TABLE_HPET *hpet;
419 /* Only one HPET device can be added. */
420 if (devclass_get_device(hpet_devclass, 0))
423 /* Search for HPET table. */
424 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
425 if (ACPI_FAILURE(status))
427 /* Search for HPET device with same ID. */
429 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
430 100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence,
432 /* If found - let it be probed in normal way. */
434 if (bus_get_resource(child, SYS_RES_MEMORY, 0,
436 bus_set_resource(child, SYS_RES_MEMORY, 0,
437 hpet->Address.Address, HPET_MEM_WIDTH);
440 /* If not - create it from table info. */
441 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
443 printf("%s: can't add child\n", __func__);
446 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
452 hpet_probe(device_t dev)
454 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
456 if (acpi_disabled("hpet") || acpi_hpet_disabled)
458 if (acpi_get_handle(dev) != NULL &&
459 ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
462 device_set_desc(dev, "High Precision Event Timer");
467 hpet_attach(device_t dev)
469 struct hpet_softc *sc;
470 struct hpet_timer *t;
471 struct make_dev_args mda;
472 int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
473 int pcpu_master, error;
474 static int maxhpetet = 0;
475 uint32_t val, val2, cvectors, dvectors;
476 uint16_t vendor, rev;
478 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
480 sc = device_get_softc(dev);
482 sc->handle = acpi_get_handle(dev);
485 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
487 if (sc->mem_res == NULL)
490 /* Validate that we can access the whole region. */
491 if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
492 device_printf(dev, "memory region width %jd too small\n",
493 rman_get_size(sc->mem_res));
494 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
498 /* Be sure timer is enabled. */
501 /* Read basic statistics about the timer. */
502 val = bus_read_4(sc->mem_res, HPET_PERIOD);
504 device_printf(dev, "invalid period\n");
506 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
510 sc->freq = (1000000000000000LL + val / 2) / val;
511 sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
512 vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
513 rev = sc->caps & HPET_CAP_REV_ID;
514 num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
516 * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
517 * Specification and provides an off by one number
518 * of timers/comparators.
519 * Additionally, they use unregistered value in VENDOR_ID field.
521 if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
523 sc->num_timers = num_timers;
526 "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
527 vendor, rev, sc->freq,
528 (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
530 (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
532 for (i = 0; i < num_timers; i++) {
536 t->mode = TIMER_STOPPED;
540 t->pcpu_misrouted = 0;
542 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
543 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
546 " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
547 t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
548 (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
549 (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
550 (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
553 if (testenv("debug.acpi.hpet_test"))
556 * Don't attach if the timer never increments. Since the spec
557 * requires it to be at least 10 MHz, it has to change in 1 us.
559 val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
561 val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
563 device_printf(dev, "HPET never increments, disabling\n");
565 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
568 /* Announce first HPET as timecounter. */
569 if (device_get_unit(dev) == 0) {
570 sc->tc.tc_get_timecount = hpet_get_timecount,
571 sc->tc.tc_counter_mask = ~0u,
572 sc->tc.tc_name = "HPET",
573 sc->tc.tc_quality = 950,
574 sc->tc.tc_frequency = sc->freq;
576 sc->tc.tc_fill_vdso_timehands = hpet_vdso_timehands;
577 #ifdef COMPAT_FREEBSD32
578 sc->tc.tc_fill_vdso_timehands32 = hpet_vdso_timehands32;
582 /* If not disabled - setup and announce event timers. */
583 if (resource_int_value(device_get_name(dev), device_get_unit(dev),
584 "clock", &i) == 0 && i == 0)
587 /* Check whether we can and want legacy routing. */
588 sc->legacy_route = 0;
589 resource_int_value(device_get_name(dev), device_get_unit(dev),
590 "legacy_route", &sc->legacy_route);
591 if ((sc->caps & HPET_CAP_LEG_RT) == 0)
592 sc->legacy_route = 0;
593 if (sc->legacy_route) {
594 sc->t[0].vectors = 0;
595 sc->t[1].vectors = 0;
598 /* Check what IRQs we want use. */
599 /* By default allow any PCI IRQs. */
600 sc->allowed_irqs = 0xffff0000;
602 * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
603 * Lower are also not always working for different reasons.
604 * SB800 fixed it, but seems do not implements level triggering
605 * properly, that makes it very unreliable - it freezes after any
606 * interrupt loss. Avoid legacy IRQs for AMD.
608 if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2 ||
609 vendor == HPET_VENDID_HYGON)
610 sc->allowed_irqs = 0x00000000;
612 * NVidia MCP5x chipsets have number of unexplained interrupt
613 * problems. For some reason, using HPET interrupts breaks HDA sound.
615 if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
616 sc->allowed_irqs = 0x00000000;
618 * ServerWorks HT1000 reported to have problems with IRQs >= 16.
619 * Lower IRQs are working, but allowed mask is not set correctly.
620 * Legacy_route mode works fine.
622 if (vendor == HPET_VENDID_SW && rev <= 0x01)
623 sc->allowed_irqs = 0x00000000;
625 * Neither QEMU nor VirtualBox report supported IRQs correctly.
626 * The only way to use HPET there is to specify IRQs manually
627 * and/or use legacy_route. Legacy_route mode works on both.
630 sc->allowed_irqs = 0x00000000;
631 /* Let user override. */
632 resource_int_value(device_get_name(dev), device_get_unit(dev),
633 "allowed_irqs", &sc->allowed_irqs);
635 /* Get how much per-CPU timers we should try to provide. */
637 resource_int_value(device_get_name(dev), device_get_unit(dev),
638 "per_cpu", &sc->per_cpu);
642 /* Find IRQ vectors for all timers. */
643 cvectors = sc->allowed_irqs & 0xffff0000;
644 dvectors = sc->allowed_irqs & 0x0000ffff;
645 if (sc->legacy_route)
646 dvectors &= 0x0000fefe;
647 for (i = 0; i < num_timers; i++) {
649 if (sc->legacy_route && i < 2)
650 t->irq = (i == 0) ? 0 : 8;
652 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
653 if ((j = PCIB_ALLOC_MSIX(
654 device_get_parent(device_get_parent(dev)), dev,
657 "Can't allocate interrupt for t%d: %d\n",
662 else if (dvectors & t->vectors) {
663 t->irq = ffs(dvectors & t->vectors) - 1;
664 dvectors &= ~(1 << t->irq);
667 t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
668 t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
669 &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
670 if (t->intr_res == NULL) {
673 "Can't map interrupt for t%d.\n", i);
674 } else if (bus_setup_intr(dev, t->intr_res,
675 INTR_TYPE_CLK, hpet_intr_single, NULL, t,
676 &t->intr_handle) != 0) {
679 "Can't setup interrupt for t%d.\n", i);
681 bus_describe_intr(dev, t->intr_res,
682 t->intr_handle, "t%d", i);
686 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
687 cvectors &= t->vectors;
688 sc->useirq |= (1 << i);
691 if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
692 sc->legacy_route = 0;
693 if (sc->legacy_route)
695 /* Group timers for per-CPU operation. */
696 num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
697 num_percpu_t = num_percpu_et * mp_ncpus;
699 cur_cpu = CPU_FIRST();
700 for (i = 0; i < num_timers; i++) {
702 if (t->irq >= 0 && num_percpu_t > 0) {
703 if (cur_cpu == CPU_FIRST())
705 t->pcpu_cpu = cur_cpu;
706 t->pcpu_master = pcpu_master;
708 pcpu_slaves[cur_cpu] = i;
709 bus_bind_intr(dev, t->intr_res, cur_cpu);
710 cur_cpu = CPU_NEXT(cur_cpu);
712 } else if (t->irq >= 0)
713 bus_bind_intr(dev, t->intr_res, CPU_FIRST());
715 bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
717 /* If at least one timer needs legacy IRQ - set it up. */
719 j = i = fls(cvectors) - 1;
720 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
722 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
723 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
724 &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
725 if (sc->intr_res == NULL)
726 device_printf(dev, "Can't map interrupt.\n");
727 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
728 hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
729 device_printf(dev, "Can't setup interrupt.\n");
731 sc->irq = rman_get_start(sc->intr_res);
732 /* Bind IRQ to BSP to avoid live migration. */
733 bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
736 /* Program and announce event timers. */
737 for (i = 0; i < num_timers; i++) {
739 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
740 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
741 t->caps &= ~(HPET_TCNF_INT_TYPE);
742 t->caps |= HPET_TCNF_32MODE;
743 if (t->irq >= 0 && sc->legacy_route && i < 2) {
744 /* Legacy route doesn't need more configuration. */
747 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
752 device_get_parent(device_get_parent(dev)), dev,
753 t->irq, &addr, &data) == 0) {
754 bus_write_4(sc->mem_res,
755 HPET_TIMER_FSB_ADDR(i), addr);
756 bus_write_4(sc->mem_res,
757 HPET_TIMER_FSB_VAL(i), data);
758 t->caps |= HPET_TCNF_FSB_EN;
764 t->caps |= (t->irq << 9);
765 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
766 t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
767 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
768 /* Skip event timers without set up IRQ. */
770 (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
772 /* Announce the reset. */
774 t->et.et_name = "HPET";
776 sprintf(t->name, "HPET%d", maxhpetet);
777 t->et.et_name = t->name;
779 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
780 t->et.et_quality = 450;
781 if (t->pcpu_master >= 0) {
782 t->et.et_flags |= ET_FLAGS_PERCPU;
783 t->et.et_quality += 100;
784 } else if (mp_ncpus >= 8)
785 t->et.et_quality -= 100;
786 if ((t->caps & HPET_TCAP_PER_INT) == 0)
787 t->et.et_quality -= 10;
788 t->et.et_frequency = sc->freq;
789 t->et.et_min_period =
790 ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
791 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
792 t->et.et_start = hpet_start;
793 t->et.et_stop = hpet_stop;
794 t->et.et_priv = &sc->t[i];
795 if (t->pcpu_master < 0 || t->pcpu_master == i) {
800 acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid);
802 make_dev_args_init(&mda);
803 mda.mda_devsw = &hpet_cdevsw;
804 mda.mda_uid = UID_ROOT;
805 mda.mda_gid = GID_WHEEL;
807 mda.mda_si_drv1 = sc;
808 error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev));
811 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow",
813 sc->mmap_allow_write = 0;
814 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write",
815 &sc->mmap_allow_write);
816 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
817 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
818 OID_AUTO, "mmap_allow",
819 CTLFLAG_RW, &sc->mmap_allow, 0,
820 "Allow userland to memory map HPET");
821 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
822 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
823 OID_AUTO, "mmap_allow_write",
824 CTLFLAG_RW, &sc->mmap_allow_write, 0,
825 "Allow userland write to the HPET register space");
827 device_printf(dev, "could not create /dev/hpet%d, error %d\n",
828 device_get_unit(dev), error);
835 hpet_detach(device_t dev)
837 ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
839 /* XXX Without a tc_remove() function, we can't detach. */
844 hpet_suspend(device_t dev)
846 // struct hpet_softc *sc;
849 * Disable the timer during suspend. The timer will not lose
850 * its state in S1 or S2, but we are required to disable
853 // sc = device_get_softc(dev);
860 hpet_resume(device_t dev)
862 struct hpet_softc *sc;
863 struct hpet_timer *t;
866 /* Re-enable the timer after a resume to keep the clock advancing. */
867 sc = device_get_softc(dev);
869 /* Restart event timers that were running on suspend. */
870 for (i = 0; i < sc->num_timers; i++) {
873 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
878 device_get_parent(device_get_parent(dev)), dev,
879 t->irq, &addr, &data) == 0) {
880 bus_write_4(sc->mem_res,
881 HPET_TIMER_FSB_ADDR(i), addr);
882 bus_write_4(sc->mem_res,
883 HPET_TIMER_FSB_VAL(i), data);
887 if (t->mode == TIMER_STOPPED)
889 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
890 if (t->mode == TIMER_PERIODIC &&
891 (t->caps & HPET_TCAP_PER_INT) != 0) {
892 t->caps |= HPET_TCNF_TYPE;
894 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
895 t->caps | HPET_TCNF_VAL_SET);
896 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
898 bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
899 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
902 t->next += sc->freq / 1024;
903 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
906 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
907 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
912 /* Print some basic latency/rate information to assist in debugging. */
914 hpet_test(struct hpet_softc *sc)
918 struct bintime b0, b1, b2;
924 u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
925 for (i = 1; i < 1000; i++)
926 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
928 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
930 bintime_sub(&b2, &b1);
931 bintime_sub(&b1, &b0);
932 bintime_sub(&b2, &b1);
933 bintime2timespec(&b2, &ts);
935 device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
936 (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
938 device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
943 hpet_remap_intr(device_t dev, device_t child, u_int irq)
945 struct hpet_softc *sc = device_get_softc(dev);
946 struct hpet_timer *t;
951 for (i = 0; i < sc->num_timers; i++) {
955 error = PCIB_MAP_MSI(
956 device_get_parent(device_get_parent(dev)), dev,
960 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
961 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
962 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
970 static device_method_t hpet_methods[] = {
971 /* Device interface */
972 DEVMETHOD(device_identify, hpet_identify),
973 DEVMETHOD(device_probe, hpet_probe),
974 DEVMETHOD(device_attach, hpet_attach),
975 DEVMETHOD(device_detach, hpet_detach),
976 DEVMETHOD(device_suspend, hpet_suspend),
977 DEVMETHOD(device_resume, hpet_resume),
980 DEVMETHOD(bus_remap_intr, hpet_remap_intr),
986 static driver_t hpet_driver = {
989 sizeof(struct hpet_softc),
992 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
993 MODULE_DEPEND(hpet, acpi, 1, 1, 1);