sys/dev/acpica/acpi_hpet.c

   1 /*-
   2  * Copyright (c) 2005 Poul-Henning Kamp
   3  * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_acpi.h"
  32 #if defined(__amd64__)
  33 #define DEV_APIC
  34 #else
  35 #include "opt_apic.h"
  36 #endif
  37 #include <sys/param.h>
  38 #include <sys/conf.h>
  39 #include <sys/bus.h>
  40 #include <sys/kernel.h>
  41 #include <sys/module.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/mman.h>
  45 #include <sys/time.h>
  46 #include <sys/smp.h>
  47 #include <sys/sysctl.h>
  48 #include <sys/timeet.h>
  49 #include <sys/timetc.h>
  50
  51 #include <contrib/dev/acpica/include/acpi.h>
  52 #include <contrib/dev/acpica/include/accommon.h>
  53
  54 #include <dev/acpica/acpivar.h>
  55 #include <dev/acpica/acpi_hpet.h>
  56
  57 #ifdef DEV_APIC
  58 #include "pcib_if.h"
  59 #endif
  60
  61 #define HPET_VENDID_AMD         0x4353
  62 #define HPET_VENDID_AMD2        0x1022
  63 #define HPET_VENDID_INTEL       0x8086
  64 #define HPET_VENDID_NVIDIA      0x10de
  65 #define HPET_VENDID_SW          0x1166
  66
  67 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
  68
  69 static devclass_t hpet_devclass;
  70
  71 /* ACPI CA debugging */
  72 #define _COMPONENT      ACPI_TIMER
  73 ACPI_MODULE_NAME("HPET")
  74
  75 struct hpet_softc {
  76         device_t                dev;
  77         int                     mem_rid;
  78         int                     intr_rid;
  79         int                     irq;
  80         int                     useirq;
  81         int                     legacy_route;
  82         int                     per_cpu;
  83         uint32_t                allowed_irqs;
  84         struct resource         *mem_res;
  85         struct resource         *intr_res;
  86         void                    *intr_handle;
  87         ACPI_HANDLE             handle;
  88         uint32_t                acpi_uid;
  89         uint64_t                freq;
  90         uint32_t                caps;
  91         struct timecounter      tc;
  92         struct hpet_timer {
  93                 struct eventtimer       et;
  94                 struct hpet_softc       *sc;
  95                 int                     num;
  96                 int                     mode;
  97                 int                     intr_rid;
  98                 int                     irq;
  99                 int                     pcpu_cpu;
 100                 int                     pcpu_misrouted;
 101                 int                     pcpu_master;
 102                 int                     pcpu_slaves[MAXCPU];
 103                 struct resource         *intr_res;
 104                 void                    *intr_handle;
 105                 uint32_t                caps;
 106                 uint32_t                vectors;
 107                 uint32_t                div;
 108                 uint32_t                next;
 109                 char                    name[8];
 110         }                       t[32];
 111         int                     num_timers;
 112         struct cdev             *pdev;
 113         int                     mmap_allow;
 114         int                     mmap_allow_write;
 115 };
 116
 117 static d_open_t hpet_open;
 118 static d_mmap_t hpet_mmap;
 119
 120 static struct cdevsw hpet_cdevsw = {
 121         .d_version =    D_VERSION,
 122         .d_name =       "hpet",
 123         .d_open =       hpet_open,
 124         .d_mmap =       hpet_mmap,
 125 };
 126
 127 static u_int hpet_get_timecount(struct timecounter *tc);
 128 static void hpet_test(struct hpet_softc *sc);
 129
 130 static char *hpet_ids[] = { "PNP0103", NULL };
 131
 132 /* Knob to disable acpi_hpet device */
 133 bool acpi_hpet_disabled = false;
 134
 135 static u_int
 136 hpet_get_timecount(struct timecounter *tc)
 137 {
 138         struct hpet_softc *sc;
 139
 140         sc = tc->tc_priv;
 141         return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
 142 }
 143
 144 static void
 145 hpet_enable(struct hpet_softc *sc)
 146 {
 147         uint32_t val;
 148
 149         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 150         if (sc->legacy_route)
 151                 val |= HPET_CNF_LEG_RT;
 152         else
 153                 val &= ~HPET_CNF_LEG_RT;
 154         val |= HPET_CNF_ENABLE;
 155         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 156 }
 157
 158 static void
 159 hpet_disable(struct hpet_softc *sc)
 160 {
 161         uint32_t val;
 162
 163         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 164         val &= ~HPET_CNF_ENABLE;
 165         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 166 }
 167
 168 static int
 169 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 170 {
 171         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 172         struct hpet_timer *t;
 173         struct hpet_softc *sc = mt->sc;
 174         uint32_t fdiv, now;
 175
 176         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 177         if (period != 0) {
 178                 t->mode = 1;
 179                 t->div = (sc->freq * period) >> 32;
 180         } else {
 181                 t->mode = 2;
 182                 t->div = 0;
 183         }
 184         if (first != 0)
 185                 fdiv = (sc->freq * first) >> 32;
 186         else
 187                 fdiv = t->div;
 188         if (t->irq < 0)
 189                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 190         t->caps |= HPET_TCNF_INT_ENB;
 191         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 192 restart:
 193         t->next = now + fdiv;
 194         if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 195                 t->caps |= HPET_TCNF_TYPE;
 196                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 197                     t->caps | HPET_TCNF_VAL_SET);
 198                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 199                     t->next);
 200                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 201                     t->div);
 202         } else {
 203                 t->caps &= ~HPET_TCNF_TYPE;
 204                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 205                     t->caps);
 206                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 207                     t->next);
 208         }
 209         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 210         if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
 211                 fdiv *= 2;
 212                 goto restart;
 213         }
 214         return (0);
 215 }
 216
 217 static int
 218 hpet_stop(struct eventtimer *et)
 219 {
 220         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 221         struct hpet_timer *t;
 222         struct hpet_softc *sc = mt->sc;
 223
 224         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 225         t->mode = 0;
 226         t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
 227         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 228         return (0);
 229 }
 230
 231 static int
 232 hpet_intr_single(void *arg)
 233 {
 234         struct hpet_timer *t = (struct hpet_timer *)arg;
 235         struct hpet_timer *mt;
 236         struct hpet_softc *sc = t->sc;
 237         uint32_t now;
 238
 239         if (t->mode == 0)
 240                 return (FILTER_STRAY);
 241         /* Check that per-CPU timer interrupt reached right CPU. */
 242         if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
 243                 if ((++t->pcpu_misrouted) % 32 == 0) {
 244                         printf("HPET interrupt routed to the wrong CPU"
 245                             " (timer %d CPU %d -> %d)!\n",
 246                             t->num, t->pcpu_cpu, curcpu);
 247                 }
 248
 249                 /*
 250                  * Reload timer, hoping that next time may be more lucky
 251                  * (system will manage proper interrupt binding).
 252                  */
 253                 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
 254                     t->mode == 2) {
 255                         t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
 256                             sc->freq / 8;
 257                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 258                             t->next);
 259                 }
 260                 return (FILTER_HANDLED);
 261         }
 262         if (t->mode == 1 &&
 263             (t->caps & HPET_TCAP_PER_INT) == 0) {
 264                 t->next += t->div;
 265                 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 266                 if ((int32_t)((now + t->div / 2) - t->next) > 0)
 267                         t->next = now + t->div / 2;
 268                 bus_write_4(sc->mem_res,
 269                     HPET_TIMER_COMPARATOR(t->num), t->next);
 270         } else if (t->mode == 2)
 271                 t->mode = 0;
 272         mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
 273         if (mt->et.et_active)
 274                 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
 275         return (FILTER_HANDLED);
 276 }
 277
 278 static int
 279 hpet_intr(void *arg)
 280 {
 281         struct hpet_softc *sc = (struct hpet_softc *)arg;
 282         int i;
 283         uint32_t val;
 284
 285         val = bus_read_4(sc->mem_res, HPET_ISR);
 286         if (val) {
 287                 bus_write_4(sc->mem_res, HPET_ISR, val);
 288                 val &= sc->useirq;
 289                 for (i = 0; i < sc->num_timers; i++) {
 290                         if ((val & (1 << i)) == 0)
 291                                 continue;
 292                         hpet_intr_single(&sc->t[i]);
 293                 }
 294                 return (FILTER_HANDLED);
 295         }
 296         return (FILTER_STRAY);
 297 }
 298
 299 uint32_t
 300 hpet_get_uid(device_t dev)
 301 {
 302         struct hpet_softc *sc;
 303
 304         sc = device_get_softc(dev);
 305         return (sc->acpi_uid);
 306 }
 307
 308 static ACPI_STATUS
 309 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
 310     void **status)
 311 {
 312         char            **ids;
 313         uint32_t        id = (uint32_t)(uintptr_t)context;
 314         uint32_t        uid = 0;
 315
 316         for (ids = hpet_ids; *ids != NULL; ids++) {
 317                 if (acpi_MatchHid(handle, *ids))
 318                         break;
 319         }
 320         if (*ids == NULL)
 321                 return (AE_OK);
 322         if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
 323             id == uid)
 324                 *status = acpi_get_device(handle);
 325         return (AE_OK);
 326 }
 327
 328 /*
 329  * Find an existing IRQ resource that matches the requested IRQ range
 330  * and return its RID.  If one is not found, use a new RID.
 331  */
 332 static int
 333 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
 334 {
 335         rman_res_t irq;
 336         int error, rid;
 337
 338         for (rid = 0;; rid++) {
 339                 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
 340                 if (error != 0 || (start <= irq && irq <= end))
 341                         return (rid);
 342         }
 343 }
 344
 345 static int
 346 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td)
 347 {
 348         struct hpet_softc *sc;
 349
 350         sc = cdev->si_drv1;
 351         if (!sc->mmap_allow)
 352                 return (EPERM);
 353         else
 354                 return (0);
 355 }
 356
 357 static int
 358 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,
 359     int nprot, vm_memattr_t *memattr)
 360 {
 361         struct hpet_softc *sc;
 362
 363         sc = cdev->si_drv1;
 364         if (offset > rman_get_size(sc->mem_res))
 365                 return (EINVAL);
 366         if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
 367                 return (EPERM);
 368         *paddr = rman_get_start(sc->mem_res) + offset;
 369         *memattr = VM_MEMATTR_UNCACHEABLE;
 370
 371         return (0);
 372 }
 373
 374 /* Discover the HPET via the ACPI table of the same name. */
 375 static void
 376 hpet_identify(driver_t *driver, device_t parent)
 377 {
 378         ACPI_TABLE_HPET *hpet;
 379         ACPI_STATUS     status;
 380         device_t        child;
 381         int             i;
 382
 383         /* Only one HPET device can be added. */
 384         if (devclass_get_device(hpet_devclass, 0))
 385                 return;
 386         for (i = 1; ; i++) {
 387                 /* Search for HPET table. */
 388                 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
 389                 if (ACPI_FAILURE(status))
 390                         return;
 391                 /* Search for HPET device with same ID. */
 392                 child = NULL;
 393                 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
 394                     100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence,
 395                     (void *)&child);
 396                 /* If found - let it be probed in normal way. */
 397                 if (child) {
 398                         if (bus_get_resource(child, SYS_RES_MEMORY, 0,
 399                             NULL, NULL) != 0)
 400                                 bus_set_resource(child, SYS_RES_MEMORY, 0,
 401                                     hpet->Address.Address, HPET_MEM_WIDTH);
 402                         continue;
 403                 }
 404                 /* If not - create it from table info. */
 405                 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
 406                 if (child == NULL) {
 407                         printf("%s: can't add child\n", __func__);
 408                         continue;
 409                 }
 410                 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
 411                     HPET_MEM_WIDTH);
 412         }
 413 }
 414
 415 static int
 416 hpet_probe(device_t dev)
 417 {
 418         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 419
 420         if (acpi_disabled("hpet") || acpi_hpet_disabled)
 421                 return (ENXIO);
 422         if (acpi_get_handle(dev) != NULL &&
 423             ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
 424                 return (ENXIO);
 425
 426         device_set_desc(dev, "High Precision Event Timer");
 427         return (0);
 428 }
 429
 430 static int
 431 hpet_attach(device_t dev)
 432 {
 433         struct hpet_softc *sc;
 434         struct hpet_timer *t;
 435         struct make_dev_args mda;
 436         int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
 437         int pcpu_master, error;
 438         static int maxhpetet = 0;
 439         uint32_t val, val2, cvectors, dvectors;
 440         uint16_t vendor, rev;
 441
 442         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 443
 444         sc = device_get_softc(dev);
 445         sc->dev = dev;
 446         sc->handle = acpi_get_handle(dev);
 447
 448         sc->mem_rid = 0;
 449         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 450             RF_ACTIVE);
 451         if (sc->mem_res == NULL)
 452                 return (ENOMEM);
 453
 454         /* Validate that we can access the whole region. */
 455         if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
 456                 device_printf(dev, "memory region width %ld too small\n",
 457                     rman_get_size(sc->mem_res));
 458                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 459                 return (ENXIO);
 460         }
 461
 462         /* Be sure timer is enabled. */
 463         hpet_enable(sc);
 464
 465         /* Read basic statistics about the timer. */
 466         val = bus_read_4(sc->mem_res, HPET_PERIOD);
 467         if (val == 0) {
 468                 device_printf(dev, "invalid period\n");
 469                 hpet_disable(sc);
 470                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 471                 return (ENXIO);
 472         }
 473
 474         sc->freq = (1000000000000000LL + val / 2) / val;
 475         sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
 476         vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
 477         rev = sc->caps & HPET_CAP_REV_ID;
 478         num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
 479         /*
 480          * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
 481          * Specification and provides an off by one number
 482          * of timers/comparators.
 483          * Additionally, they use unregistered value in VENDOR_ID field.
 484          */
 485         if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
 486                 num_timers--;
 487         sc->num_timers = num_timers;
 488         if (bootverbose) {
 489                 device_printf(dev,
 490                     "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
 491                     vendor, rev, sc->freq,
 492                     (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
 493                     num_timers,
 494                     (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
 495         }
 496         for (i = 0; i < num_timers; i++) {
 497                 t = &sc->t[i];
 498                 t->sc = sc;
 499                 t->num = i;
 500                 t->mode = 0;
 501                 t->intr_rid = -1;
 502                 t->irq = -1;
 503                 t->pcpu_cpu = -1;
 504                 t->pcpu_misrouted = 0;
 505                 t->pcpu_master = -1;
 506                 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
 507                 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
 508                 if (bootverbose) {
 509                         device_printf(dev,
 510                             " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
 511                             t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
 512                             (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
 513                             (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
 514                             (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
 515                 }
 516         }
 517         if (testenv("debug.acpi.hpet_test"))
 518                 hpet_test(sc);
 519         /*
 520          * Don't attach if the timer never increments.  Since the spec
 521          * requires it to be at least 10 MHz, it has to change in 1 us.
 522          */
 523         val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 524         DELAY(1);
 525         val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 526         if (val == val2) {
 527                 device_printf(dev, "HPET never increments, disabling\n");
 528                 hpet_disable(sc);
 529                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 530                 return (ENXIO);
 531         }
 532         /* Announce first HPET as timecounter. */
 533         if (device_get_unit(dev) == 0) {
 534                 sc->tc.tc_get_timecount = hpet_get_timecount,
 535                 sc->tc.tc_counter_mask = ~0u,
 536                 sc->tc.tc_name = "HPET",
 537                 sc->tc.tc_quality = 950,
 538                 sc->tc.tc_frequency = sc->freq;
 539                 sc->tc.tc_priv = sc;
 540                 tc_init(&sc->tc);
 541         }
 542         /* If not disabled - setup and announce event timers. */
 543         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 544              "clock", &i) == 0 && i == 0)
 545                 return (0);
 546
 547         /* Check whether we can and want legacy routing. */
 548         sc->legacy_route = 0;
 549         resource_int_value(device_get_name(dev), device_get_unit(dev),
 550              "legacy_route", &sc->legacy_route);
 551         if ((sc->caps & HPET_CAP_LEG_RT) == 0)
 552                 sc->legacy_route = 0;
 553         if (sc->legacy_route) {
 554                 sc->t[0].vectors = 0;
 555                 sc->t[1].vectors = 0;
 556         }
 557
 558         /* Check what IRQs we want use. */
 559         /* By default allow any PCI IRQs. */
 560         sc->allowed_irqs = 0xffff0000;
 561         /*
 562          * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
 563          * Lower are also not always working for different reasons.
 564          * SB800 fixed it, but seems do not implements level triggering
 565          * properly, that makes it very unreliable - it freezes after any
 566          * interrupt loss. Avoid legacy IRQs for AMD.
 567          */
 568         if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2)
 569                 sc->allowed_irqs = 0x00000000;
 570         /*
 571          * NVidia MCP5x chipsets have number of unexplained interrupt
 572          * problems. For some reason, using HPET interrupts breaks HDA sound.
 573          */
 574         if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
 575                 sc->allowed_irqs = 0x00000000;
 576         /*
 577          * ServerWorks HT1000 reported to have problems with IRQs >= 16.
 578          * Lower IRQs are working, but allowed mask is not set correctly.
 579          * Legacy_route mode works fine.
 580          */
 581         if (vendor == HPET_VENDID_SW && rev <= 0x01)
 582                 sc->allowed_irqs = 0x00000000;
 583         /*
 584          * Neither QEMU nor VirtualBox report supported IRQs correctly.
 585          * The only way to use HPET there is to specify IRQs manually
 586          * and/or use legacy_route. Legacy_route mode works on both.
 587          */
 588         if (vm_guest)
 589                 sc->allowed_irqs = 0x00000000;
 590         /* Let user override. */
 591         resource_int_value(device_get_name(dev), device_get_unit(dev),
 592              "allowed_irqs", &sc->allowed_irqs);
 593
 594         /* Get how much per-CPU timers we should try to provide. */
 595         sc->per_cpu = 1;
 596         resource_int_value(device_get_name(dev), device_get_unit(dev),
 597              "per_cpu", &sc->per_cpu);
 598
 599         num_msi = 0;
 600         sc->useirq = 0;
 601         /* Find IRQ vectors for all timers. */
 602         cvectors = sc->allowed_irqs & 0xffff0000;
 603         dvectors = sc->allowed_irqs & 0x0000ffff;
 604         if (sc->legacy_route)
 605                 dvectors &= 0x0000fefe;
 606         for (i = 0; i < num_timers; i++) {
 607                 t = &sc->t[i];
 608                 if (sc->legacy_route && i < 2)
 609                         t->irq = (i == 0) ? 0 : 8;
 610 #ifdef DEV_APIC
 611                 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
 612                         if ((j = PCIB_ALLOC_MSIX(
 613                             device_get_parent(device_get_parent(dev)), dev,
 614                             &t->irq))) {
 615                                 device_printf(dev,
 616                                     "Can't allocate interrupt for t%d: %d\n",
 617                                     i, j);
 618                         }
 619                 }
 620 #endif
 621                 else if (dvectors & t->vectors) {
 622                         t->irq = ffs(dvectors & t->vectors) - 1;
 623                         dvectors &= ~(1 << t->irq);
 624                 }
 625                 if (t->irq >= 0) {
 626                         t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
 627                         t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 628                             &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
 629                         if (t->intr_res == NULL) {
 630                                 t->irq = -1;
 631                                 device_printf(dev,
 632                                     "Can't map interrupt for t%d.\n", i);
 633                         } else if (bus_setup_intr(dev, t->intr_res,
 634                             INTR_TYPE_CLK, hpet_intr_single, NULL, t,
 635                             &t->intr_handle) != 0) {
 636                                 t->irq = -1;
 637                                 device_printf(dev,
 638                                     "Can't setup interrupt for t%d.\n", i);
 639                         } else {
 640                                 bus_describe_intr(dev, t->intr_res,
 641                                     t->intr_handle, "t%d", i);
 642                                 num_msi++;
 643                         }
 644                 }
 645                 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
 646                         cvectors &= t->vectors;
 647                         sc->useirq |= (1 << i);
 648                 }
 649         }
 650         if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
 651                 sc->legacy_route = 0;
 652         if (sc->legacy_route)
 653                 hpet_enable(sc);
 654         /* Group timers for per-CPU operation. */
 655         num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
 656         num_percpu_t = num_percpu_et * mp_ncpus;
 657         pcpu_master = 0;
 658         cur_cpu = CPU_FIRST();
 659         for (i = 0; i < num_timers; i++) {
 660                 t = &sc->t[i];
 661                 if (t->irq >= 0 && num_percpu_t > 0) {
 662                         if (cur_cpu == CPU_FIRST())
 663                                 pcpu_master = i;
 664                         t->pcpu_cpu = cur_cpu;
 665                         t->pcpu_master = pcpu_master;
 666                         sc->t[pcpu_master].
 667                             pcpu_slaves[cur_cpu] = i;
 668                         bus_bind_intr(dev, t->intr_res, cur_cpu);
 669                         cur_cpu = CPU_NEXT(cur_cpu);
 670                         num_percpu_t--;
 671                 } else if (t->irq >= 0)
 672                         bus_bind_intr(dev, t->intr_res, CPU_FIRST());
 673         }
 674         bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
 675         sc->irq = -1;
 676         /* If at least one timer needs legacy IRQ - set it up. */
 677         if (sc->useirq) {
 678                 j = i = fls(cvectors) - 1;
 679                 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
 680                         j--;
 681                 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
 682                 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 683                     &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
 684                 if (sc->intr_res == NULL)
 685                         device_printf(dev, "Can't map interrupt.\n");
 686                 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
 687                     hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
 688                         device_printf(dev, "Can't setup interrupt.\n");
 689                 } else {
 690                         sc->irq = rman_get_start(sc->intr_res);
 691                         /* Bind IRQ to BSP to avoid live migration. */
 692                         bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
 693                 }
 694         }
 695         /* Program and announce event timers. */
 696         for (i = 0; i < num_timers; i++) {
 697                 t = &sc->t[i];
 698                 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
 699                 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
 700                 t->caps &= ~(HPET_TCNF_INT_TYPE);
 701                 t->caps |= HPET_TCNF_32MODE;
 702                 if (t->irq >= 0 && sc->legacy_route && i < 2) {
 703                         /* Legacy route doesn't need more configuration. */
 704                 } else
 705 #ifdef DEV_APIC
 706                 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
 707                         uint64_t addr;
 708                         uint32_t data;
 709
 710                         if (PCIB_MAP_MSI(
 711                             device_get_parent(device_get_parent(dev)), dev,
 712                             t->irq, &addr, &data) == 0) {
 713                                 bus_write_4(sc->mem_res,
 714                                     HPET_TIMER_FSB_ADDR(i), addr);
 715                                 bus_write_4(sc->mem_res,
 716                                     HPET_TIMER_FSB_VAL(i), data);
 717                                 t->caps |= HPET_TCNF_FSB_EN;
 718                         } else
 719                                 t->irq = -2;
 720                 } else
 721 #endif
 722                 if (t->irq >= 0)
 723                         t->caps |= (t->irq << 9);
 724                 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
 725                         t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
 726                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
 727                 /* Skip event timers without set up IRQ. */
 728                 if (t->irq < 0 &&
 729                     (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
 730                         continue;
 731                 /* Announce the reset. */
 732                 if (maxhpetet == 0)
 733                         t->et.et_name = "HPET";
 734                 else {
 735                         sprintf(t->name, "HPET%d", maxhpetet);
 736                         t->et.et_name = t->name;
 737                 }
 738                 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 739                 t->et.et_quality = 450;
 740                 if (t->pcpu_master >= 0) {
 741                         t->et.et_flags |= ET_FLAGS_PERCPU;
 742                         t->et.et_quality += 100;
 743                 } else if (mp_ncpus >= 8)
 744                         t->et.et_quality -= 100;
 745                 if ((t->caps & HPET_TCAP_PER_INT) == 0)
 746                         t->et.et_quality -= 10;
 747                 t->et.et_frequency = sc->freq;
 748                 t->et.et_min_period =
 749                     ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
 750                 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
 751                 t->et.et_start = hpet_start;
 752                 t->et.et_stop = hpet_stop;
 753                 t->et.et_priv = &sc->t[i];
 754                 if (t->pcpu_master < 0 || t->pcpu_master == i) {
 755                         et_register(&t->et);
 756                         maxhpetet++;
 757                 }
 758         }
 759         acpi_GetInteger(sc->handle, "_UID", &sc->acpi_uid);
 760
 761         make_dev_args_init(&mda);
 762         mda.mda_devsw = &hpet_cdevsw;
 763         mda.mda_uid = UID_ROOT;
 764         mda.mda_gid = GID_WHEEL;
 765         mda.mda_mode = 0600;
 766         mda.mda_si_drv1 = sc;
 767         error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev));
 768         if (error == 0) {
 769                 sc->mmap_allow = 1;
 770                 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow",
 771                     &sc->mmap_allow);
 772                 sc->mmap_allow_write = 1;
 773                 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write",
 774                     &sc->mmap_allow_write);
 775                 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 776                     SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 777                     OID_AUTO, "mmap_allow",
 778                     CTLFLAG_RW, &sc->mmap_allow, 0,
 779                     "Allow userland to memory map HPET");
 780                 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 781                     SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 782                     OID_AUTO, "mmap_allow_write",
 783                     CTLFLAG_RW, &sc->mmap_allow_write, 0,
 784                     "Allow userland write to the HPET register space");
 785         } else {
 786                 device_printf(dev, "could not create /dev/hpet%d, error %d\n",
 787                     device_get_unit(dev), error);
 788         }
 789
 790         return (0);
 791 }
 792
 793 static int
 794 hpet_detach(device_t dev)
 795 {
 796         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 797
 798         /* XXX Without a tc_remove() function, we can't detach. */
 799         return (EBUSY);
 800 }
 801
 802 static int
 803 hpet_suspend(device_t dev)
 804 {
 805 //      struct hpet_softc *sc;
 806
 807         /*
 808          * Disable the timer during suspend.  The timer will not lose
 809          * its state in S1 or S2, but we are required to disable
 810          * it.
 811          */
 812 //      sc = device_get_softc(dev);
 813 //      hpet_disable(sc);
 814
 815         return (0);
 816 }
 817
 818 static int
 819 hpet_resume(device_t dev)
 820 {
 821         struct hpet_softc *sc;
 822         struct hpet_timer *t;
 823         int i;
 824
 825         /* Re-enable the timer after a resume to keep the clock advancing. */
 826         sc = device_get_softc(dev);
 827         hpet_enable(sc);
 828         /* Restart event timers that were running on suspend. */
 829         for (i = 0; i < sc->num_timers; i++) {
 830                 t = &sc->t[i];
 831 #ifdef DEV_APIC
 832                 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
 833                         uint64_t addr;
 834                         uint32_t data;
 835
 836                         if (PCIB_MAP_MSI(
 837                             device_get_parent(device_get_parent(dev)), dev,
 838                             t->irq, &addr, &data) == 0) {
 839                                 bus_write_4(sc->mem_res,
 840                                     HPET_TIMER_FSB_ADDR(i), addr);
 841                                 bus_write_4(sc->mem_res,
 842                                     HPET_TIMER_FSB_VAL(i), data);
 843                         }
 844                 }
 845 #endif
 846                 if (t->mode == 0)
 847                         continue;
 848                 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 849                 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 850                         t->caps |= HPET_TCNF_TYPE;
 851                         t->next += t->div;
 852                         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 853                             t->caps | HPET_TCNF_VAL_SET);
 854                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 855                             t->next);
 856                         bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
 857                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 858                             t->div);
 859                 } else {
 860                         t->next += sc->freq / 1024;
 861                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 862                             t->next);
 863                 }
 864                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 865                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 866         }
 867         return (0);
 868 }
 869
 870 /* Print some basic latency/rate information to assist in debugging. */
 871 static void
 872 hpet_test(struct hpet_softc *sc)
 873 {
 874         int i;
 875         uint32_t u1, u2;
 876         struct bintime b0, b1, b2;
 877         struct timespec ts;
 878
 879         binuptime(&b0);
 880         binuptime(&b0);
 881         binuptime(&b1);
 882         u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 883         for (i = 1; i < 1000; i++)
 884                 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 885         binuptime(&b2);
 886         u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 887
 888         bintime_sub(&b2, &b1);
 889         bintime_sub(&b1, &b0);
 890         bintime_sub(&b2, &b1);
 891         bintime2timespec(&b2, &ts);
 892
 893         device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
 894             (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
 895
 896         device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
 897 }
 898
 899 #ifdef DEV_APIC
 900 static int
 901 hpet_remap_intr(device_t dev, device_t child, u_int irq)
 902 {
 903         struct hpet_softc *sc = device_get_softc(dev);
 904         struct hpet_timer *t;
 905         uint64_t addr;
 906         uint32_t data;
 907         int error, i;
 908
 909         for (i = 0; i < sc->num_timers; i++) {
 910                 t = &sc->t[i];
 911                 if (t->irq != irq)
 912                         continue;
 913                 error = PCIB_MAP_MSI(
 914                     device_get_parent(device_get_parent(dev)), dev,
 915                     irq, &addr, &data);
 916                 if (error)
 917                         return (error);
 918                 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
 919                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
 920                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
 921                 hpet_enable(sc);
 922                 return (0);
 923         }
 924         return (ENOENT);
 925 }
 926 #endif
 927
 928 static device_method_t hpet_methods[] = {
 929         /* Device interface */
 930         DEVMETHOD(device_identify, hpet_identify),
 931         DEVMETHOD(device_probe, hpet_probe),
 932         DEVMETHOD(device_attach, hpet_attach),
 933         DEVMETHOD(device_detach, hpet_detach),
 934         DEVMETHOD(device_suspend, hpet_suspend),
 935         DEVMETHOD(device_resume, hpet_resume),
 936
 937 #ifdef DEV_APIC
 938         DEVMETHOD(bus_remap_intr, hpet_remap_intr),
 939 #endif
 940
 941         DEVMETHOD_END
 942 };
 943
 944 static driver_t hpet_driver = {
 945         "hpet",
 946         hpet_methods,
 947         sizeof(struct hpet_softc),
 948 };
 949
 950 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
 951 MODULE_DEPEND(hpet, acpi, 1, 1, 1);