sys/dev/acpica/acpi_hpet.c

   1 /*-
   2  * Copyright (c) 2005 Poul-Henning Kamp
   3  * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_acpi.h"
  32 #if defined(__amd64__)
  33 #define DEV_APIC
  34 #else
  35 #include "opt_apic.h"
  36 #endif
  37 #include <sys/param.h>
  38 #include <sys/conf.h>
  39 #include <sys/bus.h>
  40 #include <sys/kernel.h>
  41 #include <sys/module.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/mman.h>
  45 #include <sys/time.h>
  46 #include <sys/smp.h>
  47 #include <sys/sysctl.h>
  48 #include <sys/timeet.h>
  49 #include <sys/timetc.h>
  50
  51 #include <contrib/dev/acpica/include/acpi.h>
  52 #include <contrib/dev/acpica/include/accommon.h>
  53
  54 #include <dev/acpica/acpivar.h>
  55 #include <dev/acpica/acpi_hpet.h>
  56
  57 #ifdef DEV_APIC
  58 #include "pcib_if.h"
  59 #endif
  60
  61 #define HPET_VENDID_AMD         0x4353
  62 #define HPET_VENDID_AMD2        0x1022
  63 #define HPET_VENDID_INTEL       0x8086
  64 #define HPET_VENDID_NVIDIA      0x10de
  65 #define HPET_VENDID_SW          0x1166
  66
  67 ACPI_SERIAL_DECL(hpet, "ACPI HPET support");
  68
  69 static devclass_t hpet_devclass;
  70
  71 /* ACPI CA debugging */
  72 #define _COMPONENT      ACPI_TIMER
  73 ACPI_MODULE_NAME("HPET")
  74
  75 struct hpet_softc {
  76         device_t                dev;
  77         int                     mem_rid;
  78         int                     intr_rid;
  79         int                     irq;
  80         int                     useirq;
  81         int                     legacy_route;
  82         int                     per_cpu;
  83         uint32_t                allowed_irqs;
  84         struct resource         *mem_res;
  85         struct resource         *intr_res;
  86         void                    *intr_handle;
  87         ACPI_HANDLE             handle;
  88         uint64_t                freq;
  89         uint32_t                caps;
  90         struct timecounter      tc;
  91         struct hpet_timer {
  92                 struct eventtimer       et;
  93                 struct hpet_softc       *sc;
  94                 int                     num;
  95                 int                     mode;
  96                 int                     intr_rid;
  97                 int                     irq;
  98                 int                     pcpu_cpu;
  99                 int                     pcpu_misrouted;
 100                 int                     pcpu_master;
 101                 int                     pcpu_slaves[MAXCPU];
 102                 struct resource         *intr_res;
 103                 void                    *intr_handle;
 104                 uint32_t                caps;
 105                 uint32_t                vectors;
 106                 uint32_t                div;
 107                 uint32_t                next;
 108                 char                    name[8];
 109         }                       t[32];
 110         int                     num_timers;
 111         struct cdev             *pdev;
 112         int                     mmap_allow;
 113         int                     mmap_allow_write;
 114 };
 115
 116 static d_open_t hpet_open;
 117 static d_mmap_t hpet_mmap;
 118
 119 static struct cdevsw hpet_cdevsw = {
 120         .d_version =    D_VERSION,
 121         .d_name =       "hpet",
 122         .d_open =       hpet_open,
 123         .d_mmap =       hpet_mmap,
 124 };
 125
 126 static u_int hpet_get_timecount(struct timecounter *tc);
 127 static void hpet_test(struct hpet_softc *sc);
 128
 129 static char *hpet_ids[] = { "PNP0103", NULL };
 130
 131 /* Knob to disable acpi_hpet device */
 132 bool acpi_hpet_disabled = false;
 133
 134 static u_int
 135 hpet_get_timecount(struct timecounter *tc)
 136 {
 137         struct hpet_softc *sc;
 138
 139         sc = tc->tc_priv;
 140         return (bus_read_4(sc->mem_res, HPET_MAIN_COUNTER));
 141 }
 142
 143 static void
 144 hpet_enable(struct hpet_softc *sc)
 145 {
 146         uint32_t val;
 147
 148         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 149         if (sc->legacy_route)
 150                 val |= HPET_CNF_LEG_RT;
 151         else
 152                 val &= ~HPET_CNF_LEG_RT;
 153         val |= HPET_CNF_ENABLE;
 154         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 155 }
 156
 157 static void
 158 hpet_disable(struct hpet_softc *sc)
 159 {
 160         uint32_t val;
 161
 162         val = bus_read_4(sc->mem_res, HPET_CONFIG);
 163         val &= ~HPET_CNF_ENABLE;
 164         bus_write_4(sc->mem_res, HPET_CONFIG, val);
 165 }
 166
 167 static int
 168 hpet_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
 169 {
 170         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 171         struct hpet_timer *t;
 172         struct hpet_softc *sc = mt->sc;
 173         uint32_t fdiv, now;
 174
 175         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 176         if (period != 0) {
 177                 t->mode = 1;
 178                 t->div = (sc->freq * period) >> 32;
 179         } else {
 180                 t->mode = 2;
 181                 t->div = 0;
 182         }
 183         if (first != 0)
 184                 fdiv = (sc->freq * first) >> 32;
 185         else
 186                 fdiv = t->div;
 187         if (t->irq < 0)
 188                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 189         t->caps |= HPET_TCNF_INT_ENB;
 190         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 191 restart:
 192         t->next = now + fdiv;
 193         if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 194                 t->caps |= HPET_TCNF_TYPE;
 195                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 196                     t->caps | HPET_TCNF_VAL_SET);
 197                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 198                     t->next);
 199                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 200                     t->div);
 201         } else {
 202                 t->caps &= ~HPET_TCNF_TYPE;
 203                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 204                     t->caps);
 205                 bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 206                     t->next);
 207         }
 208         now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 209         if ((int32_t)(now - t->next + HPET_MIN_CYCLES) >= 0) {
 210                 fdiv *= 2;
 211                 goto restart;
 212         }
 213         return (0);
 214 }
 215
 216 static int
 217 hpet_stop(struct eventtimer *et)
 218 {
 219         struct hpet_timer *mt = (struct hpet_timer *)et->et_priv;
 220         struct hpet_timer *t;
 221         struct hpet_softc *sc = mt->sc;
 222
 223         t = (mt->pcpu_master < 0) ? mt : &sc->t[mt->pcpu_slaves[curcpu]];
 224         t->mode = 0;
 225         t->caps &= ~(HPET_TCNF_INT_ENB | HPET_TCNF_TYPE);
 226         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 227         return (0);
 228 }
 229
 230 static int
 231 hpet_intr_single(void *arg)
 232 {
 233         struct hpet_timer *t = (struct hpet_timer *)arg;
 234         struct hpet_timer *mt;
 235         struct hpet_softc *sc = t->sc;
 236         uint32_t now;
 237
 238         if (t->mode == 0)
 239                 return (FILTER_STRAY);
 240         /* Check that per-CPU timer interrupt reached right CPU. */
 241         if (t->pcpu_cpu >= 0 && t->pcpu_cpu != curcpu) {
 242                 if ((++t->pcpu_misrouted) % 32 == 0) {
 243                         printf("HPET interrupt routed to the wrong CPU"
 244                             " (timer %d CPU %d -> %d)!\n",
 245                             t->num, t->pcpu_cpu, curcpu);
 246                 }
 247
 248                 /*
 249                  * Reload timer, hoping that next time may be more lucky
 250                  * (system will manage proper interrupt binding).
 251                  */
 252                 if ((t->mode == 1 && (t->caps & HPET_TCAP_PER_INT) == 0) ||
 253                     t->mode == 2) {
 254                         t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER) +
 255                             sc->freq / 8;
 256                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 257                             t->next);
 258                 }
 259                 return (FILTER_HANDLED);
 260         }
 261         if (t->mode == 1 &&
 262             (t->caps & HPET_TCAP_PER_INT) == 0) {
 263                 t->next += t->div;
 264                 now = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 265                 if ((int32_t)((now + t->div / 2) - t->next) > 0)
 266                         t->next = now + t->div / 2;
 267                 bus_write_4(sc->mem_res,
 268                     HPET_TIMER_COMPARATOR(t->num), t->next);
 269         } else if (t->mode == 2)
 270                 t->mode = 0;
 271         mt = (t->pcpu_master < 0) ? t : &sc->t[t->pcpu_master];
 272         if (mt->et.et_active)
 273                 mt->et.et_event_cb(&mt->et, mt->et.et_arg);
 274         return (FILTER_HANDLED);
 275 }
 276
 277 static int
 278 hpet_intr(void *arg)
 279 {
 280         struct hpet_softc *sc = (struct hpet_softc *)arg;
 281         int i;
 282         uint32_t val;
 283
 284         val = bus_read_4(sc->mem_res, HPET_ISR);
 285         if (val) {
 286                 bus_write_4(sc->mem_res, HPET_ISR, val);
 287                 val &= sc->useirq;
 288                 for (i = 0; i < sc->num_timers; i++) {
 289                         if ((val & (1 << i)) == 0)
 290                                 continue;
 291                         hpet_intr_single(&sc->t[i]);
 292                 }
 293                 return (FILTER_HANDLED);
 294         }
 295         return (FILTER_STRAY);
 296 }
 297
 298 static ACPI_STATUS
 299 hpet_find(ACPI_HANDLE handle, UINT32 level, void *context,
 300     void **status)
 301 {
 302         char            **ids;
 303         uint32_t        id = (uint32_t)(uintptr_t)context;
 304         uint32_t        uid = 0;
 305
 306         for (ids = hpet_ids; *ids != NULL; ids++) {
 307                 if (acpi_MatchHid(handle, *ids))
 308                         break;
 309         }
 310         if (*ids == NULL)
 311                 return (AE_OK);
 312         if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &uid)) ||
 313             id == uid)
 314                 *status = acpi_get_device(handle);
 315         return (AE_OK);
 316 }
 317
 318 /*
 319  * Find an existing IRQ resource that matches the requested IRQ range
 320  * and return its RID.  If one is not found, use a new RID.
 321  */
 322 static int
 323 hpet_find_irq_rid(device_t dev, u_long start, u_long end)
 324 {
 325         rman_res_t irq;
 326         int error, rid;
 327
 328         for (rid = 0;; rid++) {
 329                 error = bus_get_resource(dev, SYS_RES_IRQ, rid, &irq, NULL);
 330                 if (error != 0 || (start <= irq && irq <= end))
 331                         return (rid);
 332         }
 333 }
 334
 335 static int
 336 hpet_open(struct cdev *cdev, int oflags, int devtype, struct thread *td)
 337 {
 338         struct hpet_softc *sc;
 339
 340         sc = cdev->si_drv1;
 341         if (!sc->mmap_allow)
 342                 return (EPERM);
 343         else
 344                 return (0);
 345 }
 346
 347 static int
 348 hpet_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr,
 349     int nprot, vm_memattr_t *memattr)
 350 {
 351         struct hpet_softc *sc;
 352
 353         sc = cdev->si_drv1;
 354         if (offset > rman_get_size(sc->mem_res))
 355                 return (EINVAL);
 356         if (!sc->mmap_allow_write && (nprot & PROT_WRITE))
 357                 return (EPERM);
 358         *paddr = rman_get_start(sc->mem_res) + offset;
 359         *memattr = VM_MEMATTR_UNCACHEABLE;
 360
 361         return (0);
 362 }
 363
 364 /* Discover the HPET via the ACPI table of the same name. */
 365 static void
 366 hpet_identify(driver_t *driver, device_t parent)
 367 {
 368         ACPI_TABLE_HPET *hpet;
 369         ACPI_STATUS     status;
 370         device_t        child;
 371         int             i;
 372
 373         /* Only one HPET device can be added. */
 374         if (devclass_get_device(hpet_devclass, 0))
 375                 return;
 376         for (i = 1; ; i++) {
 377                 /* Search for HPET table. */
 378                 status = AcpiGetTable(ACPI_SIG_HPET, i, (ACPI_TABLE_HEADER **)&hpet);
 379                 if (ACPI_FAILURE(status))
 380                         return;
 381                 /* Search for HPET device with same ID. */
 382                 child = NULL;
 383                 AcpiWalkNamespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
 384                     100, hpet_find, NULL, (void *)(uintptr_t)hpet->Sequence,
 385                     (void *)&child);
 386                 /* If found - let it be probed in normal way. */
 387                 if (child) {
 388                         if (bus_get_resource(child, SYS_RES_MEMORY, 0,
 389                             NULL, NULL) != 0)
 390                                 bus_set_resource(child, SYS_RES_MEMORY, 0,
 391                                     hpet->Address.Address, HPET_MEM_WIDTH);
 392                         continue;
 393                 }
 394                 /* If not - create it from table info. */
 395                 child = BUS_ADD_CHILD(parent, 2, "hpet", 0);
 396                 if (child == NULL) {
 397                         printf("%s: can't add child\n", __func__);
 398                         continue;
 399                 }
 400                 bus_set_resource(child, SYS_RES_MEMORY, 0, hpet->Address.Address,
 401                     HPET_MEM_WIDTH);
 402         }
 403 }
 404
 405 static int
 406 hpet_probe(device_t dev)
 407 {
 408         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 409
 410         if (acpi_disabled("hpet") || acpi_hpet_disabled)
 411                 return (ENXIO);
 412         if (acpi_get_handle(dev) != NULL &&
 413             ACPI_ID_PROBE(device_get_parent(dev), dev, hpet_ids) == NULL)
 414                 return (ENXIO);
 415
 416         device_set_desc(dev, "High Precision Event Timer");
 417         return (0);
 418 }
 419
 420 static int
 421 hpet_attach(device_t dev)
 422 {
 423         struct hpet_softc *sc;
 424         struct hpet_timer *t;
 425         struct make_dev_args mda;
 426         int i, j, num_msi, num_timers, num_percpu_et, num_percpu_t, cur_cpu;
 427         int pcpu_master, error;
 428         static int maxhpetet = 0;
 429         uint32_t val, val2, cvectors, dvectors;
 430         uint16_t vendor, rev;
 431
 432         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 433
 434         sc = device_get_softc(dev);
 435         sc->dev = dev;
 436         sc->handle = acpi_get_handle(dev);
 437
 438         sc->mem_rid = 0;
 439         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 440             RF_ACTIVE);
 441         if (sc->mem_res == NULL)
 442                 return (ENOMEM);
 443
 444         /* Validate that we can access the whole region. */
 445         if (rman_get_size(sc->mem_res) < HPET_MEM_WIDTH) {
 446                 device_printf(dev, "memory region width %ld too small\n",
 447                     rman_get_size(sc->mem_res));
 448                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 449                 return (ENXIO);
 450         }
 451
 452         /* Be sure timer is enabled. */
 453         hpet_enable(sc);
 454
 455         /* Read basic statistics about the timer. */
 456         val = bus_read_4(sc->mem_res, HPET_PERIOD);
 457         if (val == 0) {
 458                 device_printf(dev, "invalid period\n");
 459                 hpet_disable(sc);
 460                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 461                 return (ENXIO);
 462         }
 463
 464         sc->freq = (1000000000000000LL + val / 2) / val;
 465         sc->caps = bus_read_4(sc->mem_res, HPET_CAPABILITIES);
 466         vendor = (sc->caps & HPET_CAP_VENDOR_ID) >> 16;
 467         rev = sc->caps & HPET_CAP_REV_ID;
 468         num_timers = 1 + ((sc->caps & HPET_CAP_NUM_TIM) >> 8);
 469         /*
 470          * ATI/AMD violates IA-PC HPET (High Precision Event Timers)
 471          * Specification and provides an off by one number
 472          * of timers/comparators.
 473          * Additionally, they use unregistered value in VENDOR_ID field.
 474          */
 475         if (vendor == HPET_VENDID_AMD && rev < 0x10 && num_timers > 0)
 476                 num_timers--;
 477         sc->num_timers = num_timers;
 478         if (bootverbose) {
 479                 device_printf(dev,
 480                     "vendor 0x%x, rev 0x%x, %jdHz%s, %d timers,%s\n",
 481                     vendor, rev, sc->freq,
 482                     (sc->caps & HPET_CAP_COUNT_SIZE) ? " 64bit" : "",
 483                     num_timers,
 484                     (sc->caps & HPET_CAP_LEG_RT) ? " legacy route" : "");
 485         }
 486         for (i = 0; i < num_timers; i++) {
 487                 t = &sc->t[i];
 488                 t->sc = sc;
 489                 t->num = i;
 490                 t->mode = 0;
 491                 t->intr_rid = -1;
 492                 t->irq = -1;
 493                 t->pcpu_cpu = -1;
 494                 t->pcpu_misrouted = 0;
 495                 t->pcpu_master = -1;
 496                 t->caps = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i));
 497                 t->vectors = bus_read_4(sc->mem_res, HPET_TIMER_CAP_CNF(i) + 4);
 498                 if (bootverbose) {
 499                         device_printf(dev,
 500                             " t%d: irqs 0x%08x (%d)%s%s%s\n", i,
 501                             t->vectors, (t->caps & HPET_TCNF_INT_ROUTE) >> 9,
 502                             (t->caps & HPET_TCAP_FSB_INT_DEL) ? ", MSI" : "",
 503                             (t->caps & HPET_TCAP_SIZE) ? ", 64bit" : "",
 504                             (t->caps & HPET_TCAP_PER_INT) ? ", periodic" : "");
 505                 }
 506         }
 507         if (testenv("debug.acpi.hpet_test"))
 508                 hpet_test(sc);
 509         /*
 510          * Don't attach if the timer never increments.  Since the spec
 511          * requires it to be at least 10 MHz, it has to change in 1 us.
 512          */
 513         val = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 514         DELAY(1);
 515         val2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 516         if (val == val2) {
 517                 device_printf(dev, "HPET never increments, disabling\n");
 518                 hpet_disable(sc);
 519                 bus_free_resource(dev, SYS_RES_MEMORY, sc->mem_res);
 520                 return (ENXIO);
 521         }
 522         /* Announce first HPET as timecounter. */
 523         if (device_get_unit(dev) == 0) {
 524                 sc->tc.tc_get_timecount = hpet_get_timecount,
 525                 sc->tc.tc_counter_mask = ~0u,
 526                 sc->tc.tc_name = "HPET",
 527                 sc->tc.tc_quality = 950,
 528                 sc->tc.tc_frequency = sc->freq;
 529                 sc->tc.tc_priv = sc;
 530                 tc_init(&sc->tc);
 531         }
 532         /* If not disabled - setup and announce event timers. */
 533         if (resource_int_value(device_get_name(dev), device_get_unit(dev),
 534              "clock", &i) == 0 && i == 0)
 535                 return (0);
 536
 537         /* Check whether we can and want legacy routing. */
 538         sc->legacy_route = 0;
 539         resource_int_value(device_get_name(dev), device_get_unit(dev),
 540              "legacy_route", &sc->legacy_route);
 541         if ((sc->caps & HPET_CAP_LEG_RT) == 0)
 542                 sc->legacy_route = 0;
 543         if (sc->legacy_route) {
 544                 sc->t[0].vectors = 0;
 545                 sc->t[1].vectors = 0;
 546         }
 547
 548         /* Check what IRQs we want use. */
 549         /* By default allow any PCI IRQs. */
 550         sc->allowed_irqs = 0xffff0000;
 551         /*
 552          * HPETs in AMD chipsets before SB800 have problems with IRQs >= 16
 553          * Lower are also not always working for different reasons.
 554          * SB800 fixed it, but seems do not implements level triggering
 555          * properly, that makes it very unreliable - it freezes after any
 556          * interrupt loss. Avoid legacy IRQs for AMD.
 557          */
 558         if (vendor == HPET_VENDID_AMD || vendor == HPET_VENDID_AMD2)
 559                 sc->allowed_irqs = 0x00000000;
 560         /*
 561          * NVidia MCP5x chipsets have number of unexplained interrupt
 562          * problems. For some reason, using HPET interrupts breaks HDA sound.
 563          */
 564         if (vendor == HPET_VENDID_NVIDIA && rev <= 0x01)
 565                 sc->allowed_irqs = 0x00000000;
 566         /*
 567          * ServerWorks HT1000 reported to have problems with IRQs >= 16.
 568          * Lower IRQs are working, but allowed mask is not set correctly.
 569          * Legacy_route mode works fine.
 570          */
 571         if (vendor == HPET_VENDID_SW && rev <= 0x01)
 572                 sc->allowed_irqs = 0x00000000;
 573         /*
 574          * Neither QEMU nor VirtualBox report supported IRQs correctly.
 575          * The only way to use HPET there is to specify IRQs manually
 576          * and/or use legacy_route. Legacy_route mode works on both.
 577          */
 578         if (vm_guest)
 579                 sc->allowed_irqs = 0x00000000;
 580         /* Let user override. */
 581         resource_int_value(device_get_name(dev), device_get_unit(dev),
 582              "allowed_irqs", &sc->allowed_irqs);
 583
 584         /* Get how much per-CPU timers we should try to provide. */
 585         sc->per_cpu = 1;
 586         resource_int_value(device_get_name(dev), device_get_unit(dev),
 587              "per_cpu", &sc->per_cpu);
 588
 589         num_msi = 0;
 590         sc->useirq = 0;
 591         /* Find IRQ vectors for all timers. */
 592         cvectors = sc->allowed_irqs & 0xffff0000;
 593         dvectors = sc->allowed_irqs & 0x0000ffff;
 594         if (sc->legacy_route)
 595                 dvectors &= 0x0000fefe;
 596         for (i = 0; i < num_timers; i++) {
 597                 t = &sc->t[i];
 598                 if (sc->legacy_route && i < 2)
 599                         t->irq = (i == 0) ? 0 : 8;
 600 #ifdef DEV_APIC
 601                 else if (t->caps & HPET_TCAP_FSB_INT_DEL) {
 602                         if ((j = PCIB_ALLOC_MSIX(
 603                             device_get_parent(device_get_parent(dev)), dev,
 604                             &t->irq))) {
 605                                 device_printf(dev,
 606                                     "Can't allocate interrupt for t%d: %d\n",
 607                                     i, j);
 608                         }
 609                 }
 610 #endif
 611                 else if (dvectors & t->vectors) {
 612                         t->irq = ffs(dvectors & t->vectors) - 1;
 613                         dvectors &= ~(1 << t->irq);
 614                 }
 615                 if (t->irq >= 0) {
 616                         t->intr_rid = hpet_find_irq_rid(dev, t->irq, t->irq);
 617                         t->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 618                             &t->intr_rid, t->irq, t->irq, 1, RF_ACTIVE);
 619                         if (t->intr_res == NULL) {
 620                                 t->irq = -1;
 621                                 device_printf(dev,
 622                                     "Can't map interrupt for t%d.\n", i);
 623                         } else if (bus_setup_intr(dev, t->intr_res,
 624                             INTR_TYPE_CLK, hpet_intr_single, NULL, t,
 625                             &t->intr_handle) != 0) {
 626                                 t->irq = -1;
 627                                 device_printf(dev,
 628                                     "Can't setup interrupt for t%d.\n", i);
 629                         } else {
 630                                 bus_describe_intr(dev, t->intr_res,
 631                                     t->intr_handle, "t%d", i);
 632                                 num_msi++;
 633                         }
 634                 }
 635                 if (t->irq < 0 && (cvectors & t->vectors) != 0) {
 636                         cvectors &= t->vectors;
 637                         sc->useirq |= (1 << i);
 638                 }
 639         }
 640         if (sc->legacy_route && sc->t[0].irq < 0 && sc->t[1].irq < 0)
 641                 sc->legacy_route = 0;
 642         if (sc->legacy_route)
 643                 hpet_enable(sc);
 644         /* Group timers for per-CPU operation. */
 645         num_percpu_et = min(num_msi / mp_ncpus, sc->per_cpu);
 646         num_percpu_t = num_percpu_et * mp_ncpus;
 647         pcpu_master = 0;
 648         cur_cpu = CPU_FIRST();
 649         for (i = 0; i < num_timers; i++) {
 650                 t = &sc->t[i];
 651                 if (t->irq >= 0 && num_percpu_t > 0) {
 652                         if (cur_cpu == CPU_FIRST())
 653                                 pcpu_master = i;
 654                         t->pcpu_cpu = cur_cpu;
 655                         t->pcpu_master = pcpu_master;
 656                         sc->t[pcpu_master].
 657                             pcpu_slaves[cur_cpu] = i;
 658                         bus_bind_intr(dev, t->intr_res, cur_cpu);
 659                         cur_cpu = CPU_NEXT(cur_cpu);
 660                         num_percpu_t--;
 661                 } else if (t->irq >= 0)
 662                         bus_bind_intr(dev, t->intr_res, CPU_FIRST());
 663         }
 664         bus_write_4(sc->mem_res, HPET_ISR, 0xffffffff);
 665         sc->irq = -1;
 666         /* If at least one timer needs legacy IRQ - set it up. */
 667         if (sc->useirq) {
 668                 j = i = fls(cvectors) - 1;
 669                 while (j > 0 && (cvectors & (1 << (j - 1))) != 0)
 670                         j--;
 671                 sc->intr_rid = hpet_find_irq_rid(dev, j, i);
 672                 sc->intr_res = bus_alloc_resource(dev, SYS_RES_IRQ,
 673                     &sc->intr_rid, j, i, 1, RF_SHAREABLE | RF_ACTIVE);
 674                 if (sc->intr_res == NULL)
 675                         device_printf(dev, "Can't map interrupt.\n");
 676                 else if (bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
 677                     hpet_intr, NULL, sc, &sc->intr_handle) != 0) {
 678                         device_printf(dev, "Can't setup interrupt.\n");
 679                 } else {
 680                         sc->irq = rman_get_start(sc->intr_res);
 681                         /* Bind IRQ to BSP to avoid live migration. */
 682                         bus_bind_intr(dev, sc->intr_res, CPU_FIRST());
 683                 }
 684         }
 685         /* Program and announce event timers. */
 686         for (i = 0; i < num_timers; i++) {
 687                 t = &sc->t[i];
 688                 t->caps &= ~(HPET_TCNF_FSB_EN | HPET_TCNF_INT_ROUTE);
 689                 t->caps &= ~(HPET_TCNF_VAL_SET | HPET_TCNF_INT_ENB);
 690                 t->caps &= ~(HPET_TCNF_INT_TYPE);
 691                 t->caps |= HPET_TCNF_32MODE;
 692                 if (t->irq >= 0 && sc->legacy_route && i < 2) {
 693                         /* Legacy route doesn't need more configuration. */
 694                 } else
 695 #ifdef DEV_APIC
 696                 if ((t->caps & HPET_TCAP_FSB_INT_DEL) && t->irq >= 0) {
 697                         uint64_t addr;
 698                         uint32_t data;
 699
 700                         if (PCIB_MAP_MSI(
 701                             device_get_parent(device_get_parent(dev)), dev,
 702                             t->irq, &addr, &data) == 0) {
 703                                 bus_write_4(sc->mem_res,
 704                                     HPET_TIMER_FSB_ADDR(i), addr);
 705                                 bus_write_4(sc->mem_res,
 706                                     HPET_TIMER_FSB_VAL(i), data);
 707                                 t->caps |= HPET_TCNF_FSB_EN;
 708                         } else
 709                                 t->irq = -2;
 710                 } else
 711 #endif
 712                 if (t->irq >= 0)
 713                         t->caps |= (t->irq << 9);
 714                 else if (sc->irq >= 0 && (t->vectors & (1 << sc->irq)))
 715                         t->caps |= (sc->irq << 9) | HPET_TCNF_INT_TYPE;
 716                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(i), t->caps);
 717                 /* Skip event timers without set up IRQ. */
 718                 if (t->irq < 0 &&
 719                     (sc->irq < 0 || (t->vectors & (1 << sc->irq)) == 0))
 720                         continue;
 721                 /* Announce the reset. */
 722                 if (maxhpetet == 0)
 723                         t->et.et_name = "HPET";
 724                 else {
 725                         sprintf(t->name, "HPET%d", maxhpetet);
 726                         t->et.et_name = t->name;
 727                 }
 728                 t->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT;
 729                 t->et.et_quality = 450;
 730                 if (t->pcpu_master >= 0) {
 731                         t->et.et_flags |= ET_FLAGS_PERCPU;
 732                         t->et.et_quality += 100;
 733                 } else if (mp_ncpus >= 8)
 734                         t->et.et_quality -= 100;
 735                 if ((t->caps & HPET_TCAP_PER_INT) == 0)
 736                         t->et.et_quality -= 10;
 737                 t->et.et_frequency = sc->freq;
 738                 t->et.et_min_period =
 739                     ((uint64_t)(HPET_MIN_CYCLES * 2) << 32) / sc->freq;
 740                 t->et.et_max_period = (0xfffffffeLLU << 32) / sc->freq;
 741                 t->et.et_start = hpet_start;
 742                 t->et.et_stop = hpet_stop;
 743                 t->et.et_priv = &sc->t[i];
 744                 if (t->pcpu_master < 0 || t->pcpu_master == i) {
 745                         et_register(&t->et);
 746                         maxhpetet++;
 747                 }
 748         }
 749
 750         make_dev_args_init(&mda);
 751         mda.mda_devsw = &hpet_cdevsw;
 752         mda.mda_uid = UID_ROOT;
 753         mda.mda_gid = GID_WHEEL;
 754         mda.mda_mode = 0600;
 755         mda.mda_si_drv1 = sc;
 756         error = make_dev_s(&mda, &sc->pdev, "hpet%d", device_get_unit(dev));
 757         if (error == 0) {
 758                 sc->mmap_allow = 1;
 759                 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow",
 760                     &sc->mmap_allow);
 761                 sc->mmap_allow_write = 1;
 762                 TUNABLE_INT_FETCH("hw.acpi.hpet.mmap_allow_write",
 763                     &sc->mmap_allow_write);
 764                 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 765                     SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 766                     OID_AUTO, "mmap_allow",
 767                     CTLFLAG_RW, &sc->mmap_allow, 0,
 768                     "Allow userland to memory map HPET");
 769                 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
 770                     SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 771                     OID_AUTO, "mmap_allow_write",
 772                     CTLFLAG_RW, &sc->mmap_allow_write, 0,
 773                     "Allow userland write to the HPET register space");
 774         } else {
 775                 device_printf(dev, "could not create /dev/hpet%d, error %d\n",
 776                     device_get_unit(dev), error);
 777         }
 778
 779         return (0);
 780 }
 781
 782 static int
 783 hpet_detach(device_t dev)
 784 {
 785         ACPI_FUNCTION_TRACE((char *)(uintptr_t) __func__);
 786
 787         /* XXX Without a tc_remove() function, we can't detach. */
 788         return (EBUSY);
 789 }
 790
 791 static int
 792 hpet_suspend(device_t dev)
 793 {
 794 //      struct hpet_softc *sc;
 795
 796         /*
 797          * Disable the timer during suspend.  The timer will not lose
 798          * its state in S1 or S2, but we are required to disable
 799          * it.
 800          */
 801 //      sc = device_get_softc(dev);
 802 //      hpet_disable(sc);
 803
 804         return (0);
 805 }
 806
 807 static int
 808 hpet_resume(device_t dev)
 809 {
 810         struct hpet_softc *sc;
 811         struct hpet_timer *t;
 812         int i;
 813
 814         /* Re-enable the timer after a resume to keep the clock advancing. */
 815         sc = device_get_softc(dev);
 816         hpet_enable(sc);
 817         /* Restart event timers that were running on suspend. */
 818         for (i = 0; i < sc->num_timers; i++) {
 819                 t = &sc->t[i];
 820 #ifdef DEV_APIC
 821                 if (t->irq >= 0 && (sc->legacy_route == 0 || i >= 2)) {
 822                         uint64_t addr;
 823                         uint32_t data;
 824
 825                         if (PCIB_MAP_MSI(
 826                             device_get_parent(device_get_parent(dev)), dev,
 827                             t->irq, &addr, &data) == 0) {
 828                                 bus_write_4(sc->mem_res,
 829                                     HPET_TIMER_FSB_ADDR(i), addr);
 830                                 bus_write_4(sc->mem_res,
 831                                     HPET_TIMER_FSB_VAL(i), data);
 832                         }
 833                 }
 834 #endif
 835                 if (t->mode == 0)
 836                         continue;
 837                 t->next = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 838                 if (t->mode == 1 && (t->caps & HPET_TCAP_PER_INT)) {
 839                         t->caps |= HPET_TCNF_TYPE;
 840                         t->next += t->div;
 841                         bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num),
 842                             t->caps | HPET_TCNF_VAL_SET);
 843                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 844                             t->next);
 845                         bus_read_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num));
 846                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 847                             t->div);
 848                 } else {
 849                         t->next += sc->freq / 1024;
 850                         bus_write_4(sc->mem_res, HPET_TIMER_COMPARATOR(t->num),
 851                             t->next);
 852                 }
 853                 bus_write_4(sc->mem_res, HPET_ISR, 1 << t->num);
 854                 bus_write_4(sc->mem_res, HPET_TIMER_CAP_CNF(t->num), t->caps);
 855         }
 856         return (0);
 857 }
 858
 859 /* Print some basic latency/rate information to assist in debugging. */
 860 static void
 861 hpet_test(struct hpet_softc *sc)
 862 {
 863         int i;
 864         uint32_t u1, u2;
 865         struct bintime b0, b1, b2;
 866         struct timespec ts;
 867
 868         binuptime(&b0);
 869         binuptime(&b0);
 870         binuptime(&b1);
 871         u1 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 872         for (i = 1; i < 1000; i++)
 873                 u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 874         binuptime(&b2);
 875         u2 = bus_read_4(sc->mem_res, HPET_MAIN_COUNTER);
 876
 877         bintime_sub(&b2, &b1);
 878         bintime_sub(&b1, &b0);
 879         bintime_sub(&b2, &b1);
 880         bintime2timespec(&b2, &ts);
 881
 882         device_printf(sc->dev, "%ld.%09ld: %u ... %u = %u\n",
 883             (long)ts.tv_sec, ts.tv_nsec, u1, u2, u2 - u1);
 884
 885         device_printf(sc->dev, "time per call: %ld ns\n", ts.tv_nsec / 1000);
 886 }
 887
 888 #ifdef DEV_APIC
 889 static int
 890 hpet_remap_intr(device_t dev, device_t child, u_int irq)
 891 {
 892         struct hpet_softc *sc = device_get_softc(dev);
 893         struct hpet_timer *t;
 894         uint64_t addr;
 895         uint32_t data;
 896         int error, i;
 897
 898         for (i = 0; i < sc->num_timers; i++) {
 899                 t = &sc->t[i];
 900                 if (t->irq != irq)
 901                         continue;
 902                 error = PCIB_MAP_MSI(
 903                     device_get_parent(device_get_parent(dev)), dev,
 904                     irq, &addr, &data);
 905                 if (error)
 906                         return (error);
 907                 hpet_disable(sc); /* Stop timer to avoid interrupt loss. */
 908                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_ADDR(i), addr);
 909                 bus_write_4(sc->mem_res, HPET_TIMER_FSB_VAL(i), data);
 910                 hpet_enable(sc);
 911                 return (0);
 912         }
 913         return (ENOENT);
 914 }
 915 #endif
 916
 917 static device_method_t hpet_methods[] = {
 918         /* Device interface */
 919         DEVMETHOD(device_identify, hpet_identify),
 920         DEVMETHOD(device_probe, hpet_probe),
 921         DEVMETHOD(device_attach, hpet_attach),
 922         DEVMETHOD(device_detach, hpet_detach),
 923         DEVMETHOD(device_suspend, hpet_suspend),
 924         DEVMETHOD(device_resume, hpet_resume),
 925
 926 #ifdef DEV_APIC
 927         DEVMETHOD(bus_remap_intr, hpet_remap_intr),
 928 #endif
 929
 930         DEVMETHOD_END
 931 };
 932
 933 static driver_t hpet_driver = {
 934         "hpet",
 935         hpet_methods,
 936         sizeof(struct hpet_softc),
 937 };
 938
 939 DRIVER_MODULE(hpet, acpi, hpet_driver, hpet_devclass, 0, 0);
 940 MODULE_DEPEND(hpet, acpi, 1, 1, 1);