sys/dev/advansys/advlib.h

   1 /*-
   2  * Definitions for low level routines and data structures
   3  * for the Advanced Systems Inc. SCSI controllers chips.
   4  *
   5  * Copyright (c) 1996-1997, 1999-2000 Justin T. Gibbs.
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions, and the following disclaimer,
  13  *    without modification, immediately at the beginning of the file.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. The name of the author may not be used to endorse or promote products
  18  *    derived from this software without specific prior written permission.
  19  *
  20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  24  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  30  * SUCH DAMAGE.
  31  *
  32  * $FreeBSD$
  33  */
  34 /*-
  35  * Ported from:
  36  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  37  *
  38  * Copyright (c) 1995-1996 Advanced System Products, Inc.
  39  * All Rights Reserved.
  40  *
  41  * Redistribution and use in source and binary forms, with or without
  42  * modification, are permitted provided that redistributions of source
  43  * code retain the above copyright notice and this comment without
  44  * modification.
  45  */
  46
  47 #ifndef _ADVLIB_H_
  48 #define _ADVLIB_H_
  49
  50 #include <sys/queue.h>
  51
  52 struct cam_path;
  53 union ccb;
  54
  55 typedef u_int8_t target_bit_vector;
  56 #define TARGET_BIT_VECTOR_SET -1
  57 #define ADV_SCSI_ID_BITS        3
  58 #define ADV_MAX_TID             7
  59 #define ADV_MAX_LUN             7
  60
  61 #define ADV_MAXPHYS             (128 * 1024)
  62
  63 /* Enumeration of board types */
  64 typedef enum {
  65         ADV_NONE        = 0x000,
  66         ADV_ISA         = 0x001,
  67         ADV_ISAPNP      = 0x003,
  68         ADV_VL          = 0x004,
  69         ADV_PCI         = 0x010,
  70         ADV_PCMCIA      = 0x040,
  71         ADV_ULTRA       = 0x100,
  72         ADV_WIDE        = 0x200,
  73         ADV_WIDE32      = 0x400
  74 } adv_btype;
  75
  76 typedef enum {
  77         ADV_STATE_NONE                  = 0x00,
  78         ADV_RESOURCE_SHORTAGE           = 0x01,
  79         ADV_IN_TIMEOUT                  = 0x02,
  80         ADV_BUSDMA_BLOCK                = 0x04,
  81         ADV_BUSDMA_BLOCK_CLEARED        = 0x08
  82
  83 } adv_state;
  84
  85 typedef enum {
  86         ACCB_FREE               = 0x00,
  87         ACCB_ACTIVE             = 0x01,
  88         ACCB_ABORT_QUEUED       = 0x02,
  89         ACCB_RECOVERY_CCB       = 0x04
  90 } adv_ccb_state;
  91
  92 struct adv_ccb_info {
  93         adv_ccb_state   state;
  94         bus_dmamap_t    dmamap;
  95         struct callout  timer;
  96         union ccb*      ccb;
  97         SLIST_ENTRY(adv_ccb_info) links;
  98 };
  99
 100 #define ccb_cinfo_ptr spriv_ptr0
 101
 102 #define ADV_SYN_XFER_NO                 8
 103 #define ADV_SYN_MAX_OFFSET              0x0F
 104 #define ADV_DEF_SDTR_OFFSET             0x0F
 105 #define ADV_DEF_SDTR_INDEX              0x00
 106 #define ADV_OVERRUN_BSIZE               0x00000040
 107 #define ADV_MAX_CDB_LEN                 12
 108 #define ADV_MAX_SENSE_LEN               32
 109 #define ADV_MIN_SENSE_LEN               14
 110
 111 #define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) )
 112 #define ADV_TID_TO_TARGET_MASK(tid)  (0x01 << (tid))
 113 #define ADV_TIX_TO_TARGET_MASK(tix)  (0x01 << ((tix) & ADV_MAX_TID))
 114 #define ADV_TIX_TO_TID(tix)  ((tix) & ADV_MAX_TID)
 115 #define ADV_TID_TO_TIX(tid)  ((tid) & ADV_MAX_TID)
 116 #define ADV_TIX_TO_LUN(tix)  (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN )
 117
 118
 119 /*
 120  * XXX
 121  * PnP port addresses
 122  * I believe that these are standard PnP address and should be replaced
 123  * by the values in a central ISA PnP header file when we get one.
 124  */
 125 #define ADV_ISA_PNP_PORT_ADDR  (0x279)
 126 #define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800)
 127
 128 /*
 129  * Board Signatures
 130  */
 131 #define ADV_SIGNATURE_WORD                      0x0000
 132 #define          ADV_1000_ID0W                  0x04C1
 133 #define          ADV_1000_ID0W_FIX              0x00C1
 134
 135 #define ADV_SIGNATURE_BYTE                      0x0001
 136 #define          ADV_1000_ID1B                  0x25
 137
 138 #define ADV_REG_IH                              0x0002
 139 #define         ADV_INS_HALTINT                 0x6281
 140 #define         ADV_INS_HALT                    0x6280
 141 #define         ADV_INS_SINT                    0x6200
 142 #define         ADV_INS_RFLAG_WTM               0x7380
 143
 144 #define ADV_CONFIG_LSW                          0x0002
 145 #define         ADV_CFG_LSW_ISA_DMA_CHANNEL     0x0003
 146 #define         ADV_CFG_LSW_HOST_INT_ON         0x0020
 147 #define         ADV_CFG_LSW_BIOS_ON             0x0040
 148 #define         ADV_CFG_LSW_VERA_BURST_ON       0x0080
 149 #define         ADV_CFG_LSW_SCSI_PARITY_ON      0x0800
 150 #define         ADV_CFG_LSW_SCSIID              0x0700
 151 #define         ADV_CFG_LSW_SCSIID_SHIFT        8
 152 #define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID)
 153
 154 /*
 155  * Chip Revision Number
 156  */
 157 #define ADV_NONEISA_CHIP_REVISION               0x0003
 158 #define         ADV_CHIP_MIN_VER_VL             0x01
 159 #define         ADV_CHIP_MAX_VER_VL             0x07
 160 #define         ADV_CHIP_MIN_VER_PCI            0x09
 161 #define         ADV_CHIP_MAX_VER_PCI            0x0F
 162 #define         ADV_CHIP_VER_PCI_BIT            0x08
 163 #define         ADV_CHIP_VER_PCI_ULTRA_3150  (ADV_CHIP_VER_PCI_BIT | 0x02)
 164 #define         ADV_CHIP_VER_PCI_ULTRA_3050  (ADV_CHIP_VER_PCI_BIT | 0x03)
 165 #define         ADV_CHIP_MIN_VER_ISA            0x11
 166 #define         ADV_CHIP_MIN_VER_ISA_PNP        0x21
 167 #define         ADV_CHIP_MAX_VER_ISA            0x27
 168 #define         ADV_CHIP_VER_ISA_BIT            0x30
 169 #define         ADV_CHIP_VER_ISAPNP_BIT         0x20
 170 #define         ADV_CHIP_VER_ASYN_BUG           0x21
 171
 172 #define ADV_CONFIG_MSW                          0x0004
 173 #define         ADV_CFG_MSW_SCSI_TARGET_ON      0x0080
 174 #define         ADV_CFG_MSW_LRAM_8BITS_ON       0x0800
 175 #define         ADV_CFG_MSW_CLR_MASK            0x30C0
 176
 177 #define ADV_EEPROM_DATA                         0x0006
 178
 179 #define ADV_EEPROM_CMD                          0x0007
 180 #define         ADV_EEPROM_CMD_READ             0x80
 181 #define         ADV_EEPROM_CMD_WRITE            0x40
 182 #define         ADV_EEPROM_CMD_WRITE_ENABLE     0x30
 183 #define         ADV_EEPROM_CMD_WRITE_DISABLE    0x00
 184
 185 #define ADV_DMA_SPEED                           0x0007
 186 #define         ADV_DEF_ISA_DMA_SPEED           4
 187 #define ADV_REG_FLAG                            0x0007
 188
 189 #define ADV_LRAM_DATA                           0x0008
 190
 191 #define ADV_LRAM_ADDR                           0x000A
 192
 193 #define ADV_SYN_OFFSET                          0x000B
 194
 195 #define ADV_REG_PROG_COUNTER                    0x000C
 196 #define         ADV_MCODE_START_ADDR            0x0080
 197
 198 #define ADV_REG_IFC                             0x000D
 199 #define         ADV_IFC_REG_LOCK                0x00
 200 #define         ADV_IFC_REG_UNLOCK              0x09
 201 #define         ADV_IFC_WR_EN_FILTER            0x10
 202 #define         ADV_IFC_RD_NO_EEPROM            0x10
 203 #define         ADV_IFC_SLEW_RATE               0x20
 204 #define         ADV_IFC_ACT_NEG                 0x40
 205 #define         ADV_IFC_INP_FILTER              0x80
 206 #define         ADV_IFC_INIT_DEFAULT  (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK)
 207
 208 #define ADV_CHIP_STATUS                         0x000E
 209 #define         ADV_CSW_TEST1                   0x8000
 210 #define         ADV_CSW_AUTO_CONFIG             0x4000
 211 #define         ADV_CSW_RESERVED1               0x2000
 212 #define         ADV_CSW_IRQ_WRITTEN             0x1000
 213 #define         ADV_CSW_33MHZ_SELECTED          0x0800
 214 #define         ADV_CSW_TEST2                   0x0400
 215 #define         ADV_CSW_TEST3                   0x0200
 216 #define         ADV_CSW_RESERVED2               0x0100
 217 #define         ADV_CSW_DMA_DONE                0x0080
 218 #define         ADV_CSW_FIFO_RDY                0x0040
 219 #define         ADV_CSW_EEP_READ_DONE           0x0020
 220 #define         ADV_CSW_HALTED                  0x0010
 221 #define         ADV_CSW_SCSI_RESET_ACTIVE       0x0008
 222 #define         ADV_CSW_PARITY_ERR              0x0004
 223 #define         ADV_CSW_SCSI_RESET_LATCH        0x0002
 224 #define         ADV_CSW_INT_PENDING             0x0001
 225 /*
 226  * XXX I don't understand the relevance of the naming
 227  * convention change here.  What does CIW stand for?
 228  * Perhaps this is to differentiate read and write
 229  * values?
 230  */
 231 #define         ADV_CIW_INT_ACK                 0x0100
 232 #define         ADV_CIW_TEST1                   0x0200
 233 #define         ADV_CIW_TEST2                   0x0400
 234 #define         ADV_CIW_SEL_33MHZ               0x0800
 235 #define         ADV_CIW_IRQ_ACT                 0x1000
 236 #define         ADV_CIW_CLR_SCSI_RESET_INT      0x1000
 237
 238 #define ADV_CHIP_CTRL                           0x000F
 239 #define         ADV_CC_CHIP_RESET               0x80
 240 #define         ADV_CC_SCSI_RESET               0x40
 241 #define         ADV_CC_HALT                     0x20
 242 #define         ADV_CC_SINGLE_STEP              0x10
 243 #define         ADV_CC_DMA_ENABLE               0x08
 244 #define         ADV_CC_TEST                     0x04
 245 #define         ADV_CC_BANK_ONE                 0x02
 246 #define         ADV_CC_DIAG                     0x01
 247
 248 #define ADV_HALTCODE_W                          0x0040
 249 #define ADV_STOP_CODE_B                         0x0034
 250 #define         ADV_STOP_REQ_RISC_STOP          0x01
 251 #define         ADV_STOP_ACK_RISC_STOP          0x03
 252 #define         ADV_STOP_CLEAN_UP_BUSY_Q        0x10
 253 #define         ADV_STOP_CLEAN_UP_DISC_Q        0x20
 254 #define         ADV_STOP_HOST_REQ_RISC_HALT     0x40
 255
 256 /*
 257  * EEPROM routine constants
 258  * XXX What about wide controllers?
 259  * Surely they have space for 8 more targets.
 260  */
 261 #define ADV_EEPROM_CFG_BEG_VL           2
 262 #define ADV_EEPROM_MAX_ADDR_VL          15
 263 #define ADV_EEPROM_CFG_BEG              32
 264 #define ADV_EEPROM_MAX_ADDR             45
 265 #define ADV_EEPROM_MAX_RETRY            20
 266
 267 struct adv_eeprom_config {
 268         u_int16_t       cfg_lsw;
 269
 270         u_int16_t       cfg_msw;
 271
 272         u_int8_t        init_sdtr;
 273         u_int8_t        disc_enable;
 274
 275         u_int8_t        use_cmd_qng;
 276         u_int8_t        start_motor;
 277
 278         u_int8_t        max_total_qng;
 279         u_int8_t        max_tag_qng;
 280
 281         u_int8_t        bios_scan;
 282         u_int8_t        power_up_wait;
 283
 284         u_int8_t        no_scam;
 285         u_int8_t        scsi_id_dma_speed;
 286 #define         EEPROM_SCSI_ID_MASK     0x0F
 287 #define         EEPROM_DMA_SPEED_MASK   0xF0
 288 #define         EEPROM_DMA_SPEED(ep)                            \
 289                 (((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4)
 290 #define         EEPROM_SET_DMA_SPEED(ep, speed)                 \
 291                 (ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK;       \
 292                 (ep).scsi_id_dma_speed |=                               \
 293                     (((speed) << 4) & EEPROM_DMA_SPEED_MASK)
 294 #define         EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK)
 295 #define         EEPROM_SET_SCSIID(ep, id)                       \
 296                 (ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \
 297                 (ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK)
 298         u_int8_t        sdtr_data[8];
 299         u_int8_t        adapter_info[6];
 300
 301         u_int16_t       cntl;
 302
 303         u_int16_t       chksum;
 304 };
 305
 306 /* Bank 1 */
 307 #define ADV_SEQ_ACCUM                           0x0000
 308 #define ADV_QUEUE_ELEMENT_INDEX                 0x0001
 309 #define ADV_SEQ_INSTRUCTION_HOLD                0x0002
 310 #define ADV_QUEUE_ELEMENT_POINTER               0x0003
 311 #define ADV_HOST_DATA_FIFO_L                    0x0004
 312 #define ADV_HOST_SCSIID                         0x0005
 313 #define ADV_HOST_DATA_FIFO_H                    0x0006
 314 #define ADV_SCSI_CONTROL                        0x0009
 315 #define         SC_SEL                          0x80
 316 #define         SC_BSY                          0x40
 317 #define         SC_ACK                          0x20
 318 #define         SC_REQ                          0x10
 319 #define         SC_ATN                          0x08
 320 #define         SC_IO                           0x04
 321 #define         SC_CD                           0x02
 322 #define         SC_MSG                          0x01
 323 #define ADV_SCSIDATL                            0x000B
 324 #define ADV_DMA_TRANSFER_CNT                    0x000C
 325 #define ADV_DMA_TRANSFER_CNT1                   0x000E
 326
 327 /*
 328  * Instruction data and code segment addresses,
 329  * and transaction address translation (queues).
 330  * All addresses refer to on board LRAM.
 331  */
 332 #define ADV_DATA_SEC_BEG                0x0080
 333 #define ADV_DATA_SEC_END                0x0080
 334 #define ADV_CODE_SEC_BEG                0x0080
 335 #define ADV_CODE_SEC_END                0x0080
 336 #define ADV_QADR_BEG                    0x4000
 337 #define ADV_QADR_END                    0x7FFF
 338 #define ADV_QLAST_ADR                   0x7FC0
 339 #define ADV_QBLK_SIZE                   0x40
 340 #define ADV_BIOS_DATA_QBEG              0xF8
 341 #define ADV_MAX_QNO                     0xF8
 342 #define ADV_QADR_USED (ADV_MAX_QNO * 64)
 343 #define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6))
 344
 345 #define ADV_MIN_ACTIVE_QNO              0x01
 346 #define ADV_QLINK_END                   0xFF
 347
 348 #define ADV_MAX_SG_QUEUE                5
 349 #define ADV_SG_LIST_PER_Q               7
 350 #define ADV_MAX_SG_LIST                 (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE)))
 351
 352 #define ADV_MIN_REMAIN_Q                0x02
 353 #define ADV_DEF_MAX_TOTAL_QNG           0xF0
 354 #define ADV_MIN_TAG_Q_PER_DVC           0x04
 355 #define ADV_DEF_TAG_Q_PER_DVC           0x04
 356 #define ADV_MIN_FREE_Q                  ADV_MIN_REMAIN_Q
 357 #define ADV_MIN_TOTAL_QNG               ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q))
 358 #define ADV_MAX_TOTAL_QNG               240
 359 #define ADV_MAX_INRAM_TAG_QNG           16
 360 #define ADV_MAX_PCI_INRAM_TOTAL_QNG     20
 361 #define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 362 #define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
 363
 364 #define ADV_DEF_IRQ_NO                  10
 365 #define ADV_MAX_IRQ_NO                  15
 366 #define ADV_MIN_IRQ_NO                  10
 367
 368 #define ADV_SCSIQ_CPY_BEG               4
 369 #define ADV_SCSIQ_SGHD_CPY_BEG          2
 370
 371 /* SCSIQ Microcode representation offsets */
 372 #define ADV_SCSIQ_B_FWD                 0
 373 #define ADV_SCSIQ_B_BWD                 1
 374 #define ADV_SCSIQ_B_STATUS              2
 375 #define ADV_SCSIQ_B_QNO                 3
 376 #define ADV_SCSIQ_B_CNTL                4
 377 #define ADV_SCSIQ_B_SG_QUEUE_CNT        5
 378 #define ADV_SCSIQ_B_LIST_CNT            6
 379 #define ADV_SCSIQ_B_CUR_LIST_CNT        7
 380 #define ADV_SCSIQ_D_DATA_ADDR           8
 381 #define ADV_SCSIQ_D_DATA_CNT            12
 382 #define ADV_SCSIQ_B_SENSE_LEN           20
 383 #define ADV_SCSIQ_DONE_INFO_BEG         22
 384 #define ADV_SCSIQ_D_CINFO_IDX           22
 385 #define ADV_SCSIQ_B_TARGET_IX           26
 386 #define ADV_SCSIQ_B_CDB_LEN             28
 387 #define ADV_SCSIQ_B_TAG_CODE            29
 388 #define ADV_SCSIQ_W_VM_ID               30
 389 #define ADV_SCSIQ_DONE_STATUS           32
 390 #define ADV_SCSIQ_HOST_STATUS           33
 391 #define ADV_SCSIQ_SCSI_STATUS           34
 392 #define ADV_SCSIQ_CDB_BEG               36
 393 #define ADV_SCSIQ_B_FIRST_SG_QK_QP      48
 394 #define ADV_SCSIQ_B_SG_WK_QP            49
 395 #define ADV_SCSIQ_B_SG_WK_IX            50
 396 #define ADV_SCSIQ_W_ALT_DC1             52
 397 #define ADV_SCSIQ_DW_REMAIN_XFER_ADDR   56
 398 #define ADV_SCSIQ_DW_REMAIN_XFER_CNT    60
 399
 400 /* LRAM Offsets */
 401 #define ADVV_MSGOUT_BEG                 0x0000
 402 #define ADVV_MSGOUT_SDTR_PERIOD         (ADVV_MSGOUT_BEG+3)
 403 #define ADVV_MSGOUT_SDTR_OFFSET         (ADVV_MSGOUT_BEG+4)
 404
 405 #define ADVV_BREAK_SAVED_CODE           0x0006
 406
 407 #define ADVV_MSGIN_BEG                  (ADVV_MSGOUT_BEG+8)
 408 #define ADVV_MSGIN_SDTR_PERIOD          (ADVV_MSGIN_BEG+3)
 409 #define ADVV_MSGIN_SDTR_OFFSET          (ADVV_MSGIN_BEG+4)
 410
 411 #define ADVV_SDTR_DATA_BEG              (ADVV_MSGIN_BEG+8)
 412 #define ADVV_SDTR_DONE_BEG              (ADVV_SDTR_DATA_BEG+8)
 413 #define ADVV_MAX_DVC_QNG_BEG            0x0020
 414
 415 #define ADVV_BREAK_ADDR                 0x0028
 416 #define ADVV_BREAK_NOTIFY_COUNT         0x002A
 417 #define ADVV_BREAK_CONTROL              0x002C
 418 #define ADVV_BREAK_HIT_COUNT            0x002E
 419
 420 #define ADVV_ASCDVC_ERR_CODE_W          0x0030
 421 #define ADVV_MCODE_CHKSUM_W             0x0032
 422 #define ADVV_MCODE_SIZE_W               0x0034
 423 #define ADVV_STOP_CODE_B                0x0036
 424 #define ADVV_DVC_ERR_CODE_B             0x0037
 425
 426 #define ADVV_OVERRUN_PADDR_D            0x0038
 427 #define ADVV_OVERRUN_BSIZE_D            0x003C
 428
 429 #define ADVV_HALTCODE_W                 0x0040
 430 #define         ADV_HALT_EXTMSG_IN                      0x8000
 431 #define         ADV_HALT_CHK_CONDITION                  0x8100
 432 #define         ADV_HALT_SS_QUEUE_FULL                  0x8200
 433 #define         ADV_HALT_DISABLE_ASYN_USE_SYN_FIX       0x8300
 434 #define         ADV_HALT_ENABLE_ASYN_USE_SYN_FIX        0x8400
 435 #define         ADV_HALT_SDTR_REJECTED                  0x4000
 436 #define         ADV_HALT_HOST_COPY_SG_LIST_TO_RISC      0x2000
 437
 438 #define ADVV_CHKSUM_W                   0x0042
 439 #define ADVV_MC_DATE_W                  0x0044
 440 #define ADVV_MC_VER_W                   0x0046
 441 #define ADVV_NEXTRDY_B                  0x0048
 442 #define ADVV_DONENEXT_B                 0x0049
 443 #define ADVV_USE_TAGGED_QNG_B           0x004A
 444 #define ADVV_SCSIBUSY_B                 0x004B
 445 #define ADVV_Q_DONE_IN_PROGRESS_B       0x004C
 446 #define ADVV_CURCDB_B                   0x004D
 447 #define ADVV_RCLUN_B                    0x004E
 448 #define ADVV_BUSY_QHEAD_B               0x004F
 449 #define ADVV_DISC1_QHEAD_B              0x0050
 450
 451 #define ADVV_DISC_ENABLE_B              0x0052
 452 #define ADVV_CAN_TAGGED_QNG_B           0x0053
 453 #define ADVV_HOSTSCSI_ID_B              0x0055
 454 #define ADVV_MCODE_CNTL_B               0x0056
 455 #define ADVV_NULL_TARGET_B              0x0057
 456
 457 #define ADVV_FREE_Q_HEAD_W              0x0058
 458 #define ADVV_DONE_Q_TAIL_W              0x005A
 459 #define ADVV_FREE_Q_HEAD_B              (ADVV_FREE_Q_HEAD_W+1)
 460 #define ADVV_DONE_Q_TAIL_B              (ADVV_DONE_Q_TAIL_W+1)
 461
 462 #define ADVV_HOST_FLAG_B                0x005D
 463 #define         ADV_HOST_FLAG_IN_ISR    0x01
 464 #define         ADV_HOST_FLAG_ACK_INT   0x02
 465
 466
 467 #define ADVV_TOTAL_READY_Q_B              0x0064
 468 #define ADVV_VER_SERIAL_B                 0x0065
 469 #define ADVV_HALTCODE_SAVED_W             0x0066
 470 #define ADVV_WTM_FLAG_B                   0x0068
 471 #define ADVV_RISC_FLAG_B                  0x006A
 472 #define         ADV_RISC_FLAG_GEN_INT     0x01
 473 #define         ADV_RISC_FLAG_REQ_SG_LIST 0x02
 474
 475 #define ADVV_REQ_SG_LIST_QP             0x006B
 476
 477 #define ADV_TRANS_CUR           0x01    /* Modify current neogtiation status */
 478 #define ADV_TRANS_ACTIVE        0x03    /* Assume this is the active target */
 479 #define ADV_TRANS_GOAL          0x04    /* Modify negotiation goal */
 480 #define ADV_TRANS_USER          0x08    /* Modify user negotiation settings */
 481
 482 struct adv_transinfo {
 483         u_int8_t period;
 484         u_int8_t offset;
 485 };
 486
 487 struct adv_target_transinfo {
 488         struct adv_transinfo current;
 489         struct adv_transinfo goal;
 490         struct adv_transinfo user;
 491 };
 492
 493 struct adv_softc {
 494         device_t                 dev;
 495         struct resource         *res;
 496         long                     reg_off;
 497         struct cam_sim          *sim;
 498         LIST_HEAD(, ccb_hdr)     pending_ccbs;
 499         struct adv_ccb_info     *ccb_infos;
 500         SLIST_HEAD(, adv_ccb_info) free_ccb_infos;
 501         bus_dma_tag_t            parent_dmat;
 502         bus_dma_tag_t            buffer_dmat;
 503         bus_dma_tag_t            sense_dmat;
 504         bus_dmamap_t             sense_dmamap;
 505         struct scsi_sense_data  *sense_buffers;
 506         bus_addr_t               sense_physbase;
 507         bus_addr_t               overrun_physbase;
 508         adv_btype                type;
 509         struct                   adv_target_transinfo tinfo[8];
 510         target_bit_vector        fix_asyn_xfer;
 511         target_bit_vector        fix_asyn_xfer_always;
 512         target_bit_vector        disc_enable;
 513         target_bit_vector        user_disc_enable;
 514         target_bit_vector        cmd_qng_enabled;
 515         target_bit_vector        user_cmd_qng_enabled;
 516         u_int16_t                control;
 517 #define         ADV_CNTL_INITIATOR              0x0001
 518 #define         ADV_CNTL_BIOS_GT_1GB            0x0002
 519 #define         ADV_CNTL_BIOS_GT_2_DISK         0x0004
 520 #define         ADV_CNTL_BIOS_REMOVABLE         0x0008
 521 #define         ADV_CNTL_NO_SCAM                0x0010
 522 #define         ADV_CNTL_INT_MULTI_Q            0x0080
 523 #define         ADV_CNTL_NO_LUN_SUPPORT         0x0040
 524 #define         ADV_CNTL_NO_VERIFY_COPY         0x0100
 525 #define         ADV_CNTL_RESET_SCSI             0x0200
 526 #define         ADV_CNTL_INIT_INQUIRY           0x0400
 527 #define         ADV_CNTL_INIT_VERBOSE           0x0800
 528 #define         ADV_CNTL_SCSI_PARITY            0x1000
 529 #define         ADV_CNTL_BURST_MODE             0x2000
 530 #define         ADV_CNTL_SDTR_ENABLE_ULTRA      0x4000
 531
 532         u_int16_t                bug_fix_control;
 533 #define         ADV_BUG_FIX_IF_NOT_DWB          0x0001
 534 #define         ADV_BUG_FIX_ASYN_USE_SYN        0x0002
 535
 536         adv_state                state;
 537         struct cam_path         *path;
 538         int                      init_level;
 539         u_int32_t                max_dma_addr;
 540         u_int32_t                max_dma_count;
 541         u_int8_t                 isa_dma_speed;
 542         u_int8_t                 isa_dma_channel;
 543         u_int8_t                 scsi_id;
 544         u_int8_t                 chip_version;
 545         u_int8_t                 max_tags_per_target;
 546         u_int8_t                 max_openings;
 547         u_int8_t                 cur_active;
 548         u_int8_t                 openings_needed;
 549         u_int8_t                 ccb_infos_allocated;
 550         u_int8_t                *sdtr_period_tbl;
 551         u_int8_t                 sdtr_period_tbl_size;
 552         struct mtx               lock;
 553 };
 554
 555 /*
 556  * Structures for talking to the RISC engine.
 557  */
 558 struct adv_scsiq_1 {
 559         u_int8_t                status;
 560 #define         QS_FREE        0x00
 561 #define         QS_READY       0x01
 562 #define         QS_DISC1       0x02
 563 #define         QS_DISC2       0x04
 564 #define         QS_BUSY        0x08
 565 #define         QS_ABORTED     0x40
 566 #define         QS_DONE        0x80
 567
 568         u_int8_t                q_no;           /*
 569                                                  * Queue ID of the first queue
 570                                                  * used in this transaction.
 571                                                  */
 572         u_int8_t                cntl;
 573 #define         QC_NO_CALLBACK   0x01
 574 #define         QC_SG_SWAP_QUEUE 0x02
 575 #define         QC_SG_HEAD       0x04
 576 #define         QC_DATA_IN       0x08
 577 #define         QC_DATA_OUT      0x10
 578 #define         QC_URGENT        0x20
 579 #define         QC_MSG_OUT       0x40
 580 #define         QC_REQ_SENSE     0x80
 581
 582         u_int8_t                sg_queue_cnt;   /* Number of SG entries */
 583
 584         u_int8_t                target_id;      /* target id as a bit vector */
 585         u_int8_t                target_lun;     /* LUN - taken from our xs */
 586
 587         u_int32_t               data_addr;      /*
 588                                                  * physical address of first
 589                                                  * (possibly only) segment
 590                                                  * to transfer.
 591                                                  */
 592         u_int32_t               data_cnt;       /*
 593                                                  * byte count of the first
 594                                                  * (possibly only) segment
 595                                                  * to transfer.
 596                                                  */
 597         u_int32_t               sense_addr;     /*
 598                                                  * physical address of the sense
 599                                                  * buffer.
 600                                                  */
 601         u_int8_t                sense_len;      /* length of sense buffer */
 602         u_int8_t                extra_bytes;
 603 };
 604
 605 struct adv_scsiq_2 {
 606         u_int32_t               ccb_index;      /* Index to our CCB Info */
 607         u_int8_t                target_ix;      /* Combined TID and LUN */
 608
 609         u_int8_t                flag;
 610         u_int8_t                cdb_len;        /*
 611                                                  * Number of bytes in the SCSI
 612                                                  * command to execute.
 613                                                  */
 614         u_int8_t                tag_code;       /*
 615                                                  * Tag type for this transaction
 616                                                  * (SIMPLE, ORDERED, HEAD )
 617                                                  */
 618 #define         ADV_TAG_FLAG_EXTRA_BYTES               0x10
 619 #define         ADV_TAG_FLAG_DISABLE_DISCONNECT        0x04
 620 #define         ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 621 #define         ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 622
 623         u_int16_t               vm_id;
 624 };
 625
 626 struct adv_scsiq_3 {
 627         u_int8_t                done_stat;
 628 #define         QD_IN_PROGRESS                  0x00
 629 #define         QD_NO_ERROR                     0x01
 630 #define         QD_ABORTED_BY_HOST              0x02
 631 #define         QD_WITH_ERROR                   0x04
 632 #define         QD_INVALID_REQUEST              0x80
 633 #define         QD_INVALID_HOST_NUM             0x81
 634 #define         QD_INVALID_DEVICE               0x82
 635 #define         QD_ERR_INTERNAL                 0xFF
 636
 637         u_int8_t                host_stat;
 638 #define         QHSTA_NO_ERROR                  0x00
 639 #define         QHSTA_M_SEL_TIMEOUT             0x11
 640 #define         QHSTA_M_DATA_OVER_RUN           0x12
 641 #define         QHSTA_M_DATA_UNDER_RUN          0x12
 642 #define         QHSTA_M_UNEXPECTED_BUS_FREE     0x13
 643 #define         QHSTA_M_BAD_BUS_PHASE_SEQ       0x14
 644
 645 #define         QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 646 #define         QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 647 #define         QHSTA_D_HOST_ABORT_FAILED       0x23
 648 #define         QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 649 #define         QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 650 #define         QHSTA_D_ASPI_NO_BUF_POOL        0x26
 651
 652 #define         QHSTA_M_WTM_TIMEOUT             0x41
 653 #define         QHSTA_M_BAD_CMPL_STATUS_IN      0x42
 654 #define         QHSTA_M_NO_AUTO_REQ_SENSE       0x43
 655 #define         QHSTA_M_AUTO_REQ_SENSE_FAIL     0x44
 656 #define         QHSTA_M_TARGET_STATUS_BUSY      0x45
 657 #define         QHSTA_M_BAD_TAG_CODE            0x46
 658
 659 #define         QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 660 #define         QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 661
 662 #define         QHSTA_D_LRAM_CMP_ERROR          0x81
 663
 664 #define         QHSTA_M_MICRO_CODE_ERROR_HALT   0xA1
 665
 666         u_int8_t                scsi_stat;
 667         u_int8_t                scsi_msg;
 668 };
 669
 670 struct adv_scsiq_4 {
 671         u_int8_t                cdb[ADV_MAX_CDB_LEN];
 672         u_int8_t                y_first_sg_list_qp;
 673         u_int8_t                y_working_sg_qp;
 674         u_int8_t                y_working_sg_ix;
 675         u_int8_t                y_res;
 676         u_int16_t               x_req_count;
 677         u_int16_t               x_reconnect_rtn;
 678         u_int32_t               x_saved_data_addr;
 679         u_int32_t               x_saved_data_cnt;
 680 };
 681
 682 struct adv_q_done_info {
 683         struct adv_scsiq_2      d2;
 684         struct adv_scsiq_3      d3;
 685         u_int8_t                q_status;
 686         u_int8_t                q_no;
 687         u_int8_t                cntl;
 688         u_int8_t                sense_len;
 689         u_int8_t                extra_bytes;
 690         u_int8_t                res;
 691         u_int32_t               remain_bytes;
 692 };
 693
 694 struct adv_sg_entry {
 695         u_int32_t               addr;
 696         u_int32_t               bytes;
 697 };
 698
 699 struct adv_sg_head {
 700         u_int16_t               entry_cnt;      /*
 701                                                  * Number of SG entries
 702                                                  * in this list
 703                                                  */
 704
 705         u_int16_t               queue_cnt;      /*
 706                                                  * Number of queues required
 707                                                  * to store entry_cnt
 708                                                  * SG entries.
 709                                                  */
 710
 711         u_int16_t               entry_to_copy;  /*
 712                                                  * Number of SG entries to
 713                                                  * copy to the board.
 714                                                  */
 715         u_int16_t               res;
 716         struct adv_sg_entry     *sg_list;
 717 };
 718
 719 #define QCX_SORT        (0x0001)
 720 #define QCX_COALEASE    (0x0002)
 721
 722 struct adv_scsi_q {
 723         struct adv_scsiq_1      q1;
 724         struct adv_scsiq_2      q2;
 725         u_int8_t                *cdbptr;        /*
 726                                                  * Pointer to the SCSI command
 727                                                  * to execute.
 728                                                  */
 729
 730         struct adv_sg_head      *sg_head;       /*
 731                                                  * Pointer to possible SG list
 732                                                  */
 733 };
 734
 735 struct adv_scsi_req_q {
 736         struct adv_scsiq_1      r1;
 737         struct adv_scsiq_2      r2;
 738         u_int8_t                *cdbptr;
 739         struct adv_sg_head      *sg_head;
 740         u_int8_t                *sense_ptr;
 741         struct adv_scsiq_3      r3;
 742         u_int8_t                cdb[ADV_MAX_CDB_LEN];
 743         u_int8_t                sense[ADV_MIN_SENSE_LEN];
 744 };
 745
 746 struct adv_risc_q {
 747         u_int8_t                fwd;
 748         u_int8_t                bwd;
 749         struct adv_scsiq_1      i1;
 750         struct adv_scsiq_2      i2;
 751         struct adv_scsiq_3      i3;
 752         struct adv_scsiq_4      i4;
 753 };
 754
 755 struct adv_sg_list_q {
 756         u_int8_t                seq_no;
 757         u_int8_t                q_no;
 758         u_int8_t                cntl;
 759 #define         QCSG_SG_XFER_LIST  0x02
 760 #define         QCSG_SG_XFER_MORE  0x04
 761 #define         QCSG_SG_XFER_END   0x08
 762
 763         u_int8_t                sg_head_qp;
 764         u_int8_t                sg_list_cnt;
 765         u_int8_t                sg_cur_list_cnt;
 766 };
 767 #define ADV_SGQ_B_SG_CNTL               4
 768 #define ADV_SGQ_B_SG_HEAD_QP            5
 769 #define ADV_SGQ_B_SG_LIST_CNT           6
 770 #define ADV_SGQ_B_SG_CUR_LIST_CNT       7
 771 #define ADV_SGQ_LIST_BEG                8
 772
 773 struct asc_risc_sg_list_q {
 774         u_int8_t                fwd;
 775         u_int8_t                bwd;
 776         struct adv_sg_list_q    sg;
 777         struct adv_sg_entry     sg_list[ADV_SG_LIST_PER_Q];
 778 };
 779
 780 /* Chip Register functions */
 781 void      adv_set_bank(struct adv_softc *adv, u_int8_t bank);
 782
 783 /* LRAM routines */
 784 u_int8_t  adv_read_lram_8(struct adv_softc *adv, u_int16_t addr);
 785 void      adv_write_lram_8(struct adv_softc *adv, u_int16_t addr,
 786                            u_int8_t value);
 787 u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr);
 788 void      adv_write_lram_16(struct adv_softc *adv, u_int16_t addr,
 789                             u_int16_t value);
 790
 791 /* Initialization */
 792 int       adv_find_signature(struct resource *res);
 793 void      adv_lib_init(struct adv_softc *adv);
 794
 795 u_int16_t adv_get_eeprom_config(struct adv_softc *adv,
 796                                 struct adv_eeprom_config *eeprom_config);
 797 int       adv_set_eeprom_config(struct adv_softc *adv,
 798                                 struct adv_eeprom_config *eeprom_config);
 799 int       adv_reset_chip(struct adv_softc *adv, int reset_bus);
 800 int       adv_test_external_lram(struct adv_softc* adv);
 801 int       adv_init_lram_and_mcode(struct adv_softc *adv);
 802 u_int8_t  adv_get_chip_irq(struct adv_softc *adv);
 803 u_int8_t  adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no);
 804 void      adv_set_chip_scsiid(struct adv_softc *adv, int new_id);
 805
 806 /* Queue handling and execution */
 807 int       adv_execute_scsi_queue(struct adv_softc *adv,
 808                                  struct adv_scsi_q *scsiq,
 809                                  u_int32_t datalen);
 810 u_int8_t  adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr,
 811                               struct adv_q_done_info *scsiq, u_int32_t max_dma_count);
 812
 813 /* Chip Control */
 814 int       adv_start_chip(struct adv_softc *adv);
 815 void      adv_start_execution(struct adv_softc *adv);
 816 int       adv_stop_execution(struct adv_softc *adv);
 817 int       adv_stop_chip(struct adv_softc *adv);
 818 int       adv_is_chip_halted(struct adv_softc *adv);
 819
 820 /* Interrupt processing */
 821 void      adv_ack_interrupt(struct adv_softc *adv);
 822 void      adv_isr_chip_halted(struct adv_softc *adv);
 823
 824 /* SDTR Conversion */
 825 void      adv_set_syncrate(struct adv_softc *adv, struct cam_path *path,
 826                            u_int target_id, u_int period, u_int offset,
 827                            u_int type);
 828 void      adv_sdtr_to_period_offset(struct adv_softc *adv,
 829                                     u_int8_t sync_data, u_int8_t *period,
 830                                     u_int8_t *offset, int tid);
 831 u_int8_t  adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period,
 832                                     u_int *offset, int tid);
 833
 834 /* Error recovery */
 835 union ccb;
 836 int       adv_abort_ccb(struct adv_softc *adv, int target, int lun,
 837                         union ccb *ccb, u_int32_t status, int queued_only);
 838 int       adv_reset_bus(struct adv_softc *adv, int initiate_reset);
 839
 840 /* Async event callback */
 841 void    advasync(void *callback_arg, u_int32_t code,
 842                  struct cam_path *path, void *arg);
 843
 844 #define ADV_INB(adv, offset)                    \
 845         bus_read_1((adv)->res, (adv)->reg_off + offset)
 846 #define ADV_INW(adv, offset)                    \
 847         bus_read_2((adv)->res, (adv)->reg_off + offset)
 848 #define ADV_INSB(adv, offset, valp, count)      \
 849         bus_read_multi_1((adv)->res, (adv)->reg_off + offset, valp, count)
 850
 851 /* These controllers seem to have problems with PIO on some fast processors */
 852 static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int);
 853 static __inline void
 854 ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
 855 {
 856         while (count--)
 857                 *valp++ = bus_read_2(adv->res, adv->reg_off + offset);
 858 }
 859
 860 #define ADV_OUTB(adv, offset, val)              \
 861         bus_write_1((adv)->res, (adv)->reg_off + offset, val)
 862 #define ADV_OUTW(adv, offset, val)              \
 863         bus_write_2((adv)->res, (adv)->reg_off + offset, val)
 864
 865 /* These controllers seem to have problems with PIO on some fast processors */
 866 static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int);
 867 static __inline void
 868 ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
 869 {
 870         while (count--)
 871                 bus_write_2(adv->res, adv->reg_off + offset, *valp++);
 872 }
 873
 874 #endif /* _ADVLIB_H_ */