sys/dev/advansys/adwcam.c

   1 /*-
   2  * CAM SCSI interface for the Advanced Systems Inc.
   3  * Second Generation SCSI controllers.
   4  *
   5  * Product specific probe and attach routines can be found in:
   6  *
   7  * adw_pci.c    ABP[3]940UW, ABP950UW, ABP3940U2W
   8  *
   9  * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
  10  * All rights reserved.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions, and the following disclaimer,
  17  *    without modification.
  18  * 2. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  */
  33 /*
  34  * Ported from:
  35  * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
  36  *
  37  * Copyright (c) 1995-1998 Advanced System Products, Inc.
  38  * All Rights Reserved.
  39  *
  40  * Redistribution and use in source and binary forms, with or without
  41  * modification, are permitted provided that redistributions of source
  42  * code retain the above copyright notice and this comment without
  43  * modification.
  44  */
  45
  46 #include <sys/cdefs.h>
  47 __FBSDID("$FreeBSD$");
  48
  49 #include <sys/param.h>
  50 #include <sys/conf.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/malloc.h>
  54 #include <sys/lock.h>
  55 #include <sys/module.h>
  56 #include <sys/mutex.h>
  57 #include <sys/bus.h>
  58
  59 #include <machine/bus.h>
  60 #include <machine/resource.h>
  61
  62 #include <sys/rman.h>
  63
  64 #include <cam/cam.h>
  65 #include <cam/cam_ccb.h>
  66 #include <cam/cam_sim.h>
  67 #include <cam/cam_xpt_sim.h>
  68 #include <cam/cam_debug.h>
  69
  70 #include <cam/scsi/scsi_message.h>
  71
  72 #include <dev/advansys/adwvar.h>
  73
  74 /* Definitions for our use of the SIM private CCB area */
  75 #define ccb_acb_ptr spriv_ptr0
  76 #define ccb_adw_ptr spriv_ptr1
  77
  78 static __inline cam_status      adwccbstatus(union ccb*);
  79 static __inline struct acb*     adwgetacb(struct adw_softc *adw);
  80 static __inline void            adwfreeacb(struct adw_softc *adw,
  81                                            struct acb *acb);
  82
  83 static void             adwmapmem(void *arg, bus_dma_segment_t *segs,
  84                                   int nseg, int error);
  85 static struct sg_map_node*
  86                         adwallocsgmap(struct adw_softc *adw);
  87 static int              adwallocacbs(struct adw_softc *adw);
  88
  89 static void             adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs,
  90                                       int nseg, int error);
  91 static void             adw_action(struct cam_sim *sim, union ccb *ccb);
  92 static void             adw_intr_locked(struct adw_softc *adw);
  93 static void             adw_poll(struct cam_sim *sim);
  94 static void             adw_async(void *callback_arg, u_int32_t code,
  95                                   struct cam_path *path, void *arg);
  96 static void             adwprocesserror(struct adw_softc *adw, struct acb *acb);
  97 static void             adwtimeout(void *arg);
  98 static void             adw_handle_device_reset(struct adw_softc *adw,
  99                                                 u_int target);
 100 static void             adw_handle_bus_reset(struct adw_softc *adw,
 101                                              int initiated);
 102
 103 static __inline cam_status
 104 adwccbstatus(union ccb* ccb)
 105 {
 106         return (ccb->ccb_h.status & CAM_STATUS_MASK);
 107 }
 108
 109 static __inline struct acb*
 110 adwgetacb(struct adw_softc *adw)
 111 {
 112         struct  acb* acb;
 113
 114         if (!dumping)
 115                 mtx_assert(&adw->lock, MA_OWNED);
 116         if ((acb = SLIST_FIRST(&adw->free_acb_list)) != NULL) {
 117                 SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
 118         } else if (adw->num_acbs < adw->max_acbs) {
 119                 adwallocacbs(adw);
 120                 acb = SLIST_FIRST(&adw->free_acb_list);
 121                 if (acb == NULL)
 122                         device_printf(adw->device, "Can't malloc ACB\n");
 123                 else {
 124                         SLIST_REMOVE_HEAD(&adw->free_acb_list, links);
 125                 }
 126         }
 127
 128         return (acb);
 129 }
 130
 131 static __inline void
 132 adwfreeacb(struct adw_softc *adw, struct acb *acb)
 133 {
 134
 135         if (!dumping)
 136                 mtx_assert(&adw->lock, MA_OWNED);
 137         if ((acb->state & ACB_ACTIVE) != 0)
 138                 LIST_REMOVE(&acb->ccb->ccb_h, sim_links.le);
 139         if ((acb->state & ACB_RELEASE_SIMQ) != 0)
 140                 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 141         else if ((adw->state & ADW_RESOURCE_SHORTAGE) != 0
 142               && (acb->ccb->ccb_h.status & CAM_RELEASE_SIMQ) == 0) {
 143                 acb->ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
 144                 adw->state &= ~ADW_RESOURCE_SHORTAGE;
 145         }
 146         acb->state = ACB_FREE;
 147         SLIST_INSERT_HEAD(&adw->free_acb_list, acb, links);
 148 }
 149
 150 static void
 151 adwmapmem(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 152 {
 153         bus_addr_t *busaddrp;
 154
 155         busaddrp = (bus_addr_t *)arg;
 156         *busaddrp = segs->ds_addr;
 157 }
 158
 159 static struct sg_map_node *
 160 adwallocsgmap(struct adw_softc *adw)
 161 {
 162         struct sg_map_node *sg_map;
 163
 164         sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
 165
 166         if (sg_map == NULL)
 167                 return (NULL);
 168
 169         /* Allocate S/G space for the next batch of ACBS */
 170         if (bus_dmamem_alloc(adw->sg_dmat, (void **)&sg_map->sg_vaddr,
 171                              BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
 172                 free(sg_map, M_DEVBUF);
 173                 return (NULL);
 174         }
 175
 176         SLIST_INSERT_HEAD(&adw->sg_maps, sg_map, links);
 177
 178         bus_dmamap_load(adw->sg_dmat, sg_map->sg_dmamap, sg_map->sg_vaddr,
 179                         PAGE_SIZE, adwmapmem, &sg_map->sg_physaddr, /*flags*/0);
 180
 181         bzero(sg_map->sg_vaddr, PAGE_SIZE);
 182         return (sg_map);
 183 }
 184
 185 /*
 186  * Allocate another chunk of CCB's. Return count of entries added.
 187  */
 188 static int
 189 adwallocacbs(struct adw_softc *adw)
 190 {
 191         struct acb *next_acb;
 192         struct sg_map_node *sg_map;
 193         bus_addr_t busaddr;
 194         struct adw_sg_block *blocks;
 195         int newcount;
 196         int i;
 197
 198         next_acb = &adw->acbs[adw->num_acbs];
 199         sg_map = adwallocsgmap(adw);
 200
 201         if (sg_map == NULL)
 202                 return (0);
 203
 204         blocks = sg_map->sg_vaddr;
 205         busaddr = sg_map->sg_physaddr;
 206
 207         newcount = (PAGE_SIZE / (ADW_SG_BLOCKCNT * sizeof(*blocks)));
 208         for (i = 0; adw->num_acbs < adw->max_acbs && i < newcount; i++) {
 209                 int error;
 210
 211                 error = bus_dmamap_create(adw->buffer_dmat, /*flags*/0,
 212                                           &next_acb->dmamap);
 213                 if (error != 0)
 214                         break;
 215                 next_acb->queue.scsi_req_baddr = acbvtob(adw, next_acb);
 216                 next_acb->queue.scsi_req_bo = acbvtobo(adw, next_acb);
 217                 next_acb->queue.sense_baddr =
 218                     acbvtob(adw, next_acb) + offsetof(struct acb, sense_data);
 219                 next_acb->sg_blocks = blocks;
 220                 next_acb->sg_busaddr = busaddr;
 221                 next_acb->state = ACB_FREE;
 222                 callout_init_mtx(&next_acb->timer, &adw->lock, 0);
 223                 SLIST_INSERT_HEAD(&adw->free_acb_list, next_acb, links);
 224                 blocks += ADW_SG_BLOCKCNT;
 225                 busaddr += ADW_SG_BLOCKCNT * sizeof(*blocks);
 226                 next_acb++;
 227                 adw->num_acbs++;
 228         }
 229         return (i);
 230 }
 231
 232 static void
 233 adwexecuteacb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
 234 {
 235         struct   acb *acb;
 236         union    ccb *ccb;
 237         struct   adw_softc *adw;
 238
 239         acb = (struct acb *)arg;
 240         ccb = acb->ccb;
 241         adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
 242
 243         if (!dumping)
 244                 mtx_assert(&adw->lock, MA_OWNED);
 245         if (error != 0) {
 246                 if (error != EFBIG)
 247                         device_printf(adw->device, "Unexepected error 0x%x "
 248                             "returned from bus_dmamap_load\n", error);
 249                 if (ccb->ccb_h.status == CAM_REQ_INPROG) {
 250                         xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
 251                         ccb->ccb_h.status = CAM_REQ_TOO_BIG|CAM_DEV_QFRZN;
 252                 }
 253                 adwfreeacb(adw, acb);
 254                 xpt_done(ccb);
 255                 return;
 256         }
 257
 258         if (nseg != 0) {
 259                 bus_dmasync_op_t op;
 260
 261                 acb->queue.data_addr = dm_segs[0].ds_addr;
 262                 acb->queue.data_cnt = ccb->csio.dxfer_len;
 263                 if (nseg > 1) {
 264                         struct adw_sg_block *sg_block;
 265                         struct adw_sg_elm *sg;
 266                         bus_addr_t sg_busaddr;
 267                         u_int sg_index;
 268                         bus_dma_segment_t *end_seg;
 269
 270                         end_seg = dm_segs + nseg;
 271
 272                         sg_busaddr = acb->sg_busaddr;
 273                         sg_index = 0;
 274                         /* Copy the segments into our SG list */
 275                         for (sg_block = acb->sg_blocks;; sg_block++) {
 276                                 u_int i;
 277
 278                                 sg = sg_block->sg_list;
 279                                 for (i = 0; i < ADW_NO_OF_SG_PER_BLOCK; i++) {
 280                                         if (dm_segs >= end_seg)
 281                                                 break;
 282
 283                                         sg->sg_addr = dm_segs->ds_addr;
 284                                         sg->sg_count = dm_segs->ds_len;
 285                                         sg++;
 286                                         dm_segs++;
 287                                 }
 288                                 sg_block->sg_cnt = i;
 289                                 sg_index += i;
 290                                 if (dm_segs == end_seg) {
 291                                         sg_block->sg_busaddr_next = 0;
 292                                         break;
 293                                 } else {
 294                                         sg_busaddr +=
 295                                             sizeof(struct adw_sg_block);
 296                                         sg_block->sg_busaddr_next = sg_busaddr;
 297                                 }
 298                         }
 299                         acb->queue.sg_real_addr = acb->sg_busaddr;
 300                 } else {
 301                         acb->queue.sg_real_addr = 0;
 302                 }
 303
 304                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
 305                         op = BUS_DMASYNC_PREREAD;
 306                 else
 307                         op = BUS_DMASYNC_PREWRITE;
 308
 309                 bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
 310
 311         } else {
 312                 acb->queue.data_addr = 0;
 313                 acb->queue.data_cnt = 0;
 314                 acb->queue.sg_real_addr = 0;
 315         }
 316
 317         /*
 318          * Last time we need to check if this CCB needs to
 319          * be aborted.
 320          */
 321         if (ccb->ccb_h.status != CAM_REQ_INPROG) {
 322                 if (nseg != 0)
 323                         bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
 324                 adwfreeacb(adw, acb);
 325                 xpt_done(ccb);
 326                 return;
 327         }
 328
 329         acb->state |= ACB_ACTIVE;
 330         ccb->ccb_h.status |= CAM_SIM_QUEUED;
 331         LIST_INSERT_HEAD(&adw->pending_ccbs, &ccb->ccb_h, sim_links.le);
 332         callout_reset(&acb->timer, (ccb->ccb_h.timeout * hz) / 1000,
 333             adwtimeout, acb);
 334
 335         adw_send_acb(adw, acb, acbvtob(adw, acb));
 336 }
 337
 338 static void
 339 adw_action(struct cam_sim *sim, union ccb *ccb)
 340 {
 341         struct  adw_softc *adw;
 342
 343         CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("adw_action\n"));
 344
 345         adw = (struct adw_softc *)cam_sim_softc(sim);
 346         if (!dumping)
 347                 mtx_assert(&adw->lock, MA_OWNED);
 348
 349         switch (ccb->ccb_h.func_code) {
 350         /* Common cases first */
 351         case XPT_SCSI_IO:       /* Execute the requested I/O operation */
 352         {
 353                 struct  ccb_scsiio *csio;
 354                 struct  ccb_hdr *ccbh;
 355                 struct  acb *acb;
 356
 357                 csio = &ccb->csio;
 358                 ccbh = &ccb->ccb_h;
 359
 360                 /* Max supported CDB length is 12 bytes */
 361                 if (csio->cdb_len > 12) {
 362                         ccb->ccb_h.status = CAM_REQ_INVALID;
 363                         xpt_done(ccb);
 364                         return;
 365                 }
 366
 367                 if ((acb = adwgetacb(adw)) == NULL) {
 368                         adw->state |= ADW_RESOURCE_SHORTAGE;
 369                         xpt_freeze_simq(sim, /*count*/1);
 370                         ccb->ccb_h.status = CAM_REQUEUE_REQ;
 371                         xpt_done(ccb);
 372                         return;
 373                 }
 374
 375                 /* Link acb and ccb so we can find one from the other */
 376                 acb->ccb = ccb;
 377                 ccb->ccb_h.ccb_acb_ptr = acb;
 378                 ccb->ccb_h.ccb_adw_ptr = adw;
 379
 380                 acb->queue.cntl = 0;
 381                 acb->queue.target_cmd = 0;
 382                 acb->queue.target_id = ccb->ccb_h.target_id;
 383                 acb->queue.target_lun = ccb->ccb_h.target_lun;
 384
 385                 acb->queue.mflag = 0;
 386                 acb->queue.sense_len =
 387                         MIN(csio->sense_len, sizeof(acb->sense_data));
 388                 acb->queue.cdb_len = csio->cdb_len;
 389                 if ((ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) != 0) {
 390                         switch (csio->tag_action) {
 391                         case MSG_SIMPLE_Q_TAG:
 392                                 acb->queue.scsi_cntl = ADW_QSC_SIMPLE_Q_TAG;
 393                                 break;
 394                         case MSG_HEAD_OF_Q_TAG:
 395                                 acb->queue.scsi_cntl = ADW_QSC_HEAD_OF_Q_TAG;
 396                                 break;
 397                         case MSG_ORDERED_Q_TAG:
 398                                 acb->queue.scsi_cntl = ADW_QSC_ORDERED_Q_TAG;
 399                                 break;
 400                         default:
 401                                 acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
 402                                 break;
 403                         }
 404                 } else
 405                         acb->queue.scsi_cntl = ADW_QSC_NO_TAGMSG;
 406
 407                 if ((ccb->ccb_h.flags & CAM_DIS_DISCONNECT) != 0)
 408                         acb->queue.scsi_cntl |= ADW_QSC_NO_DISC;
 409
 410                 acb->queue.done_status = 0;
 411                 acb->queue.scsi_status = 0;
 412                 acb->queue.host_status = 0;
 413                 acb->queue.sg_wk_ix = 0;
 414                 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) {
 415                         if ((ccb->ccb_h.flags & CAM_CDB_PHYS) == 0) {
 416                                 bcopy(csio->cdb_io.cdb_ptr,
 417                                       acb->queue.cdb, csio->cdb_len);
 418                         } else {
 419                                 /* I guess I could map it in... */
 420                                 ccb->ccb_h.status = CAM_REQ_INVALID;
 421                                 adwfreeacb(adw, acb);
 422                                 xpt_done(ccb);
 423                                 return;
 424                         }
 425                 } else {
 426                         bcopy(csio->cdb_io.cdb_bytes,
 427                               acb->queue.cdb, csio->cdb_len);
 428                 }
 429
 430                 /*
 431                  * If we have any data to send with this command,
 432                  * map it into bus space.
 433                  */
 434                 if ((ccbh->flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
 435                         if ((ccbh->flags & CAM_SCATTER_VALID) == 0) {
 436                                 /*
 437                                  * We've been given a pointer
 438                                  * to a single buffer.
 439                                  */
 440                                 if ((ccbh->flags & CAM_DATA_PHYS) == 0) {
 441                                         int error;
 442
 443                                         error =
 444                                             bus_dmamap_load(adw->buffer_dmat,
 445                                                             acb->dmamap,
 446                                                             csio->data_ptr,
 447                                                             csio->dxfer_len,
 448                                                             adwexecuteacb,
 449                                                             acb, /*flags*/0);
 450                                         if (error == EINPROGRESS) {
 451                                                 /*
 452                                                  * So as to maintain ordering,
 453                                                  * freeze the controller queue
 454                                                  * until our mapping is
 455                                                  * returned.
 456                                                  */
 457                                                 xpt_freeze_simq(sim, 1);
 458                                                 acb->state |= CAM_RELEASE_SIMQ;
 459                                         }
 460                                 } else {
 461                                         struct bus_dma_segment seg;
 462
 463                                         /* Pointer to physical buffer */
 464                                         seg.ds_addr =
 465                                             (bus_addr_t)csio->data_ptr;
 466                                         seg.ds_len = csio->dxfer_len;
 467                                         adwexecuteacb(acb, &seg, 1, 0);
 468                                 }
 469                         } else {
 470                                 struct bus_dma_segment *segs;
 471
 472                                 if ((ccbh->flags & CAM_DATA_PHYS) != 0)
 473                                         panic("adw_action - Physical "
 474                                               "segment pointers "
 475                                               "unsupported");
 476
 477                                 if ((ccbh->flags&CAM_SG_LIST_PHYS)==0)
 478                                         panic("adw_action - Virtual "
 479                                               "segment addresses "
 480                                               "unsupported");
 481
 482                                 /* Just use the segments provided */
 483                                 segs = (struct bus_dma_segment *)csio->data_ptr;
 484                                 adwexecuteacb(acb, segs, csio->sglist_cnt,
 485                                               (csio->sglist_cnt < ADW_SGSIZE)
 486                                               ? 0 : EFBIG);
 487                         }
 488                 } else {
 489                         adwexecuteacb(acb, NULL, 0, 0);
 490                 }
 491                 break;
 492         }
 493         case XPT_RESET_DEV:     /* Bus Device Reset the specified SCSI device */
 494         {
 495                 adw_idle_cmd_status_t status;
 496
 497                 status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
 498                                            ccb->ccb_h.target_id);
 499                 if (status == ADW_IDLE_CMD_SUCCESS) {
 500                         ccb->ccb_h.status = CAM_REQ_CMP;
 501                         if (bootverbose) {
 502                                 xpt_print_path(ccb->ccb_h.path);
 503                                 printf("BDR Delivered\n");
 504                         }
 505                 } else
 506                         ccb->ccb_h.status = CAM_REQ_CMP_ERR;
 507                 xpt_done(ccb);
 508                 break;
 509         }
 510         case XPT_ABORT:                 /* Abort the specified CCB */
 511                 /* XXX Implement */
 512                 ccb->ccb_h.status = CAM_REQ_INVALID;
 513                 xpt_done(ccb);
 514                 break;
 515         case XPT_SET_TRAN_SETTINGS:
 516         {
 517                 struct ccb_trans_settings_scsi *scsi;
 518                 struct ccb_trans_settings_spi *spi;
 519                 struct    ccb_trans_settings *cts;
 520                 u_int     target_mask;
 521
 522                 cts = &ccb->cts;
 523                 target_mask = 0x01 << ccb->ccb_h.target_id;
 524
 525                 scsi = &cts->proto_specific.scsi;
 526                 spi = &cts->xport_specific.spi;
 527                 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
 528                         u_int sdtrdone;
 529
 530                         sdtrdone = adw_lram_read_16(adw, ADW_MC_SDTR_DONE);
 531                         if ((spi->valid & CTS_SPI_VALID_DISC) != 0) {
 532                                 u_int discenb;
 533
 534                                 discenb =
 535                                     adw_lram_read_16(adw, ADW_MC_DISC_ENABLE);
 536
 537                                 if ((spi->flags & CTS_SPI_FLAGS_DISC_ENB) != 0)
 538                                         discenb |= target_mask;
 539                                 else
 540                                         discenb &= ~target_mask;
 541
 542                                 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE,
 543                                                   discenb);
 544                         }
 545
 546                         if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) {
 547
 548                                 if ((scsi->flags & CTS_SCSI_FLAGS_TAG_ENB) != 0)
 549                                         adw->tagenb |= target_mask;
 550                                 else
 551                                         adw->tagenb &= ~target_mask;
 552                         }
 553
 554                         if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
 555                                 u_int wdtrenb_orig;
 556                                 u_int wdtrenb;
 557                                 u_int wdtrdone;
 558
 559                                 wdtrenb_orig =
 560                                     adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
 561                                 wdtrenb = wdtrenb_orig;
 562                                 wdtrdone = adw_lram_read_16(adw,
 563                                                             ADW_MC_WDTR_DONE);
 564                                 switch (spi->bus_width) {
 565                                 case MSG_EXT_WDTR_BUS_32_BIT:
 566                                 case MSG_EXT_WDTR_BUS_16_BIT:
 567                                         wdtrenb |= target_mask;
 568                                         break;
 569                                 case MSG_EXT_WDTR_BUS_8_BIT:
 570                                 default:
 571                                         wdtrenb &= ~target_mask;
 572                                         break;
 573                                 }
 574                                 if (wdtrenb != wdtrenb_orig) {
 575                                         adw_lram_write_16(adw,
 576                                                           ADW_MC_WDTR_ABLE,
 577                                                           wdtrenb);
 578                                         wdtrdone &= ~target_mask;
 579                                         adw_lram_write_16(adw,
 580                                                           ADW_MC_WDTR_DONE,
 581                                                           wdtrdone);
 582                                         /* Wide negotiation forces async */
 583                                         sdtrdone &= ~target_mask;
 584                                         adw_lram_write_16(adw,
 585                                                           ADW_MC_SDTR_DONE,
 586                                                           sdtrdone);
 587                                 }
 588                         }
 589
 590                         if (((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0)
 591                          || ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0)) {
 592                                 u_int sdtr_orig;
 593                                 u_int sdtr;
 594                                 u_int sdtrable_orig;
 595                                 u_int sdtrable;
 596
 597                                 sdtr = adw_get_chip_sdtr(adw,
 598                                                          ccb->ccb_h.target_id);
 599                                 sdtr_orig = sdtr;
 600                                 sdtrable = adw_lram_read_16(adw,
 601                                                             ADW_MC_SDTR_ABLE);
 602                                 sdtrable_orig = sdtrable;
 603
 604                                 if ((spi->valid
 605                                    & CTS_SPI_VALID_SYNC_RATE) != 0) {
 606
 607                                         sdtr =
 608                                             adw_find_sdtr(adw,
 609                                                           spi->sync_period);
 610                                 }
 611
 612                                 if ((spi->valid
 613                                    & CTS_SPI_VALID_SYNC_OFFSET) != 0) {
 614                                         if (spi->sync_offset == 0)
 615                                                 sdtr = ADW_MC_SDTR_ASYNC;
 616                                 }
 617
 618                                 if (sdtr == ADW_MC_SDTR_ASYNC)
 619                                         sdtrable &= ~target_mask;
 620                                 else
 621                                         sdtrable |= target_mask;
 622                                 if (sdtr != sdtr_orig
 623                                  || sdtrable != sdtrable_orig) {
 624                                         adw_set_chip_sdtr(adw,
 625                                                           ccb->ccb_h.target_id,
 626                                                           sdtr);
 627                                         sdtrdone &= ~target_mask;
 628                                         adw_lram_write_16(adw, ADW_MC_SDTR_ABLE,
 629                                                           sdtrable);
 630                                         adw_lram_write_16(adw, ADW_MC_SDTR_DONE,
 631                                                           sdtrdone);
 632
 633                                 }
 634                         }
 635                 }
 636                 ccb->ccb_h.status = CAM_REQ_CMP;
 637                 xpt_done(ccb);
 638                 break;
 639         }
 640         case XPT_GET_TRAN_SETTINGS:
 641         /* Get default/user set transfer settings for the target */
 642         {
 643                 struct ccb_trans_settings_scsi *scsi;
 644                 struct ccb_trans_settings_spi *spi;
 645                 struct  ccb_trans_settings *cts;
 646                 u_int   target_mask;
 647
 648                 cts = &ccb->cts;
 649                 target_mask = 0x01 << ccb->ccb_h.target_id;
 650                 cts->protocol = PROTO_SCSI;
 651                 cts->protocol_version = SCSI_REV_2;
 652                 cts->transport = XPORT_SPI;
 653                 cts->transport_version = 2;
 654
 655                 scsi = &cts->proto_specific.scsi;
 656                 spi = &cts->xport_specific.spi;
 657                 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
 658                         u_int mc_sdtr;
 659
 660                         spi->flags = 0;
 661                         if ((adw->user_discenb & target_mask) != 0)
 662                                 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
 663
 664                         if ((adw->user_tagenb & target_mask) != 0)
 665                                 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
 666
 667                         if ((adw->user_wdtr & target_mask) != 0)
 668                                 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 669                         else
 670                                 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 671
 672                         mc_sdtr = adw_get_user_sdtr(adw, ccb->ccb_h.target_id);
 673                         spi->sync_period = adw_find_period(adw, mc_sdtr);
 674                         if (spi->sync_period != 0)
 675                                 spi->sync_offset = 15; /* XXX ??? */
 676                         else
 677                                 spi->sync_offset = 0;
 678
 679
 680                 } else {
 681                         u_int targ_tinfo;
 682
 683                         spi->flags = 0;
 684                         if ((adw_lram_read_16(adw, ADW_MC_DISC_ENABLE)
 685                           & target_mask) != 0)
 686                                 spi->flags |= CTS_SPI_FLAGS_DISC_ENB;
 687
 688                         if ((adw->tagenb & target_mask) != 0)
 689                                 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB;
 690
 691                         targ_tinfo =
 692                             adw_lram_read_16(adw,
 693                                              ADW_MC_DEVICE_HSHK_CFG_TABLE
 694                                              + (2 * ccb->ccb_h.target_id));
 695
 696                         if ((targ_tinfo & ADW_HSHK_CFG_WIDE_XFR) != 0)
 697                                 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
 698                         else
 699                                 spi->bus_width = MSG_EXT_WDTR_BUS_8_BIT;
 700
 701                         spi->sync_period =
 702                             adw_hshk_cfg_period_factor(targ_tinfo);
 703
 704                         spi->sync_offset = targ_tinfo & ADW_HSHK_CFG_OFFSET;
 705                         if (spi->sync_period == 0)
 706                                 spi->sync_offset = 0;
 707
 708                         if (spi->sync_offset == 0)
 709                                 spi->sync_period = 0;
 710                 }
 711
 712                 spi->valid = CTS_SPI_VALID_SYNC_RATE
 713                            | CTS_SPI_VALID_SYNC_OFFSET
 714                            | CTS_SPI_VALID_BUS_WIDTH
 715                            | CTS_SPI_VALID_DISC;
 716                 scsi->valid = CTS_SCSI_VALID_TQ;
 717                 ccb->ccb_h.status = CAM_REQ_CMP;
 718                 xpt_done(ccb);
 719                 break;
 720         }
 721         case XPT_CALC_GEOMETRY:
 722         {
 723                 /*
 724                  * XXX Use Adaptec translation until I find out how to
 725                  *     get this information from the card.
 726                  */
 727                 cam_calc_geometry(&ccb->ccg, /*extended*/1);
 728                 xpt_done(ccb);
 729                 break;
 730         }
 731         case XPT_RESET_BUS:             /* Reset the specified SCSI bus */
 732         {
 733                 int failure;
 734
 735                 failure = adw_reset_bus(adw);
 736                 if (failure != 0) {
 737                         ccb->ccb_h.status = CAM_REQ_CMP_ERR;
 738                 } else {
 739                         if (bootverbose) {
 740                                 xpt_print_path(adw->path);
 741                                 printf("Bus Reset Delivered\n");
 742                         }
 743                         ccb->ccb_h.status = CAM_REQ_CMP;
 744                 }
 745                 xpt_done(ccb);
 746                 break;
 747         }
 748         case XPT_TERM_IO:               /* Terminate the I/O process */
 749                 /* XXX Implement */
 750                 ccb->ccb_h.status = CAM_REQ_INVALID;
 751                 xpt_done(ccb);
 752                 break;
 753         case XPT_PATH_INQ:              /* Path routing inquiry */
 754         {
 755                 struct ccb_pathinq *cpi = &ccb->cpi;
 756
 757                 cpi->version_num = 1;
 758                 cpi->hba_inquiry = PI_WIDE_16|PI_SDTR_ABLE|PI_TAG_ABLE;
 759                 cpi->target_sprt = 0;
 760                 cpi->hba_misc = 0;
 761                 cpi->hba_eng_cnt = 0;
 762                 cpi->max_target = ADW_MAX_TID;
 763                 cpi->max_lun = ADW_MAX_LUN;
 764                 cpi->initiator_id = adw->initiator_id;
 765                 cpi->bus_id = cam_sim_bus(sim);
 766                 cpi->base_transfer_speed = 3300;
 767                 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
 768                 strncpy(cpi->hba_vid, "AdvanSys", HBA_IDLEN);
 769                 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
 770                 cpi->unit_number = cam_sim_unit(sim);
 771                 cpi->transport = XPORT_SPI;
 772                 cpi->transport_version = 2;
 773                 cpi->protocol = PROTO_SCSI;
 774                 cpi->protocol_version = SCSI_REV_2;
 775                 cpi->ccb_h.status = CAM_REQ_CMP;
 776                 xpt_done(ccb);
 777                 break;
 778         }
 779         default:
 780                 ccb->ccb_h.status = CAM_REQ_INVALID;
 781                 xpt_done(ccb);
 782                 break;
 783         }
 784 }
 785
 786 static void
 787 adw_poll(struct cam_sim *sim)
 788 {
 789         adw_intr_locked(cam_sim_softc(sim));
 790 }
 791
 792 static void
 793 adw_async(void *callback_arg, u_int32_t code, struct cam_path *path, void *arg)
 794 {
 795 }
 796
 797 struct adw_softc *
 798 adw_alloc(device_t dev, struct resource *regs, int regs_type, int regs_id)
 799 {
 800         struct   adw_softc *adw;
 801
 802         adw = device_get_softc(dev);
 803         LIST_INIT(&adw->pending_ccbs);
 804         SLIST_INIT(&adw->sg_maps);
 805         mtx_init(&adw->lock, "adw", NULL, MTX_DEF);
 806         adw->device = dev;
 807         adw->regs_res_type = regs_type;
 808         adw->regs_res_id = regs_id;
 809         adw->regs = regs;
 810         return(adw);
 811 }
 812
 813 void
 814 adw_free(struct adw_softc *adw)
 815 {
 816         switch (adw->init_level) {
 817         case 9:
 818         {
 819                 struct sg_map_node *sg_map;
 820
 821                 while ((sg_map = SLIST_FIRST(&adw->sg_maps)) != NULL) {
 822                         SLIST_REMOVE_HEAD(&adw->sg_maps, links);
 823                         bus_dmamap_unload(adw->sg_dmat,
 824                                           sg_map->sg_dmamap);
 825                         bus_dmamem_free(adw->sg_dmat, sg_map->sg_vaddr,
 826                                         sg_map->sg_dmamap);
 827                         free(sg_map, M_DEVBUF);
 828                 }
 829                 bus_dma_tag_destroy(adw->sg_dmat);
 830         }
 831         case 8:
 832                 bus_dmamap_unload(adw->acb_dmat, adw->acb_dmamap);
 833         case 7:
 834                 bus_dmamem_free(adw->acb_dmat, adw->acbs,
 835                                 adw->acb_dmamap);
 836                 bus_dmamap_destroy(adw->acb_dmat, adw->acb_dmamap);
 837         case 6:
 838                 bus_dma_tag_destroy(adw->acb_dmat);
 839         case 5:
 840                 bus_dmamap_unload(adw->carrier_dmat, adw->carrier_dmamap);
 841         case 4:
 842                 bus_dmamem_free(adw->carrier_dmat, adw->carriers,
 843                                 adw->carrier_dmamap);
 844                 bus_dmamap_destroy(adw->carrier_dmat, adw->carrier_dmamap);
 845         case 3:
 846                 bus_dma_tag_destroy(adw->carrier_dmat);
 847         case 2:
 848                 bus_dma_tag_destroy(adw->buffer_dmat);
 849         case 1:
 850                 bus_dma_tag_destroy(adw->parent_dmat);
 851         case 0:
 852                 break;
 853         }
 854
 855         if (adw->regs != NULL)
 856                 bus_release_resource(adw->device,
 857                                      adw->regs_res_type,
 858                                      adw->regs_res_id,
 859                                      adw->regs);
 860
 861         if (adw->irq != NULL)
 862                 bus_release_resource(adw->device,
 863                                      adw->irq_res_type,
 864                                      0, adw->irq);
 865
 866         if (adw->sim != NULL) {
 867                 if (adw->path != NULL) {
 868                         xpt_async(AC_LOST_DEVICE, adw->path, NULL);
 869                         xpt_free_path(adw->path);
 870                 }
 871                 xpt_bus_deregister(cam_sim_path(adw->sim));
 872                 cam_sim_free(adw->sim, /*free_devq*/TRUE);
 873         }
 874         mtx_destroy(&adw->lock);
 875 }
 876
 877 int
 878 adw_init(struct adw_softc *adw)
 879 {
 880         struct    adw_eeprom eep_config;
 881         u_int     tid;
 882         u_int     i;
 883         u_int16_t checksum;
 884         u_int16_t scsicfg1;
 885
 886         checksum = adw_eeprom_read(adw, &eep_config);
 887         bcopy(eep_config.serial_number, adw->serial_number,
 888               sizeof(adw->serial_number));
 889         if (checksum != eep_config.checksum) {
 890                 u_int16_t serial_number[3];
 891
 892                 adw->flags |= ADW_EEPROM_FAILED;
 893                 device_printf(adw->device,
 894                     "EEPROM checksum failed.  Restoring Defaults\n");
 895
 896                 /*
 897                  * Restore the default EEPROM settings.
 898                  * Assume the 6 byte board serial number that was read
 899                  * from EEPROM is correct even if the EEPROM checksum
 900                  * failed.
 901                  */
 902                 bcopy(adw->default_eeprom, &eep_config, sizeof(eep_config));
 903                 bcopy(adw->serial_number, eep_config.serial_number,
 904                       sizeof(serial_number));
 905                 adw_eeprom_write(adw, &eep_config);
 906         }
 907
 908         /* Pull eeprom information into our softc. */
 909         adw->bios_ctrl = eep_config.bios_ctrl;
 910         adw->user_wdtr = eep_config.wdtr_able;
 911         for (tid = 0; tid < ADW_MAX_TID; tid++) {
 912                 u_int     mc_sdtr;
 913                 u_int16_t tid_mask;
 914
 915                 tid_mask = 0x1 << tid;
 916                 if ((adw->features & ADW_ULTRA) != 0) {
 917                         /*
 918                          * Ultra chips store sdtr and ultraenb
 919                          * bits in their seeprom, so we must
 920                          * construct valid mc_sdtr entries for
 921                          * indirectly.
 922                          */
 923                         if (eep_config.sync1.sync_enable & tid_mask) {
 924                                 if (eep_config.sync2.ultra_enable & tid_mask)
 925                                         mc_sdtr = ADW_MC_SDTR_20;
 926                                 else
 927                                         mc_sdtr = ADW_MC_SDTR_10;
 928                         } else
 929                                 mc_sdtr = ADW_MC_SDTR_ASYNC;
 930                 } else {
 931                         switch (ADW_TARGET_GROUP(tid)) {
 932                         case 3:
 933                                 mc_sdtr = eep_config.sync4.sdtr4;
 934                                 break;
 935                         case 2:
 936                                 mc_sdtr = eep_config.sync3.sdtr3;
 937                                 break;
 938                         case 1:
 939                                 mc_sdtr = eep_config.sync2.sdtr2;
 940                                 break;
 941                         default: /* Shut up compiler */
 942                         case 0:
 943                                 mc_sdtr = eep_config.sync1.sdtr1;
 944                                 break;
 945                         }
 946                         mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
 947                         mc_sdtr &= 0xFF;
 948                 }
 949                 adw_set_user_sdtr(adw, tid, mc_sdtr);
 950         }
 951         adw->user_tagenb = eep_config.tagqng_able;
 952         adw->user_discenb = eep_config.disc_enable;
 953         adw->max_acbs = eep_config.max_host_qng;
 954         adw->initiator_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
 955
 956         /*
 957          * Sanity check the number of host openings.
 958          */
 959         if (adw->max_acbs > ADW_DEF_MAX_HOST_QNG)
 960                 adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
 961         else if (adw->max_acbs < ADW_DEF_MIN_HOST_QNG) {
 962                 /* If the value is zero, assume it is uninitialized. */
 963                 if (adw->max_acbs == 0)
 964                         adw->max_acbs = ADW_DEF_MAX_HOST_QNG;
 965                 else
 966                         adw->max_acbs = ADW_DEF_MIN_HOST_QNG;
 967         }
 968
 969         scsicfg1 = 0;
 970         if ((adw->features & ADW_ULTRA2) != 0) {
 971                 switch (eep_config.termination_lvd) {
 972                 default:
 973                         device_printf(adw->device,
 974                             "Invalid EEPROM LVD Termination Settings.\n");
 975                         device_printf(adw->device,
 976                             "Reverting to Automatic LVD Termination\n");
 977                         /* FALLTHROUGH */
 978                 case ADW_EEPROM_TERM_AUTO:
 979                         break;
 980                 case ADW_EEPROM_TERM_BOTH_ON:
 981                         scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_LO;
 982                         /* FALLTHROUGH */
 983                 case ADW_EEPROM_TERM_HIGH_ON:
 984                         scsicfg1 |= ADW2_SCSI_CFG1_TERM_LVD_HI;
 985                         /* FALLTHROUGH */
 986                 case ADW_EEPROM_TERM_OFF:
 987                         scsicfg1 |= ADW2_SCSI_CFG1_DIS_TERM_DRV;
 988                         break;
 989                 }
 990         }
 991
 992         switch (eep_config.termination_se) {
 993         default:
 994                 device_printf(adw->device,
 995                     "Invalid SE EEPROM Termination Settings.\n");
 996                 device_printf(adw->device,
 997                     "Reverting to Automatic SE Termination\n");
 998                 /* FALLTHROUGH */
 999         case ADW_EEPROM_TERM_AUTO:
1000                 break;
1001         case ADW_EEPROM_TERM_BOTH_ON:
1002                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
1003                 /* FALLTHROUGH */
1004         case ADW_EEPROM_TERM_HIGH_ON:
1005                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
1006                 /* FALLTHROUGH */
1007         case ADW_EEPROM_TERM_OFF:
1008                 scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_MANUAL;
1009                 break;
1010         }
1011         device_printf(adw->device, "SCSI ID %d, ", adw->initiator_id);
1012
1013         /* DMA tag for mapping buffers into device visible space. */
1014         if (bus_dma_tag_create(
1015                         /* parent       */ adw->parent_dmat,
1016                         /* alignment    */ 1,
1017                         /* boundary     */ 0,
1018                         /* lowaddr      */ BUS_SPACE_MAXADDR_32BIT,
1019                         /* highaddr     */ BUS_SPACE_MAXADDR,
1020                         /* filter       */ NULL,
1021                         /* filterarg    */ NULL,
1022                         /* maxsize      */ MAXBSIZE,
1023                         /* nsegments    */ ADW_SGSIZE,
1024                         /* maxsegsz     */ BUS_SPACE_MAXSIZE_32BIT,
1025                         /* flags        */ BUS_DMA_ALLOCNOW,
1026                         /* lockfunc     */ busdma_lock_mutex,
1027                         /* lockarg      */ &adw->lock,
1028                         &adw->buffer_dmat) != 0) {
1029                 return (ENOMEM);
1030         }
1031
1032         adw->init_level++;
1033
1034         /* DMA tag for our ccb carrier structures */
1035         if (bus_dma_tag_create(
1036                         /* parent       */ adw->parent_dmat,
1037                         /* alignment    */ 0x10,
1038                         /* boundary     */ 0,
1039                         /* lowaddr      */ BUS_SPACE_MAXADDR_32BIT,
1040                         /* highaddr     */ BUS_SPACE_MAXADDR,
1041                         /* filter       */ NULL,
1042                         /* filterarg    */ NULL,
1043                         /* maxsize      */ (adw->max_acbs +
1044                                             ADW_NUM_CARRIER_QUEUES + 1) *
1045                                             sizeof(struct adw_carrier),
1046                         /* nsegments    */ 1,
1047                         /* maxsegsz     */ BUS_SPACE_MAXSIZE_32BIT,
1048                         /* flags        */ 0,
1049                         /* lockfunc     */ NULL,
1050                         /* lockarg      */ NULL,
1051                         &adw->carrier_dmat) != 0) {
1052                 return (ENOMEM);
1053         }
1054
1055         adw->init_level++;
1056
1057         /* Allocation for our ccb carrier structures */
1058         if (bus_dmamem_alloc(adw->carrier_dmat, (void **)&adw->carriers,
1059                              BUS_DMA_NOWAIT, &adw->carrier_dmamap) != 0) {
1060                 return (ENOMEM);
1061         }
1062
1063         adw->init_level++;
1064
1065         /* And permanently map them */
1066         bus_dmamap_load(adw->carrier_dmat, adw->carrier_dmamap,
1067                         adw->carriers,
1068                         (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1069                          * sizeof(struct adw_carrier),
1070                         adwmapmem, &adw->carrier_busbase, /*flags*/0);
1071
1072         /* Clear them out. */
1073         bzero(adw->carriers, (adw->max_acbs + ADW_NUM_CARRIER_QUEUES + 1)
1074                              * sizeof(struct adw_carrier));
1075
1076         /* Setup our free carrier list */
1077         adw->free_carriers = adw->carriers;
1078         for (i = 0; i < adw->max_acbs + ADW_NUM_CARRIER_QUEUES; i++) {
1079                 adw->carriers[i].carr_offset =
1080                         carriervtobo(adw, &adw->carriers[i]);
1081                 adw->carriers[i].carr_ba =
1082                         carriervtob(adw, &adw->carriers[i]);
1083                 adw->carriers[i].areq_ba = 0;
1084                 adw->carriers[i].next_ba =
1085                         carriervtobo(adw, &adw->carriers[i+1]);
1086         }
1087         /* Terminal carrier.  Never leaves the freelist */
1088         adw->carriers[i].carr_offset =
1089                 carriervtobo(adw, &adw->carriers[i]);
1090         adw->carriers[i].carr_ba =
1091                 carriervtob(adw, &adw->carriers[i]);
1092         adw->carriers[i].areq_ba = 0;
1093         adw->carriers[i].next_ba = ~0;
1094
1095         adw->init_level++;
1096
1097         /* DMA tag for our acb structures */
1098         if (bus_dma_tag_create(
1099                         /* parent       */ adw->parent_dmat,
1100                         /* alignment    */ 1,
1101                         /* boundary     */ 0,
1102                         /* lowaddr      */ BUS_SPACE_MAXADDR,
1103                         /* highaddr     */ BUS_SPACE_MAXADDR,
1104                         /* filter       */ NULL,
1105                         /* filterarg    */ NULL,
1106                         /* maxsize      */ adw->max_acbs * sizeof(struct acb),
1107                         /* nsegments    */ 1,
1108                         /* maxsegsz     */ BUS_SPACE_MAXSIZE_32BIT,
1109                         /* flags        */ 0,
1110                         /* lockfunc     */ NULL,
1111                         /* lockarg      */ NULL,
1112                         &adw->acb_dmat) != 0) {
1113                 return (ENOMEM);
1114         }
1115
1116         adw->init_level++;
1117
1118         /* Allocation for our ccbs */
1119         if (bus_dmamem_alloc(adw->acb_dmat, (void **)&adw->acbs,
1120                              BUS_DMA_NOWAIT, &adw->acb_dmamap) != 0)
1121                 return (ENOMEM);
1122
1123         adw->init_level++;
1124
1125         /* And permanently map them */
1126         bus_dmamap_load(adw->acb_dmat, adw->acb_dmamap,
1127                         adw->acbs,
1128                         adw->max_acbs * sizeof(struct acb),
1129                         adwmapmem, &adw->acb_busbase, /*flags*/0);
1130
1131         /* Clear them out. */
1132         bzero(adw->acbs, adw->max_acbs * sizeof(struct acb));
1133
1134         /* DMA tag for our S/G structures.  We allocate in page sized chunks */
1135         if (bus_dma_tag_create(
1136                         /* parent       */ adw->parent_dmat,
1137                         /* alignment    */ 1,
1138                         /* boundary     */ 0,
1139                         /* lowaddr      */ BUS_SPACE_MAXADDR,
1140                         /* highaddr     */ BUS_SPACE_MAXADDR,
1141                         /* filter       */ NULL,
1142                         /* filterarg    */ NULL,
1143                         /* maxsize      */ PAGE_SIZE,
1144                         /* nsegments    */ 1,
1145                         /* maxsegsz     */ BUS_SPACE_MAXSIZE_32BIT,
1146                         /* flags        */ 0,
1147                         /* lockfunc     */ NULL,
1148                         /* lockarg      */ NULL,
1149                         &adw->sg_dmat) != 0) {
1150                 return (ENOMEM);
1151         }
1152
1153         adw->init_level++;
1154
1155         /* Allocate our first batch of ccbs */
1156         mtx_lock(&adw->lock);
1157         if (adwallocacbs(adw) == 0) {
1158                 mtx_unlock(&adw->lock);
1159                 return (ENOMEM);
1160         }
1161
1162         if (adw_init_chip(adw, scsicfg1) != 0) {
1163                 mtx_unlock(&adw->lock);
1164                 return (ENXIO);
1165         }
1166
1167         printf("Queue Depth %d\n", adw->max_acbs);
1168         mtx_unlock(&adw->lock);
1169
1170         return (0);
1171 }
1172
1173 /*
1174  * Attach all the sub-devices we can find
1175  */
1176 int
1177 adw_attach(struct adw_softc *adw)
1178 {
1179         struct ccb_setasync csa;
1180         struct cam_devq *devq;
1181         int error;
1182
1183         /* Hook up our interrupt handler */
1184         error = bus_setup_intr(adw->device, adw->irq,
1185             INTR_TYPE_CAM | INTR_ENTROPY | INTR_MPSAFE, NULL, adw_intr, adw,
1186             &adw->ih);
1187         if (error != 0) {
1188                 device_printf(adw->device, "bus_setup_intr() failed: %d\n",
1189                               error);
1190                 return (error);
1191         }
1192
1193         /* Start the Risc processor now that we are fully configured. */
1194         adw_outw(adw, ADW_RISC_CSR, ADW_RISC_CSR_RUN);
1195
1196         /*
1197          * Create the device queue for our SIM.
1198          */
1199         devq = cam_simq_alloc(adw->max_acbs);
1200         if (devq == NULL)
1201                 return (ENOMEM);
1202
1203         /*
1204          * Construct our SIM entry.
1205          */
1206         adw->sim = cam_sim_alloc(adw_action, adw_poll, "adw", adw,
1207             device_get_unit(adw->device), &adw->lock, 1, adw->max_acbs, devq);
1208         if (adw->sim == NULL)
1209                 return (ENOMEM);
1210
1211         /*
1212          * Register the bus.
1213          */
1214         mtx_lock(&adw->lock);
1215         if (xpt_bus_register(adw->sim, adw->device, 0) != CAM_SUCCESS) {
1216                 cam_sim_free(adw->sim, /*free devq*/TRUE);
1217                 error = ENOMEM;
1218                 goto fail;
1219         }
1220
1221         if (xpt_create_path(&adw->path, /*periph*/NULL, cam_sim_path(adw->sim),
1222                             CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
1223            == CAM_REQ_CMP) {
1224                 xpt_setup_ccb(&csa.ccb_h, adw->path, /*priority*/5);
1225                 csa.ccb_h.func_code = XPT_SASYNC_CB;
1226                 csa.event_enable = AC_LOST_DEVICE;
1227                 csa.callback = adw_async;
1228                 csa.callback_arg = adw;
1229                 xpt_action((union ccb *)&csa);
1230         }
1231
1232 fail:
1233         mtx_unlock(&adw->lock);
1234         return (error);
1235 }
1236
1237 void
1238 adw_intr(void *arg)
1239 {
1240         struct  adw_softc *adw;
1241
1242         adw = arg;
1243         mtx_lock(&adw->lock);
1244         adw_intr_locked(adw);
1245         mtx_unlock(&adw->lock);
1246 }
1247
1248 void
1249 adw_intr_locked(struct adw_softc *adw)
1250 {
1251         u_int   int_stat;
1252
1253         if ((adw_inw(adw, ADW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR) == 0)
1254                 return;
1255
1256         /* Reading the register clears the interrupt. */
1257         int_stat = adw_inb(adw, ADW_INTR_STATUS_REG);
1258
1259         if ((int_stat & ADW_INTR_STATUS_INTRB) != 0) {
1260                 u_int intrb_code;
1261
1262                 /* Async Microcode Event */
1263                 intrb_code = adw_lram_read_8(adw, ADW_MC_INTRB_CODE);
1264                 switch (intrb_code) {
1265                 case ADW_ASYNC_CARRIER_READY_FAILURE:
1266                         /*
1267                          * The RISC missed our update of
1268                          * the commandq.
1269                          */
1270                         if (LIST_FIRST(&adw->pending_ccbs) != NULL)
1271                                 adw_tickle_risc(adw, ADW_TICKLE_A);
1272                         break;
1273                 case ADW_ASYNC_SCSI_BUS_RESET_DET:
1274                         /*
1275                          * The firmware detected a SCSI Bus reset.
1276                          */
1277                         device_printf(adw->device, "Someone Reset the Bus\n");
1278                         adw_handle_bus_reset(adw, /*initiated*/FALSE);
1279                         break;
1280                 case ADW_ASYNC_RDMA_FAILURE:
1281                         /*
1282                          * Handle RDMA failure by resetting the
1283                          * SCSI Bus and chip.
1284                          */
1285 #if 0 /* XXX */
1286                         AdvResetChipAndSB(adv_dvc_varp);
1287 #endif
1288                         break;
1289
1290                 case ADW_ASYNC_HOST_SCSI_BUS_RESET:
1291                         /*
1292                          * Host generated SCSI bus reset occurred.
1293                          */
1294                         adw_handle_bus_reset(adw, /*initiated*/TRUE);
1295                         break;
1296                 default:
1297                         printf("adw_intr: unknown async code 0x%x\n",
1298                                intrb_code);
1299                         break;
1300                 }
1301         }
1302
1303         /*
1304          * Run down the RequestQ.
1305          */
1306         while ((adw->responseq->next_ba & ADW_RQ_DONE) != 0) {
1307                 struct adw_carrier *free_carrier;
1308                 struct acb *acb;
1309                 union ccb *ccb;
1310
1311 #if 0
1312                 printf("0x%x, 0x%x, 0x%x, 0x%x\n",
1313                        adw->responseq->carr_offset,
1314                        adw->responseq->carr_ba,
1315                        adw->responseq->areq_ba,
1316                        adw->responseq->next_ba);
1317 #endif
1318                 /*
1319                  * The firmware copies the adw_scsi_req_q.acb_baddr
1320                  * field into the areq_ba field of the carrier.
1321                  */
1322                 acb = acbbotov(adw, adw->responseq->areq_ba);
1323
1324                 /*
1325                  * The least significant four bits of the next_ba
1326                  * field are used as flags.  Mask them out and then
1327                  * advance through the list.
1328                  */
1329                 free_carrier = adw->responseq;
1330                 adw->responseq =
1331                     carrierbotov(adw, free_carrier->next_ba & ADW_NEXT_BA_MASK);
1332                 free_carrier->next_ba = adw->free_carriers->carr_offset;
1333                 adw->free_carriers = free_carrier;
1334
1335                 /* Process CCB */
1336                 ccb = acb->ccb;
1337                 callout_stop(&acb->timer);
1338                 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1339                         bus_dmasync_op_t op;
1340
1341                         if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
1342                                 op = BUS_DMASYNC_POSTREAD;
1343                         else
1344                                 op = BUS_DMASYNC_POSTWRITE;
1345                         bus_dmamap_sync(adw->buffer_dmat, acb->dmamap, op);
1346                         bus_dmamap_unload(adw->buffer_dmat, acb->dmamap);
1347                         ccb->csio.resid = acb->queue.data_cnt;
1348                 } else
1349                         ccb->csio.resid = 0;
1350
1351                 /* Common Cases inline... */
1352                 if (acb->queue.host_status == QHSTA_NO_ERROR
1353                  && (acb->queue.done_status == QD_NO_ERROR
1354                   || acb->queue.done_status == QD_WITH_ERROR)) {
1355                         ccb->csio.scsi_status = acb->queue.scsi_status;
1356                         ccb->ccb_h.status = 0;
1357                         switch (ccb->csio.scsi_status) {
1358                         case SCSI_STATUS_OK:
1359                                 ccb->ccb_h.status |= CAM_REQ_CMP;
1360                                 break;
1361                         case SCSI_STATUS_CHECK_COND:
1362                         case SCSI_STATUS_CMD_TERMINATED:
1363                                 bcopy(&acb->sense_data, &ccb->csio.sense_data,
1364                                       ccb->csio.sense_len);
1365                                 ccb->ccb_h.status |= CAM_AUTOSNS_VALID;
1366                                 ccb->csio.sense_resid = acb->queue.sense_len;
1367                                 /* FALLTHROUGH */
1368                         default:
1369                                 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR
1370                                                   |  CAM_DEV_QFRZN;
1371                                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1372                                 break;
1373                         }
1374                         adwfreeacb(adw, acb);
1375                         xpt_done(ccb);
1376                 } else {
1377                         adwprocesserror(adw, acb);
1378                 }
1379         }
1380 }
1381
1382 static void
1383 adwprocesserror(struct adw_softc *adw, struct acb *acb)
1384 {
1385         union ccb *ccb;
1386
1387         ccb = acb->ccb;
1388         if (acb->queue.done_status == QD_ABORTED_BY_HOST) {
1389                 ccb->ccb_h.status = CAM_REQ_ABORTED;
1390         } else {
1391
1392                 switch (acb->queue.host_status) {
1393                 case QHSTA_M_SEL_TIMEOUT:
1394                         ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1395                         break;
1396                 case QHSTA_M_SXFR_OFF_UFLW:
1397                 case QHSTA_M_SXFR_OFF_OFLW:
1398                 case QHSTA_M_DATA_OVER_RUN:
1399                         ccb->ccb_h.status = CAM_DATA_RUN_ERR;
1400                         break;
1401                 case QHSTA_M_SXFR_DESELECTED:
1402                 case QHSTA_M_UNEXPECTED_BUS_FREE:
1403                         ccb->ccb_h.status = CAM_UNEXP_BUSFREE;
1404                         break;
1405                 case QHSTA_M_SCSI_BUS_RESET:
1406                 case QHSTA_M_SCSI_BUS_RESET_UNSOL:
1407                         ccb->ccb_h.status = CAM_SCSI_BUS_RESET;
1408                         break;
1409                 case QHSTA_M_BUS_DEVICE_RESET:
1410                         ccb->ccb_h.status = CAM_BDR_SENT;
1411                         break;
1412                 case QHSTA_M_QUEUE_ABORTED:
1413                         /* BDR or Bus Reset */
1414                         xpt_print_path(adw->path);
1415                         printf("Saw Queue Aborted\n");
1416                         ccb->ccb_h.status = adw->last_reset;
1417                         break;
1418                 case QHSTA_M_SXFR_SDMA_ERR:
1419                 case QHSTA_M_SXFR_SXFR_PERR:
1420                 case QHSTA_M_RDMA_PERR:
1421                         ccb->ccb_h.status = CAM_UNCOR_PARITY;
1422                         break;
1423                 case QHSTA_M_WTM_TIMEOUT:
1424                 case QHSTA_M_SXFR_WD_TMO:
1425                 {
1426                         /* The SCSI bus hung in a phase */
1427                         xpt_print_path(adw->path);
1428                         printf("Watch Dog timer expired.  Resetting bus\n");
1429                         adw_reset_bus(adw);
1430                         break;
1431                 }
1432                 case QHSTA_M_SXFR_XFR_PH_ERR:
1433                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1434                         break;
1435                 case QHSTA_M_SXFR_UNKNOWN_ERROR:
1436                         break;
1437                 case QHSTA_M_BAD_CMPL_STATUS_IN:
1438                         /* No command complete after a status message */
1439                         ccb->ccb_h.status = CAM_SEQUENCE_FAIL;
1440                         break;
1441                 case QHSTA_M_AUTO_REQ_SENSE_FAIL:
1442                         ccb->ccb_h.status = CAM_AUTOSENSE_FAIL;
1443                         break;
1444                 case QHSTA_M_INVALID_DEVICE:
1445                         ccb->ccb_h.status = CAM_PATH_INVALID;
1446                         break;
1447                 case QHSTA_M_NO_AUTO_REQ_SENSE:
1448                         /*
1449                          * User didn't request sense, but we got a
1450                          * check condition.
1451                          */
1452                         ccb->csio.scsi_status = acb->queue.scsi_status;
1453                         ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
1454                         break;
1455                 default:
1456                         panic("%s: Unhandled Host status error %x",
1457                             device_get_nameunit(adw->device),
1458                             acb->queue.host_status);
1459                         /* NOTREACHED */
1460                 }
1461         }
1462         if ((acb->state & ACB_RECOVERY_ACB) != 0) {
1463                 if (ccb->ccb_h.status == CAM_SCSI_BUS_RESET
1464                  || ccb->ccb_h.status == CAM_BDR_SENT)
1465                         ccb->ccb_h.status = CAM_CMD_TIMEOUT;
1466         }
1467         if (ccb->ccb_h.status != CAM_REQ_CMP) {
1468                 xpt_freeze_devq(ccb->ccb_h.path, /*count*/1);
1469                 ccb->ccb_h.status |= CAM_DEV_QFRZN;
1470         }
1471         adwfreeacb(adw, acb);
1472         xpt_done(ccb);
1473 }
1474
1475 static void
1476 adwtimeout(void *arg)
1477 {
1478         struct acb           *acb;
1479         union  ccb           *ccb;
1480         struct adw_softc     *adw;
1481         adw_idle_cmd_status_t status;
1482         int                   target_id;
1483
1484         acb = (struct acb *)arg;
1485         ccb = acb->ccb;
1486         adw = (struct adw_softc *)ccb->ccb_h.ccb_adw_ptr;
1487         xpt_print_path(ccb->ccb_h.path);
1488         printf("ACB %p - timed out\n", (void *)acb);
1489
1490         mtx_assert(&adw->lock, MA_OWNED);
1491
1492         if ((acb->state & ACB_ACTIVE) == 0) {
1493                 xpt_print_path(ccb->ccb_h.path);
1494                 printf("ACB %p - timed out CCB already completed\n",
1495                        (void *)acb);
1496                 return;
1497         }
1498
1499         acb->state |= ACB_RECOVERY_ACB;
1500         target_id = ccb->ccb_h.target_id;
1501
1502         /* Attempt a BDR first */
1503         status = adw_idle_cmd_send(adw, ADW_IDLE_CMD_DEVICE_RESET,
1504                                    ccb->ccb_h.target_id);
1505         if (status == ADW_IDLE_CMD_SUCCESS) {
1506                 device_printf(adw->device,
1507                     "BDR Delivered.  No longer in timeout\n");
1508                 adw_handle_device_reset(adw, target_id);
1509         } else {
1510                 adw_reset_bus(adw);
1511                 xpt_print_path(adw->path);
1512                 printf("Bus Reset Delivered.  No longer in timeout\n");
1513         }
1514 }
1515
1516 static void
1517 adw_handle_device_reset(struct adw_softc *adw, u_int target)
1518 {
1519         struct cam_path *path;
1520         cam_status error;
1521
1522         error = xpt_create_path(&path, /*periph*/NULL, cam_sim_path(adw->sim),
1523                                 target, CAM_LUN_WILDCARD);
1524
1525         if (error == CAM_REQ_CMP) {
1526                 xpt_async(AC_SENT_BDR, path, NULL);
1527                 xpt_free_path(path);
1528         }
1529         adw->last_reset = CAM_BDR_SENT;
1530 }
1531
1532 static void
1533 adw_handle_bus_reset(struct adw_softc *adw, int initiated)
1534 {
1535         if (initiated) {
1536                 /*
1537                  * The microcode currently sets the SCSI Bus Reset signal
1538                  * while handling the AscSendIdleCmd() IDLE_CMD_SCSI_RESET
1539                  * command above.  But the SCSI Bus Reset Hold Time in the
1540                  * microcode is not deterministic (it may in fact be for less
1541                  * than the SCSI Spec. minimum of 25 us).  Therefore on return
1542                  * the Adv Library sets the SCSI Bus Reset signal for
1543                  * ADW_SCSI_RESET_HOLD_TIME_US, which is defined to be greater
1544                  * than 25 us.
1545                  */
1546                 u_int scsi_ctrl;
1547
1548                 scsi_ctrl = adw_inw(adw, ADW_SCSI_CTRL) & ~ADW_SCSI_CTRL_RSTOUT;
1549                 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl | ADW_SCSI_CTRL_RSTOUT);
1550                 DELAY(ADW_SCSI_RESET_HOLD_TIME_US);
1551                 adw_outw(adw, ADW_SCSI_CTRL, scsi_ctrl);
1552
1553                 /*
1554                  * We will perform the async notification when the
1555                  * SCSI Reset interrupt occurs.
1556                  */
1557         } else
1558                 xpt_async(AC_BUS_RESET, adw->path, NULL);
1559         adw->last_reset = CAM_SCSI_BUS_RESET;
1560 }
1561 MODULE_DEPEND(adw, cam, 1, 1, 1);
1562