2 * Low level routines for Second Generation
3 * Advanced Systems Inc. SCSI controllers chips
5 * Copyright (c) 1998, 1999, 2000 Justin Gibbs.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
36 * Copyright (c) 1995-1998 Advanced System Products, Inc.
37 * All Rights Reserved.
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that redistributions of source
41 * code retain the above copyright notice and this comment without
45 #include <sys/cdefs.h>
46 __FBSDID("$FreeBSD$");
48 #include <sys/param.h>
51 #include <sys/mutex.h>
52 #include <sys/systm.h>
56 #include <machine/bus.h>
59 #include <cam/cam_ccb.h>
60 #include <cam/cam_sim.h>
61 #include <cam/cam_xpt_sim.h>
62 #include <cam/scsi/scsi_all.h>
64 #include <dev/advansys/adwlib.h>
66 const struct adw_eeprom adw_asc3550_default_eeprom =
68 ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
70 0xFFFF, /* disc_enable */
71 0xFFFF, /* wdtr_able */
72 { 0xFFFF }, /* sdtr_able */
73 0xFFFF, /* start_motor */
74 0xFFFF, /* tagqng_able */
75 0xFFFF, /* bios_scan */
76 0, /* scam_tolerant */
77 7, /* adapter_scsi_id */
78 0, /* bios_boot_delay */
79 3, /* scsi_reset_delay */
83 0xFFE7, /* bios_ctrl */
84 { 0xFFFF }, /* ultra_able */
85 { 0 }, /* reserved2 */
86 ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
87 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
90 { 0, 0, 0 }, /* serial_number */
93 0, 0, 0, 0, 0, 0, 0, 0,
94 0, 0, 0, 0, 0, 0, 0, 0
99 0, /* saved_dvc_err_code */
100 0, /* saved_adv_err_code */
101 0 /* saved_adv_err_addr */
104 const struct adw_eeprom adw_asc38C0800_default_eeprom =
106 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
107 0x0000, /* 01 cfg_msw */
108 0xFFFF, /* 02 disc_enable */
109 0xFFFF, /* 03 wdtr_able */
110 { 0x4444 }, /* 04 sdtr_speed1 */
111 0xFFFF, /* 05 start_motor */
112 0xFFFF, /* 06 tagqng_able */
113 0xFFFF, /* 07 bios_scan */
114 0, /* 08 scam_tolerant */
115 7, /* 09 adapter_scsi_id */
116 0, /* bios_boot_delay */
117 3, /* 10 scsi_reset_delay */
119 0, /* 11 termination_se */
120 0, /* termination_lvd */
121 0xFFE7, /* 12 bios_ctrl */
122 { 0x4444 }, /* 13 sdtr_speed2 */
123 { 0x4444 }, /* 14 sdtr_speed3 */
124 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
125 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
127 { 0x4444 } , /* 17 sdtr_speed4 */
128 { 0, 0, 0 }, /* 18-20 serial_number */
129 0, /* 21 check_sum */
130 { /* 22-29 oem_name[16] */
131 0, 0, 0, 0, 0, 0, 0, 0,
132 0, 0, 0, 0, 0, 0, 0, 0
134 0, /* 30 dvc_err_code */
135 0, /* 31 adv_err_code */
136 0, /* 32 adv_err_addr */
137 0, /* 33 saved_dvc_err_code */
138 0, /* 34 saved_adv_err_code */
139 0, /* 35 saved_adv_err_addr */
140 { /* 36 - 55 reserved */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
144 0, /* 56 cisptr_lsw */
145 0, /* 57 cisprt_msw */
147 (PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
150 #define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
151 #define ADW_MC_SDTR_OFFSET_ULTRA2 1
152 #define ADW_MC_SDTR_OFFSET_ULTRA 2
153 const struct adw_syncrate adw_syncrates[] =
155 /* mc_sdtr period rate */
156 { ADW_MC_SDTR_80, 9, "80.0" },
157 { ADW_MC_SDTR_40, 10, "40.0" },
158 { ADW_MC_SDTR_20, 12, "20.0" },
159 { ADW_MC_SDTR_10, 25, "10.0" },
160 { ADW_MC_SDTR_5, 50, "5.0" },
161 { ADW_MC_SDTR_ASYNC, 0, "async" }
164 const int adw_num_syncrates = sizeof(adw_syncrates) / sizeof(adw_syncrates[0]);
166 static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
167 static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
169 static void adw_eeprom_wait(struct adw_softc *adw);
172 adw_find_signature(struct adw_softc *adw)
174 if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
175 && adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
184 adw_reset_chip(struct adw_softc *adw)
186 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
188 adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
191 * Initialize Chip registers.
193 adw_outw(adw, ADW_SCSI_CFG1,
194 adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
198 * Reset the SCSI bus.
201 adw_reset_bus(struct adw_softc *adw)
203 adw_idle_cmd_status_t status;
206 mtx_assert(&adw->lock, MA_OWNED);
208 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
209 if (status != ADW_IDLE_CMD_SUCCESS) {
210 xpt_print_path(adw->path);
211 printf("Bus Reset start attempt failed\n");
214 DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
216 adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
217 if (status != ADW_IDLE_CMD_SUCCESS) {
218 xpt_print_path(adw->path);
219 printf("Bus Reset end attempt failed\n");
226 * Read the specified EEPROM location
229 adw_eeprom_read_16(struct adw_softc *adw, int addr)
231 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
232 adw_eeprom_wait(adw);
233 return (adw_inw(adw, ADW_EEP_DATA));
237 adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
239 adw_outw(adw, ADW_EEP_DATA, data);
240 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
241 adw_eeprom_wait(adw);
245 * Wait for and EEPROM command to complete
248 adw_eeprom_wait(struct adw_softc *adw)
252 for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
253 if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
257 if (i == ADW_EEP_DELAY_MS)
258 panic("%s: Timedout Reading EEPROM",
259 device_get_nameunit(adw->device));
263 * Read EEPROM configuration into the specified buffer.
265 * Return a checksum based on the EEPROM configuration read.
268 adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
275 wbuf = (u_int16_t *)eep_buf;
278 for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
279 eep_addr < ADW_EEP_DVC_CFG_END;
280 eep_addr++, wbuf++) {
281 wval = adw_eeprom_read_16(adw, eep_addr);
286 /* checksum field is not counted in the checksum */
287 *wbuf = adw_eeprom_read_16(adw, eep_addr);
290 /* Driver seeprom variables are not included in the checksum */
291 for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
292 eep_addr < ADW_EEP_MAX_WORD_ADDR;
294 *wbuf = adw_eeprom_read_16(adw, eep_addr);
300 adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
306 wbuf = (u_int16_t *)eep_buf;
309 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
310 adw_eeprom_wait(adw);
313 * Write EEPROM until checksum.
315 for (addr = ADW_EEP_DVC_CFG_BEGIN;
316 addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
318 adw_eeprom_write_16(adw, addr, *wbuf);
322 * Write calculated EEPROM checksum
324 adw_eeprom_write_16(adw, addr, chksum);
326 /* skip over buffer's checksum */
332 for (addr = ADW_EEP_DVC_CTL_BEGIN;
333 addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
334 adw_eeprom_write_16(adw, addr, *wbuf);
336 adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
337 adw_eeprom_wait(adw);
341 adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
343 u_int8_t biosmem[ADW_MC_BIOSLEN];
344 const u_int16_t *word_table;
345 const u_int8_t *byte_codes;
346 const u_int8_t *byte_codes_end;
348 u_int bytes_downloaded;
356 * Save the RISC memory BIOS region before writing the microcode.
357 * The BIOS may already be loaded and using its RISC LRAM region
358 * so its region must be saved and restored.
360 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
361 biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
364 * Save current per TID negotiated values if the BIOS has been
365 * loaded (BIOS signature is present). These will be used if
366 * we cannot get information from the EEPROM.
368 addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
369 bios_sig = biosmem[addr]
370 | (biosmem[addr + 1] << 8);
371 if (bios_sig == 0x55AA
372 && (adw->flags & ADW_EEPROM_FAILED) != 0) {
377 addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
378 minor_ver = biosmem[addr + 1] & 0xF;
379 major_ver = (biosmem[addr + 1] >> 4) & 0xF;
380 if ((adw->chip == ADW_CHIP_ASC3550)
382 || (major_ver == 3 && minor_ver <= 1))) {
384 * BIOS 3.1 and earlier location of
385 * 'wdtr_able' variable.
388 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
391 adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
393 sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
394 for (tid = 0; tid < ADW_MAX_TID; tid++) {
398 tid_mask = 0x1 << tid;
399 if ((sdtr_able & tid_mask) == 0)
400 mc_sdtr = ADW_MC_SDTR_ASYNC;
401 else if ((adw->features & ADW_DT) != 0)
402 mc_sdtr = ADW_MC_SDTR_80;
403 else if ((adw->features & ADW_ULTRA2) != 0)
404 mc_sdtr = ADW_MC_SDTR_40;
406 mc_sdtr = ADW_MC_SDTR_20;
407 adw_set_user_sdtr(adw, tid, mc_sdtr);
409 adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
413 * Load the Microcode.
415 * Assume the following compressed format of the microcode buffer:
417 * 253 word (506 byte) table indexed by byte code followed
418 * by the following byte codes:
421 * 00: Emit word 0 in table.
422 * 01: Emit word 1 in table.
424 * FD: Emit word 253 in table.
429 * FE WW WW: (3 byte code)
430 * Word to emit is the next word WW WW.
431 * FF BB WW WW: (4 byte code)
432 * Emit BB count times next word WW WW.
435 bytes_downloaded = 0;
436 word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
437 byte_codes = (const u_int8_t *)&word_table[253];
438 byte_codes_end = adw->mcode_data->mcode_buf
439 + adw->mcode_data->mcode_size;
440 adw_outw(adw, ADW_RAM_ADDR, 0);
441 while (byte_codes < byte_codes_end) {
442 if (*byte_codes == 0xFF) {
445 value = byte_codes[2]
446 | byte_codes[3] << 8;
447 adw_set_multi_2(adw, ADW_RAM_DATA,
448 value, byte_codes[1]);
449 bytes_downloaded += byte_codes[1];
451 } else if (*byte_codes == 0xFE) {
454 value = byte_codes[1]
455 | byte_codes[2] << 8;
456 adw_outw(adw, ADW_RAM_DATA, value);
460 adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
465 /* Convert from words to bytes */
466 bytes_downloaded *= 2;
469 * Clear the rest of LRAM.
471 for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
472 adw_outw(adw, ADW_RAM_DATA, 0);
475 * Verify the microcode checksum.
478 adw_outw(adw, ADW_RAM_ADDR, 0);
479 for (addr = 0; addr < bytes_downloaded; addr += 2)
480 checksum += adw_inw(adw, ADW_RAM_DATA);
482 if (checksum != adw->mcode_data->mcode_chksum) {
483 device_printf(adw->device, "Firmware load failed!\n");
488 * Restore the RISC memory BIOS region.
490 for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
491 adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
494 * Calculate and write the microcode code checksum to
495 * the microcode code checksum location.
497 addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
498 end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
500 adw_outw(adw, ADW_RAM_ADDR, addr);
501 for (; addr < end_addr; addr += 2)
502 checksum += adw_inw(adw, ADW_RAM_DATA);
503 adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
506 * Tell the microcode what kind of chip it's running on.
508 adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
511 * Leave WDTR and SDTR negotiation disabled until the XPT has
512 * informed us of device capabilities, but do set the desired
513 * user rates in case we receive an SDTR request from the target
514 * before we negotiate. We turn on tagged queuing at the microcode
515 * level for all devices, and modulate this on a per command basis.
517 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
518 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
519 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
520 adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
521 adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
522 for (tid = 0; tid < ADW_MAX_TID; tid++) {
523 /* Cam limits the maximum number of commands for us */
524 adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
527 adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
530 * Set SCSI_CFG0 Microcode Default Value.
532 * The microcode will set the SCSI_CFG0 register using this value
533 * after it is started.
535 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
536 ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
537 ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
540 * Tell the MC about the memory size that
541 * was setup by the probe code.
543 adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
544 adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
547 * Determine SCSI_CFG1 Microcode Default Value.
549 * The microcode will set the SCSI_CFG1 register using this value
550 * after it is started below.
552 scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
555 * If the internal narrow cable is reversed all of the SCSI_CTRL
556 * register signals will be set. Check for and return an error if
557 * this condition is found.
559 if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
560 device_printf(adw->device, "Illegal Cable Config!\n");
561 device_printf(adw->device, "Internal cable is reversed!\n");
566 * If this is a differential board and a single-ended device
567 * is attached to one of the connectors, return an error.
569 if ((adw->features & ADW_ULTRA) != 0) {
570 if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
571 && (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
572 device_printf(adw->device, "A Single Ended Device is "
573 "attached to our differential bus!\n");
577 if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
578 device_printf(adw->device,
579 "A High Voltage Differential Device "
580 "is attached to this controller.\n");
581 device_printf(adw->device,
582 "HVD devices are not supported.\n");
588 * Perform automatic termination control if desired.
590 if ((adw->features & ADW_ULTRA2) != 0) {
594 * Ultra2 Chips require termination disabled to
595 * detect cable presence.
597 adw_outw(adw, ADW_SCSI_CFG1,
598 scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
599 cable_det = adw_inw(adw, ADW_SCSI_CFG1);
600 adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
602 /* SE Termination first if auto-term has been specified */
603 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
606 * For all SE cable configurations, high byte
607 * termination is enabled.
609 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
610 if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
611 || (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
613 * If either cable is not present, the
614 * low byte must be terminated as well.
616 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
621 if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
622 && (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
624 * If both cables are installed, termination
625 * is disabled. Otherwise it is enabled.
627 if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
628 || (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
630 term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
633 term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
635 /* Ultra Controller Termination */
636 if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
638 int wide_cable_count;
641 wide_cable_count = 0;
642 if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
646 if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
649 /* There is only one external port */
650 if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
653 } else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
656 if (cable_count == 3) {
657 device_printf(adw->device,
658 "Illegal Cable Config!\n");
659 device_printf(adw->device,
660 "Only Two Ports may be used at a time!\n");
661 } else if (cable_count <= 1) {
663 * At least two out of three cables missing.
664 * Terminate both bytes.
666 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
667 | ADW_SCSI_CFG1_TERM_CTL_L;
668 } else if (wide_cable_count <= 1) {
669 /* No two 16bit cables present. High on. */
670 term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
675 /* Tell the user about our decission */
676 switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
677 case ADW_SCSI_CFG1_TERM_CTL_MASK:
678 printf("High & Low SE Term Enabled, ");
680 case ADW_SCSI_CFG1_TERM_CTL_H:
681 printf("High SE Termination Enabled, ");
683 case ADW_SCSI_CFG1_TERM_CTL_L:
684 printf("Low SE Term Enabled, ");
690 if ((adw->features & ADW_ULTRA2) != 0
691 && (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
692 printf("LVD Term Enabled, ");
695 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
696 * set 'scsicfg1'. The TERM_POL bit does not need to be
697 * referenced, because the hardware internally inverts
698 * the Termination High and Low bits if TERM_POL is set.
700 if ((adw->features & ADW_ULTRA2) != 0) {
701 term_scsicfg1 = ~term_scsicfg1;
702 term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
703 | ADW2_SCSI_CFG1_TERM_CTL_LVD;
704 scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
705 |ADW2_SCSI_CFG1_TERM_CTL_LVD
706 |ADW_SCSI_CFG1_BIG_ENDIAN
707 |ADW_SCSI_CFG1_TERM_POL
708 |ADW2_SCSI_CFG1_DEV_DETECT);
709 scsicfg1 |= term_scsicfg1;
711 term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
712 scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
713 scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
714 scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
718 * Set SCSI_CFG1 Microcode Default Value
720 * The microcode will set the SCSI_CFG1 register using this value
721 * after it is started below.
723 adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
726 * Only accept selections on our initiator target id.
727 * This may change in target mode scenarios...
729 adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
730 (0x01 << adw->initiator_id));
733 * Tell the microcode where it can find our
734 * Initiator Command Queue (ICQ). It is
735 * currently empty hence the "stopper" address.
737 adw->commandq = adw->free_carriers;
738 adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
739 adw->commandq->next_ba = ADW_CQ_STOPPER;
740 adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
743 * Tell the microcode where it can find our
744 * Initiator Response Queue (IRQ). It too
745 * is currently empty.
747 adw->responseq = adw->free_carriers;
748 adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
749 adw->responseq->next_ba = ADW_CQ_STOPPER;
750 adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
752 adw_outb(adw, ADW_INTR_ENABLES,
753 ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
755 adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
761 adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
763 adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
764 adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
765 mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
769 adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
773 mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
774 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
775 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
780 adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
782 u_int mc_sdtr_offset;
785 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
786 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
787 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
788 mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
789 mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
790 adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
794 adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
796 u_int mc_sdtr_offset;
799 mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
800 mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
801 mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
802 mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
803 mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
808 adw_find_sdtr(struct adw_softc *adw, u_int period)
813 if ((adw->features & ADW_DT) == 0)
814 i = ADW_MC_SDTR_OFFSET_ULTRA2;
815 if ((adw->features & ADW_ULTRA2) == 0)
816 i = ADW_MC_SDTR_OFFSET_ULTRA;
818 return ADW_MC_SDTR_ASYNC;
820 for (; i < adw_num_syncrates; i++) {
821 if (period <= adw_syncrates[i].period)
822 return (adw_syncrates[i].mc_sdtr);
824 return ADW_MC_SDTR_ASYNC;
828 adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
832 for (i = 0; i < adw_num_syncrates; i++) {
833 if (mc_sdtr == adw_syncrates[i].mc_sdtr)
836 return (adw_syncrates[i].period);
840 adw_hshk_cfg_period_factor(u_int tinfo)
842 tinfo &= ADW_HSHK_CFG_RATE_MASK;
843 tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
847 else if (tinfo == 0x10)
851 return (((tinfo * 25) + 50) / 4);
855 * Send an idle command to the chip and wait for completion.
857 adw_idle_cmd_status_t
858 adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
861 adw_idle_cmd_status_t status;
864 mtx_assert(&adw->lock, MA_OWNED);
867 * Clear the idle command status which is set by the microcode
868 * to a non-zero value to indicate when the command is completed.
870 adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
873 * Write the idle command value after the idle command parameter
874 * has been written to avoid a race condition. If the order is not
875 * followed, the microcode may process the idle command before the
876 * parameters have been written to LRAM.
878 adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
879 adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
882 * Tickle the RISC to tell it to process the idle command.
884 adw_tickle_risc(adw, ADW_TICKLE_B);
886 /* Wait for up to 10 seconds for the command to complete */
889 status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
896 panic("%s: Idle Command Timed Out!",
897 device_get_nameunit(adw->device));