2 * Definitions for low level routines and data structures
3 * for the Advanced Systems Inc. SCSI controllers chips.
5 * Copyright (c) 1998, 1999, 2000 Justin T. Gibbs.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
38 * Copyright (c) 1995-1998 Advanced System Products, Inc.
39 * All Rights Reserved.
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that redistributions of source
43 * code retain the above copyright notice and this comment without
52 #include <stddef.h> /* for offsetof */
54 #include <dev/advansys/adwmcode.h>
56 #define ADW_DEF_MAX_HOST_QNG 253
57 #define ADW_DEF_MIN_HOST_QNG 16
58 #define ADW_DEF_MAX_DVC_QNG 63
59 #define ADW_DEF_MIN_DVC_QNG 4
61 #define ADW_MAX_TID 15
64 #define ADW_ALL_TARGETS 0xFFFF
66 #define ADW_TARGET_GROUP(tid) ((tid) & ~0x3)
67 #define ADW_TARGET_GROUP_SHIFT(tid) (((tid) & 0x3) * 4)
68 #define ADW_TARGET_GROUP_MASK(tid) (0xF << ADW_TARGET_GROUP_SHIFT(tid))
71 * Board Register offsets.
73 #define ADW_INTR_STATUS_REG 0x0000
74 #define ADW_INTR_STATUS_INTRA 0x01
75 #define ADW_INTR_STATUS_INTRB 0x02
76 #define ADW_INTR_STATUS_INTRC 0x04
77 #define ADW_INTR_STATUS_INTRALL 0x07
80 #define ADW_SIGNATURE_WORD 0x0000
81 #define ADW_CHIP_ID_WORD 0x04C1
83 #define ADW_SIGNATURE_BYTE 0x0001
84 #define ADW_CHIP_ID_BYTE 0x25
86 #define ADW_INTR_ENABLES 0x0002 /*8 bit */
87 #define ADW_INTR_ENABLE_HOST_INTR 0x01
88 #define ADW_INTR_ENABLE_SEL_INTR 0x02
89 #define ADW_INTR_ENABLE_DPR_INTR 0x04
90 #define ADW_INTR_ENABLE_RTA_INTR 0x08
91 #define ADW_INTR_ENABLE_RMA_INTR 0x10
92 #define ADW_INTR_ENABLE_RST_INTR 0x20
93 #define ADW_INTR_ENABLE_DPE_INTR 0x40
94 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80
96 #define ADW_CTRL_REG 0x0002 /*16 bit*/
97 #define ADW_CTRL_REG_HOST_INTR 0x0100
98 #define ADW_CTRL_REG_SEL_INTR 0x0200
99 #define ADW_CTRL_REG_DPR_INTR 0x0400
100 #define ADW_CTRL_REG_RTA_INTR 0x0800
101 #define ADW_CTRL_REG_RMA_INTR 0x1000
102 #define ADW_CTRL_REG_RES_BIT14 0x2000
103 #define ADW_CTRL_REG_DPE_INTR 0x4000
104 #define ADW_CTRL_REG_POWER_DONE 0x8000
105 #define ADW_CTRL_REG_ANY_INTR 0xFF00
106 #define ADW_CTRL_REG_CMD_RESET 0x00C6
107 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5
108 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4
109 #define ADW_CTRL_REG_CMD_WR_PCI_CFG 0x00C3
110 #define ADW_CTRL_REG_CMD_RD_PCI_CFG 0x00C2
112 #define ADW_RAM_ADDR 0x0004
113 #define ADW_RAM_DATA 0x0006
115 #define ADW_RISC_CSR 0x000A
116 #define ADW_RISC_CSR_STOP 0x0000
117 #define ADW_RISC_TEST_COND 0x2000
118 #define ADW_RISC_CSR_RUN 0x4000
119 #define ADW_RISC_CSR_SINGLE_STEP 0x8000
121 #define ADW_SCSI_CFG0 0x000C
122 #define ADW_SCSI_CFG0_TIMER_MODEAB 0xC000 /*
124 * and Selto timer CFG
126 #define ADW_SCSI_CFG0_PARITY_EN 0x2000
127 #define ADW_SCSI_CFG0_EVEN_PARITY 0x1000
128 #define ADW_SCSI_CFG0_WD_LONG 0x0800 /*
130 * 1: 57 min, 0: 13 sec
132 #define ADW_SCSI_CFG0_QUEUE_128 0x0400 /*
137 #define ADW_SCSI_CFG0_PRIM_MODE 0x0100
138 #define ADW_SCSI_CFG0_SCAM_EN 0x0080
139 #define ADW_SCSI_CFG0_SEL_TMO_LONG 0x0040 /*
144 #define ADW_SCSI_CFG0_CFRM_ID 0x0020 /* SCAM id sel. */
145 #define ADW_SCSI_CFG0_OUR_ID_EN 0x0010
146 #define ADW_SCSI_CFG0_OUR_ID 0x000F
149 #define ADW_SCSI_CFG1 0x000E
150 #define ADW_SCSI_CFG1_BIG_ENDIAN 0x8000
151 #define ADW_SCSI_CFG1_TERM_POL 0x2000
152 #define ADW_SCSI_CFG1_SLEW_RATE 0x1000
153 #define ADW_SCSI_CFG1_FILTER_MASK 0x0C00
154 #define ADW_SCSI_CFG1_FLTR_DISABLE 0x0000
155 #define ADW_SCSI_CFG1_FLTR_11_TO_20NS 0x0800
156 #define ADW_SCSI_CFG1_FLTR_21_TO_39NS 0x0C00
157 #define ADW_SCSI_CFG1_DIS_ACTIVE_NEG 0x0200
158 #define ADW_SCSI_CFG1_DIFF_MODE 0x0100
159 #define ADW_SCSI_CFG1_DIFF_SENSE 0x0080
160 #define ADW_SCSI_CFG1_TERM_CTL_MANUAL 0x0040 /* Global Term Switch */
161 #define ADW_SCSI_CFG1_TERM_CTL_MASK 0x0030
162 #define ADW_SCSI_CFG1_TERM_CTL_H 0x0020 /* Enable SCSI-H */
163 #define ADW_SCSI_CFG1_TERM_CTL_L 0x0010 /* Enable SCSI-L */
164 #define ADW_SCSI_CFG1_CABLE_DETECT 0x000F
165 #define ADW_SCSI_CFG1_EXT16_MASK 0x0008 /* Ext16 cable pres */
166 #define ADW_SCSI_CFG1_EXT8_MASK 0x0004 /* Ext8 cable pres */
167 #define ADW_SCSI_CFG1_INT8_MASK 0x0002 /* Int8 cable pres */
168 #define ADW_SCSI_CFG1_INT16_MASK 0x0001 /* Int16 cable pres */
169 #define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK \
170 (ADW_SCSI_CFG1_EXT16_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
171 #define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \
172 (ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
175 * Addendum for ASC-38C0800 Chip
177 #define ADW2_SCSI_CFG1_DIS_TERM_DRV 0x4000 /*
184 #define ADW2_SCSI_CFG1_DEV_DETECT 0x1C00
185 #define ADW2_SCSI_CFG1_DEV_DETECT_HVD 0x1000
186 #define ADW2_SCSI_CFG1_DEV_DETECT_LVD 0x0800
187 #define ADW2_SCSI_CFG1_DEV_DETECT_SE 0x0400
189 #define ADW2_SCSI_CFG1_TERM_CTL_LVD 0x00C0 /* Ultra2 Only */
190 #define ADW2_SCSI_CFG1_TERM_LVD_HI 0x0080
191 #define ADW2_SCSI_CFG1_TERM_LVD_LO 0x0040
192 #define ADW2_SCSI_CFG1_EXTLVD_MASK 0x0008 /* ExtLVD cable pres */
193 #define ADW2_SCSI_CFG1_INTLVD_MASK 0x0004 /* IntLVD cable pres */
195 #define ADW_MEM_CFG 0x0010
196 #define ADW_MEM_CFG_BIOS_EN 0x40
197 #define ADW_MEM_CFG_FAST_EE_CLK 0x20 /* Diagnostic Bit */
198 #define ADW_MEM_CFG_RAM_SZ_MASK 0x1C /* RISC RAM Size */
199 #define ADW_MEM_CFG_RAM_SZ_2KB 0x00
200 #define ADW_MEM_CFG_RAM_SZ_4KB 0x04
201 #define ADW_MEM_CFG_RAM_SZ_8KB 0x08
202 #define ADW_MEM_CFG_RAM_SZ_16KB 0x0C
203 #define ADW_MEM_CFG_RAM_SZ_32KB 0x10
204 #define ADW_MEM_CFG_RAM_SZ_64KB 0x14
206 #define ADW_GPIO_CNTL 0x0011
207 #define ADW_GPIO_DATA 0x0012
209 #define ADW_COMMA 0x0014
210 #define ADW_COMMB 0x0018
212 #define ADW_EEP_CMD 0x001A
213 #define ADW_EEP_CMD_READ 0x0080 /* or in address */
214 #define ADW_EEP_CMD_WRITE 0x0040 /* or in address */
215 #define ADW_EEP_CMD_WRITE_ABLE 0x0030
216 #define ADW_EEP_CMD_WRITE_DISABLE 0x0000
217 #define ADW_EEP_CMD_DONE 0x0200
218 #define ADW_EEP_CMD_DONE_ERR 0x0001
219 #define ADW_EEP_DELAY_MS 100
221 #define ADW_EEP_DATA 0x001C
223 #define ADW_DMA_CFG0 0x0020
224 #define ADW_DMA_CFG0_BC_THRESH_ENB 0x80
225 #define ADW_DMA_CFG0_FIFO_THRESH 0x70
226 #define ADW_DMA_CFG0_FIFO_THRESH_16B 0x00
227 #define ADW_DMA_CFG0_FIFO_THRESH_32B 0x20
228 #define ADW_DMA_CFG0_FIFO_THRESH_48B 0x30
229 #define ADW_DMA_CFG0_FIFO_THRESH_64B 0x40
230 #define ADW_DMA_CFG0_FIFO_THRESH_80B 0x50
231 #define ADW_DMA_CFG0_FIFO_THRESH_96B 0x60
232 #define ADW_DMA_CFG0_FIFO_THRESH_112B 0x70
233 #define ADW_DMA_CFG0_START_CTL_MASK 0x0C
234 #define ADW_DMA_CFG0_START_CTL_TH 0x00 /* Start on thresh */
235 #define ADW_DMA_CFG0_START_CTL_IDLE 0x04 /* Start when idle */
236 #define ADW_DMA_CFG0_START_CTL_TH_IDLE 0x08 /* Either */
237 #define ADW_DMA_CFG0_START_CTL_EM_FU 0x0C /* Start on full/empty */
238 #define ADW_DMA_CFG0_READ_CMD_MASK 0x03
239 #define ADW_DMA_CFG0_READ_CMD_MR 0x00
240 #define ADW_DMA_CFG0_READ_CMD_MRL 0x02
241 #define ADW_DMA_CFG0_READ_CMD_MRM 0x03
243 #define ADW_TICKLE 0x0022
244 #define ADW_TICKLE_NOP 0x00
245 #define ADW_TICKLE_A 0x01
246 #define ADW_TICKLE_B 0x02
247 #define ADW_TICKLE_C 0x03
249 /* Program Counter */
252 #define ADW_SCSI_CTRL 0x0034
253 #define ADW_SCSI_CTRL_RSTOUT 0x2000
256 * ASC-38C0800 RAM BIST Register bit definitions
258 #define ADW_RAM_BIST 0x0038
259 #define ADW_RAM_BIST_RAM_TEST_MODE 0x80
260 #define ADW_RAM_BIST_PRE_TEST_MODE 0x40
261 #define ADW_RAM_BIST_NORMAL_MODE 0x00
262 #define ADW_RAM_BIST_RAM_TEST_DONE 0x10
263 #define ADW_RAM_BIST_RAM_TEST_STATUS 0x0F
264 #define ADW_RAM_BIST_RAM_TEST_HOST_ERR 0x08
265 #define ADW_RAM_BIST_RAM_TEST_RAM_ERR 0x04
266 #define ADW_RAM_BIST_RAM_TEST_RISC_ERR 0x02
267 #define ADW_RAM_BIST_RAM_TEST_SCSI_ERR 0x01
268 #define ADW_RAM_BIST_RAM_TEST_SUCCESS 0x00
269 #define ADW_RAM_BIST_PRE_TEST_VALUE 0x05
270 #define ADW_RAM_BIST_NORMAL_VALUE 0x00
271 #define ADW_PLL_TEST 0x0039
273 #define ADW_SCSI_RESET_HOLD_TIME_US 60
276 #define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
277 #define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */
279 #define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
280 #define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
282 #define ADW_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
283 #define ADW_38C1600_IOLEN 0x100 /* I/O Port Range in bytes */
284 #define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB */
286 #define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
287 #define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
289 #define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
290 #define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
291 #define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
292 #define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
293 #define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
295 /* ====================== SCSI Request Structures =========================== */
297 #define ADW_NO_OF_SG_PER_BLOCK 15
300 * Although the adapter can deal with S/G lists of indefinite size,
301 * we limit the list to 30 to conserve space as the kernel can only send
302 * us buffers of at most 64KB currently.
304 #define ADW_SG_BLOCKCNT 2
305 #define ADW_SGSIZE (ADW_NO_OF_SG_PER_BLOCK * ADW_SG_BLOCKCNT)
312 /* sg block structure used by the microcode */
313 struct adw_sg_block {
317 u_int8_t sg_cnt; /* Valid entries in this block */
318 u_int32_t sg_busaddr_next; /* link to the next sg block */
319 struct adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
322 /* Structure representing a single allocation block of adw sg blocks */
324 bus_dmamap_t sg_dmamap;
325 bus_addr_t sg_physaddr;
326 struct adw_sg_block* sg_vaddr;
327 SLIST_ENTRY(sg_map_node) links;
331 QHSTA_NO_ERROR = 0x00,
332 QHSTA_M_SEL_TIMEOUT = 0x11,
333 QHSTA_M_DATA_OVER_RUN = 0x12,
334 QHSTA_M_UNEXPECTED_BUS_FREE = 0x13,
335 QHSTA_M_QUEUE_ABORTED = 0x15,
336 QHSTA_M_SXFR_SDMA_ERR = 0x16, /* SCSI DMA Error */
337 QHSTA_M_SXFR_SXFR_PERR = 0x17, /* SCSI Bus Parity Error */
338 QHSTA_M_RDMA_PERR = 0x18, /* RISC PCI DMA parity error */
339 QHSTA_M_SXFR_OFF_UFLW = 0x19, /* Offset Underflow */
340 QHSTA_M_SXFR_OFF_OFLW = 0x20, /* Offset Overflow */
341 QHSTA_M_SXFR_WD_TMO = 0x21, /* Watchdog Timeout */
342 QHSTA_M_SXFR_DESELECTED = 0x22, /* Deselected */
343 QHSTA_M_SXFR_XFR_PH_ERR = 0x24, /* Transfer Phase Error */
344 QHSTA_M_SXFR_UNKNOWN_ERROR = 0x25, /* SXFR_STATUS Unknown Error */
345 QHSTA_M_WTM_TIMEOUT = 0x41,
346 QHSTA_M_BAD_CMPL_STATUS_IN = 0x42,
347 QHSTA_M_NO_AUTO_REQ_SENSE = 0x43,
348 QHSTA_M_AUTO_REQ_SENSE_FAIL = 0x44,
349 QHSTA_M_INVALID_DEVICE = 0x45 /* Bad target ID */
353 QD_NO_STATUS = 0x00, /* Request not completed yet. */
355 QD_ABORTED_BY_HOST = 0x02,
360 * Microcode request structure
362 * All fields in this structure are used by the microcode so their
363 * size and ordering cannot be changed.
365 struct adw_scsi_req_q {
366 u_int8_t cntl; /* Ucode flags and state. */
368 u_int8_t target_id; /* Device target identifier. */
369 u_int8_t target_lun; /* Device target logical unit number. */
370 u_int32_t data_addr; /* Data buffer physical address. */
371 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
372 u_int32_t sense_baddr; /* Sense buffer bus address. */
373 u_int32_t carrier_baddr; /* Carrier bus address. */
374 u_int8_t mflag; /* microcode flag field. */
375 u_int8_t sense_len; /* Auto-sense length. Residual on complete. */
376 u_int8_t cdb_len; /* SCSI CDB length. */
377 u_int8_t scsi_cntl; /* SCSI command control flags (tags, nego) */
378 #define ADW_QSC_NO_DISC 0x01
379 #define ADW_QSC_NO_TAGMSG 0x02
380 #define ADW_QSC_NO_SYNC 0x04
381 #define ADW_QSC_NO_WIDE 0x08
382 #define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR */
383 #define ADW_QSC_HEAD_OF_Q_TAG 0x40
384 #define ADW_QSC_ORDERED_Q_TAG 0x80
385 u_int8_t done_status; /* Completion status. */
386 u_int8_t scsi_status; /* SCSI status byte. */
387 u_int8_t host_status; /* Ucode host status. */
388 u_int8_t sg_wk_ix; /* Microcode working SG index. */
389 u_int8_t cdb[12]; /* SCSI command block. */
390 u_int32_t sg_real_addr; /* SG list physical address. */
391 u_int32_t scsi_req_baddr; /* Bus address of this structure. */
392 u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */
394 * The 'tokens' placed in these two fields are
395 * used to identify the scsi request and the next
396 * carrier in the response queue, *not* physical
397 * addresses. This driver uses byte offsets for
398 * portability and speed of mapping back to either
399 * a virtual or physical address.
401 u_int32_t scsi_req_bo; /* byte offset of this structure */
402 u_int32_t carrier_bo; /* byte offst of our carrier. */
408 ACB_RELEASE_SIMQ = 0x02
412 struct adw_scsi_req_q queue;
416 struct adw_sg_block* sg_blocks;
417 bus_addr_t sg_busaddr;
418 struct scsi_sense_data sense_data;
419 SLIST_ENTRY(acb) links;
423 * EEPROM configuration format
425 * Field naming convention:
427 * *_enable indicates the field enables or disables the feature. The
428 * value is never reset.
430 * *_able indicates both whether a feature should be enabled or disabled
431 * and whether a device is capable of the feature. At initialization
432 * this field may be set, but later if a device is found to be incapable
433 * of the feature, the field is cleared.
435 * Default values are maintained in a_init.c in the structure
436 * Default_EEPROM_Config.
440 u_int16_t cfg_lsw; /* 00 power up initialization */
441 #define ADW_EEPROM_BIG_ENDIAN 0x8000
442 #define ADW_EEPROM_BIOS_ENABLE 0x4000
443 #define ADW_EEPROM_TERM_POL 0x2000
444 #define ADW_EEPROM_CIS_LD 0x1000
446 /* bit 13 set - Term Polarity Control */
447 /* bit 14 set - BIOS Enable */
448 /* bit 15 set - Big Endian Mode */
449 u_int16_t cfg_msw; /* unused */
450 u_int16_t disc_enable;
454 * sync enable bits for UW cards,
455 * actual sync rate for TID 0-3
456 * on U2W and U160 cards.
458 u_int16_t sync_enable;
461 u_int16_t start_motor;
462 u_int16_t tagqng_able;
464 u_int16_t scam_tolerant;
466 u_int8_t adapter_scsi_id;
467 u_int8_t bios_boot_delay;
469 u_int8_t scsi_reset_delay;
470 u_int8_t bios_id_lun; /* high nibble is lun */
471 /* low nibble is scsi id */
473 u_int8_t termination_se; /* 0 - automatic */
474 #define ADW_EEPROM_TERM_AUTO 0
475 #define ADW_EEPROM_TERM_OFF 1
476 #define ADW_EEPROM_TERM_HIGH_ON 2
477 #define ADW_EEPROM_TERM_BOTH_ON 3
479 u_int8_t termination_lvd;
481 #define ADW_BIOS_INIT_DIS 0x0001 /* Don't act as initiator */
482 #define ADW_BIOS_EXT_TRANS 0x0002 /* > 1 GB support */
483 #define ADW_BIOS_MORE_2DISK 0x0004 /* > 1 GB support */
484 #define ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */
485 #define ADW_BIOS_CD_BOOT 0x0010 /* support bootable CD */
486 #define ADW_BIOS_SCAN_EN 0x0020 /* BIOS SCAN enabled */
487 #define ADW_BIOS_MULTI_LUN 0x0040 /* probe luns */
488 #define ADW_BIOS_MESSAGE 0x0080 /* display BIOS message */
489 #define ADW_BIOS_RESET_BUS 0x0200 /* reset SCSI bus durint init */
490 #define ADW_BIOS_QUIET 0x0800 /* No verbose initialization */
491 #define ADW_BIOS_SCSI_PAR_EN 0x1000 /* SCSI parity enabled */
495 * ultra enable bits for UW cards,
496 * actual sync rate for TID 4-7
497 * on U2W and U160 cards.
499 u_int16_t ultra_enable;
504 * reserved for UW cards,
505 * actual sync rate for TID 8-11
506 * on U2W and U160 cards.
511 u_int8_t max_host_qng; /* 15 maximum host queuing */
512 u_int8_t max_dvc_qng; /* maximum per device queuing */
513 u_int16_t dvc_cntl; /* 16 control bit for driver */
516 * reserved for UW cards,
517 * actual sync rate for TID 12-15
518 * on U2W and U160 cards.
523 u_int16_t serial_number[3]; /* 18-20 */
524 u_int16_t checksum; /* 21 */
525 u_int8_t oem_name[16]; /* 22 - 29 */
526 u_int16_t dvc_err_code; /* 30 */
527 u_int16_t adv_err_code; /* 31 */
528 u_int16_t adv_err_addr; /* 32 */
529 u_int16_t saved_dvc_err_code; /* 33 */
530 u_int16_t saved_adv_err_code; /* 34 */
531 u_int16_t saved_adv_err_addr; /* 35 */
532 u_int16_t reserved[20]; /* 36 - 55 */
533 u_int16_t cisptr_lsw; /* 56 CIS data */
534 u_int16_t cisptr_msw; /* 57 CIS data */
535 u_int32_t subid; /* 58-59 SubSystem Vendor/Dev ID */
536 u_int16_t reserved2[4];
539 /* EEProm Addresses */
540 #define ADW_EEP_DVC_CFG_BEGIN 0x00
541 #define ADW_EEP_DVC_CFG_END (offsetof(struct adw_eeprom, checksum)/2)
542 #define ADW_EEP_DVC_CTL_BEGIN (offsetof(struct adw_eeprom, oem_name)/2)
543 #define ADW_EEP_MAX_WORD_ADDR (sizeof(struct adw_eeprom)/2)
547 ADW_CHIP_ASC3550, /* Ultra-Wide IC */
548 ADW_CHIP_ASC38C0800, /* Ultra2-Wide/LVD IC */
549 ADW_CHIP_ASC38C1600 /* Ultra3-Wide/LVD2 IC */
554 ADW_ULTRA = 0x0001, /* Supports 20MHz Transfers */
555 ADW_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
556 ADW_DT = 0x0004, /* Supports Double Transistion REQ/ACK*/
557 ADW_WIDE = 0x0008, /* Wide Channel */
558 ADW_ASC3550_FE = ADW_ULTRA,
559 ADW_ASC38C0800_FE = ADW_ULTRA2,
560 ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT
565 ADW_EEPROM_FAILED = 0x0001
569 ADW_STATE_NORMAL = 0x00,
570 ADW_RESOURCE_SHORTAGE = 0x01
589 /* We have an input and output queue for our carrier structures */
590 #define ADW_OUTPUT_QUEUE 0 /* Offset into carriers member */
591 #define ADW_INPUT_QUEUE 1 /* Offset into carriers member */
592 #define ADW_NUM_CARRIER_QUEUES 2
596 bus_space_handle_t bsh;
598 bus_dma_tag_t buffer_dmat;
600 struct adw_carrier *carriers;
601 struct adw_carrier *free_carriers;
602 struct adw_carrier *commandq;
603 struct adw_carrier *responseq;
604 LIST_HEAD(, ccb_hdr) pending_ccbs;
605 SLIST_HEAD(, acb) free_acb_list;
606 bus_dma_tag_t parent_dmat;
607 bus_dma_tag_t carrier_dmat; /* dmat for our acb carriers*/
608 bus_dmamap_t carrier_dmamap;
609 bus_dma_tag_t acb_dmat; /* dmat for our ccb array */
610 bus_dmamap_t acb_dmamap;
611 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
612 SLIST_HEAD(, sg_map_node) sg_maps;
613 bus_addr_t acb_busbase;
614 bus_addr_t carrier_busbase;
616 adw_feature features;
620 struct cam_path *path;
622 struct resource *regs;
623 struct resource *irq;
625 const struct adw_mcode *mcode_data;
626 const struct adw_eeprom *default_eeprom;
637 cam_status last_reset; /* Last reset type */
639 adw_idle_cmd_t idle_cmd;
640 u_int idle_cmd_param;
641 volatile int idle_command_cmp;
643 u_int16_t user_sdtr[4]; /* A nibble per-device */
644 u_int16_t user_tagenb;
646 u_int16_t user_discenb;
647 u_int16_t serial_number[3];
650 extern const struct adw_eeprom adw_asc3550_default_eeprom;
651 extern const struct adw_eeprom adw_asc38C0800_default_eeprom;
652 extern const struct adw_syncrate adw_syncrates[];
653 extern const int adw_num_syncrates;
655 #define adw_inb(adw, port) \
656 bus_space_read_1((adw)->tag, (adw)->bsh, port)
657 #define adw_inw(adw, port) \
658 bus_space_read_2((adw)->tag, (adw)->bsh, port)
659 #define adw_inl(adw, port) \
660 bus_space_read_4((adw)->tag, (adw)->bsh, port)
662 #define adw_outb(adw, port, value) \
663 bus_space_write_1((adw)->tag, (adw)->bsh, port, value)
664 #define adw_outw(adw, port, value) \
665 bus_space_write_2((adw)->tag, (adw)->bsh, port, value)
666 #define adw_outl(adw, port, value) \
667 bus_space_write_4((adw)->tag, (adw)->bsh, port, value)
669 #define adw_set_multi_2(adw, port, value, count) \
670 bus_space_set_multi_2((adw)->tag, (adw)->bsh, port, value, count)
672 static __inline const char* adw_name(struct adw_softc *adw);
673 static __inline u_int adw_lram_read_8(struct adw_softc *adw, u_int addr);
674 static __inline u_int adw_lram_read_16(struct adw_softc *adw, u_int addr);
675 static __inline u_int adw_lram_read_32(struct adw_softc *adw, u_int addr);
676 static __inline void adw_lram_write_8(struct adw_softc *adw, u_int addr,
678 static __inline void adw_lram_write_16(struct adw_softc *adw, u_int addr,
680 static __inline void adw_lram_write_32(struct adw_softc *adw, u_int addr,
683 static __inline u_int32_t acbvtobo(struct adw_softc *adw,
685 static __inline u_int32_t acbvtob(struct adw_softc *adw,
687 static __inline struct acb * acbbotov(struct adw_softc *adw,
689 static __inline struct acb * acbbtov(struct adw_softc *adw,
691 static __inline u_int32_t carriervtobo(struct adw_softc *adw,
692 struct adw_carrier *carrier);
693 static __inline u_int32_t carriervtob(struct adw_softc *adw,
694 struct adw_carrier *carrier);
695 static __inline struct adw_carrier *
696 carrierbotov(struct adw_softc *adw,
697 u_int32_t byte_offset);
698 static __inline struct adw_carrier *
699 carrierbtov(struct adw_softc *adw,
702 static __inline const char*
703 adw_name(struct adw_softc *adw)
708 static __inline u_int
709 adw_lram_read_8(struct adw_softc *adw, u_int addr)
711 adw_outw(adw, ADW_RAM_ADDR, addr);
712 return (adw_inb(adw, ADW_RAM_DATA));
715 static __inline u_int
716 adw_lram_read_16(struct adw_softc *adw, u_int addr)
718 adw_outw(adw, ADW_RAM_ADDR, addr);
719 return (adw_inw(adw, ADW_RAM_DATA));
722 static __inline u_int
723 adw_lram_read_32(struct adw_softc *adw, u_int addr)
727 adw_outw(adw, ADW_RAM_ADDR, addr);
728 retval = adw_inw(adw, ADW_RAM_DATA);
729 retval |= (adw_inw(adw, ADW_RAM_DATA) << 16);
734 adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value)
736 adw_outw(adw, ADW_RAM_ADDR, addr);
737 adw_outb(adw, ADW_RAM_DATA, value);
741 adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value)
743 adw_outw(adw, ADW_RAM_ADDR, addr);
744 adw_outw(adw, ADW_RAM_DATA, value);
748 adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
750 adw_outw(adw, ADW_RAM_ADDR, addr);
751 adw_outw(adw, ADW_RAM_DATA, value);
752 adw_outw(adw, ADW_RAM_DATA, value >> 16);
755 static __inline u_int32_t
756 acbvtobo(struct adw_softc *adw, struct acb *acb)
758 return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
761 static __inline u_int32_t
762 acbvtob(struct adw_softc *adw, struct acb *acb)
764 return (adw->acb_busbase + acbvtobo(adw, acb));
767 static __inline struct acb *
768 acbbotov(struct adw_softc *adw, u_int32_t byteoffset)
770 return ((struct acb *)((caddr_t)adw->acbs + byteoffset));
773 static __inline struct acb *
774 acbbtov(struct adw_softc *adw, u_int32_t busaddr)
776 return (acbbotov(adw, busaddr - adw->acb_busbase));
780 * Return the byte offset for a carrier relative to our array of carriers.
782 static __inline u_int32_t
783 carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier)
785 return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers));
788 static __inline u_int32_t
789 carriervtob(struct adw_softc *adw, struct adw_carrier *carrier)
791 return (adw->carrier_busbase + carriervtobo(adw, carrier));
794 static __inline struct adw_carrier *
795 carrierbotov(struct adw_softc *adw, u_int32_t byte_offset)
797 return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset));
800 static __inline struct adw_carrier *
801 carrierbtov(struct adw_softc *adw, u_int32_t baddr)
803 return (carrierbotov(adw, baddr - adw->carrier_busbase));
807 int adw_find_signature(struct adw_softc *adw);
808 void adw_reset_chip(struct adw_softc *adw);
809 u_int16_t adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
810 void adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
811 int adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
812 void adw_set_user_sdtr(struct adw_softc *adw,
813 u_int tid, u_int mc_sdtr);
814 u_int adw_get_user_sdtr(struct adw_softc *adw, u_int tid);
815 void adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr);
816 u_int adw_get_chip_sdtr(struct adw_softc *adw, u_int tid);
817 u_int adw_find_sdtr(struct adw_softc *adw, u_int period);
818 u_int adw_find_period(struct adw_softc *adw, u_int mc_sdtr);
819 u_int adw_hshk_cfg_period_factor(u_int tinfo);
822 void adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
824 adw_idle_cmd_status_t adw_idle_cmd_wait(struct adw_softc *adw);
826 /* SCSI Transaction Processing */
827 static __inline void adw_send_acb(struct adw_softc *adw, struct acb *acb,
828 u_int32_t acb_baddr);
830 static __inline void adw_tickle_risc(struct adw_softc *adw, u_int value)
833 * Tickle the RISC to tell it to read its Command Queue Head pointer.
835 adw_outb(adw, ADW_TICKLE, value);
836 if (adw->chip == ADW_CHIP_ASC3550) {
838 * Clear the tickle value. In the ASC-3550 the RISC flag
839 * command 'clr_tickle_a' does not work unless the host
842 adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP);
847 adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
849 struct adw_carrier *new_cq;
851 new_cq = adw->free_carriers;
852 adw->free_carriers = carrierbotov(adw, new_cq->next_ba);
853 new_cq->next_ba = ADW_CQ_STOPPER;
855 acb->queue.carrier_baddr = adw->commandq->carr_ba;
856 acb->queue.carrier_bo = adw->commandq->carr_offset;
857 adw->commandq->areq_ba = acbvtob(adw, acb);
858 adw->commandq->next_ba = new_cq->carr_ba;
860 printf("EnQ 0x%x 0x%x 0x%x 0x%x\n",
861 adw->commandq->carr_offset,
862 adw->commandq->carr_ba,
863 adw->commandq->areq_ba,
864 adw->commandq->next_ba);
866 adw->commandq = new_cq;
869 adw_tickle_risc(adw, ADW_TICKLE_A);
872 #endif /* _ADWLIB_H_ */