2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter.
27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/module.h>
44 #include <sys/queue.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/taskqueue.h>
52 #include <net/if_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/if_types.h>
58 #include <net/if_vlan_var.h>
60 #include <netinet/in.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/ip.h>
63 #include <netinet/tcp.h>
65 #include <dev/mii/mii.h>
66 #include <dev/mii/miivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/pci/pcivar.h>
70 #include <machine/bus.h>
72 #include "miibus_if.h"
78 * Devices supported by this driver.
80 static struct ae_dev {
85 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2,
86 "Attansic Technology Corp, L2 FastEthernet" },
88 #define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs))
90 static struct resource_spec ae_res_spec_mem[] = {
91 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
94 static struct resource_spec ae_res_spec_irq[] = {
95 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
98 static struct resource_spec ae_res_spec_msi[] = {
99 { SYS_RES_IRQ, 1, RF_ACTIVE },
103 static int ae_probe(device_t dev);
104 static int ae_attach(device_t dev);
105 static void ae_pcie_init(ae_softc_t *sc);
106 static void ae_phy_reset(ae_softc_t *sc);
107 static void ae_phy_init(ae_softc_t *sc);
108 static int ae_reset(ae_softc_t *sc);
109 static void ae_init(void *arg);
110 static int ae_init_locked(ae_softc_t *sc);
111 static int ae_detach(device_t dev);
112 static int ae_miibus_readreg(device_t dev, int phy, int reg);
113 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val);
114 static void ae_miibus_statchg(device_t dev);
115 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
116 static int ae_mediachange(struct ifnet *ifp);
117 static void ae_retrieve_address(ae_softc_t *sc);
118 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs,
120 static int ae_alloc_rings(ae_softc_t *sc);
121 static void ae_dma_free(ae_softc_t *sc);
122 static int ae_shutdown(device_t dev);
123 static int ae_suspend(device_t dev);
124 static void ae_powersave_disable(ae_softc_t *sc);
125 static void ae_powersave_enable(ae_softc_t *sc);
126 static int ae_resume(device_t dev);
127 static unsigned int ae_tx_avail_size(ae_softc_t *sc);
128 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head);
129 static void ae_start(struct ifnet *ifp);
130 static void ae_start_locked(struct ifnet *ifp);
131 static void ae_link_task(void *arg, int pending);
132 static void ae_stop_rxmac(ae_softc_t *sc);
133 static void ae_stop_txmac(ae_softc_t *sc);
134 static void ae_mac_config(ae_softc_t *sc);
135 static int ae_intr(void *arg);
136 static void ae_int_task(void *arg, int pending);
137 static void ae_tx_intr(ae_softc_t *sc);
138 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
139 static void ae_rx_intr(ae_softc_t *sc);
140 static void ae_watchdog(ae_softc_t *sc);
141 static void ae_tick(void *arg);
142 static void ae_rxfilter(ae_softc_t *sc);
143 static void ae_rxvlan(ae_softc_t *sc);
144 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
145 static void ae_stop(ae_softc_t *sc);
146 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc);
147 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word);
148 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr);
149 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr);
150 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats);
151 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats);
152 static void ae_init_tunables(ae_softc_t *sc);
154 static device_method_t ae_methods[] = {
155 /* Device interface. */
156 DEVMETHOD(device_probe, ae_probe),
157 DEVMETHOD(device_attach, ae_attach),
158 DEVMETHOD(device_detach, ae_detach),
159 DEVMETHOD(device_shutdown, ae_shutdown),
160 DEVMETHOD(device_suspend, ae_suspend),
161 DEVMETHOD(device_resume, ae_resume),
164 DEVMETHOD(miibus_readreg, ae_miibus_readreg),
165 DEVMETHOD(miibus_writereg, ae_miibus_writereg),
166 DEVMETHOD(miibus_statchg, ae_miibus_statchg),
170 static driver_t ae_driver = {
175 static devclass_t ae_devclass;
177 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0);
178 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0);
179 MODULE_DEPEND(ae, pci, 1, 1, 1);
180 MODULE_DEPEND(ae, ether, 1, 1, 1);
181 MODULE_DEPEND(ae, miibus, 1, 1, 1);
186 static int msi_disable = 0;
187 TUNABLE_INT("hw.ae.msi_disable", &msi_disable);
189 #define AE_READ_4(sc, reg) \
190 bus_read_4((sc)->mem[0], (reg))
191 #define AE_READ_2(sc, reg) \
192 bus_read_2((sc)->mem[0], (reg))
193 #define AE_READ_1(sc, reg) \
194 bus_read_1((sc)->mem[0], (reg))
195 #define AE_WRITE_4(sc, reg, val) \
196 bus_write_4((sc)->mem[0], (reg), (val))
197 #define AE_WRITE_2(sc, reg, val) \
198 bus_write_2((sc)->mem[0], (reg), (val))
199 #define AE_WRITE_1(sc, reg, val) \
200 bus_write_1((sc)->mem[0], (reg), (val))
201 #define AE_PHY_READ(sc, reg) \
202 ae_miibus_readreg(sc->dev, 0, reg)
203 #define AE_PHY_WRITE(sc, reg, val) \
204 ae_miibus_writereg(sc->dev, 0, reg, val)
205 #define AE_CHECK_EADDR_VALID(eaddr) \
206 ((eaddr[0] == 0 && eaddr[1] == 0) || \
207 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff))
208 #define AE_RXD_VLAN(vtag) \
209 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9))
210 #define AE_TXD_VLAN(vtag) \
211 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08))
214 ae_probe(device_t dev)
216 uint16_t deviceid, vendorid;
219 vendorid = pci_get_vendor(dev);
220 deviceid = pci_get_device(dev);
223 * Search through the list of supported devs for matching one.
225 for (i = 0; i < AE_DEVS_COUNT; i++) {
226 if (vendorid == ae_devs[i].vendorid &&
227 deviceid == ae_devs[i].deviceid) {
228 device_set_desc(dev, ae_devs[i].name);
229 return (BUS_PROBE_DEFAULT);
236 ae_attach(device_t dev)
245 sc = device_get_softc(dev); /* Automatically allocated and zeroed
247 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
251 * Initialize mutexes and tasks.
253 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
254 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0);
255 TASK_INIT(&sc->int_task, 0, ae_int_task, sc);
256 TASK_INIT(&sc->link_task, 0, ae_link_task, sc);
258 pci_enable_busmaster(dev); /* Enable bus mastering. */
260 sc->spec_mem = ae_res_spec_mem;
263 * Allocate memory-mapped registers.
265 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem);
267 device_printf(dev, "could not allocate memory resources.\n");
273 * Retrieve PCI and chip revisions.
275 pcirev = pci_get_revid(dev);
276 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &
277 AE_MASTER_REVNUM_MASK;
279 device_printf(dev, "pci device revision: %#04x\n", pcirev);
280 device_printf(dev, "chip id: %#02x\n", chiprev);
282 nmsi = pci_msi_count(dev);
284 device_printf(dev, "MSI count: %d.\n", nmsi);
287 * Allocate interrupt resources.
289 if (msi_disable == 0 && nmsi == 1) {
290 error = pci_alloc_msi(dev, &nmsi);
292 device_printf(dev, "Using MSI messages.\n");
293 sc->spec_irq = ae_res_spec_msi;
294 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
296 device_printf(dev, "MSI allocation failed.\n");
298 pci_release_msi(dev);
300 sc->flags |= AE_FLAG_MSI;
304 if (sc->spec_irq == NULL) {
305 sc->spec_irq = ae_res_spec_irq;
306 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
308 device_printf(dev, "could not allocate IRQ resources.\n");
314 ae_init_tunables(sc);
316 ae_phy_reset(sc); /* Reset PHY. */
317 error = ae_reset(sc); /* Reset the controller itself. */
323 ae_retrieve_address(sc); /* Load MAC address. */
325 error = ae_alloc_rings(sc); /* Allocate ring buffers. */
329 ifp = sc->ifp = if_alloc(IFT_ETHER);
331 device_printf(dev, "could not allocate ifnet structure.\n");
337 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
339 ifp->if_ioctl = ae_ioctl;
340 ifp->if_start = ae_start;
341 ifp->if_init = ae_init;
342 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
343 ifp->if_hwassist = 0;
344 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
345 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
346 IFQ_SET_READY(&ifp->if_snd);
347 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
348 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
349 sc->flags |= AE_FLAG_PMG;
351 ifp->if_capenable = ifp->if_capabilities;
354 * Configure and attach MII bus.
356 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange,
357 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT,
360 device_printf(dev, "attaching PHYs failed\n");
364 ether_ifattach(ifp, sc->eaddr);
365 /* Tell the upper layer(s) we support long frames. */
366 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
369 * Create and run all helper tasks.
371 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK,
372 taskqueue_thread_enqueue, &sc->tq);
373 if (sc->tq == NULL) {
374 device_printf(dev, "could not create taskqueue.\n");
379 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
380 device_get_nameunit(sc->dev));
383 * Configure interrupt handlers.
385 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE,
386 ae_intr, NULL, sc, &sc->intrhand);
388 device_printf(dev, "could not set up interrupt handler.\n");
389 taskqueue_free(sc->tq);
402 #define AE_SYSCTL(stx, parent, name, desc, ptr) \
403 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc)
406 ae_init_tunables(ae_softc_t *sc)
408 struct sysctl_ctx_list *ctx;
409 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx;
410 struct ae_stats *ae_stats;
412 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
413 ae_stats = &sc->stats;
415 ctx = device_get_sysctl_ctx(sc->dev);
416 root = device_get_sysctl_tree(sc->dev);
417 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats",
418 CTLFLAG_RD, NULL, "ae statistics");
421 * Receiver statistcics.
423 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx",
424 CTLFLAG_RD, NULL, "Rx MAC statistics");
425 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast",
426 "broadcast frames", &ae_stats->rx_bcast);
427 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast",
428 "multicast frames", &ae_stats->rx_mcast);
429 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause",
430 "PAUSE frames", &ae_stats->rx_pause);
431 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control",
432 "control frames", &ae_stats->rx_ctrl);
433 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors",
434 "frames with CRC errors", &ae_stats->rx_crcerr);
435 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors",
436 "frames with invalid opcode", &ae_stats->rx_codeerr);
437 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt",
438 "runt frames", &ae_stats->rx_runt);
439 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag",
440 "fragmented frames", &ae_stats->rx_frag);
441 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors",
442 "frames with alignment errors", &ae_stats->rx_align);
443 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated",
444 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc);
447 * Receiver statistcics.
449 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx",
450 CTLFLAG_RD, NULL, "Tx MAC statistics");
451 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast",
452 "broadcast frames", &ae_stats->tx_bcast);
453 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast",
454 "multicast frames", &ae_stats->tx_mcast);
455 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause",
456 "PAUSE frames", &ae_stats->tx_pause);
457 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control",
458 "control frames", &ae_stats->tx_ctrl);
459 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers",
460 "deferrals occuried", &ae_stats->tx_defer);
461 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers",
462 "excessive deferrals occuried", &ae_stats->tx_excdefer);
463 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols",
464 "single collisions occuried", &ae_stats->tx_singlecol);
465 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols",
466 "multiple collisions occuried", &ae_stats->tx_multicol);
467 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols",
468 "late collisions occuried", &ae_stats->tx_latecol);
469 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts",
470 "transmit aborts due collisions", &ae_stats->tx_abortcol);
471 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns",
472 "Tx FIFO underruns", &ae_stats->tx_underrun);
476 ae_pcie_init(ae_softc_t *sc)
479 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT);
480 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT);
484 ae_phy_reset(ae_softc_t *sc)
487 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE);
488 DELAY(1000); /* XXX: pause(9) ? */
492 ae_reset(ae_softc_t *sc)
497 * Issue a soft reset.
499 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET);
500 bus_barrier(sc->mem[0], AE_MASTER_REG, 4,
501 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
504 * Wait for reset to complete.
506 for (i = 0; i < AE_RESET_TIMEOUT; i++) {
507 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)
511 if (i == AE_RESET_TIMEOUT) {
512 device_printf(sc->dev, "reset timeout.\n");
517 * Wait for everything to enter idle state.
519 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
520 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
524 if (i == AE_IDLE_TIMEOUT) {
525 device_printf(sc->dev, "could not enter idle state.\n");
536 sc = (ae_softc_t *)arg;
543 ae_phy_init(ae_softc_t *sc)
547 * Enable link status change interrupt.
551 AE_PHY_WRITE(sc, 18, 0xc00);
556 ae_init_locked(ae_softc_t *sc)
559 struct mii_data *mii;
560 uint8_t eaddr[ETHER_ADDR_LEN];
567 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
569 mii = device_get_softc(sc->miibus);
573 ae_pcie_init(sc); /* Initialize PCIE stuff. */
575 ae_powersave_disable(sc);
578 * Clear and disable interrupts.
580 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
583 * Set the MAC address.
585 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
586 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5];
587 AE_WRITE_4(sc, AE_EADDR0_REG, val);
588 val = eaddr[0] << 8 | eaddr[1];
589 AE_WRITE_4(sc, AE_EADDR1_REG, val);
591 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING);
592 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT);
593 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4);
595 * Set ring buffers base addresses.
597 addr = sc->dma_rxd_busaddr;
598 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr));
599 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
600 addr = sc->dma_txd_busaddr;
601 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
602 addr = sc->dma_txs_busaddr;
603 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr));
606 * Configure ring buffers sizes.
608 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT);
609 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4);
610 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT);
613 * Configure interframe gap parameters.
615 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) &
617 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) &
619 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) &
621 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) &
623 AE_WRITE_4(sc, AE_IFG_REG, val);
626 * Configure half-duplex operation.
628 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) &
630 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) &
631 AE_HDPX_RETRY_MASK) |
632 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) &
633 AE_HDPX_ABEBT_MASK) |
634 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) &
635 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN;
636 AE_WRITE_4(sc, AE_HDPX_REG, val);
639 * Configure interrupt moderate timer.
641 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT);
642 val = AE_READ_4(sc, AE_MASTER_REG);
643 val |= AE_MASTER_IMT_EN;
644 AE_WRITE_4(sc, AE_MASTER_REG, val);
647 * Configure interrupt clearing timer.
649 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT);
654 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
656 AE_WRITE_2(sc, AE_MTU_REG, val);
659 * Configure cut-through threshold.
661 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT);
664 * Configure flow control.
666 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7);
667 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) >
668 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) :
669 (AE_RXD_COUNT_DEFAULT / 12));
674 sc->txd_cur = sc->rxd_cur = 0;
675 sc->txs_ack = sc->txd_ack = 0;
677 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur);
678 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
680 sc->tx_inproc = 0; /* Number of packets the chip processes now. */
681 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */
686 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
687 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
690 * Check if everything is OK.
692 val = AE_READ_4(sc, AE_ISR_REG);
693 if ((val & AE_ISR_PHY_LINKDOWN) != 0) {
694 device_printf(sc->dev, "Initialization failed.\n");
699 * Clear interrupt status.
701 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff);
702 AE_WRITE_4(sc, AE_ISR_REG, 0x0);
707 val = AE_READ_4(sc, AE_MASTER_REG);
708 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT);
709 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT);
714 AE_WRITE_4(sc, AE_WOL_REG, 0);
719 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD |
720 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY |
721 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN |
722 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) |
723 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) &
724 AE_MAC_PREAMBLE_MASK);
725 AE_WRITE_4(sc, AE_MAC_REG, val);
736 val = AE_READ_4(sc, AE_MAC_REG);
737 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN);
739 sc->flags &= ~AE_FLAG_LINK;
740 mii_mediachg(mii); /* Switch to the current media. */
742 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
744 ifp->if_drv_flags |= IFF_DRV_RUNNING;
745 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
748 device_printf(sc->dev, "Initialization complete.\n");
755 ae_detach(device_t dev)
760 sc = device_get_softc(dev);
761 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
763 if (device_is_attached(dev)) {
765 sc->flags |= AE_FLAG_DETACH;
768 callout_drain(&sc->tick_ch);
769 taskqueue_drain(sc->tq, &sc->int_task);
770 taskqueue_drain(taskqueue_swi, &sc->link_task);
773 if (sc->tq != NULL) {
774 taskqueue_drain(sc->tq, &sc->int_task);
775 taskqueue_free(sc->tq);
778 if (sc->miibus != NULL) {
779 device_delete_child(dev, sc->miibus);
782 bus_generic_detach(sc->dev);
784 if (sc->intrhand != NULL) {
785 bus_teardown_intr(dev, sc->irq[0], sc->intrhand);
792 if (sc->spec_irq != NULL)
793 bus_release_resources(dev, sc->spec_irq, sc->irq);
794 if (sc->spec_mem != NULL)
795 bus_release_resources(dev, sc->spec_mem, sc->mem);
796 if ((sc->flags & AE_FLAG_MSI) != 0)
797 pci_release_msi(dev);
798 mtx_destroy(&sc->mtx);
804 ae_miibus_readreg(device_t dev, int phy, int reg)
810 sc = device_get_softc(dev);
811 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
814 * Locking is done in upper layers.
817 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
818 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE |
819 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK);
820 AE_WRITE_4(sc, AE_MDIO_REG, val);
823 * Wait for operation to complete.
825 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
827 val = AE_READ_4(sc, AE_MDIO_REG);
828 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
831 if (i == AE_MDIO_TIMEOUT) {
832 device_printf(sc->dev, "phy read timeout: %d.\n", reg);
835 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
839 ae_miibus_writereg(device_t dev, int phy, int reg, int val)
845 sc = device_get_softc(dev);
846 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
849 * Locking is done in upper layers.
852 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
853 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE |
854 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) |
855 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
856 AE_WRITE_4(sc, AE_MDIO_REG, aereg);
859 * Wait for operation to complete.
861 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
863 aereg = AE_READ_4(sc, AE_MDIO_REG);
864 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
867 if (i == AE_MDIO_TIMEOUT) {
868 device_printf(sc->dev, "phy write timeout: %d.\n", reg);
874 ae_miibus_statchg(device_t dev)
878 sc = device_get_softc(dev);
879 taskqueue_enqueue(taskqueue_swi, &sc->link_task);
883 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
886 struct mii_data *mii;
889 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
892 mii = device_get_softc(sc->miibus);
894 ifmr->ifm_status = mii->mii_media_status;
895 ifmr->ifm_active = mii->mii_media_active;
900 ae_mediachange(struct ifnet *ifp)
903 struct mii_data *mii;
904 struct mii_softc *mii_sc;
907 /* XXX: check IFF_UP ?? */
909 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
911 mii = device_get_softc(sc->miibus);
912 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list)
914 error = mii_mediachg(mii);
921 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc)
926 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__));
929 * Not sure why, but Linux does this.
931 val = AE_READ_4(sc, AE_SPICTL_REG);
932 if ((val & AE_SPICTL_VPD_EN) != 0) {
933 val &= ~AE_SPICTL_VPD_EN;
934 AE_WRITE_4(sc, AE_SPICTL_REG, val);
936 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc);
941 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word)
946 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */
949 * VPD registers start at offset 0x100. Read them.
951 val = 0x100 + reg * 4;
952 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) &
953 AE_VPD_CAP_ADDR_MASK);
954 for (i = 0; i < AE_VPD_TIMEOUT; i++) {
956 val = AE_READ_4(sc, AE_VPD_CAP_REG);
957 if ((val & AE_VPD_CAP_DONE) != 0)
960 if (i == AE_VPD_TIMEOUT) {
961 device_printf(sc->dev, "timeout reading VPD register %d.\n",
965 *word = AE_READ_4(sc, AE_VPD_DATA_REG);
970 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr)
972 uint32_t word, reg, val;
978 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
979 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__));
984 error = ae_check_eeprom_present(sc, &vpdc);
989 * Read the VPD configuration space.
990 * Each register is prefixed with signature,
991 * so we can check if it is valid.
993 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) {
994 error = ae_vpd_read_word(sc, i, &word);
1001 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG)
1003 reg = word >> AE_VPD_REG_SHIFT;
1004 i++; /* Move to the next word. */
1006 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG)
1009 error = ae_vpd_read_word(sc, i, &val);
1012 if (reg == AE_EADDR0_REG)
1022 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1023 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1025 device_printf(sc->dev,
1026 "VPD ethernet address registers are invalid.\n");
1033 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr)
1037 * BIOS is supposed to set this.
1039 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);
1040 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);
1041 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1043 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1045 device_printf(sc->dev,
1046 "Ethernet address registers are invalid.\n");
1053 ae_retrieve_address(ae_softc_t *sc)
1055 uint32_t eaddr[2] = {0, 0};
1061 error = ae_get_vpd_eaddr(sc, eaddr);
1063 error = ae_get_reg_eaddr(sc, eaddr);
1066 device_printf(sc->dev,
1067 "Generating random ethernet address.\n");
1068 eaddr[0] = arc4random();
1071 * Set OUI to ASUSTek COMPUTER INC.
1073 sc->eaddr[0] = 0x02; /* U/L bit set. */
1074 sc->eaddr[1] = 0x1f;
1075 sc->eaddr[2] = 0xc6;
1076 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1077 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1078 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1080 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff;
1081 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff;
1082 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff;
1083 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1084 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1085 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1090 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1092 bus_addr_t *addr = arg;
1096 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__,
1098 *addr = segs[0].ds_addr;
1102 ae_alloc_rings(ae_softc_t *sc)
1108 * Create parent DMA tag.
1110 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
1111 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1112 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1113 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1114 &sc->dma_parent_tag);
1116 device_printf(sc->dev, "could not creare parent DMA tag.\n");
1121 * Create DMA tag for TxD.
1123 error = bus_dma_tag_create(sc->dma_parent_tag,
1124 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1125 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1,
1126 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL,
1129 device_printf(sc->dev, "could not creare TxD DMA tag.\n");
1134 * Create DMA tag for TxS.
1136 error = bus_dma_tag_create(sc->dma_parent_tag,
1137 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1138 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1,
1139 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL,
1142 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1147 * Create DMA tag for RxD.
1149 error = bus_dma_tag_create(sc->dma_parent_tag,
1150 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1151 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1,
1152 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL,
1155 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1160 * Allocate TxD DMA memory.
1162 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base,
1163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1166 device_printf(sc->dev,
1167 "could not allocate DMA memory for TxD ring.\n");
1170 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base,
1171 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1172 if (error != 0 || busaddr == 0) {
1173 device_printf(sc->dev,
1174 "could not load DMA map for TxD ring.\n");
1177 sc->dma_txd_busaddr = busaddr;
1180 * Allocate TxS DMA memory.
1182 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base,
1183 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1186 device_printf(sc->dev,
1187 "could not allocate DMA memory for TxS ring.\n");
1190 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base,
1191 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1192 if (error != 0 || busaddr == 0) {
1193 device_printf(sc->dev,
1194 "could not load DMA map for TxS ring.\n");
1197 sc->dma_txs_busaddr = busaddr;
1200 * Allocate RxD DMA memory.
1202 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma,
1203 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1206 device_printf(sc->dev,
1207 "could not allocate DMA memory for RxD ring.\n");
1210 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map,
1211 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING,
1212 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1213 if (error != 0 || busaddr == 0) {
1214 device_printf(sc->dev,
1215 "could not load DMA map for RxD ring.\n");
1218 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING;
1219 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING);
1225 ae_dma_free(ae_softc_t *sc)
1228 if (sc->dma_txd_tag != NULL) {
1229 if (sc->dma_txd_busaddr != 0)
1230 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map);
1231 if (sc->txd_base != NULL)
1232 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base,
1234 bus_dma_tag_destroy(sc->dma_txd_tag);
1235 sc->dma_txd_tag = NULL;
1236 sc->txd_base = NULL;
1237 sc->dma_txd_busaddr = 0;
1239 if (sc->dma_txs_tag != NULL) {
1240 if (sc->dma_txs_busaddr != 0)
1241 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map);
1242 if (sc->txs_base != NULL)
1243 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base,
1245 bus_dma_tag_destroy(sc->dma_txs_tag);
1246 sc->dma_txs_tag = NULL;
1247 sc->txs_base = NULL;
1248 sc->dma_txs_busaddr = 0;
1250 if (sc->dma_rxd_tag != NULL) {
1251 if (sc->dma_rxd_busaddr != 0)
1252 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map);
1253 if (sc->rxd_base_dma != NULL)
1254 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma,
1256 bus_dma_tag_destroy(sc->dma_rxd_tag);
1257 sc->dma_rxd_tag = NULL;
1258 sc->rxd_base_dma = NULL;
1259 sc->dma_rxd_busaddr = 0;
1261 if (sc->dma_parent_tag != NULL) {
1262 bus_dma_tag_destroy(sc->dma_parent_tag);
1263 sc->dma_parent_tag = NULL;
1268 ae_shutdown(device_t dev)
1273 sc = device_get_softc(dev);
1274 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
1276 error = ae_suspend(dev);
1278 ae_powersave_enable(sc);
1284 ae_powersave_disable(ae_softc_t *sc)
1290 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1291 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1292 if (val & AE_PHY_DBG_POWERSAVE) {
1293 val &= ~AE_PHY_DBG_POWERSAVE;
1294 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val);
1300 ae_powersave_enable(ae_softc_t *sc)
1307 * XXX magic numbers.
1309 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1310 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1311 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000);
1312 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2);
1313 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000);
1314 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3);
1315 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0);
1319 ae_pm_init(ae_softc_t *sc)
1324 struct mii_data *mii;
1330 if ((sc->flags & AE_FLAG_PMG) == 0) {
1331 /* Disable WOL entirely. */
1332 AE_WRITE_4(sc, AE_WOL_REG, 0);
1337 * Configure WOL if enabled.
1339 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1340 mii = device_get_softc(sc->miibus);
1342 if ((mii->mii_media_status & IFM_AVALID) != 0 &&
1343 (mii->mii_media_status & IFM_ACTIVE) != 0) {
1344 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \
1350 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \
1351 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \
1352 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \
1353 AE_HALFBUF_MASK) | \
1354 ((AE_MAC_PREAMBLE_DEFAULT << \
1355 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \
1356 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN;
1357 if ((IFM_OPTIONS(mii->mii_media_active) & \
1359 val |= AE_MAC_FULL_DUPLEX;
1360 AE_WRITE_4(sc, AE_MAC_REG, val);
1362 } else { /* No link. */
1363 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \
1365 AE_WRITE_4(sc, AE_MAC_REG, 0);
1368 ae_powersave_enable(sc);
1372 * PCIE hacks. Magic numbers.
1374 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);
1375 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET;
1376 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val);
1377 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);
1378 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK;
1379 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val);
1384 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1385 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1386 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1387 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1388 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1389 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1394 ae_suspend(device_t dev)
1398 sc = device_get_softc(dev);
1409 ae_resume(device_t dev)
1413 sc = device_get_softc(dev);
1414 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1417 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */
1418 if ((sc->ifp->if_flags & IFF_UP) != 0)
1426 ae_tx_avail_size(ae_softc_t *sc)
1430 if (sc->txd_cur >= sc->txd_ack)
1431 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack);
1433 avail = sc->txd_ack - sc->txd_cur;
1439 ae_encap(ae_softc_t *sc, struct mbuf **m_head)
1443 unsigned int to_end;
1449 len = m0->m_pkthdr.len;
1451 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 ||
1452 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) {
1454 if_printf(sc->ifp, "No free Tx available.\n");
1459 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur);
1460 bzero(hdr, sizeof(*hdr));
1461 /* Skip header size. */
1462 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT;
1463 /* Space available to the end of the ring */
1464 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur;
1465 if (to_end >= len) {
1466 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur));
1468 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base +
1470 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base);
1474 * Set TxD flags and parameters.
1476 if ((m0->m_flags & M_VLANTAG) != 0) {
1477 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag));
1478 hdr->len = htole16(len | AE_TXD_INSERT_VTAG);
1480 hdr->len = htole16(len);
1484 * Set current TxD position and round up to a 4-byte boundary.
1486 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1487 if (sc->txd_cur == sc->txd_ack)
1488 sc->flags &= ~AE_FLAG_TXAVAIL;
1490 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur);
1494 * Update TxS position and check if there are empty TxS available.
1496 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE);
1497 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT;
1498 if (sc->txs_cur == sc->txs_ack)
1499 sc->flags &= ~AE_FLAG_TXAVAIL;
1502 * Synchronize DMA memory.
1504 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD |
1505 BUS_DMASYNC_PREWRITE);
1506 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1513 ae_start(struct ifnet *ifp)
1519 ae_start_locked(ifp);
1524 ae_start_locked(struct ifnet *ifp)
1532 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1536 if_printf(ifp, "Start called.\n");
1539 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1540 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0)
1544 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
1545 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
1547 break; /* Nothing to do. */
1549 error = ae_encap(sc, &m0);
1552 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
1553 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1555 if_printf(ifp, "Setting OACTIVE.\n");
1563 /* Bounce a copy of the frame to BPF. */
1564 ETHER_BPF_MTAP(ifp, m0);
1569 if (count > 0) { /* Something was dequeued. */
1570 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4);
1571 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */
1573 if_printf(ifp, "%d packets dequeued.\n", count);
1574 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur);
1580 ae_link_task(void *arg, int pending)
1583 struct mii_data *mii;
1587 sc = (ae_softc_t *)arg;
1588 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1592 mii = device_get_softc(sc->miibus);
1593 if (mii == NULL || ifp == NULL ||
1594 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1595 AE_UNLOCK(sc); /* XXX: could happen? */
1599 sc->flags &= ~AE_FLAG_LINK;
1600 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
1601 (IFM_AVALID | IFM_ACTIVE)) {
1602 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1605 sc->flags |= AE_FLAG_LINK;
1618 if ((sc->flags & AE_FLAG_LINK) != 0) {
1622 * Restart DMA engines.
1624 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
1625 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
1628 * Enable Rx and Tx MACs.
1630 val = AE_READ_4(sc, AE_MAC_REG);
1631 val |= AE_MAC_TX_EN | AE_MAC_RX_EN;
1632 AE_WRITE_4(sc, AE_MAC_REG, val);
1638 ae_stop_rxmac(ae_softc_t *sc)
1646 * Stop Rx MAC engine.
1648 val = AE_READ_4(sc, AE_MAC_REG);
1649 if ((val & AE_MAC_RX_EN) != 0) {
1650 val &= ~AE_MAC_RX_EN;
1651 AE_WRITE_4(sc, AE_MAC_REG, val);
1655 * Stop Rx DMA engine.
1657 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN)
1658 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0);
1661 * Wait for IDLE state.
1663 for (i = 0; i < AE_IDLE_TIMEOUT; i--) {
1664 val = AE_READ_4(sc, AE_IDLE_REG);
1665 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0)
1669 if (i == AE_IDLE_TIMEOUT)
1670 device_printf(sc->dev, "timed out while stopping Rx MAC.\n");
1674 ae_stop_txmac(ae_softc_t *sc)
1682 * Stop Tx MAC engine.
1684 val = AE_READ_4(sc, AE_MAC_REG);
1685 if ((val & AE_MAC_TX_EN) != 0) {
1686 val &= ~AE_MAC_TX_EN;
1687 AE_WRITE_4(sc, AE_MAC_REG, val);
1691 * Stop Tx DMA engine.
1693 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN)
1694 AE_WRITE_1(sc, AE_DMAREAD_REG, 0);
1697 * Wait for IDLE state.
1699 for (i = 0; i < AE_IDLE_TIMEOUT; i--) {
1700 val = AE_READ_4(sc, AE_IDLE_REG);
1701 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0)
1705 if (i == AE_IDLE_TIMEOUT)
1706 device_printf(sc->dev, "timed out while stopping Tx MAC.\n");
1710 ae_mac_config(ae_softc_t *sc)
1712 struct mii_data *mii;
1717 mii = device_get_softc(sc->miibus);
1718 val = AE_READ_4(sc, AE_MAC_REG);
1719 val &= ~AE_MAC_FULL_DUPLEX;
1720 /* XXX disable AE_MAC_TX_FLOW_EN? */
1722 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1723 val |= AE_MAC_FULL_DUPLEX;
1725 AE_WRITE_4(sc, AE_MAC_REG, val);
1734 sc = (ae_softc_t *)arg;
1735 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1737 val = AE_READ_4(sc, AE_ISR_REG);
1738 if (val == 0 || (val & AE_IMR_DEFAULT) == 0)
1739 return (FILTER_STRAY);
1741 /* Disable interrupts. */
1742 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE);
1744 /* Schedule interrupt processing. */
1745 taskqueue_enqueue(sc->tq, &sc->int_task);
1747 return (FILTER_HANDLED);
1751 ae_int_task(void *arg, int pending)
1757 sc = (ae_softc_t *)arg;
1763 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */
1770 * Clear interrupts and disable them.
1772 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE);
1775 if_printf(ifp, "Interrupt received: 0x%08x\n", val);
1778 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1779 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT |
1780 AE_ISR_PHY_LINKDOWN)) != 0) {
1781 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1786 if ((val & AE_ISR_TX_EVENT) != 0)
1788 if ((val & AE_ISR_RX_EVENT) != 0)
1791 * Re-enable interrupts.
1793 AE_WRITE_4(sc, AE_ISR_REG, 0);
1795 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) {
1796 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1797 ae_start_locked(ifp);
1805 ae_tx_intr(ae_softc_t *sc)
1817 if_printf(ifp, "Tx interrupt occuried.\n");
1821 * Syncronize DMA buffers.
1823 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1824 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1825 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1826 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1829 txs = sc->txs_base + sc->txs_ack;
1830 flags = le16toh(txs->flags);
1831 if ((flags & AE_TXS_UPDATE) == 0)
1833 txs->flags = htole16(flags & ~AE_TXS_UPDATE);
1835 ae_update_stats_tx(flags, &sc->stats);
1838 * Update TxS position.
1840 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT;
1841 sc->flags |= AE_FLAG_TXAVAIL;
1843 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack);
1844 if (txs->len != txd->len)
1845 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n",
1846 le16toh(txs->len), le16toh(txd->len));
1849 * Move txd ack and align on 4-byte boundary.
1851 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) +
1852 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1854 if ((flags & AE_TXS_SUCCESS) != 0)
1855 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1857 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1862 if ((sc->flags & AE_FLAG_TXAVAIL) != 0)
1863 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1864 if (sc->tx_inproc < 0) {
1865 if_printf(ifp, "Received stray Tx interrupt(s).\n");
1869 if (sc->tx_inproc == 0)
1870 sc->wd_timer = 0; /* Unarm watchdog. */
1873 * Syncronize DMA buffers.
1875 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1876 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1877 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1882 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
1892 flags = le16toh(rxd->flags);
1895 if_printf(ifp, "Rx interrupt occuried.\n");
1897 size = le16toh(rxd->len) - ETHER_CRC_LEN;
1898 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) {
1899 if_printf(ifp, "Runt frame received.");
1900 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1904 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL);
1906 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1910 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1911 (flags & AE_RXD_HAS_VLAN) != 0) {
1912 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan));
1913 m->m_flags |= M_VLANTAG;
1916 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1921 (*ifp->if_input)(ifp, m);
1926 ae_rx_intr(ae_softc_t *sc)
1933 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1940 * Syncronize DMA buffers.
1942 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1943 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1945 for (count = 0;; count++) {
1946 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur);
1947 flags = le16toh(rxd->flags);
1948 if ((flags & AE_RXD_UPDATE) == 0)
1950 rxd->flags = htole16(flags & ~AE_RXD_UPDATE);
1952 ae_update_stats_rx(flags, &sc->stats);
1955 * Update position index.
1957 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT;
1959 if ((flags & AE_RXD_SUCCESS) != 0)
1962 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1966 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1967 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1971 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
1976 ae_watchdog(ae_softc_t *sc)
1980 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1984 if (sc->wd_timer == 0 || --sc->wd_timer != 0)
1985 return; /* Noting to do. */
1987 if ((sc->flags & AE_FLAG_LINK) == 0)
1988 if_printf(ifp, "watchdog timeout (missed link).\n");
1990 if_printf(ifp, "watchdog timeout - resetting.\n");
1992 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1993 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1995 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1996 ae_start_locked(ifp);
2003 struct mii_data *mii;
2005 sc = (ae_softc_t *)arg;
2006 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2009 mii = device_get_softc(sc->miibus);
2011 ae_watchdog(sc); /* Watchdog check. */
2012 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
2016 ae_rxvlan(ae_softc_t *sc)
2023 val = AE_READ_4(sc, AE_MAC_REG);
2024 val &= ~AE_MAC_RMVLAN_EN;
2025 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2026 val |= AE_MAC_RMVLAN_EN;
2027 AE_WRITE_4(sc, AE_MAC_REG, val);
2031 ae_rxfilter(ae_softc_t *sc)
2034 struct ifmultiaddr *ifma;
2039 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2045 rxcfg = AE_READ_4(sc, AE_MAC_REG);
2046 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN);
2048 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2049 rxcfg |= AE_MAC_BCAST_EN;
2050 if ((ifp->if_flags & IFF_PROMISC) != 0)
2051 rxcfg |= AE_MAC_PROMISC_EN;
2052 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2053 rxcfg |= AE_MAC_MCAST_EN;
2056 * Wipe old settings.
2058 AE_WRITE_4(sc, AE_REG_MHT0, 0);
2059 AE_WRITE_4(sc, AE_REG_MHT1, 0);
2060 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2061 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff);
2062 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff);
2063 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2068 * Load multicast tables.
2070 bzero(mchash, sizeof(mchash));
2071 if_maddr_rlock(ifp);
2072 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2073 if (ifma->ifma_addr->sa_family != AF_LINK)
2075 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2076 ifma->ifma_addr), ETHER_ADDR_LEN);
2077 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2079 if_maddr_runlock(ifp);
2080 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]);
2081 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]);
2082 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2086 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2088 struct ae_softc *sc;
2090 struct mii_data *mii;
2094 ifr = (struct ifreq *)data;
2099 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU)
2101 else if (ifp->if_mtu != ifr->ifr_mtu) {
2103 ifp->if_mtu = ifr->ifr_mtu;
2104 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2105 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2113 if ((ifp->if_flags & IFF_UP) != 0) {
2114 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2115 if (((ifp->if_flags ^ sc->if_flags)
2116 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2119 if ((sc->flags & AE_FLAG_DETACH) == 0)
2123 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2126 sc->if_flags = ifp->if_flags;
2132 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2138 mii = device_get_softc(sc->miibus);
2139 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2143 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2144 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2145 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2146 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2149 VLAN_CAPABILITIES(ifp);
2153 error = ether_ioctl(ifp, cmd, data);
2160 ae_stop(ae_softc_t *sc)
2168 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2169 sc->flags &= ~AE_FLAG_LINK;
2170 sc->wd_timer = 0; /* Cancel watchdog. */
2171 callout_stop(&sc->tick_ch);
2174 * Clear and disable interrupts.
2176 AE_WRITE_4(sc, AE_IMR_REG, 0);
2177 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
2188 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN);
2189 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN);
2192 * Wait for everything to enter idle state.
2194 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
2195 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
2199 if (i == AE_IDLE_TIMEOUT)
2200 device_printf(sc->dev, "could not enter idle state in stop.\n");
2204 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats)
2207 if ((flags & AE_TXS_BCAST) != 0)
2209 if ((flags & AE_TXS_MCAST) != 0)
2211 if ((flags & AE_TXS_PAUSE) != 0)
2213 if ((flags & AE_TXS_CTRL) != 0)
2215 if ((flags & AE_TXS_DEFER) != 0)
2217 if ((flags & AE_TXS_EXCDEFER) != 0)
2218 stats->tx_excdefer++;
2219 if ((flags & AE_TXS_SINGLECOL) != 0)
2220 stats->tx_singlecol++;
2221 if ((flags & AE_TXS_MULTICOL) != 0)
2222 stats->tx_multicol++;
2223 if ((flags & AE_TXS_LATECOL) != 0)
2224 stats->tx_latecol++;
2225 if ((flags & AE_TXS_ABORTCOL) != 0)
2226 stats->tx_abortcol++;
2227 if ((flags & AE_TXS_UNDERRUN) != 0)
2228 stats->tx_underrun++;
2232 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats)
2235 if ((flags & AE_RXD_BCAST) != 0)
2237 if ((flags & AE_RXD_MCAST) != 0)
2239 if ((flags & AE_RXD_PAUSE) != 0)
2241 if ((flags & AE_RXD_CTRL) != 0)
2243 if ((flags & AE_RXD_CRCERR) != 0)
2245 if ((flags & AE_RXD_CODEERR) != 0)
2246 stats->rx_codeerr++;
2247 if ((flags & AE_RXD_RUNT) != 0)
2249 if ((flags & AE_RXD_FRAG) != 0)
2251 if ((flags & AE_RXD_TRUNC) != 0)
2253 if ((flags & AE_RXD_ALIGN) != 0)