2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * Driver for Attansic Technology Corp. L2 FastEthernet adapter.
29 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
41 #include <sys/malloc.h>
43 #include <sys/mutex.h>
45 #include <sys/module.h>
46 #include <sys/queue.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/sysctl.h>
50 #include <sys/taskqueue.h>
54 #include <net/if_var.h>
55 #include <net/if_arp.h>
56 #include <net/ethernet.h>
57 #include <net/if_dl.h>
58 #include <net/if_media.h>
59 #include <net/if_types.h>
60 #include <net/if_vlan_var.h>
62 #include <netinet/in.h>
63 #include <netinet/in_systm.h>
64 #include <netinet/ip.h>
65 #include <netinet/tcp.h>
67 #include <dev/mii/mii.h>
68 #include <dev/mii/miivar.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
72 #include <machine/bus.h>
74 #include "miibus_if.h"
80 * Devices supported by this driver.
82 static struct ae_dev {
87 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2,
88 "Attansic Technology Corp, L2 FastEthernet" },
90 #define AE_DEVS_COUNT nitems(ae_devs)
92 static struct resource_spec ae_res_spec_mem[] = {
93 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
96 static struct resource_spec ae_res_spec_irq[] = {
97 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
100 static struct resource_spec ae_res_spec_msi[] = {
101 { SYS_RES_IRQ, 1, RF_ACTIVE },
105 static int ae_probe(device_t dev);
106 static int ae_attach(device_t dev);
107 static void ae_pcie_init(ae_softc_t *sc);
108 static void ae_phy_reset(ae_softc_t *sc);
109 static void ae_phy_init(ae_softc_t *sc);
110 static int ae_reset(ae_softc_t *sc);
111 static void ae_init(void *arg);
112 static int ae_init_locked(ae_softc_t *sc);
113 static int ae_detach(device_t dev);
114 static int ae_miibus_readreg(device_t dev, int phy, int reg);
115 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val);
116 static void ae_miibus_statchg(device_t dev);
117 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
118 static int ae_mediachange(struct ifnet *ifp);
119 static void ae_retrieve_address(ae_softc_t *sc);
120 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs,
122 static int ae_alloc_rings(ae_softc_t *sc);
123 static void ae_dma_free(ae_softc_t *sc);
124 static int ae_shutdown(device_t dev);
125 static int ae_suspend(device_t dev);
126 static void ae_powersave_disable(ae_softc_t *sc);
127 static void ae_powersave_enable(ae_softc_t *sc);
128 static int ae_resume(device_t dev);
129 static unsigned int ae_tx_avail_size(ae_softc_t *sc);
130 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head);
131 static void ae_start(struct ifnet *ifp);
132 static void ae_start_locked(struct ifnet *ifp);
133 static void ae_link_task(void *arg, int pending);
134 static void ae_stop_rxmac(ae_softc_t *sc);
135 static void ae_stop_txmac(ae_softc_t *sc);
136 static void ae_mac_config(ae_softc_t *sc);
137 static int ae_intr(void *arg);
138 static void ae_int_task(void *arg, int pending);
139 static void ae_tx_intr(ae_softc_t *sc);
140 static void ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
141 static void ae_rx_intr(ae_softc_t *sc);
142 static void ae_watchdog(ae_softc_t *sc);
143 static void ae_tick(void *arg);
144 static void ae_rxfilter(ae_softc_t *sc);
145 static void ae_rxvlan(ae_softc_t *sc);
146 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
147 static void ae_stop(ae_softc_t *sc);
148 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc);
149 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word);
150 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr);
151 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr);
152 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats);
153 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats);
154 static void ae_init_tunables(ae_softc_t *sc);
156 static device_method_t ae_methods[] = {
157 /* Device interface. */
158 DEVMETHOD(device_probe, ae_probe),
159 DEVMETHOD(device_attach, ae_attach),
160 DEVMETHOD(device_detach, ae_detach),
161 DEVMETHOD(device_shutdown, ae_shutdown),
162 DEVMETHOD(device_suspend, ae_suspend),
163 DEVMETHOD(device_resume, ae_resume),
166 DEVMETHOD(miibus_readreg, ae_miibus_readreg),
167 DEVMETHOD(miibus_writereg, ae_miibus_writereg),
168 DEVMETHOD(miibus_statchg, ae_miibus_statchg),
172 static driver_t ae_driver = {
177 static devclass_t ae_devclass;
179 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0);
180 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0);
181 MODULE_DEPEND(ae, pci, 1, 1, 1);
182 MODULE_DEPEND(ae, ether, 1, 1, 1);
183 MODULE_DEPEND(ae, miibus, 1, 1, 1);
188 static int msi_disable = 0;
189 TUNABLE_INT("hw.ae.msi_disable", &msi_disable);
191 #define AE_READ_4(sc, reg) \
192 bus_read_4((sc)->mem[0], (reg))
193 #define AE_READ_2(sc, reg) \
194 bus_read_2((sc)->mem[0], (reg))
195 #define AE_READ_1(sc, reg) \
196 bus_read_1((sc)->mem[0], (reg))
197 #define AE_WRITE_4(sc, reg, val) \
198 bus_write_4((sc)->mem[0], (reg), (val))
199 #define AE_WRITE_2(sc, reg, val) \
200 bus_write_2((sc)->mem[0], (reg), (val))
201 #define AE_WRITE_1(sc, reg, val) \
202 bus_write_1((sc)->mem[0], (reg), (val))
203 #define AE_PHY_READ(sc, reg) \
204 ae_miibus_readreg(sc->dev, 0, reg)
205 #define AE_PHY_WRITE(sc, reg, val) \
206 ae_miibus_writereg(sc->dev, 0, reg, val)
207 #define AE_CHECK_EADDR_VALID(eaddr) \
208 ((eaddr[0] == 0 && eaddr[1] == 0) || \
209 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff))
210 #define AE_RXD_VLAN(vtag) \
211 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9))
212 #define AE_TXD_VLAN(vtag) \
213 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08))
216 ae_probe(device_t dev)
218 uint16_t deviceid, vendorid;
221 vendorid = pci_get_vendor(dev);
222 deviceid = pci_get_device(dev);
225 * Search through the list of supported devs for matching one.
227 for (i = 0; i < AE_DEVS_COUNT; i++) {
228 if (vendorid == ae_devs[i].vendorid &&
229 deviceid == ae_devs[i].deviceid) {
230 device_set_desc(dev, ae_devs[i].name);
231 return (BUS_PROBE_DEFAULT);
238 ae_attach(device_t dev)
247 sc = device_get_softc(dev); /* Automatically allocated and zeroed
249 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
253 * Initialize mutexes and tasks.
255 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
256 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0);
257 TASK_INIT(&sc->int_task, 0, ae_int_task, sc);
258 TASK_INIT(&sc->link_task, 0, ae_link_task, sc);
260 pci_enable_busmaster(dev); /* Enable bus mastering. */
262 sc->spec_mem = ae_res_spec_mem;
265 * Allocate memory-mapped registers.
267 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem);
269 device_printf(dev, "could not allocate memory resources.\n");
275 * Retrieve PCI and chip revisions.
277 pcirev = pci_get_revid(dev);
278 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &
279 AE_MASTER_REVNUM_MASK;
281 device_printf(dev, "pci device revision: %#04x\n", pcirev);
282 device_printf(dev, "chip id: %#02x\n", chiprev);
284 nmsi = pci_msi_count(dev);
286 device_printf(dev, "MSI count: %d.\n", nmsi);
289 * Allocate interrupt resources.
291 if (msi_disable == 0 && nmsi == 1) {
292 error = pci_alloc_msi(dev, &nmsi);
294 device_printf(dev, "Using MSI messages.\n");
295 sc->spec_irq = ae_res_spec_msi;
296 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
298 device_printf(dev, "MSI allocation failed.\n");
300 pci_release_msi(dev);
302 sc->flags |= AE_FLAG_MSI;
306 if (sc->spec_irq == NULL) {
307 sc->spec_irq = ae_res_spec_irq;
308 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
310 device_printf(dev, "could not allocate IRQ resources.\n");
316 ae_init_tunables(sc);
318 ae_phy_reset(sc); /* Reset PHY. */
319 error = ae_reset(sc); /* Reset the controller itself. */
325 ae_retrieve_address(sc); /* Load MAC address. */
327 error = ae_alloc_rings(sc); /* Allocate ring buffers. */
331 ifp = sc->ifp = if_alloc(IFT_ETHER);
333 device_printf(dev, "could not allocate ifnet structure.\n");
339 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
340 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
341 ifp->if_ioctl = ae_ioctl;
342 ifp->if_start = ae_start;
343 ifp->if_init = ae_init;
344 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
345 ifp->if_hwassist = 0;
346 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
347 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
348 IFQ_SET_READY(&ifp->if_snd);
349 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
350 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
351 sc->flags |= AE_FLAG_PMG;
353 ifp->if_capenable = ifp->if_capabilities;
356 * Configure and attach MII bus.
358 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange,
359 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT,
362 device_printf(dev, "attaching PHYs failed\n");
366 ether_ifattach(ifp, sc->eaddr);
367 /* Tell the upper layer(s) we support long frames. */
368 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
371 * Create and run all helper tasks.
373 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK,
374 taskqueue_thread_enqueue, &sc->tq);
375 if (sc->tq == NULL) {
376 device_printf(dev, "could not create taskqueue.\n");
381 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
382 device_get_nameunit(sc->dev));
385 * Configure interrupt handlers.
387 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE,
388 ae_intr, NULL, sc, &sc->intrhand);
390 device_printf(dev, "could not set up interrupt handler.\n");
391 taskqueue_free(sc->tq);
404 #define AE_SYSCTL(stx, parent, name, desc, ptr) \
405 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc)
408 ae_init_tunables(ae_softc_t *sc)
410 struct sysctl_ctx_list *ctx;
411 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx;
412 struct ae_stats *ae_stats;
414 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
415 ae_stats = &sc->stats;
417 ctx = device_get_sysctl_ctx(sc->dev);
418 root = device_get_sysctl_tree(sc->dev);
419 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats",
420 CTLFLAG_RD, NULL, "ae statistics");
423 * Receiver statistcics.
425 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx",
426 CTLFLAG_RD, NULL, "Rx MAC statistics");
427 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast",
428 "broadcast frames", &ae_stats->rx_bcast);
429 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast",
430 "multicast frames", &ae_stats->rx_mcast);
431 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause",
432 "PAUSE frames", &ae_stats->rx_pause);
433 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control",
434 "control frames", &ae_stats->rx_ctrl);
435 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors",
436 "frames with CRC errors", &ae_stats->rx_crcerr);
437 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors",
438 "frames with invalid opcode", &ae_stats->rx_codeerr);
439 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt",
440 "runt frames", &ae_stats->rx_runt);
441 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag",
442 "fragmented frames", &ae_stats->rx_frag);
443 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors",
444 "frames with alignment errors", &ae_stats->rx_align);
445 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated",
446 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc);
449 * Receiver statistcics.
451 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx",
452 CTLFLAG_RD, NULL, "Tx MAC statistics");
453 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast",
454 "broadcast frames", &ae_stats->tx_bcast);
455 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast",
456 "multicast frames", &ae_stats->tx_mcast);
457 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause",
458 "PAUSE frames", &ae_stats->tx_pause);
459 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control",
460 "control frames", &ae_stats->tx_ctrl);
461 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers",
462 "deferrals occuried", &ae_stats->tx_defer);
463 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers",
464 "excessive deferrals occuried", &ae_stats->tx_excdefer);
465 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols",
466 "single collisions occuried", &ae_stats->tx_singlecol);
467 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols",
468 "multiple collisions occuried", &ae_stats->tx_multicol);
469 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols",
470 "late collisions occuried", &ae_stats->tx_latecol);
471 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts",
472 "transmit aborts due collisions", &ae_stats->tx_abortcol);
473 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns",
474 "Tx FIFO underruns", &ae_stats->tx_underrun);
478 ae_pcie_init(ae_softc_t *sc)
481 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT);
482 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT);
486 ae_phy_reset(ae_softc_t *sc)
489 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE);
490 DELAY(1000); /* XXX: pause(9) ? */
494 ae_reset(ae_softc_t *sc)
499 * Issue a soft reset.
501 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET);
502 bus_barrier(sc->mem[0], AE_MASTER_REG, 4,
503 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
506 * Wait for reset to complete.
508 for (i = 0; i < AE_RESET_TIMEOUT; i++) {
509 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)
513 if (i == AE_RESET_TIMEOUT) {
514 device_printf(sc->dev, "reset timeout.\n");
519 * Wait for everything to enter idle state.
521 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
522 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
526 if (i == AE_IDLE_TIMEOUT) {
527 device_printf(sc->dev, "could not enter idle state.\n");
538 sc = (ae_softc_t *)arg;
545 ae_phy_init(ae_softc_t *sc)
549 * Enable link status change interrupt.
553 AE_PHY_WRITE(sc, 18, 0xc00);
558 ae_init_locked(ae_softc_t *sc)
561 struct mii_data *mii;
562 uint8_t eaddr[ETHER_ADDR_LEN];
569 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
571 mii = device_get_softc(sc->miibus);
575 ae_pcie_init(sc); /* Initialize PCIE stuff. */
577 ae_powersave_disable(sc);
580 * Clear and disable interrupts.
582 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
585 * Set the MAC address.
587 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
588 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5];
589 AE_WRITE_4(sc, AE_EADDR0_REG, val);
590 val = eaddr[0] << 8 | eaddr[1];
591 AE_WRITE_4(sc, AE_EADDR1_REG, val);
593 bzero(sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING);
594 bzero(sc->txd_base, AE_TXD_BUFSIZE_DEFAULT);
595 bzero(sc->txs_base, AE_TXS_COUNT_DEFAULT * 4);
597 * Set ring buffers base addresses.
599 addr = sc->dma_rxd_busaddr;
600 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr));
601 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
602 addr = sc->dma_txd_busaddr;
603 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
604 addr = sc->dma_txs_busaddr;
605 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr));
608 * Configure ring buffers sizes.
610 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT);
611 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4);
612 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT);
615 * Configure interframe gap parameters.
617 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) &
619 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) &
621 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) &
623 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) &
625 AE_WRITE_4(sc, AE_IFG_REG, val);
628 * Configure half-duplex operation.
630 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) &
632 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) &
633 AE_HDPX_RETRY_MASK) |
634 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) &
635 AE_HDPX_ABEBT_MASK) |
636 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) &
637 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN;
638 AE_WRITE_4(sc, AE_HDPX_REG, val);
641 * Configure interrupt moderate timer.
643 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT);
644 val = AE_READ_4(sc, AE_MASTER_REG);
645 val |= AE_MASTER_IMT_EN;
646 AE_WRITE_4(sc, AE_MASTER_REG, val);
649 * Configure interrupt clearing timer.
651 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT);
656 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
658 AE_WRITE_2(sc, AE_MTU_REG, val);
661 * Configure cut-through threshold.
663 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT);
666 * Configure flow control.
668 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7);
669 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) >
670 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) :
671 (AE_RXD_COUNT_DEFAULT / 12));
676 sc->txd_cur = sc->rxd_cur = 0;
677 sc->txs_ack = sc->txd_ack = 0;
679 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur);
680 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
682 sc->tx_inproc = 0; /* Number of packets the chip processes now. */
683 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */
688 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
689 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
692 * Check if everything is OK.
694 val = AE_READ_4(sc, AE_ISR_REG);
695 if ((val & AE_ISR_PHY_LINKDOWN) != 0) {
696 device_printf(sc->dev, "Initialization failed.\n");
701 * Clear interrupt status.
703 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff);
704 AE_WRITE_4(sc, AE_ISR_REG, 0x0);
709 val = AE_READ_4(sc, AE_MASTER_REG);
710 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT);
711 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT);
716 AE_WRITE_4(sc, AE_WOL_REG, 0);
721 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD |
722 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY |
723 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN |
724 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) |
725 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) &
726 AE_MAC_PREAMBLE_MASK);
727 AE_WRITE_4(sc, AE_MAC_REG, val);
738 val = AE_READ_4(sc, AE_MAC_REG);
739 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN);
741 sc->flags &= ~AE_FLAG_LINK;
742 mii_mediachg(mii); /* Switch to the current media. */
744 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
746 ifp->if_drv_flags |= IFF_DRV_RUNNING;
747 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
750 device_printf(sc->dev, "Initialization complete.\n");
757 ae_detach(device_t dev)
762 sc = device_get_softc(dev);
763 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
765 if (device_is_attached(dev)) {
767 sc->flags |= AE_FLAG_DETACH;
770 callout_drain(&sc->tick_ch);
771 taskqueue_drain(sc->tq, &sc->int_task);
772 taskqueue_drain(taskqueue_swi, &sc->link_task);
775 if (sc->tq != NULL) {
776 taskqueue_drain(sc->tq, &sc->int_task);
777 taskqueue_free(sc->tq);
780 if (sc->miibus != NULL) {
781 device_delete_child(dev, sc->miibus);
784 bus_generic_detach(sc->dev);
786 if (sc->intrhand != NULL) {
787 bus_teardown_intr(dev, sc->irq[0], sc->intrhand);
794 if (sc->spec_irq != NULL)
795 bus_release_resources(dev, sc->spec_irq, sc->irq);
796 if (sc->spec_mem != NULL)
797 bus_release_resources(dev, sc->spec_mem, sc->mem);
798 if ((sc->flags & AE_FLAG_MSI) != 0)
799 pci_release_msi(dev);
800 mtx_destroy(&sc->mtx);
806 ae_miibus_readreg(device_t dev, int phy, int reg)
812 sc = device_get_softc(dev);
813 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
816 * Locking is done in upper layers.
819 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
820 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE |
821 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK);
822 AE_WRITE_4(sc, AE_MDIO_REG, val);
825 * Wait for operation to complete.
827 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
829 val = AE_READ_4(sc, AE_MDIO_REG);
830 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
833 if (i == AE_MDIO_TIMEOUT) {
834 device_printf(sc->dev, "phy read timeout: %d.\n", reg);
837 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
841 ae_miibus_writereg(device_t dev, int phy, int reg, int val)
847 sc = device_get_softc(dev);
848 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
851 * Locking is done in upper layers.
854 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
855 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE |
856 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) |
857 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
858 AE_WRITE_4(sc, AE_MDIO_REG, aereg);
861 * Wait for operation to complete.
863 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
865 aereg = AE_READ_4(sc, AE_MDIO_REG);
866 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
869 if (i == AE_MDIO_TIMEOUT) {
870 device_printf(sc->dev, "phy write timeout: %d.\n", reg);
876 ae_miibus_statchg(device_t dev)
880 sc = device_get_softc(dev);
881 taskqueue_enqueue(taskqueue_swi, &sc->link_task);
885 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
888 struct mii_data *mii;
891 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
894 mii = device_get_softc(sc->miibus);
896 ifmr->ifm_status = mii->mii_media_status;
897 ifmr->ifm_active = mii->mii_media_active;
902 ae_mediachange(struct ifnet *ifp)
905 struct mii_data *mii;
906 struct mii_softc *mii_sc;
909 /* XXX: check IFF_UP ?? */
911 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
913 mii = device_get_softc(sc->miibus);
914 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list)
916 error = mii_mediachg(mii);
923 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc)
928 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__));
931 * Not sure why, but Linux does this.
933 val = AE_READ_4(sc, AE_SPICTL_REG);
934 if ((val & AE_SPICTL_VPD_EN) != 0) {
935 val &= ~AE_SPICTL_VPD_EN;
936 AE_WRITE_4(sc, AE_SPICTL_REG, val);
938 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc);
943 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word)
948 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */
951 * VPD registers start at offset 0x100. Read them.
953 val = 0x100 + reg * 4;
954 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) &
955 AE_VPD_CAP_ADDR_MASK);
956 for (i = 0; i < AE_VPD_TIMEOUT; i++) {
958 val = AE_READ_4(sc, AE_VPD_CAP_REG);
959 if ((val & AE_VPD_CAP_DONE) != 0)
962 if (i == AE_VPD_TIMEOUT) {
963 device_printf(sc->dev, "timeout reading VPD register %d.\n",
967 *word = AE_READ_4(sc, AE_VPD_DATA_REG);
972 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr)
974 uint32_t word, reg, val;
980 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
981 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__));
986 error = ae_check_eeprom_present(sc, &vpdc);
991 * Read the VPD configuration space.
992 * Each register is prefixed with signature,
993 * so we can check if it is valid.
995 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) {
996 error = ae_vpd_read_word(sc, i, &word);
1003 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG)
1005 reg = word >> AE_VPD_REG_SHIFT;
1006 i++; /* Move to the next word. */
1008 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG)
1011 error = ae_vpd_read_word(sc, i, &val);
1014 if (reg == AE_EADDR0_REG)
1024 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1025 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1027 device_printf(sc->dev,
1028 "VPD ethernet address registers are invalid.\n");
1035 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr)
1039 * BIOS is supposed to set this.
1041 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);
1042 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);
1043 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1045 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1047 device_printf(sc->dev,
1048 "Ethernet address registers are invalid.\n");
1055 ae_retrieve_address(ae_softc_t *sc)
1057 uint32_t eaddr[2] = {0, 0};
1063 error = ae_get_vpd_eaddr(sc, eaddr);
1065 error = ae_get_reg_eaddr(sc, eaddr);
1068 device_printf(sc->dev,
1069 "Generating random ethernet address.\n");
1070 eaddr[0] = arc4random();
1073 * Set OUI to ASUSTek COMPUTER INC.
1075 sc->eaddr[0] = 0x02; /* U/L bit set. */
1076 sc->eaddr[1] = 0x1f;
1077 sc->eaddr[2] = 0xc6;
1078 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1079 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1080 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1082 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff;
1083 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff;
1084 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff;
1085 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1086 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1087 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1092 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1094 bus_addr_t *addr = arg;
1098 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__,
1100 *addr = segs[0].ds_addr;
1104 ae_alloc_rings(ae_softc_t *sc)
1110 * Create parent DMA tag.
1112 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
1113 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1114 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1115 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1116 &sc->dma_parent_tag);
1118 device_printf(sc->dev, "could not creare parent DMA tag.\n");
1123 * Create DMA tag for TxD.
1125 error = bus_dma_tag_create(sc->dma_parent_tag,
1126 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1127 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1,
1128 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL,
1131 device_printf(sc->dev, "could not creare TxD DMA tag.\n");
1136 * Create DMA tag for TxS.
1138 error = bus_dma_tag_create(sc->dma_parent_tag,
1139 8, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1140 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1,
1141 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL,
1144 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1149 * Create DMA tag for RxD.
1151 error = bus_dma_tag_create(sc->dma_parent_tag,
1152 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1153 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 1,
1154 AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING, 0, NULL, NULL,
1157 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1162 * Allocate TxD DMA memory.
1164 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base,
1165 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1168 device_printf(sc->dev,
1169 "could not allocate DMA memory for TxD ring.\n");
1172 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base,
1173 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1174 if (error != 0 || busaddr == 0) {
1175 device_printf(sc->dev,
1176 "could not load DMA map for TxD ring.\n");
1179 sc->dma_txd_busaddr = busaddr;
1182 * Allocate TxS DMA memory.
1184 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base,
1185 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1188 device_printf(sc->dev,
1189 "could not allocate DMA memory for TxS ring.\n");
1192 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base,
1193 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1194 if (error != 0 || busaddr == 0) {
1195 device_printf(sc->dev,
1196 "could not load DMA map for TxS ring.\n");
1199 sc->dma_txs_busaddr = busaddr;
1202 * Allocate RxD DMA memory.
1204 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma,
1205 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1208 device_printf(sc->dev,
1209 "could not allocate DMA memory for RxD ring.\n");
1212 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map,
1213 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + AE_RXD_PADDING,
1214 ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1215 if (error != 0 || busaddr == 0) {
1216 device_printf(sc->dev,
1217 "could not load DMA map for RxD ring.\n");
1220 sc->dma_rxd_busaddr = busaddr + AE_RXD_PADDING;
1221 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + AE_RXD_PADDING);
1227 ae_dma_free(ae_softc_t *sc)
1230 if (sc->dma_txd_tag != NULL) {
1231 if (sc->dma_txd_busaddr != 0)
1232 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map);
1233 if (sc->txd_base != NULL)
1234 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base,
1236 bus_dma_tag_destroy(sc->dma_txd_tag);
1237 sc->dma_txd_tag = NULL;
1238 sc->txd_base = NULL;
1239 sc->dma_txd_busaddr = 0;
1241 if (sc->dma_txs_tag != NULL) {
1242 if (sc->dma_txs_busaddr != 0)
1243 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map);
1244 if (sc->txs_base != NULL)
1245 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base,
1247 bus_dma_tag_destroy(sc->dma_txs_tag);
1248 sc->dma_txs_tag = NULL;
1249 sc->txs_base = NULL;
1250 sc->dma_txs_busaddr = 0;
1252 if (sc->dma_rxd_tag != NULL) {
1253 if (sc->dma_rxd_busaddr != 0)
1254 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map);
1255 if (sc->rxd_base_dma != NULL)
1256 bus_dmamem_free(sc->dma_rxd_tag, sc->rxd_base_dma,
1258 bus_dma_tag_destroy(sc->dma_rxd_tag);
1259 sc->dma_rxd_tag = NULL;
1260 sc->rxd_base_dma = NULL;
1261 sc->dma_rxd_busaddr = 0;
1263 if (sc->dma_parent_tag != NULL) {
1264 bus_dma_tag_destroy(sc->dma_parent_tag);
1265 sc->dma_parent_tag = NULL;
1270 ae_shutdown(device_t dev)
1275 sc = device_get_softc(dev);
1276 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
1278 error = ae_suspend(dev);
1280 ae_powersave_enable(sc);
1286 ae_powersave_disable(ae_softc_t *sc)
1292 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1293 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1294 if (val & AE_PHY_DBG_POWERSAVE) {
1295 val &= ~AE_PHY_DBG_POWERSAVE;
1296 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val);
1302 ae_powersave_enable(ae_softc_t *sc)
1309 * XXX magic numbers.
1311 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1312 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1313 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000);
1314 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2);
1315 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000);
1316 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3);
1317 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0);
1321 ae_pm_init(ae_softc_t *sc)
1326 struct mii_data *mii;
1332 if ((sc->flags & AE_FLAG_PMG) == 0) {
1333 /* Disable WOL entirely. */
1334 AE_WRITE_4(sc, AE_WOL_REG, 0);
1339 * Configure WOL if enabled.
1341 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1342 mii = device_get_softc(sc->miibus);
1344 if ((mii->mii_media_status & IFM_AVALID) != 0 &&
1345 (mii->mii_media_status & IFM_ACTIVE) != 0) {
1346 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \
1352 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \
1353 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \
1354 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \
1355 AE_HALFBUF_MASK) | \
1356 ((AE_MAC_PREAMBLE_DEFAULT << \
1357 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \
1358 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN;
1359 if ((IFM_OPTIONS(mii->mii_media_active) & \
1361 val |= AE_MAC_FULL_DUPLEX;
1362 AE_WRITE_4(sc, AE_MAC_REG, val);
1364 } else { /* No link. */
1365 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \
1367 AE_WRITE_4(sc, AE_MAC_REG, 0);
1370 ae_powersave_enable(sc);
1374 * PCIE hacks. Magic numbers.
1376 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);
1377 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET;
1378 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val);
1379 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);
1380 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK;
1381 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val);
1386 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1387 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1388 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1389 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1390 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1391 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1396 ae_suspend(device_t dev)
1400 sc = device_get_softc(dev);
1411 ae_resume(device_t dev)
1415 sc = device_get_softc(dev);
1416 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1419 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */
1420 if ((sc->ifp->if_flags & IFF_UP) != 0)
1428 ae_tx_avail_size(ae_softc_t *sc)
1432 if (sc->txd_cur >= sc->txd_ack)
1433 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack);
1435 avail = sc->txd_ack - sc->txd_cur;
1441 ae_encap(ae_softc_t *sc, struct mbuf **m_head)
1445 unsigned int to_end;
1451 len = m0->m_pkthdr.len;
1453 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 ||
1454 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) {
1456 if_printf(sc->ifp, "No free Tx available.\n");
1461 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur);
1462 bzero(hdr, sizeof(*hdr));
1463 /* Skip header size. */
1464 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT;
1465 /* Space available to the end of the ring */
1466 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur;
1467 if (to_end >= len) {
1468 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur));
1470 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base +
1472 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base);
1476 * Set TxD flags and parameters.
1478 if ((m0->m_flags & M_VLANTAG) != 0) {
1479 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag));
1480 hdr->len = htole16(len | AE_TXD_INSERT_VTAG);
1482 hdr->len = htole16(len);
1486 * Set current TxD position and round up to a 4-byte boundary.
1488 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1489 if (sc->txd_cur == sc->txd_ack)
1490 sc->flags &= ~AE_FLAG_TXAVAIL;
1492 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur);
1496 * Update TxS position and check if there are empty TxS available.
1498 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE);
1499 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT;
1500 if (sc->txs_cur == sc->txs_ack)
1501 sc->flags &= ~AE_FLAG_TXAVAIL;
1504 * Synchronize DMA memory.
1506 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD |
1507 BUS_DMASYNC_PREWRITE);
1508 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1509 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1515 ae_start(struct ifnet *ifp)
1521 ae_start_locked(ifp);
1526 ae_start_locked(struct ifnet *ifp)
1534 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1538 if_printf(ifp, "Start called.\n");
1541 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1542 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0)
1546 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
1547 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
1549 break; /* Nothing to do. */
1551 error = ae_encap(sc, &m0);
1554 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
1555 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1557 if_printf(ifp, "Setting OACTIVE.\n");
1565 /* Bounce a copy of the frame to BPF. */
1566 ETHER_BPF_MTAP(ifp, m0);
1571 if (count > 0) { /* Something was dequeued. */
1572 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4);
1573 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */
1575 if_printf(ifp, "%d packets dequeued.\n", count);
1576 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur);
1582 ae_link_task(void *arg, int pending)
1585 struct mii_data *mii;
1589 sc = (ae_softc_t *)arg;
1590 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1594 mii = device_get_softc(sc->miibus);
1595 if (mii == NULL || ifp == NULL ||
1596 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1597 AE_UNLOCK(sc); /* XXX: could happen? */
1601 sc->flags &= ~AE_FLAG_LINK;
1602 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
1603 (IFM_AVALID | IFM_ACTIVE)) {
1604 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1607 sc->flags |= AE_FLAG_LINK;
1620 if ((sc->flags & AE_FLAG_LINK) != 0) {
1624 * Restart DMA engines.
1626 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
1627 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
1630 * Enable Rx and Tx MACs.
1632 val = AE_READ_4(sc, AE_MAC_REG);
1633 val |= AE_MAC_TX_EN | AE_MAC_RX_EN;
1634 AE_WRITE_4(sc, AE_MAC_REG, val);
1640 ae_stop_rxmac(ae_softc_t *sc)
1648 * Stop Rx MAC engine.
1650 val = AE_READ_4(sc, AE_MAC_REG);
1651 if ((val & AE_MAC_RX_EN) != 0) {
1652 val &= ~AE_MAC_RX_EN;
1653 AE_WRITE_4(sc, AE_MAC_REG, val);
1657 * Stop Rx DMA engine.
1659 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN)
1660 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0);
1663 * Wait for IDLE state.
1665 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
1666 val = AE_READ_4(sc, AE_IDLE_REG);
1667 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0)
1671 if (i == AE_IDLE_TIMEOUT)
1672 device_printf(sc->dev, "timed out while stopping Rx MAC.\n");
1676 ae_stop_txmac(ae_softc_t *sc)
1684 * Stop Tx MAC engine.
1686 val = AE_READ_4(sc, AE_MAC_REG);
1687 if ((val & AE_MAC_TX_EN) != 0) {
1688 val &= ~AE_MAC_TX_EN;
1689 AE_WRITE_4(sc, AE_MAC_REG, val);
1693 * Stop Tx DMA engine.
1695 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN)
1696 AE_WRITE_1(sc, AE_DMAREAD_REG, 0);
1699 * Wait for IDLE state.
1701 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
1702 val = AE_READ_4(sc, AE_IDLE_REG);
1703 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0)
1707 if (i == AE_IDLE_TIMEOUT)
1708 device_printf(sc->dev, "timed out while stopping Tx MAC.\n");
1712 ae_mac_config(ae_softc_t *sc)
1714 struct mii_data *mii;
1719 mii = device_get_softc(sc->miibus);
1720 val = AE_READ_4(sc, AE_MAC_REG);
1721 val &= ~AE_MAC_FULL_DUPLEX;
1722 /* XXX disable AE_MAC_TX_FLOW_EN? */
1724 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1725 val |= AE_MAC_FULL_DUPLEX;
1727 AE_WRITE_4(sc, AE_MAC_REG, val);
1736 sc = (ae_softc_t *)arg;
1737 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1739 val = AE_READ_4(sc, AE_ISR_REG);
1740 if (val == 0 || (val & AE_IMR_DEFAULT) == 0)
1741 return (FILTER_STRAY);
1743 /* Disable interrupts. */
1744 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE);
1746 /* Schedule interrupt processing. */
1747 taskqueue_enqueue(sc->tq, &sc->int_task);
1749 return (FILTER_HANDLED);
1753 ae_int_task(void *arg, int pending)
1759 sc = (ae_softc_t *)arg;
1765 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */
1772 * Clear interrupts and disable them.
1774 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE);
1777 if_printf(ifp, "Interrupt received: 0x%08x\n", val);
1780 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1781 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT |
1782 AE_ISR_PHY_LINKDOWN)) != 0) {
1783 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1788 if ((val & AE_ISR_TX_EVENT) != 0)
1790 if ((val & AE_ISR_RX_EVENT) != 0)
1793 * Re-enable interrupts.
1795 AE_WRITE_4(sc, AE_ISR_REG, 0);
1797 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) {
1798 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1799 ae_start_locked(ifp);
1807 ae_tx_intr(ae_softc_t *sc)
1819 if_printf(ifp, "Tx interrupt occuried.\n");
1823 * Syncronize DMA buffers.
1825 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1826 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1827 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1828 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1831 txs = sc->txs_base + sc->txs_ack;
1832 flags = le16toh(txs->flags);
1833 if ((flags & AE_TXS_UPDATE) == 0)
1835 txs->flags = htole16(flags & ~AE_TXS_UPDATE);
1837 ae_update_stats_tx(flags, &sc->stats);
1840 * Update TxS position.
1842 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT;
1843 sc->flags |= AE_FLAG_TXAVAIL;
1845 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack);
1846 if (txs->len != txd->len)
1847 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n",
1848 le16toh(txs->len), le16toh(txd->len));
1851 * Move txd ack and align on 4-byte boundary.
1853 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) +
1854 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1856 if ((flags & AE_TXS_SUCCESS) != 0)
1857 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1859 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1864 if ((sc->flags & AE_FLAG_TXAVAIL) != 0)
1865 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1866 if (sc->tx_inproc < 0) {
1867 if_printf(ifp, "Received stray Tx interrupt(s).\n");
1871 if (sc->tx_inproc == 0)
1872 sc->wd_timer = 0; /* Unarm watchdog. */
1875 * Syncronize DMA buffers.
1877 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1878 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1879 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1884 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
1894 flags = le16toh(rxd->flags);
1897 if_printf(ifp, "Rx interrupt occuried.\n");
1899 size = le16toh(rxd->len) - ETHER_CRC_LEN;
1900 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) {
1901 if_printf(ifp, "Runt frame received.");
1902 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1906 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL);
1908 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1912 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1913 (flags & AE_RXD_HAS_VLAN) != 0) {
1914 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan));
1915 m->m_flags |= M_VLANTAG;
1918 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1923 (*ifp->if_input)(ifp, m);
1928 ae_rx_intr(ae_softc_t *sc)
1935 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1942 * Syncronize DMA buffers.
1944 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1945 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1947 for (count = 0;; count++) {
1948 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur);
1949 flags = le16toh(rxd->flags);
1950 if ((flags & AE_RXD_UPDATE) == 0)
1952 rxd->flags = htole16(flags & ~AE_RXD_UPDATE);
1954 ae_update_stats_rx(flags, &sc->stats);
1957 * Update position index.
1959 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT;
1961 if ((flags & AE_RXD_SUCCESS) != 0)
1964 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1968 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1969 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1973 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
1978 ae_watchdog(ae_softc_t *sc)
1982 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1986 if (sc->wd_timer == 0 || --sc->wd_timer != 0)
1987 return; /* Noting to do. */
1989 if ((sc->flags & AE_FLAG_LINK) == 0)
1990 if_printf(ifp, "watchdog timeout (missed link).\n");
1992 if_printf(ifp, "watchdog timeout - resetting.\n");
1994 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1995 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1997 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1998 ae_start_locked(ifp);
2005 struct mii_data *mii;
2007 sc = (ae_softc_t *)arg;
2008 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2011 mii = device_get_softc(sc->miibus);
2013 ae_watchdog(sc); /* Watchdog check. */
2014 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
2018 ae_rxvlan(ae_softc_t *sc)
2025 val = AE_READ_4(sc, AE_MAC_REG);
2026 val &= ~AE_MAC_RMVLAN_EN;
2027 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2028 val |= AE_MAC_RMVLAN_EN;
2029 AE_WRITE_4(sc, AE_MAC_REG, val);
2033 ae_rxfilter(ae_softc_t *sc)
2036 struct ifmultiaddr *ifma;
2041 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2047 rxcfg = AE_READ_4(sc, AE_MAC_REG);
2048 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN);
2050 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2051 rxcfg |= AE_MAC_BCAST_EN;
2052 if ((ifp->if_flags & IFF_PROMISC) != 0)
2053 rxcfg |= AE_MAC_PROMISC_EN;
2054 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2055 rxcfg |= AE_MAC_MCAST_EN;
2058 * Wipe old settings.
2060 AE_WRITE_4(sc, AE_REG_MHT0, 0);
2061 AE_WRITE_4(sc, AE_REG_MHT1, 0);
2062 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2063 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff);
2064 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff);
2065 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2070 * Load multicast tables.
2072 bzero(mchash, sizeof(mchash));
2073 if_maddr_rlock(ifp);
2074 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2075 if (ifma->ifma_addr->sa_family != AF_LINK)
2077 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2078 ifma->ifma_addr), ETHER_ADDR_LEN);
2079 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2081 if_maddr_runlock(ifp);
2082 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]);
2083 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]);
2084 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2088 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2090 struct ae_softc *sc;
2092 struct mii_data *mii;
2096 ifr = (struct ifreq *)data;
2101 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU)
2103 else if (ifp->if_mtu != ifr->ifr_mtu) {
2105 ifp->if_mtu = ifr->ifr_mtu;
2106 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2107 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2115 if ((ifp->if_flags & IFF_UP) != 0) {
2116 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2117 if (((ifp->if_flags ^ sc->if_flags)
2118 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2121 if ((sc->flags & AE_FLAG_DETACH) == 0)
2125 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2128 sc->if_flags = ifp->if_flags;
2134 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2140 mii = device_get_softc(sc->miibus);
2141 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2145 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2146 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2147 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2148 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2151 VLAN_CAPABILITIES(ifp);
2155 error = ether_ioctl(ifp, cmd, data);
2162 ae_stop(ae_softc_t *sc)
2170 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2171 sc->flags &= ~AE_FLAG_LINK;
2172 sc->wd_timer = 0; /* Cancel watchdog. */
2173 callout_stop(&sc->tick_ch);
2176 * Clear and disable interrupts.
2178 AE_WRITE_4(sc, AE_IMR_REG, 0);
2179 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
2190 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN);
2191 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN);
2194 * Wait for everything to enter idle state.
2196 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
2197 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
2201 if (i == AE_IDLE_TIMEOUT)
2202 device_printf(sc->dev, "could not enter idle state in stop.\n");
2206 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats)
2209 if ((flags & AE_TXS_BCAST) != 0)
2211 if ((flags & AE_TXS_MCAST) != 0)
2213 if ((flags & AE_TXS_PAUSE) != 0)
2215 if ((flags & AE_TXS_CTRL) != 0)
2217 if ((flags & AE_TXS_DEFER) != 0)
2219 if ((flags & AE_TXS_EXCDEFER) != 0)
2220 stats->tx_excdefer++;
2221 if ((flags & AE_TXS_SINGLECOL) != 0)
2222 stats->tx_singlecol++;
2223 if ((flags & AE_TXS_MULTICOL) != 0)
2224 stats->tx_multicol++;
2225 if ((flags & AE_TXS_LATECOL) != 0)
2226 stats->tx_latecol++;
2227 if ((flags & AE_TXS_ABORTCOL) != 0)
2228 stats->tx_abortcol++;
2229 if ((flags & AE_TXS_UNDERRUN) != 0)
2230 stats->tx_underrun++;
2234 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats)
2237 if ((flags & AE_RXD_BCAST) != 0)
2239 if ((flags & AE_RXD_MCAST) != 0)
2241 if ((flags & AE_RXD_PAUSE) != 0)
2243 if ((flags & AE_RXD_CTRL) != 0)
2245 if ((flags & AE_RXD_CRCERR) != 0)
2247 if ((flags & AE_RXD_CODEERR) != 0)
2248 stats->rx_codeerr++;
2249 if ((flags & AE_RXD_RUNT) != 0)
2251 if ((flags & AE_RXD_FRAG) != 0)
2253 if ((flags & AE_RXD_TRUNC) != 0)
2255 if ((flags & AE_RXD_ALIGN) != 0)