2 * Copyright (c) 2008 Stanislav Sedov <stas@FreeBSD.org>.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * Driver for Attansic Technology Corp. L2 FastEthernet adapter.
27 * This driver is heavily based on age(4) Attansic L1 driver by Pyun YongHyeon.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/if_types.h>
55 #include <net/if_vlan_var.h>
57 #include <netinet/in.h>
58 #include <netinet/in_systm.h>
59 #include <netinet/ip.h>
60 #include <netinet/tcp.h>
62 #include <dev/mii/mii.h>
63 #include <dev/mii/miivar.h>
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
67 #include <machine/bus.h>
69 #include "miibus_if.h"
75 * Devices supported by this driver.
77 static struct ae_dev {
82 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L2,
83 "Attansic Technology Corp, L2 FastEthernet" },
85 #define AE_DEVS_COUNT (sizeof(ae_devs) / sizeof(*ae_devs))
87 static struct resource_spec ae_res_spec_mem[] = {
88 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
91 static struct resource_spec ae_res_spec_irq[] = {
92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
95 static struct resource_spec ae_res_spec_msi[] = {
96 { SYS_RES_IRQ, 1, RF_ACTIVE },
100 static int ae_probe(device_t dev);
101 static int ae_attach(device_t dev);
102 static void ae_pcie_init(ae_softc_t *sc);
103 static void ae_phy_reset(ae_softc_t *sc);
104 static void ae_phy_init(ae_softc_t *sc);
105 static int ae_reset(ae_softc_t *sc);
106 static void ae_init(void *arg);
107 static int ae_init_locked(ae_softc_t *sc);
108 static int ae_detach(device_t dev);
109 static int ae_miibus_readreg(device_t dev, int phy, int reg);
110 static int ae_miibus_writereg(device_t dev, int phy, int reg, int val);
111 static void ae_miibus_statchg(device_t dev);
112 static void ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
113 static int ae_mediachange(struct ifnet *ifp);
114 static void ae_retrieve_address(ae_softc_t *sc);
115 static void ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs,
117 static int ae_alloc_rings(ae_softc_t *sc);
118 static void ae_dma_free(ae_softc_t *sc);
119 static int ae_shutdown(device_t dev);
120 static int ae_suspend(device_t dev);
121 static void ae_powersave_disable(ae_softc_t *sc);
122 static void ae_powersave_enable(ae_softc_t *sc);
123 static int ae_resume(device_t dev);
124 static unsigned int ae_tx_avail_size(ae_softc_t *sc);
125 static int ae_encap(ae_softc_t *sc, struct mbuf **m_head);
126 static void ae_start(struct ifnet *ifp);
127 static void ae_start_locked(struct ifnet *ifp);
128 static void ae_link_task(void *arg, int pending);
129 static void ae_stop_rxmac(ae_softc_t *sc);
130 static void ae_stop_txmac(ae_softc_t *sc);
131 static void ae_mac_config(ae_softc_t *sc);
132 static int ae_intr(void *arg);
133 static void ae_int_task(void *arg, int pending);
134 static void ae_tx_intr(ae_softc_t *sc);
135 static int ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd);
136 static void ae_rx_intr(ae_softc_t *sc);
137 static void ae_watchdog(ae_softc_t *sc);
138 static void ae_tick(void *arg);
139 static void ae_rxfilter(ae_softc_t *sc);
140 static void ae_rxvlan(ae_softc_t *sc);
141 static int ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
142 static void ae_stop(ae_softc_t *sc);
143 static int ae_check_eeprom_present(ae_softc_t *sc, int *vpdc);
144 static int ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word);
145 static int ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr);
146 static int ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr);
147 static void ae_update_stats_rx(uint16_t flags, ae_stats_t *stats);
148 static void ae_update_stats_tx(uint16_t flags, ae_stats_t *stats);
149 static void ae_init_tunables(ae_softc_t *sc);
151 static device_method_t ae_methods[] = {
152 /* Device interface. */
153 DEVMETHOD(device_probe, ae_probe),
154 DEVMETHOD(device_attach, ae_attach),
155 DEVMETHOD(device_detach, ae_detach),
156 DEVMETHOD(device_shutdown, ae_shutdown),
157 DEVMETHOD(device_suspend, ae_suspend),
158 DEVMETHOD(device_resume, ae_resume),
161 DEVMETHOD(miibus_readreg, ae_miibus_readreg),
162 DEVMETHOD(miibus_writereg, ae_miibus_writereg),
163 DEVMETHOD(miibus_statchg, ae_miibus_statchg),
167 static driver_t ae_driver = {
172 static devclass_t ae_devclass;
174 DRIVER_MODULE(ae, pci, ae_driver, ae_devclass, 0, 0);
175 DRIVER_MODULE(miibus, ae, miibus_driver, miibus_devclass, 0, 0);
176 MODULE_DEPEND(ae, pci, 1, 1, 1);
177 MODULE_DEPEND(ae, ether, 1, 1, 1);
178 MODULE_DEPEND(ae, miibus, 1, 1, 1);
183 static int msi_disable = 0;
184 TUNABLE_INT("hw.ae.msi_disable", &msi_disable);
186 #define AE_READ_4(sc, reg) \
187 bus_read_4((sc)->mem[0], (reg))
188 #define AE_READ_2(sc, reg) \
189 bus_read_2((sc)->mem[0], (reg))
190 #define AE_READ_1(sc, reg) \
191 bus_read_1((sc)->mem[0], (reg))
192 #define AE_WRITE_4(sc, reg, val) \
193 bus_write_4((sc)->mem[0], (reg), (val))
194 #define AE_WRITE_2(sc, reg, val) \
195 bus_write_2((sc)->mem[0], (reg), (val))
196 #define AE_WRITE_1(sc, reg, val) \
197 bus_write_1((sc)->mem[0], (reg), (val))
198 #define AE_PHY_READ(sc, reg) \
199 ae_miibus_readreg(sc->dev, 0, reg)
200 #define AE_PHY_WRITE(sc, reg, val) \
201 ae_miibus_writereg(sc->dev, 0, reg, val)
202 #define AE_CHECK_EADDR_VALID(eaddr) \
203 ((eaddr[0] == 0 && eaddr[1] == 0) || \
204 (eaddr[0] == 0xffffffff && eaddr[1] == 0xffff))
205 #define AE_RXD_VLAN(vtag) \
206 (((vtag) >> 4) | (((vtag) & 0x07) << 13) | (((vtag) & 0x08) << 9))
207 #define AE_TXD_VLAN(vtag) \
208 (((vtag) << 4) | (((vtag) >> 13) & 0x07) | (((vtag) >> 9) & 0x08))
211 ae_probe(device_t dev)
213 uint16_t deviceid, vendorid;
216 vendorid = pci_get_vendor(dev);
217 deviceid = pci_get_device(dev);
220 * Search through the list of supported devs for matching one.
222 for (i = 0; i < AE_DEVS_COUNT; i++) {
223 if (vendorid == ae_devs[i].vendorid &&
224 deviceid == ae_devs[i].deviceid) {
225 device_set_desc(dev, ae_devs[i].name);
226 return (BUS_PROBE_DEFAULT);
233 ae_attach(device_t dev)
242 sc = device_get_softc(dev); /* Automatically allocated and zeroed
244 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
248 * Initialize mutexes and tasks.
250 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, MTX_DEF);
251 callout_init_mtx(&sc->tick_ch, &sc->mtx, 0);
252 TASK_INIT(&sc->int_task, 0, ae_int_task, sc);
253 TASK_INIT(&sc->link_task, 0, ae_link_task, sc);
255 pci_enable_busmaster(dev); /* Enable bus mastering. */
257 sc->spec_mem = ae_res_spec_mem;
260 * Allocate memory-mapped registers.
262 error = bus_alloc_resources(dev, sc->spec_mem, sc->mem);
264 device_printf(dev, "could not allocate memory resources.\n");
270 * Retrieve PCI and chip revisions.
272 pcirev = pci_get_revid(dev);
273 chiprev = (AE_READ_4(sc, AE_MASTER_REG) >> AE_MASTER_REVNUM_SHIFT) &
274 AE_MASTER_REVNUM_MASK;
276 device_printf(dev, "pci device revision: %#04x\n", pcirev);
277 device_printf(dev, "chip id: %#02x\n", chiprev);
279 nmsi = pci_msi_count(dev);
281 device_printf(dev, "MSI count: %d.\n", nmsi);
284 * Allocate interrupt resources.
286 if (msi_disable == 0 && nmsi == 1) {
287 error = pci_alloc_msi(dev, &nmsi);
289 device_printf(dev, "Using MSI messages.\n");
290 sc->spec_irq = ae_res_spec_msi;
291 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
293 device_printf(dev, "MSI allocation failed.\n");
295 pci_release_msi(dev);
297 sc->flags |= AE_FLAG_MSI;
301 if (sc->spec_irq == NULL) {
302 sc->spec_irq = ae_res_spec_irq;
303 error = bus_alloc_resources(dev, sc->spec_irq, sc->irq);
305 device_printf(dev, "could not allocate IRQ resources.\n");
311 ae_init_tunables(sc);
313 ae_phy_reset(sc); /* Reset PHY. */
314 error = ae_reset(sc); /* Reset the controller itself. */
320 ae_retrieve_address(sc); /* Load MAC address. */
322 error = ae_alloc_rings(sc); /* Allocate ring buffers. */
326 ifp = sc->ifp = if_alloc(IFT_ETHER);
328 device_printf(dev, "could not allocate ifnet structure.\n");
334 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
336 ifp->if_ioctl = ae_ioctl;
337 ifp->if_start = ae_start;
338 ifp->if_init = ae_init;
339 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
340 ifp->if_hwassist = 0;
341 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
342 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
343 IFQ_SET_READY(&ifp->if_snd);
344 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
345 ifp->if_capabilities |= IFCAP_WOL_MAGIC;
346 sc->flags |= AE_FLAG_PMG;
348 ifp->if_capenable = ifp->if_capabilities;
351 * Configure and attach MII bus.
353 error = mii_attach(dev, &sc->miibus, ifp, ae_mediachange,
354 ae_mediastatus, BMSR_DEFCAPMASK, AE_PHYADDR_DEFAULT,
357 device_printf(dev, "attaching PHYs failed\n");
361 ether_ifattach(ifp, sc->eaddr);
362 /* Tell the upper layer(s) we support long frames. */
363 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
366 * Create and run all helper tasks.
368 sc->tq = taskqueue_create_fast("ae_taskq", M_WAITOK,
369 taskqueue_thread_enqueue, &sc->tq);
370 if (sc->tq == NULL) {
371 device_printf(dev, "could not create taskqueue.\n");
376 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
377 device_get_nameunit(sc->dev));
380 * Configure interrupt handlers.
382 error = bus_setup_intr(dev, sc->irq[0], INTR_TYPE_NET | INTR_MPSAFE,
383 ae_intr, NULL, sc, &sc->intrhand);
385 device_printf(dev, "could not set up interrupt handler.\n");
386 taskqueue_free(sc->tq);
399 #define AE_SYSCTL(stx, parent, name, desc, ptr) \
400 SYSCTL_ADD_UINT(ctx, parent, OID_AUTO, name, CTLFLAG_RD, ptr, 0, desc)
403 ae_init_tunables(ae_softc_t *sc)
405 struct sysctl_ctx_list *ctx;
406 struct sysctl_oid *root, *stats, *stats_rx, *stats_tx;
407 struct ae_stats *ae_stats;
409 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
410 ae_stats = &sc->stats;
412 ctx = device_get_sysctl_ctx(sc->dev);
413 root = device_get_sysctl_tree(sc->dev);
414 stats = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(root), OID_AUTO, "stats",
415 CTLFLAG_RD, NULL, "ae statistics");
418 * Receiver statistcics.
420 stats_rx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "rx",
421 CTLFLAG_RD, NULL, "Rx MAC statistics");
422 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "bcast",
423 "broadcast frames", &ae_stats->rx_bcast);
424 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "mcast",
425 "multicast frames", &ae_stats->rx_mcast);
426 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "pause",
427 "PAUSE frames", &ae_stats->rx_pause);
428 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "control",
429 "control frames", &ae_stats->rx_ctrl);
430 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "crc_errors",
431 "frames with CRC errors", &ae_stats->rx_crcerr);
432 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "code_errors",
433 "frames with invalid opcode", &ae_stats->rx_codeerr);
434 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "runt",
435 "runt frames", &ae_stats->rx_runt);
436 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "frag",
437 "fragmented frames", &ae_stats->rx_frag);
438 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "align_errors",
439 "frames with alignment errors", &ae_stats->rx_align);
440 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_rx), "truncated",
441 "frames truncated due to Rx FIFO inderrun", &ae_stats->rx_trunc);
444 * Receiver statistcics.
446 stats_tx = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(stats), OID_AUTO, "tx",
447 CTLFLAG_RD, NULL, "Tx MAC statistics");
448 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "bcast",
449 "broadcast frames", &ae_stats->tx_bcast);
450 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "mcast",
451 "multicast frames", &ae_stats->tx_mcast);
452 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "pause",
453 "PAUSE frames", &ae_stats->tx_pause);
454 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "control",
455 "control frames", &ae_stats->tx_ctrl);
456 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "defers",
457 "deferrals occuried", &ae_stats->tx_defer);
458 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "exc_defers",
459 "excessive deferrals occuried", &ae_stats->tx_excdefer);
460 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "singlecols",
461 "single collisions occuried", &ae_stats->tx_singlecol);
462 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "multicols",
463 "multiple collisions occuried", &ae_stats->tx_multicol);
464 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "latecols",
465 "late collisions occuried", &ae_stats->tx_latecol);
466 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "aborts",
467 "transmit aborts due collisions", &ae_stats->tx_abortcol);
468 AE_SYSCTL(ctx, SYSCTL_CHILDREN(stats_tx), "underruns",
469 "Tx FIFO underruns", &ae_stats->tx_underrun);
473 ae_pcie_init(ae_softc_t *sc)
476 AE_WRITE_4(sc, AE_PCIE_LTSSM_TESTMODE_REG, AE_PCIE_LTSSM_TESTMODE_DEFAULT);
477 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, AE_PCIE_DLL_TX_CTRL_DEFAULT);
481 ae_phy_reset(ae_softc_t *sc)
484 AE_WRITE_4(sc, AE_PHY_ENABLE_REG, AE_PHY_ENABLE);
485 DELAY(1000); /* XXX: pause(9) ? */
489 ae_reset(ae_softc_t *sc)
494 * Issue a soft reset.
496 AE_WRITE_4(sc, AE_MASTER_REG, AE_MASTER_SOFT_RESET);
497 bus_barrier(sc->mem[0], AE_MASTER_REG, 4,
498 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
501 * Wait for reset to complete.
503 for (i = 0; i < AE_RESET_TIMEOUT; i++) {
504 if ((AE_READ_4(sc, AE_MASTER_REG) & AE_MASTER_SOFT_RESET) == 0)
508 if (i == AE_RESET_TIMEOUT) {
509 device_printf(sc->dev, "reset timeout.\n");
514 * Wait for everything to enter idle state.
516 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
517 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
521 if (i == AE_IDLE_TIMEOUT) {
522 device_printf(sc->dev, "could not enter idle state.\n");
533 sc = (ae_softc_t *)arg;
540 ae_phy_init(ae_softc_t *sc)
544 * Enable link status change interrupt.
548 AE_PHY_WRITE(sc, 18, 0xc00);
553 ae_init_locked(ae_softc_t *sc)
556 struct mii_data *mii;
557 uint8_t eaddr[ETHER_ADDR_LEN];
564 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
566 mii = device_get_softc(sc->miibus);
570 ae_pcie_init(sc); /* Initialize PCIE stuff. */
572 ae_powersave_disable(sc);
575 * Clear and disable interrupts.
577 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
580 * Set the MAC address.
582 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
583 val = eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5];
584 AE_WRITE_4(sc, AE_EADDR0_REG, val);
585 val = eaddr[0] << 8 | eaddr[1];
586 AE_WRITE_4(sc, AE_EADDR1_REG, val);
589 * Set ring buffers base addresses.
591 addr = sc->dma_rxd_busaddr;
592 AE_WRITE_4(sc, AE_DESC_ADDR_HI_REG, BUS_ADDR_HI(addr));
593 AE_WRITE_4(sc, AE_RXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
594 addr = sc->dma_txd_busaddr;
595 AE_WRITE_4(sc, AE_TXD_ADDR_LO_REG, BUS_ADDR_LO(addr));
596 addr = sc->dma_txs_busaddr;
597 AE_WRITE_4(sc, AE_TXS_ADDR_LO_REG, BUS_ADDR_LO(addr));
600 * Configure ring buffers sizes.
602 AE_WRITE_2(sc, AE_RXD_COUNT_REG, AE_RXD_COUNT_DEFAULT);
603 AE_WRITE_2(sc, AE_TXD_BUFSIZE_REG, AE_TXD_BUFSIZE_DEFAULT / 4);
604 AE_WRITE_2(sc, AE_TXS_COUNT_REG, AE_TXS_COUNT_DEFAULT);
607 * Configure interframe gap parameters.
609 val = ((AE_IFG_TXIPG_DEFAULT << AE_IFG_TXIPG_SHIFT) &
611 ((AE_IFG_RXIPG_DEFAULT << AE_IFG_RXIPG_SHIFT) &
613 ((AE_IFG_IPGR1_DEFAULT << AE_IFG_IPGR1_SHIFT) &
615 ((AE_IFG_IPGR2_DEFAULT << AE_IFG_IPGR2_SHIFT) &
617 AE_WRITE_4(sc, AE_IFG_REG, val);
620 * Configure half-duplex operation.
622 val = ((AE_HDPX_LCOL_DEFAULT << AE_HDPX_LCOL_SHIFT) &
624 ((AE_HDPX_RETRY_DEFAULT << AE_HDPX_RETRY_SHIFT) &
625 AE_HDPX_RETRY_MASK) |
626 ((AE_HDPX_ABEBT_DEFAULT << AE_HDPX_ABEBT_SHIFT) &
627 AE_HDPX_ABEBT_MASK) |
628 ((AE_HDPX_JAMIPG_DEFAULT << AE_HDPX_JAMIPG_SHIFT) &
629 AE_HDPX_JAMIPG_MASK) | AE_HDPX_EXC_EN;
630 AE_WRITE_4(sc, AE_HDPX_REG, val);
633 * Configure interrupt moderate timer.
635 AE_WRITE_2(sc, AE_IMT_REG, AE_IMT_DEFAULT);
636 val = AE_READ_4(sc, AE_MASTER_REG);
637 val |= AE_MASTER_IMT_EN;
638 AE_WRITE_4(sc, AE_MASTER_REG, val);
641 * Configure interrupt clearing timer.
643 AE_WRITE_2(sc, AE_ICT_REG, AE_ICT_DEFAULT);
648 val = ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
650 AE_WRITE_2(sc, AE_MTU_REG, val);
653 * Configure cut-through threshold.
655 AE_WRITE_4(sc, AE_CUT_THRESH_REG, AE_CUT_THRESH_DEFAULT);
658 * Configure flow control.
660 AE_WRITE_2(sc, AE_FLOW_THRESH_HI_REG, (AE_RXD_COUNT_DEFAULT / 8) * 7);
661 AE_WRITE_2(sc, AE_FLOW_THRESH_LO_REG, (AE_RXD_COUNT_MIN / 8) >
662 (AE_RXD_COUNT_DEFAULT / 12) ? (AE_RXD_COUNT_MIN / 8) :
663 (AE_RXD_COUNT_DEFAULT / 12));
668 sc->txd_cur = sc->rxd_cur = 0;
669 sc->txs_ack = sc->txd_ack = 0;
671 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur);
672 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
674 sc->tx_inproc = 0; /* Number of packets the chip processes now. */
675 sc->flags |= AE_FLAG_TXAVAIL; /* Free Tx's available. */
680 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
681 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
684 * Check if everything is OK.
686 val = AE_READ_4(sc, AE_ISR_REG);
687 if ((val & AE_ISR_PHY_LINKDOWN) != 0) {
688 device_printf(sc->dev, "Initialization failed.\n");
693 * Clear interrupt status.
695 AE_WRITE_4(sc, AE_ISR_REG, 0x3fffffff);
696 AE_WRITE_4(sc, AE_ISR_REG, 0x0);
701 val = AE_READ_4(sc, AE_MASTER_REG);
702 AE_WRITE_4(sc, AE_MASTER_REG, val | AE_MASTER_MANUAL_INT);
703 AE_WRITE_4(sc, AE_IMR_REG, AE_IMR_DEFAULT);
708 AE_WRITE_4(sc, AE_WOL_REG, 0);
713 val = AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD |
714 AE_MAC_FULL_DUPLEX | AE_MAC_CLK_PHY |
715 AE_MAC_TX_FLOW_EN | AE_MAC_RX_FLOW_EN |
716 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & AE_HALFBUF_MASK) |
717 ((AE_MAC_PREAMBLE_DEFAULT << AE_MAC_PREAMBLE_SHIFT) &
718 AE_MAC_PREAMBLE_MASK);
719 AE_WRITE_4(sc, AE_MAC_REG, val);
730 val = AE_READ_4(sc, AE_MAC_REG);
731 AE_WRITE_4(sc, AE_MAC_REG, val | AE_MAC_TX_EN | AE_MAC_RX_EN);
733 sc->flags &= ~AE_FLAG_LINK;
734 mii_mediachg(mii); /* Switch to the current media. */
736 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
738 ifp->if_drv_flags |= IFF_DRV_RUNNING;
739 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
742 device_printf(sc->dev, "Initialization complete.\n");
749 ae_detach(device_t dev)
754 sc = device_get_softc(dev);
755 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
757 if (device_is_attached(dev)) {
759 sc->flags |= AE_FLAG_DETACH;
762 callout_drain(&sc->tick_ch);
763 taskqueue_drain(sc->tq, &sc->int_task);
764 taskqueue_drain(taskqueue_swi, &sc->link_task);
767 if (sc->tq != NULL) {
768 taskqueue_drain(sc->tq, &sc->int_task);
769 taskqueue_free(sc->tq);
772 if (sc->miibus != NULL) {
773 device_delete_child(dev, sc->miibus);
776 bus_generic_detach(sc->dev);
778 if (sc->intrhand != NULL) {
779 bus_teardown_intr(dev, sc->irq[0], sc->intrhand);
786 if (sc->spec_irq != NULL)
787 bus_release_resources(dev, sc->spec_irq, sc->irq);
788 if (sc->spec_mem != NULL)
789 bus_release_resources(dev, sc->spec_mem, sc->mem);
790 if ((sc->flags & AE_FLAG_MSI) != 0)
791 pci_release_msi(dev);
792 mtx_destroy(&sc->mtx);
798 ae_miibus_readreg(device_t dev, int phy, int reg)
804 sc = device_get_softc(dev);
805 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
808 * Locking is done in upper layers.
811 val = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
812 AE_MDIO_START | AE_MDIO_READ | AE_MDIO_SUP_PREAMBLE |
813 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK);
814 AE_WRITE_4(sc, AE_MDIO_REG, val);
817 * Wait for operation to complete.
819 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
821 val = AE_READ_4(sc, AE_MDIO_REG);
822 if ((val & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
825 if (i == AE_MDIO_TIMEOUT) {
826 device_printf(sc->dev, "phy read timeout: %d.\n", reg);
829 return ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
833 ae_miibus_writereg(device_t dev, int phy, int reg, int val)
839 sc = device_get_softc(dev);
840 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
843 * Locking is done in upper layers.
846 aereg = ((reg << AE_MDIO_REGADDR_SHIFT) & AE_MDIO_REGADDR_MASK) |
847 AE_MDIO_START | AE_MDIO_SUP_PREAMBLE |
848 ((AE_MDIO_CLK_25_4 << AE_MDIO_CLK_SHIFT) & AE_MDIO_CLK_MASK) |
849 ((val << AE_MDIO_DATA_SHIFT) & AE_MDIO_DATA_MASK);
850 AE_WRITE_4(sc, AE_MDIO_REG, aereg);
853 * Wait for operation to complete.
855 for (i = 0; i < AE_MDIO_TIMEOUT; i++) {
857 aereg = AE_READ_4(sc, AE_MDIO_REG);
858 if ((aereg & (AE_MDIO_START | AE_MDIO_BUSY)) == 0)
861 if (i == AE_MDIO_TIMEOUT) {
862 device_printf(sc->dev, "phy write timeout: %d.\n", reg);
868 ae_miibus_statchg(device_t dev)
872 sc = device_get_softc(dev);
873 taskqueue_enqueue(taskqueue_swi, &sc->link_task);
877 ae_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
880 struct mii_data *mii;
883 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
886 mii = device_get_softc(sc->miibus);
888 ifmr->ifm_status = mii->mii_media_status;
889 ifmr->ifm_active = mii->mii_media_active;
894 ae_mediachange(struct ifnet *ifp)
897 struct mii_data *mii;
898 struct mii_softc *mii_sc;
901 /* XXX: check IFF_UP ?? */
903 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
905 mii = device_get_softc(sc->miibus);
906 LIST_FOREACH(mii_sc, &mii->mii_phys, mii_list)
908 error = mii_mediachg(mii);
915 ae_check_eeprom_present(ae_softc_t *sc, int *vpdc)
920 KASSERT(vpdc != NULL, ("[ae, %d]: vpdc is NULL!\n", __LINE__));
923 * Not sure why, but Linux does this.
925 val = AE_READ_4(sc, AE_SPICTL_REG);
926 if ((val & AE_SPICTL_VPD_EN) != 0) {
927 val &= ~AE_SPICTL_VPD_EN;
928 AE_WRITE_4(sc, AE_SPICTL_REG, val);
930 error = pci_find_cap(sc->dev, PCIY_VPD, vpdc);
935 ae_vpd_read_word(ae_softc_t *sc, int reg, uint32_t *word)
940 AE_WRITE_4(sc, AE_VPD_DATA_REG, 0); /* Clear register value. */
943 * VPD registers start at offset 0x100. Read them.
945 val = 0x100 + reg * 4;
946 AE_WRITE_4(sc, AE_VPD_CAP_REG, (val << AE_VPD_CAP_ADDR_SHIFT) &
947 AE_VPD_CAP_ADDR_MASK);
948 for (i = 0; i < AE_VPD_TIMEOUT; i++) {
950 val = AE_READ_4(sc, AE_VPD_CAP_REG);
951 if ((val & AE_VPD_CAP_DONE) != 0)
954 if (i == AE_VPD_TIMEOUT) {
955 device_printf(sc->dev, "timeout reading VPD register %d.\n",
959 *word = AE_READ_4(sc, AE_VPD_DATA_REG);
964 ae_get_vpd_eaddr(ae_softc_t *sc, uint32_t *eaddr)
966 uint32_t word, reg, val;
972 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
973 KASSERT(eaddr != NULL, ("[ae, %d]: eaddr is NULL", __LINE__));
978 error = ae_check_eeprom_present(sc, &vpdc);
983 * Read the VPD configuration space.
984 * Each register is prefixed with signature,
985 * so we can check if it is valid.
987 for (i = 0, found = 0; i < AE_VPD_NREGS; i++) {
988 error = ae_vpd_read_word(sc, i, &word);
995 if ((word & AE_VPD_SIG_MASK) != AE_VPD_SIG)
997 reg = word >> AE_VPD_REG_SHIFT;
998 i++; /* Move to the next word. */
1000 if (reg != AE_EADDR0_REG && reg != AE_EADDR1_REG)
1003 error = ae_vpd_read_word(sc, i, &val);
1006 if (reg == AE_EADDR0_REG)
1016 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1017 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1019 device_printf(sc->dev,
1020 "VPD ethernet address registers are invalid.\n");
1027 ae_get_reg_eaddr(ae_softc_t *sc, uint32_t *eaddr)
1031 * BIOS is supposed to set this.
1033 eaddr[0] = AE_READ_4(sc, AE_EADDR0_REG);
1034 eaddr[1] = AE_READ_4(sc, AE_EADDR1_REG);
1035 eaddr[1] &= 0xffff; /* Only last 2 bytes are used. */
1037 if (AE_CHECK_EADDR_VALID(eaddr) != 0) {
1039 device_printf(sc->dev,
1040 "Ethernet address registers are invalid.\n");
1047 ae_retrieve_address(ae_softc_t *sc)
1049 uint32_t eaddr[2] = {0, 0};
1055 error = ae_get_vpd_eaddr(sc, eaddr);
1057 error = ae_get_reg_eaddr(sc, eaddr);
1060 device_printf(sc->dev,
1061 "Generating random ethernet address.\n");
1062 eaddr[0] = arc4random();
1065 * Set OUI to ASUSTek COMPUTER INC.
1067 sc->eaddr[0] = 0x02; /* U/L bit set. */
1068 sc->eaddr[1] = 0x1f;
1069 sc->eaddr[2] = 0xc6;
1070 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1071 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1072 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1074 sc->eaddr[0] = (eaddr[1] >> 8) & 0xff;
1075 sc->eaddr[1] = (eaddr[1] >> 0) & 0xff;
1076 sc->eaddr[2] = (eaddr[0] >> 24) & 0xff;
1077 sc->eaddr[3] = (eaddr[0] >> 16) & 0xff;
1078 sc->eaddr[4] = (eaddr[0] >> 8) & 0xff;
1079 sc->eaddr[5] = (eaddr[0] >> 0) & 0xff;
1084 ae_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1086 bus_addr_t *addr = arg;
1090 KASSERT(nsegs == 1, ("[ae, %d]: %d segments instead of 1!", __LINE__,
1092 *addr = segs[0].ds_addr;
1096 ae_alloc_rings(ae_softc_t *sc)
1102 * Create parent DMA tag.
1104 error = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
1105 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1106 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0,
1107 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
1108 &sc->dma_parent_tag);
1110 device_printf(sc->dev, "could not creare parent DMA tag.\n");
1115 * Create DMA tag for TxD.
1117 error = bus_dma_tag_create(sc->dma_parent_tag,
1118 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1119 NULL, NULL, AE_TXD_BUFSIZE_DEFAULT, 1,
1120 AE_TXD_BUFSIZE_DEFAULT, 0, NULL, NULL,
1123 device_printf(sc->dev, "could not creare TxD DMA tag.\n");
1128 * Create DMA tag for TxS.
1130 error = bus_dma_tag_create(sc->dma_parent_tag,
1131 4, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1132 NULL, NULL, AE_TXS_COUNT_DEFAULT * 4, 1,
1133 AE_TXS_COUNT_DEFAULT * 4, 0, NULL, NULL,
1136 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1141 * Create DMA tag for RxD.
1143 error = bus_dma_tag_create(sc->dma_parent_tag,
1144 128, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1145 NULL, NULL, AE_RXD_COUNT_DEFAULT * 1536 + 120, 1,
1146 AE_RXD_COUNT_DEFAULT * 1536 + 120, 0, NULL, NULL,
1149 device_printf(sc->dev, "could not creare TxS DMA tag.\n");
1154 * Allocate TxD DMA memory.
1156 error = bus_dmamem_alloc(sc->dma_txd_tag, (void **)&sc->txd_base,
1157 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1160 device_printf(sc->dev,
1161 "could not allocate DMA memory for TxD ring.\n");
1164 error = bus_dmamap_load(sc->dma_txd_tag, sc->dma_txd_map, sc->txd_base,
1165 AE_TXD_BUFSIZE_DEFAULT, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1166 if (error != 0 || busaddr == 0) {
1167 device_printf(sc->dev,
1168 "could not load DMA map for TxD ring.\n");
1171 sc->dma_txd_busaddr = busaddr;
1174 * Allocate TxS DMA memory.
1176 error = bus_dmamem_alloc(sc->dma_txs_tag, (void **)&sc->txs_base,
1177 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1180 device_printf(sc->dev,
1181 "could not allocate DMA memory for TxS ring.\n");
1184 error = bus_dmamap_load(sc->dma_txs_tag, sc->dma_txs_map, sc->txs_base,
1185 AE_TXS_COUNT_DEFAULT * 4, ae_dmamap_cb, &busaddr, BUS_DMA_NOWAIT);
1186 if (error != 0 || busaddr == 0) {
1187 device_printf(sc->dev,
1188 "could not load DMA map for TxS ring.\n");
1191 sc->dma_txs_busaddr = busaddr;
1194 * Allocate RxD DMA memory.
1196 error = bus_dmamem_alloc(sc->dma_rxd_tag, (void **)&sc->rxd_base_dma,
1197 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1200 device_printf(sc->dev,
1201 "could not allocate DMA memory for RxD ring.\n");
1204 error = bus_dmamap_load(sc->dma_rxd_tag, sc->dma_rxd_map,
1205 sc->rxd_base_dma, AE_RXD_COUNT_DEFAULT * 1536 + 120, ae_dmamap_cb,
1206 &busaddr, BUS_DMA_NOWAIT);
1207 if (error != 0 || busaddr == 0) {
1208 device_printf(sc->dev,
1209 "could not load DMA map for RxD ring.\n");
1212 sc->dma_rxd_busaddr = busaddr + 120;
1213 sc->rxd_base = (ae_rxd_t *)(sc->rxd_base_dma + 120);
1219 ae_dma_free(ae_softc_t *sc)
1222 if (sc->dma_txd_tag != NULL) {
1223 if (sc->dma_txd_map != NULL) {
1224 bus_dmamap_unload(sc->dma_txd_tag, sc->dma_txd_map);
1225 if (sc->txd_base != NULL)
1226 bus_dmamem_free(sc->dma_txd_tag, sc->txd_base,
1230 bus_dma_tag_destroy(sc->dma_txd_tag);
1231 sc->dma_txd_map = NULL;
1232 sc->dma_txd_tag = NULL;
1233 sc->txd_base = NULL;
1235 if (sc->dma_txs_tag != NULL) {
1236 if (sc->dma_txs_map != NULL) {
1237 bus_dmamap_unload(sc->dma_txs_tag, sc->dma_txs_map);
1238 if (sc->txs_base != NULL)
1239 bus_dmamem_free(sc->dma_txs_tag, sc->txs_base,
1243 bus_dma_tag_destroy(sc->dma_txs_tag);
1244 sc->dma_txs_map = NULL;
1245 sc->dma_txs_tag = NULL;
1246 sc->txs_base = NULL;
1248 if (sc->dma_rxd_tag != NULL) {
1249 if (sc->dma_rxd_map != NULL) {
1250 bus_dmamap_unload(sc->dma_rxd_tag, sc->dma_rxd_map);
1251 if (sc->rxd_base_dma != NULL)
1252 bus_dmamem_free(sc->dma_rxd_tag,
1253 sc->rxd_base_dma, sc->dma_rxd_map);
1256 bus_dma_tag_destroy(sc->dma_rxd_tag);
1257 sc->dma_rxd_map = NULL;
1258 sc->dma_rxd_tag = NULL;
1259 sc->rxd_base_dma = NULL;
1261 if (sc->dma_parent_tag != NULL) {
1262 bus_dma_tag_destroy(sc->dma_parent_tag);
1263 sc->dma_parent_tag = NULL;
1268 ae_shutdown(device_t dev)
1273 sc = device_get_softc(dev);
1274 KASSERT(sc != NULL, ("[ae: %d]: sc is NULL", __LINE__));
1276 error = ae_suspend(dev);
1278 ae_powersave_enable(sc);
1284 ae_powersave_disable(ae_softc_t *sc)
1290 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1291 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1292 if (val & AE_PHY_DBG_POWERSAVE) {
1293 val &= ~AE_PHY_DBG_POWERSAVE;
1294 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, val);
1300 ae_powersave_enable(ae_softc_t *sc)
1307 * XXX magic numbers.
1309 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 0);
1310 val = AE_PHY_READ(sc, AE_PHY_DBG_DATA);
1311 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, val | 0x1000);
1312 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 2);
1313 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0x3000);
1314 AE_PHY_WRITE(sc, AE_PHY_DBG_ADDR, 3);
1315 AE_PHY_WRITE(sc, AE_PHY_DBG_DATA, 0);
1319 ae_pm_init(ae_softc_t *sc)
1324 struct mii_data *mii;
1330 if ((sc->flags & AE_FLAG_PMG) == 0) {
1331 /* Disable WOL entirely. */
1332 AE_WRITE_4(sc, AE_WOL_REG, 0);
1337 * Configure WOL if enabled.
1339 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1340 mii = device_get_softc(sc->miibus);
1342 if ((mii->mii_media_status & IFM_AVALID) != 0 &&
1343 (mii->mii_media_status & IFM_ACTIVE) != 0) {
1344 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_MAGIC | \
1350 val = AE_MAC_RX_EN | AE_MAC_CLK_PHY | \
1351 AE_MAC_TX_CRC_EN | AE_MAC_TX_AUTOPAD | \
1352 ((AE_HALFBUF_DEFAULT << AE_HALFBUF_SHIFT) & \
1353 AE_HALFBUF_MASK) | \
1354 ((AE_MAC_PREAMBLE_DEFAULT << \
1355 AE_MAC_PREAMBLE_SHIFT) & AE_MAC_PREAMBLE_MASK) | \
1356 AE_MAC_BCAST_EN | AE_MAC_MCAST_EN;
1357 if ((IFM_OPTIONS(mii->mii_media_active) & \
1359 val |= AE_MAC_FULL_DUPLEX;
1360 AE_WRITE_4(sc, AE_MAC_REG, val);
1362 } else { /* No link. */
1363 AE_WRITE_4(sc, AE_WOL_REG, AE_WOL_LNKCHG | \
1365 AE_WRITE_4(sc, AE_MAC_REG, 0);
1368 ae_powersave_enable(sc);
1372 * PCIE hacks. Magic numbers.
1374 val = AE_READ_4(sc, AE_PCIE_PHYMISC_REG);
1375 val |= AE_PCIE_PHYMISC_FORCE_RCV_DET;
1376 AE_WRITE_4(sc, AE_PCIE_PHYMISC_REG, val);
1377 val = AE_READ_4(sc, AE_PCIE_DLL_TX_CTRL_REG);
1378 val |= AE_PCIE_DLL_TX_CTRL_SEL_NOR_CLK;
1379 AE_WRITE_4(sc, AE_PCIE_DLL_TX_CTRL_REG, val);
1384 if (pci_find_cap(sc->dev, PCIY_PMG, &pmc) == 0) {
1385 pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
1386 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1387 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1388 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1389 pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1394 ae_suspend(device_t dev)
1398 sc = device_get_softc(dev);
1409 ae_resume(device_t dev)
1413 sc = device_get_softc(dev);
1414 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1417 AE_READ_4(sc, AE_WOL_REG); /* Clear WOL status. */
1418 if ((sc->ifp->if_flags & IFF_UP) != 0)
1426 ae_tx_avail_size(ae_softc_t *sc)
1430 if (sc->txd_cur >= sc->txd_ack)
1431 avail = AE_TXD_BUFSIZE_DEFAULT - (sc->txd_cur - sc->txd_ack);
1433 avail = sc->txd_ack - sc->txd_cur;
1439 ae_encap(ae_softc_t *sc, struct mbuf **m_head)
1443 unsigned int to_end;
1449 len = m0->m_pkthdr.len;
1451 if ((sc->flags & AE_FLAG_TXAVAIL) == 0 ||
1452 len + sizeof(ae_txd_t) + 3 > ae_tx_avail_size(sc)) {
1454 if_printf(sc->ifp, "No free Tx available.\n");
1459 hdr = (ae_txd_t *)(sc->txd_base + sc->txd_cur);
1460 bzero(hdr, sizeof(*hdr));
1461 /* Skip header size. */
1462 sc->txd_cur = (sc->txd_cur + sizeof(ae_txd_t)) % AE_TXD_BUFSIZE_DEFAULT;
1463 /* Space available to the end of the ring */
1464 to_end = AE_TXD_BUFSIZE_DEFAULT - sc->txd_cur;
1465 if (to_end >= len) {
1466 m_copydata(m0, 0, len, (caddr_t)(sc->txd_base + sc->txd_cur));
1468 m_copydata(m0, 0, to_end, (caddr_t)(sc->txd_base +
1470 m_copydata(m0, to_end, len - to_end, (caddr_t)sc->txd_base);
1474 * Set TxD flags and parameters.
1476 if ((m0->m_flags & M_VLANTAG) != 0) {
1477 hdr->vlan = htole16(AE_TXD_VLAN(m0->m_pkthdr.ether_vtag));
1478 hdr->len = htole16(len | AE_TXD_INSERT_VTAG);
1480 hdr->len = htole16(len);
1484 * Set current TxD position and round up to a 4-byte boundary.
1486 sc->txd_cur = ((sc->txd_cur + len + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1487 if (sc->txd_cur == sc->txd_ack)
1488 sc->flags &= ~AE_FLAG_TXAVAIL;
1490 if_printf(sc->ifp, "New txd_cur = %d.\n", sc->txd_cur);
1494 * Update TxS position and check if there are empty TxS available.
1496 sc->txs_base[sc->txs_cur].flags &= ~htole16(AE_TXS_UPDATE);
1497 sc->txs_cur = (sc->txs_cur + 1) % AE_TXS_COUNT_DEFAULT;
1498 if (sc->txs_cur == sc->txs_ack)
1499 sc->flags &= ~AE_FLAG_TXAVAIL;
1502 * Synchronize DMA memory.
1504 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map, BUS_DMASYNC_PREREAD |
1505 BUS_DMASYNC_PREWRITE);
1506 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1507 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1513 ae_start(struct ifnet *ifp)
1519 ae_start_locked(ifp);
1524 ae_start_locked(struct ifnet *ifp)
1532 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1536 if_printf(ifp, "Start called.\n");
1539 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1540 IFF_DRV_RUNNING || (sc->flags & AE_FLAG_LINK) == 0)
1544 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
1545 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0);
1547 break; /* Nothing to do. */
1549 error = ae_encap(sc, &m0);
1552 IFQ_DRV_PREPEND(&ifp->if_snd, m0);
1553 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1555 if_printf(ifp, "Setting OACTIVE.\n");
1563 /* Bounce a copy of the frame to BPF. */
1564 ETHER_BPF_MTAP(ifp, m0);
1569 if (count > 0) { /* Something was dequeued. */
1570 AE_WRITE_2(sc, AE_MB_TXD_IDX_REG, sc->txd_cur / 4);
1571 sc->wd_timer = AE_TX_TIMEOUT; /* Load watchdog. */
1573 if_printf(ifp, "%d packets dequeued.\n", count);
1574 if_printf(ifp, "Tx pos now is %d.\n", sc->txd_cur);
1580 ae_link_task(void *arg, int pending)
1583 struct mii_data *mii;
1587 sc = (ae_softc_t *)arg;
1588 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1592 mii = device_get_softc(sc->miibus);
1593 if (mii == NULL || ifp == NULL ||
1594 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1595 AE_UNLOCK(sc); /* XXX: could happen? */
1599 sc->flags &= ~AE_FLAG_LINK;
1600 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
1601 (IFM_AVALID | IFM_ACTIVE)) {
1602 switch(IFM_SUBTYPE(mii->mii_media_active)) {
1605 sc->flags |= AE_FLAG_LINK;
1618 if ((sc->flags & AE_FLAG_LINK) != 0) {
1622 * Restart DMA engines.
1624 AE_WRITE_1(sc, AE_DMAREAD_REG, AE_DMAREAD_EN);
1625 AE_WRITE_1(sc, AE_DMAWRITE_REG, AE_DMAWRITE_EN);
1628 * Enable Rx and Tx MACs.
1630 val = AE_READ_4(sc, AE_MAC_REG);
1631 val |= AE_MAC_TX_EN | AE_MAC_RX_EN;
1632 AE_WRITE_4(sc, AE_MAC_REG, val);
1638 ae_stop_rxmac(ae_softc_t *sc)
1646 * Stop Rx MAC engine.
1648 val = AE_READ_4(sc, AE_MAC_REG);
1649 if ((val & AE_MAC_RX_EN) != 0) {
1650 val &= ~AE_MAC_RX_EN;
1651 AE_WRITE_4(sc, AE_MAC_REG, val);
1655 * Stop Rx DMA engine.
1657 if (AE_READ_1(sc, AE_DMAWRITE_REG) == AE_DMAWRITE_EN)
1658 AE_WRITE_1(sc, AE_DMAWRITE_REG, 0);
1661 * Wait for IDLE state.
1663 for (i = 0; i < AE_IDLE_TIMEOUT; i--) {
1664 val = AE_READ_4(sc, AE_IDLE_REG);
1665 if ((val & (AE_IDLE_RXMAC | AE_IDLE_DMAWRITE)) == 0)
1669 if (i == AE_IDLE_TIMEOUT)
1670 device_printf(sc->dev, "timed out while stopping Rx MAC.\n");
1674 ae_stop_txmac(ae_softc_t *sc)
1682 * Stop Tx MAC engine.
1684 val = AE_READ_4(sc, AE_MAC_REG);
1685 if ((val & AE_MAC_TX_EN) != 0) {
1686 val &= ~AE_MAC_TX_EN;
1687 AE_WRITE_4(sc, AE_MAC_REG, val);
1691 * Stop Tx DMA engine.
1693 if (AE_READ_1(sc, AE_DMAREAD_REG) == AE_DMAREAD_EN)
1694 AE_WRITE_1(sc, AE_DMAREAD_REG, 0);
1697 * Wait for IDLE state.
1699 for (i = 0; i < AE_IDLE_TIMEOUT; i--) {
1700 val = AE_READ_4(sc, AE_IDLE_REG);
1701 if ((val & (AE_IDLE_TXMAC | AE_IDLE_DMAREAD)) == 0)
1705 if (i == AE_IDLE_TIMEOUT)
1706 device_printf(sc->dev, "timed out while stopping Tx MAC.\n");
1710 ae_mac_config(ae_softc_t *sc)
1712 struct mii_data *mii;
1717 mii = device_get_softc(sc->miibus);
1718 val = AE_READ_4(sc, AE_MAC_REG);
1719 val &= ~AE_MAC_FULL_DUPLEX;
1720 /* XXX disable AE_MAC_TX_FLOW_EN? */
1722 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1723 val |= AE_MAC_FULL_DUPLEX;
1725 AE_WRITE_4(sc, AE_MAC_REG, val);
1734 sc = (ae_softc_t *)arg;
1735 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL", __LINE__));
1737 val = AE_READ_4(sc, AE_ISR_REG);
1738 if (val == 0 || (val & AE_IMR_DEFAULT) == 0)
1739 return (FILTER_STRAY);
1741 /* Disable interrupts. */
1742 AE_WRITE_4(sc, AE_ISR_REG, AE_ISR_DISABLE);
1744 /* Schedule interrupt processing. */
1745 taskqueue_enqueue(sc->tq, &sc->int_task);
1747 return (FILTER_HANDLED);
1751 ae_int_task(void *arg, int pending)
1757 sc = (ae_softc_t *)arg;
1763 val = AE_READ_4(sc, AE_ISR_REG); /* Read interrupt status. */
1766 * Clear interrupts and disable them.
1768 AE_WRITE_4(sc, AE_ISR_REG, val | AE_ISR_DISABLE);
1771 if_printf(ifp, "Interrupt received: 0x%08x\n", val);
1774 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1775 if ((val & (AE_ISR_DMAR_TIMEOUT | AE_ISR_DMAW_TIMEOUT |
1776 AE_ISR_PHY_LINKDOWN)) != 0) {
1777 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1782 if ((val & AE_ISR_TX_EVENT) != 0)
1784 if ((val & AE_ISR_RX_EVENT) != 0)
1789 * Re-enable interrupts.
1791 AE_WRITE_4(sc, AE_ISR_REG, 0);
1797 ae_tx_intr(ae_softc_t *sc)
1809 if_printf(ifp, "Tx interrupt occuried.\n");
1813 * Syncronize DMA buffers.
1815 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1816 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1817 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1818 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1821 txs = sc->txs_base + sc->txs_ack;
1822 flags = le16toh(txs->flags);
1823 if ((flags & AE_TXS_UPDATE) == 0)
1825 txs->flags = htole16(flags & ~AE_TXS_UPDATE);
1827 ae_update_stats_tx(flags, &sc->stats);
1830 * Update TxS position.
1832 sc->txs_ack = (sc->txs_ack + 1) % AE_TXS_COUNT_DEFAULT;
1833 sc->flags |= AE_FLAG_TXAVAIL;
1835 txd = (ae_txd_t *)(sc->txd_base + sc->txd_ack);
1836 if (txs->len != txd->len)
1837 device_printf(sc->dev, "Size mismatch: TxS:%d TxD:%d\n",
1838 le16toh(txs->len), le16toh(txd->len));
1841 * Move txd ack and align on 4-byte boundary.
1843 sc->txd_ack = ((sc->txd_ack + le16toh(txd->len) +
1844 sizeof(ae_txs_t) + 3) & ~3) % AE_TXD_BUFSIZE_DEFAULT;
1846 if ((flags & AE_TXS_SUCCESS) != 0)
1853 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1856 if (sc->tx_inproc < 0) {
1857 if_printf(ifp, "Received stray Tx interrupt(s).\n");
1861 if (sc->tx_inproc == 0)
1862 sc->wd_timer = 0; /* Unarm watchdog. */
1864 if ((sc->flags & AE_FLAG_TXAVAIL) != 0) {
1865 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1866 ae_start_locked(ifp);
1870 * Syncronize DMA buffers.
1872 bus_dmamap_sync(sc->dma_txd_tag, sc->dma_txd_map,
1873 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1874 bus_dmamap_sync(sc->dma_txs_tag, sc->dma_txs_map,
1875 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1879 ae_rxeof(ae_softc_t *sc, ae_rxd_t *rxd)
1889 flags = le16toh(rxd->flags);
1892 if_printf(ifp, "Rx interrupt occuried.\n");
1894 size = le16toh(rxd->len) - ETHER_CRC_LEN;
1895 if (size < (ETHER_MIN_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)) {
1896 if_printf(ifp, "Runt frame received.");
1900 m = m_devget(&rxd->data[0], size, ETHER_ALIGN, ifp, NULL);
1904 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
1905 (flags & AE_RXD_HAS_VLAN) != 0) {
1906 m->m_pkthdr.ether_vtag = AE_RXD_VLAN(le16toh(rxd->vlan));
1907 m->m_flags |= M_VLANTAG;
1914 (*ifp->if_input)(ifp, m);
1921 ae_rx_intr(ae_softc_t *sc)
1928 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1935 * Syncronize DMA buffers.
1937 bus_dmamap_sync(sc->dma_rxd_tag, sc->dma_rxd_map,
1938 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1941 rxd = (ae_rxd_t *)(sc->rxd_base + sc->rxd_cur);
1942 flags = le16toh(rxd->flags);
1943 if ((flags & AE_RXD_UPDATE) == 0)
1945 rxd->flags = htole16(flags & ~AE_RXD_UPDATE);
1947 ae_update_stats_rx(flags, &sc->stats);
1950 * Update position index.
1952 sc->rxd_cur = (sc->rxd_cur + 1) % AE_RXD_COUNT_DEFAULT;
1954 if ((flags & AE_RXD_SUCCESS) == 0) {
1958 error = ae_rxeof(sc, rxd);
1970 AE_WRITE_2(sc, AE_MB_RXD_IDX_REG, sc->rxd_cur);
1974 ae_watchdog(ae_softc_t *sc)
1978 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
1982 if (sc->wd_timer == 0 || --sc->wd_timer != 0)
1983 return; /* Noting to do. */
1985 if ((sc->flags & AE_FLAG_LINK) == 0)
1986 if_printf(ifp, "watchdog timeout (missed link).\n");
1988 if_printf(ifp, "watchdog timeout - resetting.\n");
1991 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1993 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1994 ae_start_locked(ifp);
2001 struct mii_data *mii;
2003 sc = (ae_softc_t *)arg;
2004 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2007 mii = device_get_softc(sc->miibus);
2009 ae_watchdog(sc); /* Watchdog check. */
2010 callout_reset(&sc->tick_ch, hz, ae_tick, sc);
2014 ae_rxvlan(ae_softc_t *sc)
2021 val = AE_READ_4(sc, AE_MAC_REG);
2022 val &= ~AE_MAC_RMVLAN_EN;
2023 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2024 val |= AE_MAC_RMVLAN_EN;
2025 AE_WRITE_4(sc, AE_MAC_REG, val);
2029 ae_rxfilter(ae_softc_t *sc)
2032 struct ifmultiaddr *ifma;
2037 KASSERT(sc != NULL, ("[ae, %d]: sc is NULL!", __LINE__));
2043 rxcfg = AE_READ_4(sc, AE_MAC_REG);
2044 rxcfg &= ~(AE_MAC_MCAST_EN | AE_MAC_BCAST_EN | AE_MAC_PROMISC_EN);
2046 if ((ifp->if_flags & IFF_BROADCAST) != 0)
2047 rxcfg |= AE_MAC_BCAST_EN;
2048 if ((ifp->if_flags & IFF_PROMISC) != 0)
2049 rxcfg |= AE_MAC_PROMISC_EN;
2050 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2051 rxcfg |= AE_MAC_MCAST_EN;
2054 * Wipe old settings.
2056 AE_WRITE_4(sc, AE_REG_MHT0, 0);
2057 AE_WRITE_4(sc, AE_REG_MHT1, 0);
2058 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2059 AE_WRITE_4(sc, AE_REG_MHT0, 0xffffffff);
2060 AE_WRITE_4(sc, AE_REG_MHT1, 0xffffffff);
2061 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2066 * Load multicast tables.
2068 bzero(mchash, sizeof(mchash));
2069 if_maddr_rlock(ifp);
2070 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2071 if (ifma->ifma_addr->sa_family != AF_LINK)
2073 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2074 ifma->ifma_addr), ETHER_ADDR_LEN);
2075 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2077 if_maddr_runlock(ifp);
2078 AE_WRITE_4(sc, AE_REG_MHT0, mchash[0]);
2079 AE_WRITE_4(sc, AE_REG_MHT1, mchash[1]);
2080 AE_WRITE_4(sc, AE_MAC_REG, rxcfg);
2084 ae_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2086 struct ae_softc *sc;
2088 struct mii_data *mii;
2092 ifr = (struct ifreq *)data;
2097 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU)
2099 else if (ifp->if_mtu != ifr->ifr_mtu) {
2101 ifp->if_mtu = ifr->ifr_mtu;
2102 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2103 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2111 if ((ifp->if_flags & IFF_UP) != 0) {
2112 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2113 if (((ifp->if_flags ^ sc->if_flags)
2114 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
2117 if ((sc->flags & AE_FLAG_DETACH) == 0)
2121 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2124 sc->if_flags = ifp->if_flags;
2130 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2136 mii = device_get_softc(sc->miibus);
2137 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2141 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2142 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2143 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2144 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2147 VLAN_CAPABILITIES(ifp);
2151 error = ether_ioctl(ifp, cmd, data);
2158 ae_stop(ae_softc_t *sc)
2166 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2167 sc->flags &= ~AE_FLAG_LINK;
2168 sc->wd_timer = 0; /* Cancel watchdog. */
2169 callout_stop(&sc->tick_ch);
2172 * Clear and disable interrupts.
2174 AE_WRITE_4(sc, AE_IMR_REG, 0);
2175 AE_WRITE_4(sc, AE_ISR_REG, 0xffffffff);
2186 AE_WRITE_1(sc, AE_DMAREAD_REG, ~AE_DMAREAD_EN);
2187 AE_WRITE_1(sc, AE_DMAWRITE_REG, ~AE_DMAWRITE_EN);
2190 * Wait for everything to enter idle state.
2192 for (i = 0; i < AE_IDLE_TIMEOUT; i++) {
2193 if (AE_READ_4(sc, AE_IDLE_REG) == 0)
2197 if (i == AE_IDLE_TIMEOUT)
2198 device_printf(sc->dev, "could not enter idle state in stop.\n");
2202 ae_update_stats_tx(uint16_t flags, ae_stats_t *stats)
2205 if ((flags & AE_TXS_BCAST) != 0)
2207 if ((flags & AE_TXS_MCAST) != 0)
2209 if ((flags & AE_TXS_PAUSE) != 0)
2211 if ((flags & AE_TXS_CTRL) != 0)
2213 if ((flags & AE_TXS_DEFER) != 0)
2215 if ((flags & AE_TXS_EXCDEFER) != 0)
2216 stats->tx_excdefer++;
2217 if ((flags & AE_TXS_SINGLECOL) != 0)
2218 stats->tx_singlecol++;
2219 if ((flags & AE_TXS_MULTICOL) != 0)
2220 stats->tx_multicol++;
2221 if ((flags & AE_TXS_LATECOL) != 0)
2222 stats->tx_latecol++;
2223 if ((flags & AE_TXS_ABORTCOL) != 0)
2224 stats->tx_abortcol++;
2225 if ((flags & AE_TXS_UNDERRUN) != 0)
2226 stats->tx_underrun++;
2230 ae_update_stats_rx(uint16_t flags, ae_stats_t *stats)
2233 if ((flags & AE_RXD_BCAST) != 0)
2235 if ((flags & AE_RXD_MCAST) != 0)
2237 if ((flags & AE_RXD_PAUSE) != 0)
2239 if ((flags & AE_RXD_CTRL) != 0)
2241 if ((flags & AE_RXD_CRCERR) != 0)
2243 if ((flags & AE_RXD_CODEERR) != 0)
2244 stats->rx_codeerr++;
2245 if ((flags & AE_RXD_RUNT) != 0)
2247 if ((flags & AE_RXD_FRAG) != 0)
2249 if ((flags & AE_RXD_TRUNC) != 0)
2251 if ((flags & AE_RXD_ALIGN) != 0)