2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
36 #include <sys/endian.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
41 #include <sys/module.h>
42 #include <sys/queue.h>
43 #include <sys/socket.h>
44 #include <sys/sockio.h>
45 #include <sys/sysctl.h>
46 #include <sys/taskqueue.h>
50 #include <net/if_var.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_vlan_var.h>
58 #include <netinet/in.h>
59 #include <netinet/in_systm.h>
60 #include <netinet/ip.h>
61 #include <netinet/tcp.h>
63 #include <dev/mii/mii.h>
64 #include <dev/mii/miivar.h>
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
69 #include <machine/bus.h>
70 #include <machine/in_cksum.h>
72 #include <dev/age/if_agereg.h>
73 #include <dev/age/if_agevar.h>
75 /* "device miibus" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
78 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
80 MODULE_DEPEND(age, pci, 1, 1, 1);
81 MODULE_DEPEND(age, ether, 1, 1, 1);
82 MODULE_DEPEND(age, miibus, 1, 1, 1);
85 static int msi_disable = 0;
86 static int msix_disable = 0;
87 TUNABLE_INT("hw.age.msi_disable", &msi_disable);
88 TUNABLE_INT("hw.age.msix_disable", &msix_disable);
91 * Devices supported by this driver.
93 static struct age_dev {
94 uint16_t age_vendorid;
95 uint16_t age_deviceid;
98 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
99 "Attansic Technology Corp, L1 Gigabit Ethernet" },
102 static int age_miibus_readreg(device_t, int, int);
103 static int age_miibus_writereg(device_t, int, int, int);
104 static void age_miibus_statchg(device_t);
105 static void age_mediastatus(struct ifnet *, struct ifmediareq *);
106 static int age_mediachange(struct ifnet *);
107 static int age_probe(device_t);
108 static void age_get_macaddr(struct age_softc *);
109 static void age_phy_reset(struct age_softc *);
110 static int age_attach(device_t);
111 static int age_detach(device_t);
112 static void age_sysctl_node(struct age_softc *);
113 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
114 static int age_check_boundary(struct age_softc *);
115 static int age_dma_alloc(struct age_softc *);
116 static void age_dma_free(struct age_softc *);
117 static int age_shutdown(device_t);
118 static void age_setwol(struct age_softc *);
119 static int age_suspend(device_t);
120 static int age_resume(device_t);
121 static int age_encap(struct age_softc *, struct mbuf **);
122 static void age_start(struct ifnet *);
123 static void age_start_locked(struct ifnet *);
124 static void age_watchdog(struct age_softc *);
125 static int age_ioctl(struct ifnet *, u_long, caddr_t);
126 static void age_mac_config(struct age_softc *);
127 static void age_link_task(void *, int);
128 static void age_stats_update(struct age_softc *);
129 static int age_intr(void *);
130 static void age_int_task(void *, int);
131 static void age_txintr(struct age_softc *, int);
132 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *);
133 static int age_rxintr(struct age_softc *, int, int);
134 static void age_tick(void *);
135 static void age_reset(struct age_softc *);
136 static void age_init(void *);
137 static void age_init_locked(struct age_softc *);
138 static void age_stop(struct age_softc *);
139 static void age_stop_txmac(struct age_softc *);
140 static void age_stop_rxmac(struct age_softc *);
141 static void age_init_tx_ring(struct age_softc *);
142 static int age_init_rx_ring(struct age_softc *);
143 static void age_init_rr_ring(struct age_softc *);
144 static void age_init_cmb_block(struct age_softc *);
145 static void age_init_smb_block(struct age_softc *);
146 #ifndef __NO_STRICT_ALIGNMENT
147 static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *);
149 static int age_newbuf(struct age_softc *, struct age_rxdesc *);
150 static void age_rxvlan(struct age_softc *);
151 static void age_rxfilter(struct age_softc *);
152 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS);
153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
154 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS);
155 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
158 static device_method_t age_methods[] = {
159 /* Device interface. */
160 DEVMETHOD(device_probe, age_probe),
161 DEVMETHOD(device_attach, age_attach),
162 DEVMETHOD(device_detach, age_detach),
163 DEVMETHOD(device_shutdown, age_shutdown),
164 DEVMETHOD(device_suspend, age_suspend),
165 DEVMETHOD(device_resume, age_resume),
168 DEVMETHOD(miibus_readreg, age_miibus_readreg),
169 DEVMETHOD(miibus_writereg, age_miibus_writereg),
170 DEVMETHOD(miibus_statchg, age_miibus_statchg),
175 static driver_t age_driver = {
178 sizeof(struct age_softc)
181 static devclass_t age_devclass;
183 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0);
184 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0);
186 static struct resource_spec age_res_spec_mem[] = {
187 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE },
191 static struct resource_spec age_irq_spec_legacy[] = {
192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
196 static struct resource_spec age_irq_spec_msi[] = {
197 { SYS_RES_IRQ, 1, RF_ACTIVE },
201 static struct resource_spec age_irq_spec_msix[] = {
202 { SYS_RES_IRQ, 1, RF_ACTIVE },
207 * Read a PHY register on the MII of the L1.
210 age_miibus_readreg(device_t dev, int phy, int reg)
212 struct age_softc *sc;
216 sc = device_get_softc(dev);
218 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
219 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
220 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
222 v = CSR_READ_4(sc, AGE_MDIO);
223 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
228 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
232 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
236 * Write a PHY register on the MII of the L1.
239 age_miibus_writereg(device_t dev, int phy, int reg, int val)
241 struct age_softc *sc;
245 sc = device_get_softc(dev);
247 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
248 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
249 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
250 for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
252 v = CSR_READ_4(sc, AGE_MDIO);
253 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
258 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
264 * Callback from MII layer when media changes.
267 age_miibus_statchg(device_t dev)
269 struct age_softc *sc;
271 sc = device_get_softc(dev);
272 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task);
276 * Get the current interface media status.
279 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
281 struct age_softc *sc;
282 struct mii_data *mii;
286 mii = device_get_softc(sc->age_miibus);
289 ifmr->ifm_status = mii->mii_media_status;
290 ifmr->ifm_active = mii->mii_media_active;
295 * Set hardware to newly-selected media.
298 age_mediachange(struct ifnet *ifp)
300 struct age_softc *sc;
301 struct mii_data *mii;
302 struct mii_softc *miisc;
307 mii = device_get_softc(sc->age_miibus);
308 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
310 error = mii_mediachg(mii);
317 age_probe(device_t dev)
321 uint16_t vendor, devid;
323 vendor = pci_get_vendor(dev);
324 devid = pci_get_device(dev);
326 for (i = 0; i < nitems(age_devs); i++, sp++) {
327 if (vendor == sp->age_vendorid &&
328 devid == sp->age_deviceid) {
329 device_set_desc(dev, sp->age_name);
330 return (BUS_PROBE_DEFAULT);
338 age_get_macaddr(struct age_softc *sc)
343 reg = CSR_READ_4(sc, AGE_SPI_CTRL);
344 if ((reg & SPI_VPD_ENB) != 0) {
345 /* Get VPD stored in TWSI EEPROM. */
347 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
350 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) {
352 * PCI VPD capability found, let TWSI reload EEPROM.
353 * This will set ethernet address of controller.
355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
356 TWSI_CTRL_SW_LD_START);
357 for (i = 100; i > 0; i--) {
359 reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
360 if ((reg & TWSI_CTRL_SW_LD_START) == 0)
364 device_printf(sc->age_dev,
365 "reloading EEPROM timeout!\n");
368 device_printf(sc->age_dev,
369 "PCI VPD capability not found!\n");
372 ea[0] = CSR_READ_4(sc, AGE_PAR0);
373 ea[1] = CSR_READ_4(sc, AGE_PAR1);
374 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
375 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
376 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
377 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
378 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
379 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
383 age_phy_reset(struct age_softc *sc)
389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
391 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
394 #define ATPHY_DBG_ADDR 0x1D
395 #define ATPHY_DBG_DATA 0x1E
396 #define ATPHY_CDTC 0x16
397 #define PHY_CDTC_ENB 0x0001
398 #define PHY_CDTC_POFF 8
399 #define ATPHY_CDTS 0x1C
400 #define PHY_CDTS_STAT_OK 0x0000
401 #define PHY_CDTS_STAT_SHORT 0x0100
402 #define PHY_CDTS_STAT_OPEN 0x0200
403 #define PHY_CDTS_STAT_INVAL 0x0300
404 #define PHY_CDTS_STAT_MASK 0x0300
406 /* Check power saving mode. Magic from Linux. */
407 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
408 for (linkup = 0, pn = 0; pn < 4; pn++) {
409 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC,
410 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB);
411 for (i = 200; i > 0; i--) {
413 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
415 if ((reg & PHY_CDTC_ENB) == 0)
419 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
421 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) {
426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR,
427 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
429 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
431 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
432 ATPHY_DBG_DATA, 0x124E);
433 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
435 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr,
437 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
438 ATPHY_DBG_DATA, reg | 0x03);
441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
443 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
444 ATPHY_DBG_DATA, 0x024E);
447 #undef ATPHY_DBG_ADDR
448 #undef ATPHY_DBG_DATA
453 #undef PHY_CDTS_STAT_OK
454 #undef PHY_CDTS_STAT_SHORT
455 #undef PHY_CDTS_STAT_OPEN
456 #undef PHY_CDTS_STAT_INVAL
457 #undef PHY_CDTS_STAT_MASK
461 age_attach(device_t dev)
463 struct age_softc *sc;
466 int error, i, msic, msixc, pmc;
469 sc = device_get_softc(dev);
472 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
474 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0);
475 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc);
476 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc);
478 /* Map the device. */
479 pci_enable_busmaster(dev);
480 sc->age_res_spec = age_res_spec_mem;
481 sc->age_irq_spec = age_irq_spec_legacy;
482 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res);
484 device_printf(dev, "cannot allocate memory resources.\n");
488 /* Set PHY address. */
489 sc->age_phyaddr = AGE_PHY_ADDR;
494 /* Reset the ethernet controller. */
497 /* Get PCI and chip id/revision. */
498 sc->age_rev = pci_get_revid(dev);
499 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
500 MASTER_CHIP_REV_SHIFT;
502 device_printf(dev, "PCI device revision : 0x%04x\n",
504 device_printf(dev, "Chip id/revision : 0x%04x\n",
510 * Unintialized hardware returns an invalid chip id/revision
511 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
512 * unplugged cable results in putting hardware into automatic
513 * power down mode which in turn returns invalld chip revision.
515 if (sc->age_chip_rev == 0xFFFF) {
516 device_printf(dev,"invalid chip revision : 0x%04x -- "
517 "not initialized?\n", sc->age_chip_rev);
522 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
523 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
524 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
526 /* Allocate IRQ resources. */
527 msixc = pci_msix_count(dev);
528 msic = pci_msi_count(dev);
530 device_printf(dev, "MSIX count : %d\n", msixc);
531 device_printf(dev, "MSI count : %d\n", msic);
534 /* Prefer MSIX over MSI. */
535 if (msix_disable == 0 || msi_disable == 0) {
536 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES &&
537 pci_alloc_msix(dev, &msixc) == 0) {
538 if (msic == AGE_MSIX_MESSAGES) {
539 device_printf(dev, "Using %d MSIX messages.\n",
541 sc->age_flags |= AGE_FLAG_MSIX;
542 sc->age_irq_spec = age_irq_spec_msix;
544 pci_release_msi(dev);
546 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 &&
547 msic == AGE_MSI_MESSAGES &&
548 pci_alloc_msi(dev, &msic) == 0) {
549 if (msic == AGE_MSI_MESSAGES) {
550 device_printf(dev, "Using %d MSI messages.\n",
552 sc->age_flags |= AGE_FLAG_MSI;
553 sc->age_irq_spec = age_irq_spec_msi;
555 pci_release_msi(dev);
559 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq);
561 device_printf(dev, "cannot allocate IRQ resources.\n");
566 /* Get DMA parameters from PCIe device control register. */
567 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
568 sc->age_flags |= AGE_FLAG_PCIE;
569 burst = pci_read_config(dev, i + 0x08, 2);
570 /* Max read request size. */
571 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) <<
572 DMA_CFG_RD_BURST_SHIFT;
573 /* Max payload size. */
574 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) <<
575 DMA_CFG_WR_BURST_SHIFT;
577 device_printf(dev, "Read request size : %d bytes.\n",
578 128 << ((burst >> 12) & 0x07));
579 device_printf(dev, "TLP payload size : %d bytes.\n",
580 128 << ((burst >> 5) & 0x07));
583 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
584 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
587 /* Create device sysctl node. */
590 if ((error = age_dma_alloc(sc)) != 0)
593 /* Load station address. */
596 ifp = sc->age_ifp = if_alloc(IFT_ETHER);
598 device_printf(dev, "cannot allocate ifnet structure.\n");
604 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
606 ifp->if_ioctl = age_ioctl;
607 ifp->if_start = age_start;
608 ifp->if_init = age_init;
609 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1;
610 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
611 IFQ_SET_READY(&ifp->if_snd);
612 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
613 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO;
614 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
615 sc->age_flags |= AGE_FLAG_PMCAP;
616 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
618 ifp->if_capenable = ifp->if_capabilities;
620 /* Set up MII bus. */
621 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange,
622 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY,
625 device_printf(dev, "attaching PHYs failed\n");
629 ether_ifattach(ifp, sc->age_eaddr);
631 /* VLAN capability setup. */
632 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
633 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
634 ifp->if_capenable = ifp->if_capabilities;
636 /* Tell the upper layer(s) we support long frames. */
637 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
639 /* Create local taskq. */
640 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK,
641 taskqueue_thread_enqueue, &sc->age_tq);
642 if (sc->age_tq == NULL) {
643 device_printf(dev, "could not create taskqueue.\n");
648 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq",
649 device_get_nameunit(sc->age_dev));
651 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
652 msic = AGE_MSIX_MESSAGES;
653 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
654 msic = AGE_MSI_MESSAGES;
657 for (i = 0; i < msic; i++) {
658 error = bus_setup_intr(dev, sc->age_irq[i],
659 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc,
660 &sc->age_intrhand[i]);
665 device_printf(dev, "could not set up interrupt handler.\n");
666 taskqueue_free(sc->age_tq);
680 age_detach(device_t dev)
682 struct age_softc *sc;
686 sc = device_get_softc(dev);
689 if (device_is_attached(dev)) {
691 sc->age_flags |= AGE_FLAG_DETACH;
694 callout_drain(&sc->age_tick_ch);
695 taskqueue_drain(sc->age_tq, &sc->age_int_task);
696 taskqueue_drain(taskqueue_swi, &sc->age_link_task);
700 if (sc->age_tq != NULL) {
701 taskqueue_drain(sc->age_tq, &sc->age_int_task);
702 taskqueue_free(sc->age_tq);
706 if (sc->age_miibus != NULL) {
707 device_delete_child(dev, sc->age_miibus);
708 sc->age_miibus = NULL;
710 bus_generic_detach(dev);
718 if ((sc->age_flags & AGE_FLAG_MSIX) != 0)
719 msic = AGE_MSIX_MESSAGES;
720 else if ((sc->age_flags & AGE_FLAG_MSI) != 0)
721 msic = AGE_MSI_MESSAGES;
724 for (i = 0; i < msic; i++) {
725 if (sc->age_intrhand[i] != NULL) {
726 bus_teardown_intr(dev, sc->age_irq[i],
727 sc->age_intrhand[i]);
728 sc->age_intrhand[i] = NULL;
732 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq);
733 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0)
734 pci_release_msi(dev);
735 bus_release_resources(dev, sc->age_res_spec, sc->age_res);
736 mtx_destroy(&sc->age_mtx);
742 age_sysctl_node(struct age_softc *sc)
746 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
747 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
748 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats,
751 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
752 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
753 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0,
754 sysctl_hw_age_int_mod, "I", "age interrupt moderation");
756 /* Pull in device tunables. */
757 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
758 error = resource_int_value(device_get_name(sc->age_dev),
759 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
761 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
762 sc->age_int_mod > AGE_IM_TIMER_MAX) {
763 device_printf(sc->age_dev,
764 "int_mod value out of range; using default: %d\n",
765 AGE_IM_TIMER_DEFAULT);
766 sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
770 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev),
771 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO,
772 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit,
773 0, sysctl_hw_age_proc_limit, "I",
774 "max number of Rx events to process");
776 /* Pull in device tunables. */
777 sc->age_process_limit = AGE_PROC_DEFAULT;
778 error = resource_int_value(device_get_name(sc->age_dev),
779 device_get_unit(sc->age_dev), "process_limit",
780 &sc->age_process_limit);
782 if (sc->age_process_limit < AGE_PROC_MIN ||
783 sc->age_process_limit > AGE_PROC_MAX) {
784 device_printf(sc->age_dev,
785 "process_limit value out of range; "
786 "using default: %d\n", AGE_PROC_DEFAULT);
787 sc->age_process_limit = AGE_PROC_DEFAULT;
792 struct age_dmamap_arg {
793 bus_addr_t age_busaddr;
797 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
799 struct age_dmamap_arg *ctx;
804 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
806 ctx = (struct age_dmamap_arg *)arg;
807 ctx->age_busaddr = segs[0].ds_addr;
811 * Attansic L1 controller have single register to specify high
812 * address part of DMA blocks. So all descriptor structures and
813 * DMA memory blocks should have the same high address of given
814 * 4GB address space(i.e. crossing 4GB boundary is not allowed).
817 age_check_boundary(struct age_softc *sc)
819 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
820 bus_addr_t cmb_block_end, smb_block_end;
822 /* Tx/Rx descriptor queue should reside within 4GB boundary. */
823 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
824 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
825 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
826 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
827 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
829 if ((AGE_ADDR_HI(tx_ring_end) !=
830 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
831 (AGE_ADDR_HI(rx_ring_end) !=
832 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
833 (AGE_ADDR_HI(rr_ring_end) !=
834 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
835 (AGE_ADDR_HI(cmb_block_end) !=
836 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
837 (AGE_ADDR_HI(smb_block_end) !=
838 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
841 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
842 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
843 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
844 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
851 age_dma_alloc(struct age_softc *sc)
853 struct age_txdesc *txd;
854 struct age_rxdesc *rxd;
856 struct age_dmamap_arg ctx;
859 lowaddr = BUS_SPACE_MAXADDR;
862 /* Create parent ring/DMA block tag. */
863 error = bus_dma_tag_create(
864 bus_get_dma_tag(sc->age_dev), /* parent */
865 1, 0, /* alignment, boundary */
866 lowaddr, /* lowaddr */
867 BUS_SPACE_MAXADDR, /* highaddr */
868 NULL, NULL, /* filter, filterarg */
869 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
871 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
873 NULL, NULL, /* lockfunc, lockarg */
874 &sc->age_cdata.age_parent_tag);
876 device_printf(sc->age_dev,
877 "could not create parent DMA tag.\n");
881 /* Create tag for Tx ring. */
882 error = bus_dma_tag_create(
883 sc->age_cdata.age_parent_tag, /* parent */
884 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */
885 BUS_SPACE_MAXADDR, /* lowaddr */
886 BUS_SPACE_MAXADDR, /* highaddr */
887 NULL, NULL, /* filter, filterarg */
888 AGE_TX_RING_SZ, /* maxsize */
890 AGE_TX_RING_SZ, /* maxsegsize */
892 NULL, NULL, /* lockfunc, lockarg */
893 &sc->age_cdata.age_tx_ring_tag);
895 device_printf(sc->age_dev,
896 "could not create Tx ring DMA tag.\n");
900 /* Create tag for Rx ring. */
901 error = bus_dma_tag_create(
902 sc->age_cdata.age_parent_tag, /* parent */
903 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */
904 BUS_SPACE_MAXADDR, /* lowaddr */
905 BUS_SPACE_MAXADDR, /* highaddr */
906 NULL, NULL, /* filter, filterarg */
907 AGE_RX_RING_SZ, /* maxsize */
909 AGE_RX_RING_SZ, /* maxsegsize */
911 NULL, NULL, /* lockfunc, lockarg */
912 &sc->age_cdata.age_rx_ring_tag);
914 device_printf(sc->age_dev,
915 "could not create Rx ring DMA tag.\n");
919 /* Create tag for Rx return ring. */
920 error = bus_dma_tag_create(
921 sc->age_cdata.age_parent_tag, /* parent */
922 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */
923 BUS_SPACE_MAXADDR, /* lowaddr */
924 BUS_SPACE_MAXADDR, /* highaddr */
925 NULL, NULL, /* filter, filterarg */
926 AGE_RR_RING_SZ, /* maxsize */
928 AGE_RR_RING_SZ, /* maxsegsize */
930 NULL, NULL, /* lockfunc, lockarg */
931 &sc->age_cdata.age_rr_ring_tag);
933 device_printf(sc->age_dev,
934 "could not create Rx return ring DMA tag.\n");
938 /* Create tag for coalesing message block. */
939 error = bus_dma_tag_create(
940 sc->age_cdata.age_parent_tag, /* parent */
941 AGE_CMB_ALIGN, 0, /* alignment, boundary */
942 BUS_SPACE_MAXADDR, /* lowaddr */
943 BUS_SPACE_MAXADDR, /* highaddr */
944 NULL, NULL, /* filter, filterarg */
945 AGE_CMB_BLOCK_SZ, /* maxsize */
947 AGE_CMB_BLOCK_SZ, /* maxsegsize */
949 NULL, NULL, /* lockfunc, lockarg */
950 &sc->age_cdata.age_cmb_block_tag);
952 device_printf(sc->age_dev,
953 "could not create CMB DMA tag.\n");
957 /* Create tag for statistics message block. */
958 error = bus_dma_tag_create(
959 sc->age_cdata.age_parent_tag, /* parent */
960 AGE_SMB_ALIGN, 0, /* alignment, boundary */
961 BUS_SPACE_MAXADDR, /* lowaddr */
962 BUS_SPACE_MAXADDR, /* highaddr */
963 NULL, NULL, /* filter, filterarg */
964 AGE_SMB_BLOCK_SZ, /* maxsize */
966 AGE_SMB_BLOCK_SZ, /* maxsegsize */
968 NULL, NULL, /* lockfunc, lockarg */
969 &sc->age_cdata.age_smb_block_tag);
971 device_printf(sc->age_dev,
972 "could not create SMB DMA tag.\n");
976 /* Allocate DMA'able memory and load the DMA map. */
977 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
978 (void **)&sc->age_rdata.age_tx_ring,
979 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
980 &sc->age_cdata.age_tx_ring_map);
982 device_printf(sc->age_dev,
983 "could not allocate DMA'able memory for Tx ring.\n");
987 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
988 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
989 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
990 if (error != 0 || ctx.age_busaddr == 0) {
991 device_printf(sc->age_dev,
992 "could not load DMA'able memory for Tx ring.\n");
995 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
997 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
998 (void **)&sc->age_rdata.age_rx_ring,
999 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1000 &sc->age_cdata.age_rx_ring_map);
1002 device_printf(sc->age_dev,
1003 "could not allocate DMA'able memory for Rx ring.\n");
1006 ctx.age_busaddr = 0;
1007 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
1008 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
1009 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
1010 if (error != 0 || ctx.age_busaddr == 0) {
1011 device_printf(sc->age_dev,
1012 "could not load DMA'able memory for Rx ring.\n");
1015 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
1016 /* Rx return ring */
1017 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
1018 (void **)&sc->age_rdata.age_rr_ring,
1019 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1020 &sc->age_cdata.age_rr_ring_map);
1022 device_printf(sc->age_dev,
1023 "could not allocate DMA'able memory for Rx return ring.\n");
1026 ctx.age_busaddr = 0;
1027 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
1028 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
1029 AGE_RR_RING_SZ, age_dmamap_cb,
1031 if (error != 0 || ctx.age_busaddr == 0) {
1032 device_printf(sc->age_dev,
1033 "could not load DMA'able memory for Rx return ring.\n");
1036 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
1038 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
1039 (void **)&sc->age_rdata.age_cmb_block,
1040 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1041 &sc->age_cdata.age_cmb_block_map);
1043 device_printf(sc->age_dev,
1044 "could not allocate DMA'able memory for CMB block.\n");
1047 ctx.age_busaddr = 0;
1048 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1049 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1050 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1051 if (error != 0 || ctx.age_busaddr == 0) {
1052 device_printf(sc->age_dev,
1053 "could not load DMA'able memory for CMB block.\n");
1056 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1058 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1059 (void **)&sc->age_rdata.age_smb_block,
1060 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1061 &sc->age_cdata.age_smb_block_map);
1063 device_printf(sc->age_dev,
1064 "could not allocate DMA'able memory for SMB block.\n");
1067 ctx.age_busaddr = 0;
1068 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1069 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1070 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1071 if (error != 0 || ctx.age_busaddr == 0) {
1072 device_printf(sc->age_dev,
1073 "could not load DMA'able memory for SMB block.\n");
1076 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1079 * All ring buffer and DMA blocks should have the same
1080 * high address part of 64bit DMA address space.
1082 if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1083 (error = age_check_boundary(sc)) != 0) {
1084 device_printf(sc->age_dev, "4GB boundary crossed, "
1085 "switching to 32bit DMA addressing mode.\n");
1087 /* Limit DMA address space to 32bit and try again. */
1088 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1093 * Create Tx/Rx buffer parent tag.
1094 * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1095 * so it needs separate parent DMA tag.
1097 * It seems enabling 64bit DMA causes data corruption. Limit
1098 * DMA address space to 32bit.
1100 error = bus_dma_tag_create(
1101 bus_get_dma_tag(sc->age_dev), /* parent */
1102 1, 0, /* alignment, boundary */
1103 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1104 BUS_SPACE_MAXADDR, /* highaddr */
1105 NULL, NULL, /* filter, filterarg */
1106 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
1108 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1110 NULL, NULL, /* lockfunc, lockarg */
1111 &sc->age_cdata.age_buffer_tag);
1113 device_printf(sc->age_dev,
1114 "could not create parent buffer DMA tag.\n");
1118 /* Create tag for Tx buffers. */
1119 error = bus_dma_tag_create(
1120 sc->age_cdata.age_buffer_tag, /* parent */
1121 1, 0, /* alignment, boundary */
1122 BUS_SPACE_MAXADDR, /* lowaddr */
1123 BUS_SPACE_MAXADDR, /* highaddr */
1124 NULL, NULL, /* filter, filterarg */
1125 AGE_TSO_MAXSIZE, /* maxsize */
1126 AGE_MAXTXSEGS, /* nsegments */
1127 AGE_TSO_MAXSEGSIZE, /* maxsegsize */
1129 NULL, NULL, /* lockfunc, lockarg */
1130 &sc->age_cdata.age_tx_tag);
1132 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1136 /* Create tag for Rx buffers. */
1137 error = bus_dma_tag_create(
1138 sc->age_cdata.age_buffer_tag, /* parent */
1139 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */
1140 BUS_SPACE_MAXADDR, /* lowaddr */
1141 BUS_SPACE_MAXADDR, /* highaddr */
1142 NULL, NULL, /* filter, filterarg */
1143 MCLBYTES, /* maxsize */
1145 MCLBYTES, /* maxsegsize */
1147 NULL, NULL, /* lockfunc, lockarg */
1148 &sc->age_cdata.age_rx_tag);
1150 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1154 /* Create DMA maps for Tx buffers. */
1155 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1156 txd = &sc->age_cdata.age_txdesc[i];
1158 txd->tx_dmamap = NULL;
1159 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1162 device_printf(sc->age_dev,
1163 "could not create Tx dmamap.\n");
1167 /* Create DMA maps for Rx buffers. */
1168 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1169 &sc->age_cdata.age_rx_sparemap)) != 0) {
1170 device_printf(sc->age_dev,
1171 "could not create spare Rx dmamap.\n");
1174 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1175 rxd = &sc->age_cdata.age_rxdesc[i];
1177 rxd->rx_dmamap = NULL;
1178 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1181 device_printf(sc->age_dev,
1182 "could not create Rx dmamap.\n");
1192 age_dma_free(struct age_softc *sc)
1194 struct age_txdesc *txd;
1195 struct age_rxdesc *rxd;
1199 if (sc->age_cdata.age_tx_tag != NULL) {
1200 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1201 txd = &sc->age_cdata.age_txdesc[i];
1202 if (txd->tx_dmamap != NULL) {
1203 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1205 txd->tx_dmamap = NULL;
1208 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1209 sc->age_cdata.age_tx_tag = NULL;
1212 if (sc->age_cdata.age_rx_tag != NULL) {
1213 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1214 rxd = &sc->age_cdata.age_rxdesc[i];
1215 if (rxd->rx_dmamap != NULL) {
1216 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1218 rxd->rx_dmamap = NULL;
1221 if (sc->age_cdata.age_rx_sparemap != NULL) {
1222 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1223 sc->age_cdata.age_rx_sparemap);
1224 sc->age_cdata.age_rx_sparemap = NULL;
1226 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1227 sc->age_cdata.age_rx_tag = NULL;
1230 if (sc->age_cdata.age_tx_ring_tag != NULL) {
1231 if (sc->age_rdata.age_tx_ring_paddr != 0)
1232 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1233 sc->age_cdata.age_tx_ring_map);
1234 if (sc->age_rdata.age_tx_ring != NULL)
1235 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1236 sc->age_rdata.age_tx_ring,
1237 sc->age_cdata.age_tx_ring_map);
1238 sc->age_rdata.age_tx_ring_paddr = 0;
1239 sc->age_rdata.age_tx_ring = NULL;
1240 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1241 sc->age_cdata.age_tx_ring_tag = NULL;
1244 if (sc->age_cdata.age_rx_ring_tag != NULL) {
1245 if (sc->age_rdata.age_rx_ring_paddr != 0)
1246 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1247 sc->age_cdata.age_rx_ring_map);
1248 if (sc->age_rdata.age_rx_ring != NULL)
1249 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1250 sc->age_rdata.age_rx_ring,
1251 sc->age_cdata.age_rx_ring_map);
1252 sc->age_rdata.age_rx_ring_paddr = 0;
1253 sc->age_rdata.age_rx_ring = NULL;
1254 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1255 sc->age_cdata.age_rx_ring_tag = NULL;
1257 /* Rx return ring. */
1258 if (sc->age_cdata.age_rr_ring_tag != NULL) {
1259 if (sc->age_rdata.age_rr_ring_paddr != 0)
1260 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1261 sc->age_cdata.age_rr_ring_map);
1262 if (sc->age_rdata.age_rr_ring != NULL)
1263 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1264 sc->age_rdata.age_rr_ring,
1265 sc->age_cdata.age_rr_ring_map);
1266 sc->age_rdata.age_rr_ring_paddr = 0;
1267 sc->age_rdata.age_rr_ring = NULL;
1268 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1269 sc->age_cdata.age_rr_ring_tag = NULL;
1272 if (sc->age_cdata.age_cmb_block_tag != NULL) {
1273 if (sc->age_rdata.age_cmb_block_paddr != 0)
1274 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1275 sc->age_cdata.age_cmb_block_map);
1276 if (sc->age_rdata.age_cmb_block != NULL)
1277 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1278 sc->age_rdata.age_cmb_block,
1279 sc->age_cdata.age_cmb_block_map);
1280 sc->age_rdata.age_cmb_block_paddr = 0;
1281 sc->age_rdata.age_cmb_block = NULL;
1282 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1283 sc->age_cdata.age_cmb_block_tag = NULL;
1286 if (sc->age_cdata.age_smb_block_tag != NULL) {
1287 if (sc->age_rdata.age_smb_block_paddr != 0)
1288 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1289 sc->age_cdata.age_smb_block_map);
1290 if (sc->age_rdata.age_smb_block != NULL)
1291 bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1292 sc->age_rdata.age_smb_block,
1293 sc->age_cdata.age_smb_block_map);
1294 sc->age_rdata.age_smb_block_paddr = 0;
1295 sc->age_rdata.age_smb_block = NULL;
1296 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1297 sc->age_cdata.age_smb_block_tag = NULL;
1300 if (sc->age_cdata.age_buffer_tag != NULL) {
1301 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1302 sc->age_cdata.age_buffer_tag = NULL;
1304 if (sc->age_cdata.age_parent_tag != NULL) {
1305 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1306 sc->age_cdata.age_parent_tag = NULL;
1311 * Make sure the interface is stopped at reboot time.
1314 age_shutdown(device_t dev)
1317 return (age_suspend(dev));
1321 age_setwol(struct age_softc *sc)
1324 struct mii_data *mii;
1329 AGE_LOCK_ASSERT(sc);
1331 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) {
1332 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1334 * No PME capability, PHY power down.
1336 * Due to an unknown reason powering down PHY resulted
1337 * in unexpected results such as inaccessbility of
1338 * hardware of freshly rebooted system. Disable
1339 * powering down PHY until I got more information for
1340 * Attansic/Atheros PHY hardwares.
1343 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1344 MII_BMCR, BMCR_PDOWN);
1350 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1352 * Note, this driver resets the link speed to 10/100Mbps with
1353 * auto-negotiation but we don't know whether that operation
1354 * would succeed or not as it have no control after powering
1355 * off. If the renegotiation fail WOL may not work. Running
1356 * at 1Gbps will draw more power than 375mA at 3.3V which is
1357 * specified in PCI specification and that would result in
1358 * complete shutdowning power to ethernet controller.
1361 * Save current negotiated media speed/duplex/flow-control
1362 * to softc and restore the same link again after resuming.
1363 * PHY handling such as power down/resetting to 100Mbps
1364 * may be better handled in suspend method in phy driver.
1366 mii = device_get_softc(sc->age_miibus);
1369 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1370 switch IFM_SUBTYPE(mii->mii_media_active) {
1380 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1382 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1383 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1384 ANAR_10 | ANAR_CSMA);
1385 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1386 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1389 /* Poll link state until age(4) get a 10/100 link. */
1390 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1392 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1393 switch (IFM_SUBTYPE(
1394 mii->mii_media_active)) {
1404 pause("agelnk", hz);
1407 if (i == MII_ANEGTICKS_GIGE)
1408 device_printf(sc->age_dev,
1409 "establishing link failed, "
1410 "WOL may not work!");
1413 * No link, force MAC to have 100Mbps, full-duplex link.
1414 * This is the last resort and may/may not work.
1416 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1417 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1423 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1424 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1425 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1426 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1427 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1428 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1429 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1430 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1431 if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1432 reg |= MAC_CFG_RX_ENB;
1433 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1437 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1438 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1439 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1440 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1441 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1443 /* See above for powering down PHY issues. */
1444 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1445 /* No WOL, PHY power down. */
1446 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1447 MII_BMCR, BMCR_PDOWN);
1453 age_suspend(device_t dev)
1455 struct age_softc *sc;
1457 sc = device_get_softc(dev);
1468 age_resume(device_t dev)
1470 struct age_softc *sc;
1473 sc = device_get_softc(dev);
1478 if ((ifp->if_flags & IFF_UP) != 0)
1479 age_init_locked(sc);
1487 age_encap(struct age_softc *sc, struct mbuf **m_head)
1489 struct age_txdesc *txd, *txd_last;
1490 struct tx_desc *desc;
1494 bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1496 uint32_t cflags, hdrlen, ip_off, poff, vtag;
1497 int error, i, nsegs, prod, si;
1499 AGE_LOCK_ASSERT(sc);
1501 M_ASSERTPKTHDR((*m_head));
1508 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1510 * L1 requires offset of TCP/UDP payload in its Tx
1511 * descriptor to perform hardware Tx checksum offload.
1512 * Additionally, TSO requires IP/TCP header size and
1513 * modification of IP/TCP header in order to make TSO
1514 * engine work. This kind of operation takes many CPU
1515 * cycles on FreeBSD so fast host CPU is needed to get
1516 * smooth TSO performance.
1518 struct ether_header *eh;
1520 if (M_WRITABLE(m) == 0) {
1521 /* Get a writable copy. */
1522 m = m_dup(*m_head, M_NOWAIT);
1523 /* Release original mbufs. */
1531 ip_off = sizeof(struct ether_header);
1532 m = m_pullup(m, ip_off);
1537 eh = mtod(m, struct ether_header *);
1539 * Check if hardware VLAN insertion is off.
1540 * Additional check for LLC/SNAP frame?
1542 if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1543 ip_off = sizeof(struct ether_vlan_header);
1544 m = m_pullup(m, ip_off);
1550 m = m_pullup(m, ip_off + sizeof(struct ip));
1555 ip = (struct ip *)(mtod(m, char *) + ip_off);
1556 poff = ip_off + (ip->ip_hl << 2);
1557 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1558 m = m_pullup(m, poff + sizeof(struct tcphdr));
1563 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1564 m = m_pullup(m, poff + (tcp->th_off << 2));
1570 * L1 requires IP/TCP header size and offset as
1571 * well as TCP pseudo checksum which complicates
1572 * TSO configuration. I guess this comes from the
1573 * adherence to Microsoft NDIS Large Send
1574 * specification which requires insertion of
1575 * pseudo checksum by upper stack. The pseudo
1576 * checksum that NDIS refers to doesn't include
1577 * TCP payload length so age(4) should recompute
1578 * the pseudo checksum here. Hopefully this wouldn't
1579 * be much burden on modern CPUs.
1580 * Reset IP checksum and recompute TCP pseudo
1581 * checksum as NDIS specification said.
1583 ip = (struct ip *)(mtod(m, char *) + ip_off);
1584 tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1586 tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1587 ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1592 si = prod = sc->age_cdata.age_tx_prod;
1593 txd = &sc->age_cdata.age_txdesc[prod];
1595 map = txd->tx_dmamap;
1597 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1598 *m_head, txsegs, &nsegs, 0);
1599 if (error == EFBIG) {
1600 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS);
1607 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map,
1608 *m_head, txsegs, &nsegs, 0);
1614 } else if (error != 0)
1622 /* Check descriptor overrun. */
1623 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1624 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1629 /* Configure VLAN hardware tag insertion. */
1630 if ((m->m_flags & M_VLANTAG) != 0) {
1631 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1632 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1633 cflags |= AGE_TD_INSERT_VLAN_TAG;
1638 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1639 /* Request TSO and set MSS. */
1640 cflags |= AGE_TD_TSO_IPV4;
1641 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM;
1642 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz <<
1643 AGE_TD_TSO_MSS_SHIFT);
1644 /* Set IP/TCP header size. */
1645 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT;
1646 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT;
1648 * L1 requires the first buffer should only hold IP/TCP
1649 * header data. TCP payload should be handled in other
1652 hdrlen = poff + (tcp->th_off << 2);
1653 desc = &sc->age_rdata.age_tx_ring[prod];
1654 desc->addr = htole64(txsegs[0].ds_addr);
1655 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag);
1656 desc->flags = htole32(cflags);
1657 sc->age_cdata.age_tx_cnt++;
1658 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1659 if (m->m_len - hdrlen > 0) {
1660 /* Handle remaining payload of the 1st fragment. */
1661 desc = &sc->age_rdata.age_tx_ring[prod];
1662 desc->addr = htole64(txsegs[0].ds_addr + hdrlen);
1663 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) |
1665 desc->flags = htole32(cflags);
1666 sc->age_cdata.age_tx_cnt++;
1667 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1669 /* Handle remaining fragments. */
1671 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1672 /* Configure Tx IP/TCP/UDP checksum offload. */
1673 cflags |= AGE_TD_CSUM;
1674 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1675 cflags |= AGE_TD_TCPCSUM;
1676 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1677 cflags |= AGE_TD_UDPCSUM;
1678 /* Set checksum start offset. */
1679 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1680 /* Set checksum insertion position of TCP/UDP. */
1681 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1682 AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1684 for (; i < nsegs; i++) {
1685 desc = &sc->age_rdata.age_tx_ring[prod];
1686 desc->addr = htole64(txsegs[i].ds_addr);
1687 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1688 desc->flags = htole32(cflags);
1689 sc->age_cdata.age_tx_cnt++;
1690 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1692 /* Update producer index. */
1693 sc->age_cdata.age_tx_prod = prod;
1695 /* Set EOP on the last descriptor. */
1696 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1697 desc = &sc->age_rdata.age_tx_ring[prod];
1698 desc->flags |= htole32(AGE_TD_EOP);
1700 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */
1701 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1702 desc = &sc->age_rdata.age_tx_ring[si];
1703 desc->flags |= htole32(AGE_TD_TSO_HDR);
1706 /* Swap dmamap of the first and the last. */
1707 txd = &sc->age_cdata.age_txdesc[prod];
1708 map = txd_last->tx_dmamap;
1709 txd_last->tx_dmamap = txd->tx_dmamap;
1710 txd->tx_dmamap = map;
1713 /* Sync descriptors. */
1714 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1715 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1716 sc->age_cdata.age_tx_ring_map,
1717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1723 age_start(struct ifnet *ifp)
1725 struct age_softc *sc;
1729 age_start_locked(ifp);
1734 age_start_locked(struct ifnet *ifp)
1736 struct age_softc *sc;
1737 struct mbuf *m_head;
1742 AGE_LOCK_ASSERT(sc);
1744 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1745 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0)
1748 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1749 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1753 * Pack the data into the transmit ring. If we
1754 * don't have room, set the OACTIVE flag and wait
1755 * for the NIC to drain the ring.
1757 if (age_encap(sc, &m_head)) {
1760 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1761 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1767 * If there's a BPF listener, bounce a copy of this frame
1770 ETHER_BPF_MTAP(ifp, m_head);
1775 AGE_COMMIT_MBOX(sc);
1776 /* Set a timeout in case the chip goes out to lunch. */
1777 sc->age_watchdog_timer = AGE_TX_TIMEOUT;
1782 age_watchdog(struct age_softc *sc)
1786 AGE_LOCK_ASSERT(sc);
1788 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer)
1792 if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1793 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n");
1794 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1795 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1796 age_init_locked(sc);
1799 if (sc->age_cdata.age_tx_cnt == 0) {
1800 if_printf(sc->age_ifp,
1801 "watchdog timeout (missed Tx interrupts) -- recovering\n");
1802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1803 age_start_locked(ifp);
1806 if_printf(sc->age_ifp, "watchdog timeout\n");
1807 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1808 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1809 age_init_locked(sc);
1810 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1811 age_start_locked(ifp);
1815 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1817 struct age_softc *sc;
1819 struct mii_data *mii;
1824 ifr = (struct ifreq *)data;
1828 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU)
1830 else if (ifp->if_mtu != ifr->ifr_mtu) {
1832 ifp->if_mtu = ifr->ifr_mtu;
1833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1834 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1835 age_init_locked(sc);
1842 if ((ifp->if_flags & IFF_UP) != 0) {
1843 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1844 if (((ifp->if_flags ^ sc->age_if_flags)
1845 & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1848 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1849 age_init_locked(sc);
1852 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1855 sc->age_if_flags = ifp->if_flags;
1861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1867 mii = device_get_softc(sc->age_miibus);
1868 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1872 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1873 if ((mask & IFCAP_TXCSUM) != 0 &&
1874 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1875 ifp->if_capenable ^= IFCAP_TXCSUM;
1876 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1877 ifp->if_hwassist |= AGE_CSUM_FEATURES;
1879 ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1881 if ((mask & IFCAP_RXCSUM) != 0 &&
1882 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1883 ifp->if_capenable ^= IFCAP_RXCSUM;
1884 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1885 reg &= ~MAC_CFG_RXCSUM_ENB;
1886 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1887 reg |= MAC_CFG_RXCSUM_ENB;
1888 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1890 if ((mask & IFCAP_TSO4) != 0 &&
1891 (ifp->if_capabilities & IFCAP_TSO4) != 0) {
1892 ifp->if_capenable ^= IFCAP_TSO4;
1893 if ((ifp->if_capenable & IFCAP_TSO4) != 0)
1894 ifp->if_hwassist |= CSUM_TSO;
1896 ifp->if_hwassist &= ~CSUM_TSO;
1899 if ((mask & IFCAP_WOL_MCAST) != 0 &&
1900 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
1901 ifp->if_capenable ^= IFCAP_WOL_MCAST;
1902 if ((mask & IFCAP_WOL_MAGIC) != 0 &&
1903 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
1904 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
1905 if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1906 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
1907 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1908 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1909 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
1910 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1911 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1912 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1913 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1914 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
1915 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
1919 VLAN_CAPABILITIES(ifp);
1922 error = ether_ioctl(ifp, cmd, data);
1930 age_mac_config(struct age_softc *sc)
1932 struct mii_data *mii;
1935 AGE_LOCK_ASSERT(sc);
1937 mii = device_get_softc(sc->age_miibus);
1938 reg = CSR_READ_4(sc, AGE_MAC_CFG);
1939 reg &= ~MAC_CFG_FULL_DUPLEX;
1940 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1941 reg &= ~MAC_CFG_SPEED_MASK;
1942 /* Reprogram MAC with resolved speed/duplex. */
1943 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1946 reg |= MAC_CFG_SPEED_10_100;
1949 reg |= MAC_CFG_SPEED_1000;
1952 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1953 reg |= MAC_CFG_FULL_DUPLEX;
1955 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1956 reg |= MAC_CFG_TX_FC;
1957 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1958 reg |= MAC_CFG_RX_FC;
1962 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1966 age_link_task(void *arg, int pending)
1968 struct age_softc *sc;
1969 struct mii_data *mii;
1973 sc = (struct age_softc *)arg;
1976 mii = device_get_softc(sc->age_miibus);
1978 if (mii == NULL || ifp == NULL ||
1979 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1984 sc->age_flags &= ~AGE_FLAG_LINK;
1985 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1986 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1990 sc->age_flags |= AGE_FLAG_LINK;
1997 /* Stop Rx/Tx MACs. */
2001 /* Program MACs with resolved speed/duplex/flow-control. */
2002 if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
2004 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2005 /* Restart DMA engine and Tx/Rx MAC. */
2006 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
2007 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
2008 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
2009 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2016 age_stats_update(struct age_softc *sc)
2018 struct age_stats *stat;
2022 AGE_LOCK_ASSERT(sc);
2024 stat = &sc->age_stat;
2026 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2027 sc->age_cdata.age_smb_block_map,
2028 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2030 smb = sc->age_rdata.age_smb_block;
2031 if (smb->updated == 0)
2036 stat->rx_frames += smb->rx_frames;
2037 stat->rx_bcast_frames += smb->rx_bcast_frames;
2038 stat->rx_mcast_frames += smb->rx_mcast_frames;
2039 stat->rx_pause_frames += smb->rx_pause_frames;
2040 stat->rx_control_frames += smb->rx_control_frames;
2041 stat->rx_crcerrs += smb->rx_crcerrs;
2042 stat->rx_lenerrs += smb->rx_lenerrs;
2043 stat->rx_bytes += smb->rx_bytes;
2044 stat->rx_runts += smb->rx_runts;
2045 stat->rx_fragments += smb->rx_fragments;
2046 stat->rx_pkts_64 += smb->rx_pkts_64;
2047 stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2048 stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2049 stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2050 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2051 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2052 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2053 stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2054 stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2055 stat->rx_desc_oflows += smb->rx_desc_oflows;
2056 stat->rx_alignerrs += smb->rx_alignerrs;
2057 stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2058 stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2059 stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2062 stat->tx_frames += smb->tx_frames;
2063 stat->tx_bcast_frames += smb->tx_bcast_frames;
2064 stat->tx_mcast_frames += smb->tx_mcast_frames;
2065 stat->tx_pause_frames += smb->tx_pause_frames;
2066 stat->tx_excess_defer += smb->tx_excess_defer;
2067 stat->tx_control_frames += smb->tx_control_frames;
2068 stat->tx_deferred += smb->tx_deferred;
2069 stat->tx_bytes += smb->tx_bytes;
2070 stat->tx_pkts_64 += smb->tx_pkts_64;
2071 stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2072 stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2073 stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2074 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2075 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2076 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2077 stat->tx_single_colls += smb->tx_single_colls;
2078 stat->tx_multi_colls += smb->tx_multi_colls;
2079 stat->tx_late_colls += smb->tx_late_colls;
2080 stat->tx_excess_colls += smb->tx_excess_colls;
2081 stat->tx_underrun += smb->tx_underrun;
2082 stat->tx_desc_underrun += smb->tx_desc_underrun;
2083 stat->tx_lenerrs += smb->tx_lenerrs;
2084 stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2085 stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2086 stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2088 /* Update counters in ifnet. */
2089 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2091 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2092 smb->tx_multi_colls + smb->tx_late_colls +
2093 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2095 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls +
2096 smb->tx_late_colls + smb->tx_underrun +
2097 smb->tx_pkts_truncated);
2099 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2101 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs +
2102 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated +
2103 smb->rx_fifo_oflows + smb->rx_desc_oflows +
2106 /* Update done, clear. */
2109 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2110 sc->age_cdata.age_smb_block_map,
2111 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2117 struct age_softc *sc;
2120 sc = (struct age_softc *)arg;
2122 status = CSR_READ_4(sc, AGE_INTR_STATUS);
2123 if (status == 0 || (status & AGE_INTRS) == 0)
2124 return (FILTER_STRAY);
2125 /* Disable interrupts. */
2126 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
2127 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2129 return (FILTER_HANDLED);
2133 age_int_task(void *arg, int pending)
2135 struct age_softc *sc;
2140 sc = (struct age_softc *)arg;
2144 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2145 sc->age_cdata.age_cmb_block_map,
2146 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2147 cmb = sc->age_rdata.age_cmb_block;
2148 status = le32toh(cmb->intr_status);
2149 if (sc->age_morework != 0)
2150 status |= INTR_CMB_RX;
2151 if ((status & AGE_INTRS) == 0)
2154 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
2156 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
2158 /* Let hardware know CMB was served. */
2159 cmb->intr_status = 0;
2160 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2161 sc->age_cdata.age_cmb_block_map,
2162 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2165 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2166 if ((status & INTR_CMB_RX) != 0)
2167 sc->age_morework = age_rxintr(sc, sc->age_rr_prod,
2168 sc->age_process_limit);
2169 if ((status & INTR_CMB_TX) != 0)
2170 age_txintr(sc, sc->age_tpd_cons);
2171 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2172 if ((status & INTR_DMA_RD_TO_RST) != 0)
2173 device_printf(sc->age_dev,
2174 "DMA read error! -- resetting\n");
2175 if ((status & INTR_DMA_WR_TO_RST) != 0)
2176 device_printf(sc->age_dev,
2177 "DMA write error! -- resetting\n");
2178 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2179 age_init_locked(sc);
2181 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2182 age_start_locked(ifp);
2183 if ((status & INTR_SMB) != 0)
2184 age_stats_update(sc);
2187 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
2188 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2189 sc->age_cdata.age_cmb_block_map,
2190 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2191 status = le32toh(cmb->intr_status);
2192 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) {
2193 taskqueue_enqueue(sc->age_tq, &sc->age_int_task);
2199 /* Re-enable interrupts. */
2200 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2205 age_txintr(struct age_softc *sc, int tpd_cons)
2208 struct age_txdesc *txd;
2211 AGE_LOCK_ASSERT(sc);
2215 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2216 sc->age_cdata.age_tx_ring_map,
2217 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2220 * Go through our Tx list and free mbufs for those
2221 * frames which have been transmitted.
2223 cons = sc->age_cdata.age_tx_cons;
2224 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
2225 if (sc->age_cdata.age_tx_cnt <= 0)
2228 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2229 sc->age_cdata.age_tx_cnt--;
2230 txd = &sc->age_cdata.age_txdesc[cons];
2232 * Clear Tx descriptors, it's not required but would
2233 * help debugging in case of Tx issues.
2235 txd->tx_desc->addr = 0;
2236 txd->tx_desc->len = 0;
2237 txd->tx_desc->flags = 0;
2239 if (txd->tx_m == NULL)
2241 /* Reclaim transmitted mbufs. */
2242 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap,
2243 BUS_DMASYNC_POSTWRITE);
2244 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
2250 sc->age_cdata.age_tx_cons = cons;
2253 * Unarm watchdog timer only when there are no pending
2254 * Tx descriptors in queue.
2256 if (sc->age_cdata.age_tx_cnt == 0)
2257 sc->age_watchdog_timer = 0;
2258 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2259 sc->age_cdata.age_tx_ring_map,
2260 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2264 #ifndef __NO_STRICT_ALIGNMENT
2265 static struct mbuf *
2266 age_fixup_rx(struct ifnet *ifp, struct mbuf *m)
2270 uint16_t *src, *dst;
2272 src = mtod(m, uint16_t *);
2275 if (m->m_next == NULL) {
2276 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2282 * Append a new mbuf to received mbuf chain and copy ethernet
2283 * header from the mbuf chain. This can save lots of CPU
2284 * cycles for jumbo frame.
2286 MGETHDR(n, M_NOWAIT, MT_DATA);
2288 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2292 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN);
2293 m->m_data += ETHER_HDR_LEN;
2294 m->m_len -= ETHER_HDR_LEN;
2295 n->m_len = ETHER_HDR_LEN;
2296 M_MOVE_PKTHDR(n, m);
2302 /* Receive a frame. */
2304 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2306 struct age_rxdesc *rxd;
2308 struct mbuf *mp, *m;
2309 uint32_t status, index, vtag;
2313 AGE_LOCK_ASSERT(sc);
2316 status = le32toh(rxrd->flags);
2317 index = le32toh(rxrd->index);
2318 rx_cons = AGE_RX_CONS(index);
2319 nsegs = AGE_RX_NSEGS(index);
2321 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2322 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) {
2324 * We want to pass the following frames to upper
2325 * layer regardless of error status of Rx return
2328 * o IP/TCP/UDP checksum is bad.
2329 * o frame length and protocol specific length
2332 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK;
2333 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2334 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0)
2338 for (count = 0; count < nsegs; count++,
2339 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2340 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2342 /* Add a new receive buffer to the ring. */
2343 if (age_newbuf(sc, rxd) != 0) {
2344 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2345 /* Reuse Rx buffers. */
2346 if (sc->age_cdata.age_rxhead != NULL)
2347 m_freem(sc->age_cdata.age_rxhead);
2352 * Assume we've received a full sized frame.
2353 * Actual size is fixed when we encounter the end of
2354 * multi-segmented frame.
2356 mp->m_len = AGE_RX_BUF_SIZE;
2358 /* Chain received mbufs. */
2359 if (sc->age_cdata.age_rxhead == NULL) {
2360 sc->age_cdata.age_rxhead = mp;
2361 sc->age_cdata.age_rxtail = mp;
2363 mp->m_flags &= ~M_PKTHDR;
2364 sc->age_cdata.age_rxprev_tail =
2365 sc->age_cdata.age_rxtail;
2366 sc->age_cdata.age_rxtail->m_next = mp;
2367 sc->age_cdata.age_rxtail = mp;
2370 if (count == nsegs - 1) {
2371 /* Last desc. for this frame. */
2372 m = sc->age_cdata.age_rxhead;
2373 m->m_flags |= M_PKTHDR;
2375 * It seems that L1 controller has no way
2376 * to tell hardware to strip CRC bytes.
2378 m->m_pkthdr.len = sc->age_cdata.age_rxlen -
2381 /* Set last mbuf size. */
2382 mp->m_len = sc->age_cdata.age_rxlen -
2383 ((nsegs - 1) * AGE_RX_BUF_SIZE);
2384 /* Remove the CRC bytes in chained mbufs. */
2385 if (mp->m_len <= ETHER_CRC_LEN) {
2386 sc->age_cdata.age_rxtail =
2387 sc->age_cdata.age_rxprev_tail;
2388 sc->age_cdata.age_rxtail->m_len -=
2389 (ETHER_CRC_LEN - mp->m_len);
2390 sc->age_cdata.age_rxtail->m_next = NULL;
2393 mp->m_len -= ETHER_CRC_LEN;
2396 m->m_len = m->m_pkthdr.len;
2397 m->m_pkthdr.rcvif = ifp;
2399 * Set checksum information.
2400 * It seems that L1 controller can compute partial
2401 * checksum. The partial checksum value can be used
2402 * to accelerate checksum computation for fragmented
2403 * TCP/UDP packets. Upper network stack already
2404 * takes advantage of the partial checksum value in
2405 * IP reassembly stage. But I'm not sure the
2406 * correctness of the partial hardware checksum
2407 * assistance due to lack of data sheet. If it is
2408 * proven to work on L1 I'll enable it.
2410 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2411 (status & AGE_RRD_IPV4) != 0) {
2412 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2413 m->m_pkthdr.csum_flags |=
2414 CSUM_IP_CHECKED | CSUM_IP_VALID;
2415 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2416 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2417 m->m_pkthdr.csum_flags |=
2418 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2419 m->m_pkthdr.csum_data = 0xffff;
2422 * Don't mark bad checksum for TCP/UDP frames
2423 * as fragmented frames may always have set
2424 * bad checksummed bit of descriptor status.
2428 /* Check for VLAN tagged frames. */
2429 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2430 (status & AGE_RRD_VLAN) != 0) {
2431 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2432 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag);
2433 m->m_flags |= M_VLANTAG;
2435 #ifndef __NO_STRICT_ALIGNMENT
2436 m = age_fixup_rx(ifp, m);
2442 (*ifp->if_input)(ifp, m);
2448 /* Reset mbuf chains. */
2449 AGE_RXCHAIN_RESET(sc);
2453 age_rxintr(struct age_softc *sc, int rr_prod, int count)
2455 struct rx_rdesc *rxrd;
2456 int rr_cons, nsegs, pktlen, prog;
2458 AGE_LOCK_ASSERT(sc);
2460 rr_cons = sc->age_cdata.age_rr_cons;
2461 if (rr_cons == rr_prod)
2464 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2465 sc->age_cdata.age_rr_ring_map,
2466 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2467 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2468 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE);
2470 for (prog = 0; rr_cons != rr_prod; prog++) {
2473 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2474 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2478 * Check number of segments against received bytes.
2479 * Non-matching value would indicate that hardware
2480 * is still trying to update Rx return descriptors.
2481 * I'm not sure whether this check is really needed.
2483 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2484 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE))
2487 /* Received a frame. */
2488 age_rxeof(sc, rxrd);
2489 /* Clear return ring. */
2491 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2492 sc->age_cdata.age_rx_cons += nsegs;
2493 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2497 /* Update the consumer index. */
2498 sc->age_cdata.age_rr_cons = rr_cons;
2500 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2501 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2502 /* Sync descriptors. */
2503 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2504 sc->age_cdata.age_rr_ring_map,
2505 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2507 /* Notify hardware availability of new Rx buffers. */
2508 AGE_COMMIT_MBOX(sc);
2511 return (count > 0 ? 0 : EAGAIN);
2517 struct age_softc *sc;
2518 struct mii_data *mii;
2520 sc = (struct age_softc *)arg;
2522 AGE_LOCK_ASSERT(sc);
2524 mii = device_get_softc(sc->age_miibus);
2527 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2531 age_reset(struct age_softc *sc)
2536 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2537 CSR_READ_4(sc, AGE_MASTER_CFG);
2539 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2540 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2546 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2547 /* Initialize PCIe module. From Linux. */
2548 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2549 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2555 struct age_softc *sc;
2557 sc = (struct age_softc *)xsc;
2559 age_init_locked(sc);
2564 age_init_locked(struct age_softc *sc)
2567 struct mii_data *mii;
2568 uint8_t eaddr[ETHER_ADDR_LEN];
2570 uint32_t reg, fsize;
2571 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2574 AGE_LOCK_ASSERT(sc);
2577 mii = device_get_softc(sc->age_miibus);
2579 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2583 * Cancel any pending I/O.
2588 * Reset the chip to a known state.
2592 /* Initialize descriptors. */
2593 error = age_init_rx_ring(sc);
2595 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2599 age_init_rr_ring(sc);
2600 age_init_tx_ring(sc);
2601 age_init_cmb_block(sc);
2602 age_init_smb_block(sc);
2604 /* Reprogram the station address. */
2605 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2606 CSR_WRITE_4(sc, AGE_PAR0,
2607 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2608 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2610 /* Set descriptor base addresses. */
2611 paddr = sc->age_rdata.age_tx_ring_paddr;
2612 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2613 paddr = sc->age_rdata.age_rx_ring_paddr;
2614 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2615 paddr = sc->age_rdata.age_rr_ring_paddr;
2616 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2617 paddr = sc->age_rdata.age_tx_ring_paddr;
2618 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2619 paddr = sc->age_rdata.age_cmb_block_paddr;
2620 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2621 paddr = sc->age_rdata.age_smb_block_paddr;
2622 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2623 /* Set Rx/Rx return descriptor counter. */
2624 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2625 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2626 DESC_RRD_CNT_MASK) |
2627 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2628 /* Set Tx descriptor counter. */
2629 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2630 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2632 /* Tell hardware that we're ready to load descriptors. */
2633 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2636 * Initialize mailbox register.
2637 * Updated producer/consumer index information is exchanged
2638 * through this mailbox register. However Tx producer and
2639 * Rx return consumer/Rx producer are all shared such that
2640 * it's hard to separate code path between Tx and Rx without
2641 * locking. If L1 hardware have a separate mail box register
2642 * for Tx and Rx consumer/producer management we could have
2643 * indepent Tx/Rx handler which in turn Rx handler could have
2644 * been run without any locking.
2646 AGE_COMMIT_MBOX(sc);
2648 /* Configure IPG/IFG parameters. */
2649 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2650 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2651 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2652 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2653 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2655 /* Set parameters for half-duplex media. */
2656 CSR_WRITE_4(sc, AGE_HDPX_CFG,
2657 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2658 HDPX_CFG_LCOL_MASK) |
2659 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2660 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2661 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2662 HDPX_CFG_ABEBT_MASK) |
2663 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2664 HDPX_CFG_JAMIPG_MASK));
2666 /* Configure interrupt moderation timer. */
2667 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2668 reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2669 reg &= ~MASTER_MTIMER_ENB;
2670 if (AGE_USECS(sc->age_int_mod) == 0)
2671 reg &= ~MASTER_ITIMER_ENB;
2673 reg |= MASTER_ITIMER_ENB;
2674 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2676 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2678 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2680 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2681 if (ifp->if_mtu < ETHERMTU)
2682 sc->age_max_frame_size = ETHERMTU;
2684 sc->age_max_frame_size = ifp->if_mtu;
2685 sc->age_max_frame_size += ETHER_HDR_LEN +
2686 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2687 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2688 /* Configure jumbo frame. */
2689 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2690 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2691 (((fsize / sizeof(uint64_t)) <<
2692 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2693 ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2694 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2695 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2696 RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2698 /* Configure flow-control parameters. From Linux. */
2699 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2701 * Magic workaround for old-L1.
2702 * Don't know which hw revision requires this magic.
2704 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2706 * Another magic workaround for flow-control mode
2707 * change. From Linux.
2709 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2713 * Should understand pause parameter relationships between FIFO
2714 * size and number of Rx descriptors and Rx return descriptors.
2716 * Magic parameters came from Linux.
2718 switch (sc->age_chip_rev) {
2723 rxf_hi = AGE_RX_RING_CNT / 16;
2724 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2725 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2726 rrd_lo = AGE_RR_RING_CNT / 16;
2729 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2733 rxf_hi = (reg * 7) / 8;
2734 if (rxf_hi < rxf_lo)
2735 rxf_hi = rxf_lo + 16;
2736 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2738 rrd_hi = (reg * 7) / 8;
2741 if (rrd_hi < rrd_lo)
2742 rrd_hi = rrd_lo + 3;
2745 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2746 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2747 RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2748 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2749 RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2750 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2751 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2752 RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2753 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2754 RXQ_RRD_PAUSE_THRESH_HI_MASK));
2756 /* Configure RxQ. */
2757 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2758 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2759 RXQ_CFG_RD_BURST_MASK) |
2760 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2761 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2762 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2763 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2764 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2766 /* Configure TxQ. */
2767 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2768 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2769 TXQ_CFG_TPD_BURST_MASK) |
2770 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2771 TXQ_CFG_TX_FIFO_BURST_MASK) |
2772 ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2773 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2776 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2777 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2778 TX_JUMBO_TPD_TH_MASK) |
2779 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2780 TX_JUMBO_TPD_IPG_MASK));
2781 /* Configure DMA parameters. */
2782 CSR_WRITE_4(sc, AGE_DMA_CFG,
2783 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2784 sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2785 sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2787 /* Configure CMB DMA write threshold. */
2788 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2789 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2790 CMB_WR_THRESH_RRD_MASK) |
2791 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2792 CMB_WR_THRESH_TPD_MASK));
2794 /* Set CMB/SMB timer and enable them. */
2795 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2796 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2797 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2798 /* Request SMB updates for every seconds. */
2799 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2800 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2803 * Disable all WOL bits as WOL can interfere normal Rx
2806 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2809 * Configure Tx/Rx MACs.
2810 * - Auto-padding for short frames.
2811 * - Enable CRC generation.
2812 * Start with full-duplex/1000Mbps media. Actual reconfiguration
2813 * of MAC is followed after link establishment.
2815 CSR_WRITE_4(sc, AGE_MAC_CFG,
2816 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2817 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2818 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2819 MAC_CFG_PREAMBLE_MASK));
2820 /* Set up the receive filter. */
2824 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2825 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2826 reg |= MAC_CFG_RXCSUM_ENB;
2828 /* Ack all pending interrupts and clear it. */
2829 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2830 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2832 /* Finally enable Tx/Rx MAC. */
2833 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2835 sc->age_flags &= ~AGE_FLAG_LINK;
2836 /* Switch to the current media. */
2839 callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2841 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2842 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2846 age_stop(struct age_softc *sc)
2849 struct age_txdesc *txd;
2850 struct age_rxdesc *rxd;
2854 AGE_LOCK_ASSERT(sc);
2856 * Mark the interface down and cancel the watchdog timer.
2859 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2860 sc->age_flags &= ~AGE_FLAG_LINK;
2861 callout_stop(&sc->age_tick_ch);
2862 sc->age_watchdog_timer = 0;
2865 * Disable interrupts.
2867 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2868 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2869 /* Stop CMB/SMB updates. */
2870 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2871 /* Stop Rx/Tx MAC. */
2875 CSR_WRITE_4(sc, AGE_DMA_CFG,
2876 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2878 CSR_WRITE_4(sc, AGE_TXQ_CFG,
2879 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2880 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2881 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2882 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2883 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2888 device_printf(sc->age_dev,
2889 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2891 /* Reclaim Rx buffers that have been processed. */
2892 if (sc->age_cdata.age_rxhead != NULL)
2893 m_freem(sc->age_cdata.age_rxhead);
2894 AGE_RXCHAIN_RESET(sc);
2896 * Free RX and TX mbufs still in the queues.
2898 for (i = 0; i < AGE_RX_RING_CNT; i++) {
2899 rxd = &sc->age_cdata.age_rxdesc[i];
2900 if (rxd->rx_m != NULL) {
2901 bus_dmamap_sync(sc->age_cdata.age_rx_tag,
2902 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
2903 bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2909 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2910 txd = &sc->age_cdata.age_txdesc[i];
2911 if (txd->tx_m != NULL) {
2912 bus_dmamap_sync(sc->age_cdata.age_tx_tag,
2913 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2914 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2923 age_stop_txmac(struct age_softc *sc)
2928 AGE_LOCK_ASSERT(sc);
2930 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2931 if ((reg & MAC_CFG_TX_ENB) != 0) {
2932 reg &= ~MAC_CFG_TX_ENB;
2933 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2935 /* Stop Tx DMA engine. */
2936 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2937 if ((reg & DMA_CFG_RD_ENB) != 0) {
2938 reg &= ~DMA_CFG_RD_ENB;
2939 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2941 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2942 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2943 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2948 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2952 age_stop_rxmac(struct age_softc *sc)
2957 AGE_LOCK_ASSERT(sc);
2959 reg = CSR_READ_4(sc, AGE_MAC_CFG);
2960 if ((reg & MAC_CFG_RX_ENB) != 0) {
2961 reg &= ~MAC_CFG_RX_ENB;
2962 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2964 /* Stop Rx DMA engine. */
2965 reg = CSR_READ_4(sc, AGE_DMA_CFG);
2966 if ((reg & DMA_CFG_WR_ENB) != 0) {
2967 reg &= ~DMA_CFG_WR_ENB;
2968 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2970 for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2971 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2972 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2977 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2981 age_init_tx_ring(struct age_softc *sc)
2983 struct age_ring_data *rd;
2984 struct age_txdesc *txd;
2987 AGE_LOCK_ASSERT(sc);
2989 sc->age_cdata.age_tx_prod = 0;
2990 sc->age_cdata.age_tx_cons = 0;
2991 sc->age_cdata.age_tx_cnt = 0;
2993 rd = &sc->age_rdata;
2994 bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2995 for (i = 0; i < AGE_TX_RING_CNT; i++) {
2996 txd = &sc->age_cdata.age_txdesc[i];
2997 txd->tx_desc = &rd->age_tx_ring[i];
3001 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
3002 sc->age_cdata.age_tx_ring_map,
3003 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3007 age_init_rx_ring(struct age_softc *sc)
3009 struct age_ring_data *rd;
3010 struct age_rxdesc *rxd;
3013 AGE_LOCK_ASSERT(sc);
3015 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
3016 sc->age_morework = 0;
3017 rd = &sc->age_rdata;
3018 bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
3019 for (i = 0; i < AGE_RX_RING_CNT; i++) {
3020 rxd = &sc->age_cdata.age_rxdesc[i];
3022 rxd->rx_desc = &rd->age_rx_ring[i];
3023 if (age_newbuf(sc, rxd) != 0)
3027 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
3028 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
3034 age_init_rr_ring(struct age_softc *sc)
3036 struct age_ring_data *rd;
3038 AGE_LOCK_ASSERT(sc);
3040 sc->age_cdata.age_rr_cons = 0;
3041 AGE_RXCHAIN_RESET(sc);
3043 rd = &sc->age_rdata;
3044 bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
3045 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
3046 sc->age_cdata.age_rr_ring_map,
3047 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3051 age_init_cmb_block(struct age_softc *sc)
3053 struct age_ring_data *rd;
3055 AGE_LOCK_ASSERT(sc);
3057 rd = &sc->age_rdata;
3058 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
3059 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
3060 sc->age_cdata.age_cmb_block_map,
3061 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3065 age_init_smb_block(struct age_softc *sc)
3067 struct age_ring_data *rd;
3069 AGE_LOCK_ASSERT(sc);
3071 rd = &sc->age_rdata;
3072 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
3073 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
3074 sc->age_cdata.age_smb_block_map,
3075 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3079 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd)
3081 struct rx_desc *desc;
3083 bus_dma_segment_t segs[1];
3087 AGE_LOCK_ASSERT(sc);
3089 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
3092 m->m_len = m->m_pkthdr.len = MCLBYTES;
3093 #ifndef __NO_STRICT_ALIGNMENT
3094 m_adj(m, AGE_RX_BUF_ALIGN);
3097 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag,
3098 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) {
3102 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
3104 if (rxd->rx_m != NULL) {
3105 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3106 BUS_DMASYNC_POSTREAD);
3107 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
3109 map = rxd->rx_dmamap;
3110 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
3111 sc->age_cdata.age_rx_sparemap = map;
3112 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
3113 BUS_DMASYNC_PREREAD);
3116 desc = rxd->rx_desc;
3117 desc->addr = htole64(segs[0].ds_addr);
3118 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
3124 age_rxvlan(struct age_softc *sc)
3129 AGE_LOCK_ASSERT(sc);
3132 reg = CSR_READ_4(sc, AGE_MAC_CFG);
3133 reg &= ~MAC_CFG_VLAN_TAG_STRIP;
3134 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3135 reg |= MAC_CFG_VLAN_TAG_STRIP;
3136 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
3140 age_rxfilter(struct age_softc *sc)
3143 struct ifmultiaddr *ifma;
3148 AGE_LOCK_ASSERT(sc);
3152 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
3153 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3154 if ((ifp->if_flags & IFF_BROADCAST) != 0)
3155 rxcfg |= MAC_CFG_BCAST;
3156 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3157 if ((ifp->if_flags & IFF_PROMISC) != 0)
3158 rxcfg |= MAC_CFG_PROMISC;
3159 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3160 rxcfg |= MAC_CFG_ALLMULTI;
3161 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
3162 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
3163 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3167 /* Program new filter. */
3168 bzero(mchash, sizeof(mchash));
3170 if_maddr_rlock(ifp);
3171 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) {
3172 if (ifma->ifma_addr->sa_family != AF_LINK)
3174 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
3175 ifma->ifma_addr), ETHER_ADDR_LEN);
3176 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3178 if_maddr_runlock(ifp);
3180 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
3181 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
3182 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
3186 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
3188 struct age_softc *sc;
3189 struct age_stats *stats;
3193 error = sysctl_handle_int(oidp, &result, 0, req);
3195 if (error != 0 || req->newptr == NULL)
3201 sc = (struct age_softc *)arg1;
3202 stats = &sc->age_stat;
3203 printf("%s statistics:\n", device_get_nameunit(sc->age_dev));
3204 printf("Transmit good frames : %ju\n",
3205 (uintmax_t)stats->tx_frames);
3206 printf("Transmit good broadcast frames : %ju\n",
3207 (uintmax_t)stats->tx_bcast_frames);
3208 printf("Transmit good multicast frames : %ju\n",
3209 (uintmax_t)stats->tx_mcast_frames);
3210 printf("Transmit pause control frames : %u\n",
3211 stats->tx_pause_frames);
3212 printf("Transmit control frames : %u\n",
3213 stats->tx_control_frames);
3214 printf("Transmit frames with excessive deferrals : %u\n",
3215 stats->tx_excess_defer);
3216 printf("Transmit deferrals : %u\n",
3217 stats->tx_deferred);
3218 printf("Transmit good octets : %ju\n",
3219 (uintmax_t)stats->tx_bytes);
3220 printf("Transmit good broadcast octets : %ju\n",
3221 (uintmax_t)stats->tx_bcast_bytes);
3222 printf("Transmit good multicast octets : %ju\n",
3223 (uintmax_t)stats->tx_mcast_bytes);
3224 printf("Transmit frames 64 bytes : %ju\n",
3225 (uintmax_t)stats->tx_pkts_64);
3226 printf("Transmit frames 65 to 127 bytes : %ju\n",
3227 (uintmax_t)stats->tx_pkts_65_127);
3228 printf("Transmit frames 128 to 255 bytes : %ju\n",
3229 (uintmax_t)stats->tx_pkts_128_255);
3230 printf("Transmit frames 256 to 511 bytes : %ju\n",
3231 (uintmax_t)stats->tx_pkts_256_511);
3232 printf("Transmit frames 512 to 1024 bytes : %ju\n",
3233 (uintmax_t)stats->tx_pkts_512_1023);
3234 printf("Transmit frames 1024 to 1518 bytes : %ju\n",
3235 (uintmax_t)stats->tx_pkts_1024_1518);
3236 printf("Transmit frames 1519 to MTU bytes : %ju\n",
3237 (uintmax_t)stats->tx_pkts_1519_max);
3238 printf("Transmit single collisions : %u\n",
3239 stats->tx_single_colls);
3240 printf("Transmit multiple collisions : %u\n",
3241 stats->tx_multi_colls);
3242 printf("Transmit late collisions : %u\n",
3243 stats->tx_late_colls);
3244 printf("Transmit abort due to excessive collisions : %u\n",
3245 stats->tx_excess_colls);
3246 printf("Transmit underruns due to FIFO underruns : %u\n",
3247 stats->tx_underrun);
3248 printf("Transmit descriptor write-back errors : %u\n",
3249 stats->tx_desc_underrun);
3250 printf("Transmit frames with length mismatched frame size : %u\n",
3252 printf("Transmit frames with truncated due to MTU size : %u\n",
3255 printf("Receive good frames : %ju\n",
3256 (uintmax_t)stats->rx_frames);
3257 printf("Receive good broadcast frames : %ju\n",
3258 (uintmax_t)stats->rx_bcast_frames);
3259 printf("Receive good multicast frames : %ju\n",
3260 (uintmax_t)stats->rx_mcast_frames);
3261 printf("Receive pause control frames : %u\n",
3262 stats->rx_pause_frames);
3263 printf("Receive control frames : %u\n",
3264 stats->rx_control_frames);
3265 printf("Receive CRC errors : %u\n",
3267 printf("Receive frames with length errors : %u\n",
3269 printf("Receive good octets : %ju\n",
3270 (uintmax_t)stats->rx_bytes);
3271 printf("Receive good broadcast octets : %ju\n",
3272 (uintmax_t)stats->rx_bcast_bytes);
3273 printf("Receive good multicast octets : %ju\n",
3274 (uintmax_t)stats->rx_mcast_bytes);
3275 printf("Receive frames too short : %u\n",
3277 printf("Receive fragmented frames : %ju\n",
3278 (uintmax_t)stats->rx_fragments);
3279 printf("Receive frames 64 bytes : %ju\n",
3280 (uintmax_t)stats->rx_pkts_64);
3281 printf("Receive frames 65 to 127 bytes : %ju\n",
3282 (uintmax_t)stats->rx_pkts_65_127);
3283 printf("Receive frames 128 to 255 bytes : %ju\n",
3284 (uintmax_t)stats->rx_pkts_128_255);
3285 printf("Receive frames 256 to 511 bytes : %ju\n",
3286 (uintmax_t)stats->rx_pkts_256_511);
3287 printf("Receive frames 512 to 1024 bytes : %ju\n",
3288 (uintmax_t)stats->rx_pkts_512_1023);
3289 printf("Receive frames 1024 to 1518 bytes : %ju\n",
3290 (uintmax_t)stats->rx_pkts_1024_1518);
3291 printf("Receive frames 1519 to MTU bytes : %ju\n",
3292 (uintmax_t)stats->rx_pkts_1519_max);
3293 printf("Receive frames too long : %ju\n",
3294 (uint64_t)stats->rx_pkts_truncated);
3295 printf("Receive frames with FIFO overflow : %u\n",
3296 stats->rx_fifo_oflows);
3297 printf("Receive frames with return descriptor overflow : %u\n",
3298 stats->rx_desc_oflows);
3299 printf("Receive frames with alignment errors : %u\n",
3300 stats->rx_alignerrs);
3301 printf("Receive frames dropped due to address filtering : %ju\n",
3302 (uint64_t)stats->rx_pkts_filtered);
3308 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3314 value = *(int *)arg1;
3315 error = sysctl_handle_int(oidp, &value, 0, req);
3316 if (error || req->newptr == NULL)
3318 if (value < low || value > high)
3320 *(int *)arg1 = value;
3326 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS)
3328 return (sysctl_int_range(oidp, arg1, arg2, req,
3329 AGE_PROC_MIN, AGE_PROC_MAX));
3333 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
3336 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,