2 * Copyright (c) 2000 Doug Rabson
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <pci/agppriv.h>
45 #include <pci/agpreg.h>
48 #include <vm/vm_object.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
54 MALLOC_DECLARE(M_AGP);
56 #define READ2(off) bus_space_read_2(sc->bst, sc->bsh, off)
57 #define READ4(off) bus_space_read_4(sc->bst, sc->bsh, off)
58 #define WRITE2(off,v) bus_space_write_2(sc->bst, sc->bsh, off, v)
59 #define WRITE4(off,v) bus_space_write_4(sc->bst, sc->bsh, off, v)
63 u_int32_t *ag_virtual; /* virtual address of gatt */
64 vm_offset_t ag_physical;
65 u_int32_t *ag_vdir; /* virtual address of page dir */
66 vm_offset_t ag_pdir; /* physical address of page dir */
69 struct agp_amd_softc {
71 struct resource *regs; /* memory mapped control registers */
72 bus_space_tag_t bst; /* bus_space tag */
73 bus_space_handle_t bsh; /* bus_space handle */
74 u_int32_t initial_aperture; /* aperture size at startup */
75 struct agp_amd_gatt *gatt;
78 static struct agp_amd_gatt *
79 agp_amd_alloc_gatt(device_t dev)
81 u_int32_t apsize = AGP_GET_APERTURE(dev);
82 u_int32_t entries = apsize >> AGP_PAGE_SHIFT;
83 struct agp_amd_gatt *gatt;
84 int i, npages, pdir_offset;
88 "allocating GATT for aperture of size %dM\n",
89 apsize / (1024*1024));
91 gatt = malloc(sizeof(struct agp_amd_gatt), M_AGP, M_NOWAIT);
96 * The AMD751 uses a page directory to map a non-contiguous
97 * gatt so we don't need to use contigmalloc.
98 * Malloc individual gatt pages and map them into the page
101 gatt->ag_entries = entries;
102 gatt->ag_virtual = malloc(entries * sizeof(u_int32_t),
104 if (!gatt->ag_virtual) {
106 device_printf(dev, "allocation failed\n");
110 bzero(gatt->ag_virtual, entries * sizeof(u_int32_t));
113 * Allocate the page directory.
115 gatt->ag_vdir = malloc(AGP_PAGE_SIZE, M_AGP, M_NOWAIT);
116 if (!gatt->ag_vdir) {
119 "failed to allocate page directory\n");
120 free(gatt->ag_virtual, M_AGP);
124 bzero(gatt->ag_vdir, AGP_PAGE_SIZE);
126 gatt->ag_pdir = vtophys((vm_offset_t) gatt->ag_vdir);
128 device_printf(dev, "gatt -> ag_pdir %#lx\n",
129 (u_long)gatt->ag_pdir);
131 * Allocate the gatt pages
133 gatt->ag_entries = entries;
135 device_printf(dev, "allocating GATT for %d AGP page entries\n",
138 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
141 * Map the pages of the GATT into the page directory.
143 * The GATT page addresses are mapped into the directory offset by
144 * an amount dependent on the base address of the aperture. This
145 * is and offset into the page directory, not an offset added to
146 * the addresses of the gatt pages.
149 pdir_offset = pci_read_config(dev, AGP_AMD751_APBASE, 4) >> 22;
151 npages = ((entries * sizeof(u_int32_t) + AGP_PAGE_SIZE - 1)
154 for (i = 0; i < npages; i++) {
158 va = ((vm_offset_t) gatt->ag_virtual) + i * AGP_PAGE_SIZE;
160 gatt->ag_vdir[i + pdir_offset] = pa | 1;
164 * Make sure the chipset can see everything.
172 agp_amd_free_gatt(struct agp_amd_gatt *gatt)
174 free(gatt->ag_virtual, M_AGP);
175 free(gatt->ag_vdir, M_AGP);
180 agp_amd_match(device_t dev)
182 if (pci_get_class(dev) != PCIC_BRIDGE
183 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
186 if (agp_find_caps(dev) == 0)
189 switch (pci_get_devid(dev)) {
191 return ("AMD 751 host to AGP bridge");
193 return ("AMD 761 host to AGP bridge");
195 return ("AMD 762 host to AGP bridge");
202 agp_amd_probe(device_t dev)
206 if (resource_disabled("agp", device_get_unit(dev)))
208 desc = agp_amd_match(dev);
211 device_set_desc(dev, desc);
212 return BUS_PROBE_DEFAULT;
219 agp_amd_attach(device_t dev)
221 struct agp_amd_softc *sc = device_get_softc(dev);
222 struct agp_amd_gatt *gatt;
225 error = agp_generic_attach(dev);
229 rid = AGP_AMD751_REGISTERS;
230 sc->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
233 agp_generic_detach(dev);
237 sc->bst = rman_get_bustag(sc->regs);
238 sc->bsh = rman_get_bushandle(sc->regs);
240 sc->initial_aperture = AGP_GET_APERTURE(dev);
243 gatt = agp_amd_alloc_gatt(dev);
248 * Probably contigmalloc failure. Try reducing the
249 * aperture so that the gatt size reduces.
251 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
256 /* Install the gatt. */
257 WRITE4(AGP_AMD751_ATTBASE, gatt->ag_pdir);
259 /* Enable synchronisation between host and agp. */
260 pci_write_config(dev,
262 AGP_AMD751_MODECTRL_SYNEN, 1);
264 /* Set indexing mode for two-level and enable page dir cache */
265 pci_write_config(dev,
266 AGP_AMD751_MODECTRL2,
267 AGP_AMD751_MODECTRL2_GPDCE, 1);
269 /* Enable the TLB and flush */
270 WRITE2(AGP_AMD751_STATUS,
271 READ2(AGP_AMD751_STATUS) | AGP_AMD751_STATUS_GCE);
278 agp_amd_detach(device_t dev)
280 struct agp_amd_softc *sc = device_get_softc(dev);
283 error = agp_generic_detach(dev);
287 /* Disable the TLB.. */
288 WRITE2(AGP_AMD751_STATUS,
289 READ2(AGP_AMD751_STATUS) & ~AGP_AMD751_STATUS_GCE);
291 /* Disable host-agp sync */
292 pci_write_config(dev, AGP_AMD751_MODECTRL, 0x00, 1);
294 /* Clear the GATT base */
295 WRITE4(AGP_AMD751_ATTBASE, 0);
297 /* Put the aperture back the way it started. */
298 AGP_SET_APERTURE(dev, sc->initial_aperture);
300 agp_amd_free_gatt(sc->gatt);
302 bus_release_resource(dev, SYS_RES_MEMORY,
303 AGP_AMD751_REGISTERS, sc->regs);
309 agp_amd_get_aperture(device_t dev)
314 * The aperture size is equal to 32M<<vas.
316 vas = (pci_read_config(dev, AGP_AMD751_APCTRL, 1) & 0x06) >> 1;
317 return (32*1024*1024) << vas;
321 agp_amd_set_aperture(device_t dev, u_int32_t aperture)
326 * Check for a power of two and make sure its within the
327 * programmable range.
329 if (aperture & (aperture - 1)
330 || aperture < 32*1024*1024
331 || aperture > 2U*1024*1024*1024)
334 vas = ffs(aperture / 32*1024*1024) - 1;
337 * While the size register is bits 1-3 of APCTRL, bit 0 must be
338 * set for the size value to be 'valid'
340 pci_write_config(dev, AGP_AMD751_APCTRL,
341 (((pci_read_config(dev, AGP_AMD751_APCTRL, 1) & ~0x06)
342 | ((vas << 1) | 1))), 1);
348 agp_amd_bind_page(device_t dev, int offset, vm_offset_t physical)
350 struct agp_amd_softc *sc = device_get_softc(dev);
352 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
355 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 1;
357 /* invalidate the cache */
363 agp_amd_unbind_page(device_t dev, int offset)
365 struct agp_amd_softc *sc = device_get_softc(dev);
367 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
370 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
375 agp_amd_flush_tlb(device_t dev)
377 struct agp_amd_softc *sc = device_get_softc(dev);
379 /* Set the cache invalidate bit and wait for the chipset to clear */
380 WRITE4(AGP_AMD751_TLBCTRL, 1);
383 } while (READ4(AGP_AMD751_TLBCTRL));
386 static device_method_t agp_amd_methods[] = {
387 /* Device interface */
388 DEVMETHOD(device_probe, agp_amd_probe),
389 DEVMETHOD(device_attach, agp_amd_attach),
390 DEVMETHOD(device_detach, agp_amd_detach),
391 DEVMETHOD(device_shutdown, bus_generic_shutdown),
392 DEVMETHOD(device_suspend, bus_generic_suspend),
393 DEVMETHOD(device_resume, bus_generic_resume),
396 DEVMETHOD(agp_get_aperture, agp_amd_get_aperture),
397 DEVMETHOD(agp_set_aperture, agp_amd_set_aperture),
398 DEVMETHOD(agp_bind_page, agp_amd_bind_page),
399 DEVMETHOD(agp_unbind_page, agp_amd_unbind_page),
400 DEVMETHOD(agp_flush_tlb, agp_amd_flush_tlb),
401 DEVMETHOD(agp_enable, agp_generic_enable),
402 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
403 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
404 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
405 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
410 static driver_t agp_amd_driver = {
413 sizeof(struct agp_amd_softc),
416 static devclass_t agp_devclass;
418 DRIVER_MODULE(agp_amd, pci, agp_amd_driver, agp_devclass, 0, 0);
419 MODULE_DEPEND(agp_amd, agp, 1, 1, 1);
420 MODULE_DEPEND(agp_amd, pci, 1, 1, 1);