2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
42 #include <dev/agp/agppriv.h>
43 #include <dev/agp/agpreg.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
48 #include <vm/vm_object.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
55 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56 extern uint32_t pci_cfgregread(int, int, int, int, int);
58 static void agp_amd64_apbase_fixup(device_t);
60 static void agp_amd64_uli_init(device_t);
61 static int agp_amd64_uli_set_aperture(device_t, uint32_t);
63 static int agp_amd64_nvidia_match(uint16_t);
64 static void agp_amd64_nvidia_init(device_t);
65 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
67 static int agp_amd64_via_match(void);
68 static void agp_amd64_via_init(device_t);
69 static int agp_amd64_via_set_aperture(device_t, uint32_t);
71 MALLOC_DECLARE(M_AGP);
73 #define AMD64_MAX_MCTRL 8
75 struct agp_amd64_softc {
77 uint32_t initial_aperture;
78 struct agp_gatt *gatt;
80 int mctrl[AMD64_MAX_MCTRL];
86 agp_amd64_match(device_t dev)
88 if (pci_get_class(dev) != PCIC_BRIDGE ||
89 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
90 agp_find_caps(dev) == 0)
93 switch (pci_get_devid(dev)) {
95 return ("AMD 8151 AGP graphics tunnel");
97 return ("SiS 755 host to AGP bridge");
99 return ("SiS 760 host to AGP bridge");
101 return ("ULi M1689 AGP Controller");
103 if (agp_amd64_nvidia_match(0x00d2))
105 return ("NVIDIA nForce3 AGP Controller");
107 if (agp_amd64_nvidia_match(0x00e2))
109 return ("NVIDIA nForce3-250 AGP Controller");
111 return ("VIA 8380 host to PCI bridge");
113 return ("VIA 3238 host to PCI bridge");
115 return ("VIA K8T800Pro host to PCI bridge");
117 return ("VIA 8385 host to PCI bridge");
124 agp_amd64_nvidia_match(uint16_t devid)
126 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
127 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
128 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
129 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
130 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
137 agp_amd64_via_match(void)
139 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
140 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
141 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
142 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
143 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
144 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
151 agp_amd64_probe(device_t dev)
155 if (resource_disabled("agp", device_get_unit(dev)))
157 if ((desc = agp_amd64_match(dev))) {
158 device_set_desc(dev, desc);
159 return (BUS_PROBE_DEFAULT);
166 agp_amd64_attach(device_t dev)
168 struct agp_amd64_softc *sc = device_get_softc(dev);
169 struct agp_gatt *gatt;
173 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
174 devid = pci_cfgregread(0, i, 3, 0, 4);
175 if (devid == 0x11031022 || devid == 0x12031022) {
186 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
189 if ((error = agp_generic_attach(dev)))
192 sc->initial_aperture = AGP_GET_APERTURE(dev);
195 gatt = agp_alloc_gatt(dev);
200 * Probably contigmalloc failure. Try reducing the
201 * aperture so that the gatt size reduces.
203 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
204 agp_generic_detach(dev);
210 switch (pci_get_vendor(dev)) {
211 case 0x10b9: /* ULi */
212 agp_amd64_uli_init(dev);
213 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
217 case 0x10de: /* nVidia */
218 agp_amd64_nvidia_init(dev);
219 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
223 case 0x1106: /* VIA */
224 sc->via_agp = agp_amd64_via_match();
226 agp_amd64_via_init(dev);
227 if (agp_amd64_via_set_aperture(dev,
228 sc->initial_aperture))
234 /* Install the gatt and enable aperture. */
235 for (i = 0; i < sc->n_mctrl; i++) {
236 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
237 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
239 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
240 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
241 AGP_AMD64_APCTRL_GARTEN) &
242 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
250 agp_amd64_detach(device_t dev)
252 struct agp_amd64_softc *sc = device_get_softc(dev);
257 for (i = 0; i < sc->n_mctrl; i++)
258 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
259 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
260 ~AGP_AMD64_APCTRL_GARTEN, 4);
262 AGP_SET_APERTURE(dev, sc->initial_aperture);
263 agp_free_gatt(sc->gatt);
269 static uint32_t agp_amd64_table[] = {
270 0x02000000, /* 32 MB */
271 0x04000000, /* 64 MB */
272 0x08000000, /* 128 MB */
273 0x10000000, /* 256 MB */
274 0x20000000, /* 512 MB */
275 0x40000000, /* 1024 MB */
276 0x80000000, /* 2048 MB */
279 #define AGP_AMD64_TABLE_SIZE nitems(agp_amd64_table)
282 agp_amd64_get_aperture(device_t dev)
284 struct agp_amd64_softc *sc = device_get_softc(dev);
287 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
288 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
290 if (i >= AGP_AMD64_TABLE_SIZE)
293 return (agp_amd64_table[i]);
297 agp_amd64_set_aperture(device_t dev, uint32_t aperture)
299 struct agp_amd64_softc *sc = device_get_softc(dev);
303 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
304 if (agp_amd64_table[i] == aperture)
306 if (i >= AGP_AMD64_TABLE_SIZE)
309 for (j = 0; j < sc->n_mctrl; j++)
310 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
311 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
312 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
314 switch (pci_get_vendor(dev)) {
315 case 0x10b9: /* ULi */
316 return (agp_amd64_uli_set_aperture(dev, aperture));
319 case 0x10de: /* nVidia */
320 return (agp_amd64_nvidia_set_aperture(dev, aperture));
323 case 0x1106: /* VIA */
325 return (agp_amd64_via_set_aperture(dev, aperture));
333 agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
335 struct agp_amd64_softc *sc = device_get_softc(dev);
337 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
340 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
341 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
347 agp_amd64_unbind_page(device_t dev, vm_offset_t offset)
349 struct agp_amd64_softc *sc = device_get_softc(dev);
351 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
354 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
360 agp_amd64_flush_tlb(device_t dev)
362 struct agp_amd64_softc *sc = device_get_softc(dev);
365 for (i = 0; i < sc->n_mctrl; i++)
366 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
367 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
368 AGP_AMD64_CACHECTRL_INVGART, 4);
372 agp_amd64_apbase_fixup(device_t dev)
374 struct agp_amd64_softc *sc = device_get_softc(dev);
378 sc->apbase = rman_get_start(sc->agp.as_aperture);
379 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
380 for (i = 0; i < sc->n_mctrl; i++)
381 pci_cfgregwrite(0, sc->mctrl[i], 3,
382 AGP_AMD64_APBASE, apbase, 4);
386 agp_amd64_uli_init(device_t dev)
388 struct agp_amd64_softc *sc = device_get_softc(dev);
390 agp_amd64_apbase_fixup(dev);
391 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
392 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
394 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
398 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
400 struct agp_amd64_softc *sc = device_get_softc(dev);
403 case 0x02000000: /* 32 MB */
404 case 0x04000000: /* 64 MB */
405 case 0x08000000: /* 128 MB */
406 case 0x10000000: /* 256 MB */
412 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
413 sc->apbase + aperture - 1, 4);
419 agp_amd64_nvidia_init(device_t dev)
421 struct agp_amd64_softc *sc = device_get_softc(dev);
423 agp_amd64_apbase_fixup(dev);
424 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
425 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
427 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
428 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
432 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
434 struct agp_amd64_softc *sc = device_get_softc(dev);
438 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
439 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
440 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
441 case 0x10000000: apsize = 0x08; break; /* 256 MB */
442 case 0x20000000: apsize = 0x00; break; /* 512 MB */
447 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
448 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
449 0xfffffff0) | apsize, 4);
450 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
451 sc->apbase + aperture - 1, 4);
452 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
453 sc->apbase + aperture - 1, 4);
459 agp_amd64_via_init(device_t dev)
461 struct agp_amd64_softc *sc = device_get_softc(dev);
463 agp_amd64_apbase_fixup(dev);
464 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
465 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
466 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
470 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
474 apsize = ((aperture - 1) >> 20) ^ 0xff;
475 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
477 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
482 static device_method_t agp_amd64_methods[] = {
483 /* Device interface */
484 DEVMETHOD(device_probe, agp_amd64_probe),
485 DEVMETHOD(device_attach, agp_amd64_attach),
486 DEVMETHOD(device_detach, agp_amd64_detach),
487 DEVMETHOD(device_shutdown, bus_generic_shutdown),
488 DEVMETHOD(device_suspend, bus_generic_suspend),
489 DEVMETHOD(device_resume, bus_generic_resume),
492 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
493 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
494 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
495 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
496 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
497 DEVMETHOD(agp_enable, agp_generic_enable),
498 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
499 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
500 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
501 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
506 static driver_t agp_amd64_driver = {
509 sizeof(struct agp_amd64_softc),
512 static devclass_t agp_devclass;
514 DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0);
515 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
516 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);