2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
42 #include <dev/pci/pcivar.h>
43 #include <dev/pci/pcireg.h>
44 #include <pci/agppriv.h>
45 #include <pci/agpreg.h>
48 #include <vm/vm_object.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
55 extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56 extern uint32_t pci_cfgregread(int, int, int, int, int);
58 static void agp_amd64_apbase_fixup(device_t);
60 static void agp_amd64_uli_init(device_t);
61 static int agp_amd64_uli_set_aperture(device_t, uint32_t);
63 static int agp_amd64_nvidia_match(uint16_t);
64 static void agp_amd64_nvidia_init(device_t);
65 static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
67 static int agp_amd64_via_match(void);
68 static void agp_amd64_via_init(device_t);
69 static int agp_amd64_via_set_aperture(device_t, uint32_t);
71 MALLOC_DECLARE(M_AGP);
73 #define AMD64_MAX_MCTRL 8
75 struct agp_amd64_softc {
77 uint32_t initial_aperture;
78 struct agp_gatt *gatt;
80 int mctrl[AMD64_MAX_MCTRL];
86 agp_amd64_match(device_t dev)
88 if (pci_get_class(dev) != PCIC_BRIDGE
89 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
92 if (agp_find_caps(dev) == 0)
95 switch (pci_get_devid(dev)) {
97 return ("AMD 8151 AGP graphics tunnel");
99 return ("SiS 755 host to AGP bridge");
101 return ("ULi M1689 AGP Controller");
103 if (agp_amd64_nvidia_match(0x00d2))
105 return ("NVIDIA nForce3 AGP Controller");
107 if (agp_amd64_nvidia_match(0x00e2))
109 return ("NVIDIA nForce3-250 AGP Controller");
111 return ("VIA 8380 host to PCI bridge");
113 return ("VIA 3238 host to PCI bridge");
115 return ("VIA K8T800Pro host to PCI bridge");
117 return ("VIA 8385 host to PCI bridge");
124 agp_amd64_nvidia_match(uint16_t devid)
126 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
127 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
128 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
129 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
130 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
137 agp_amd64_via_match(void)
139 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
140 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
141 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
142 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
143 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
144 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
151 agp_amd64_probe(device_t dev)
155 if (resource_disabled("agp", device_get_unit(dev)))
157 if ((desc = agp_amd64_match(dev))) {
159 device_set_desc(dev, desc);
160 return BUS_PROBE_DEFAULT;
167 agp_amd64_attach(device_t dev)
169 struct agp_amd64_softc *sc = device_get_softc(dev);
170 struct agp_gatt *gatt;
173 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
174 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
185 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
187 for (i = 0; i < sc->n_mctrl; i++)
188 device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
189 pci_cfgregread(0, sc->mctrl[i], 3,
190 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
193 if ((error = agp_generic_attach(dev)))
196 sc->initial_aperture = AGP_GET_APERTURE(dev);
199 gatt = agp_alloc_gatt(dev);
204 * Probably contigmalloc failure. Try reducing the
205 * aperture so that the gatt size reduces.
207 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
208 agp_generic_detach(dev);
214 switch (pci_get_vendor(dev)) {
215 case 0x10b9: /* ULi */
216 agp_amd64_uli_init(dev);
217 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
221 case 0x10de: /* nVidia */
222 agp_amd64_nvidia_init(dev);
223 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
227 case 0x1106: /* VIA */
228 sc->via_agp = agp_amd64_via_match();
230 agp_amd64_via_init(dev);
231 if (agp_amd64_via_set_aperture(dev,
232 sc->initial_aperture))
238 /* Install the gatt and enable aperture. */
239 for (i = 0; i < sc->n_mctrl; i++) {
240 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
241 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
243 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
244 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
245 AGP_AMD64_APCTRL_GARTEN) &
246 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
256 agp_amd64_detach(device_t dev)
258 struct agp_amd64_softc *sc = device_get_softc(dev);
261 if ((error = agp_generic_detach(dev)))
264 for (i = 0; i < sc->n_mctrl; i++)
265 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
266 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
267 ~AGP_AMD64_APCTRL_GARTEN, 4);
269 AGP_SET_APERTURE(dev, sc->initial_aperture);
270 agp_free_gatt(sc->gatt);
275 static uint32_t agp_amd64_table[] = {
276 0x02000000, /* 32 MB */
277 0x04000000, /* 64 MB */
278 0x08000000, /* 128 MB */
279 0x10000000, /* 256 MB */
280 0x20000000, /* 512 MB */
281 0x40000000, /* 1024 MB */
282 0x80000000, /* 2048 MB */
285 #define AGP_AMD64_TABLE_SIZE \
286 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
289 agp_amd64_get_aperture(device_t dev)
291 struct agp_amd64_softc *sc = device_get_softc(dev);
294 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
295 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
297 if (i >= AGP_AMD64_TABLE_SIZE)
300 return (agp_amd64_table[i]);
304 agp_amd64_set_aperture(device_t dev, uint32_t aperture)
306 struct agp_amd64_softc *sc = device_get_softc(dev);
310 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
311 if (agp_amd64_table[i] == aperture)
313 if (i >= AGP_AMD64_TABLE_SIZE)
316 for (j = 0; j < sc->n_mctrl; j++)
317 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
318 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
319 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
321 switch (pci_get_vendor(dev)) {
322 case 0x10b9: /* ULi */
323 return (agp_amd64_uli_set_aperture(dev, aperture));
326 case 0x10de: /* nVidia */
327 return (agp_amd64_nvidia_set_aperture(dev, aperture));
330 case 0x1106: /* VIA */
332 return (agp_amd64_via_set_aperture(dev, aperture));
340 agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
342 struct agp_amd64_softc *sc = device_get_softc(dev);
344 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
347 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
352 agp_amd64_unbind_page(device_t dev, int offset)
354 struct agp_amd64_softc *sc = device_get_softc(dev);
356 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
359 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
364 agp_amd64_flush_tlb(device_t dev)
366 struct agp_amd64_softc *sc = device_get_softc(dev);
369 for (i = 0; i < sc->n_mctrl; i++)
370 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
371 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
372 AGP_AMD64_CACHECTRL_INVGART, 4);
376 agp_amd64_apbase_fixup(device_t dev)
378 struct agp_amd64_softc *sc = device_get_softc(dev);
382 apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
383 for (i = 0; i < sc->n_mctrl; i++)
384 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
385 apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
386 sc->apbase = apbase << 25;
390 agp_amd64_uli_init(device_t dev)
392 struct agp_amd64_softc *sc = device_get_softc(dev);
394 agp_amd64_apbase_fixup(dev);
395 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
396 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
398 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
402 agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
404 struct agp_amd64_softc *sc = device_get_softc(dev);
407 case 0x02000000: /* 32 MB */
408 case 0x04000000: /* 64 MB */
409 case 0x08000000: /* 128 MB */
410 case 0x10000000: /* 256 MB */
416 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
417 sc->apbase + aperture - 1, 4);
423 agp_amd64_nvidia_init(device_t dev)
425 struct agp_amd64_softc *sc = device_get_softc(dev);
427 agp_amd64_apbase_fixup(dev);
428 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
429 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
431 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
432 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
436 agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
438 struct agp_amd64_softc *sc = device_get_softc(dev);
442 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
443 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
444 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
445 case 0x10000000: apsize = 0x08; break; /* 256 MB */
446 case 0x20000000: apsize = 0x00; break; /* 512 MB */
451 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
452 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
453 0xfffffff0) | apsize, 4);
454 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
455 sc->apbase + aperture - 1, 4);
456 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
457 sc->apbase + aperture - 1, 4);
463 agp_amd64_via_init(device_t dev)
465 struct agp_amd64_softc *sc = device_get_softc(dev);
467 agp_amd64_apbase_fixup(dev);
468 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
469 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
470 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
474 agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
478 apsize = ((aperture - 1) >> 20) ^ 0xff;
479 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
481 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
486 static device_method_t agp_amd64_methods[] = {
487 /* Device interface */
488 DEVMETHOD(device_probe, agp_amd64_probe),
489 DEVMETHOD(device_attach, agp_amd64_attach),
490 DEVMETHOD(device_detach, agp_amd64_detach),
491 DEVMETHOD(device_shutdown, bus_generic_shutdown),
492 DEVMETHOD(device_suspend, bus_generic_suspend),
493 DEVMETHOD(device_resume, bus_generic_resume),
496 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
497 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
498 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
499 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
500 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
501 DEVMETHOD(agp_enable, agp_generic_enable),
502 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
503 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
504 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
505 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
510 static driver_t agp_amd64_driver = {
513 sizeof(struct agp_amd64_softc),
516 static devclass_t agp_devclass;
518 DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0);
519 MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
520 MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);