sys/dev/agp/agp_i810.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2000 Doug Rabson
   5  * Copyright (c) 2000 Ruslan Ermilov
   6  * Copyright (c) 2011 The FreeBSD Foundation
   7  * All rights reserved.
   8  *
   9  * Portions of this software were developed by Konstantin Belousov
  10  * under sponsorship from the FreeBSD Foundation.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions and the following disclaimer.
  17  * 2. Redistributions in binary form must reproduce the above copyright
  18  *    notice, this list of conditions and the following disclaimer in the
  19  *    documentation and/or other materials provided with the distribution.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  */
  33
  34 /*
  35  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
  36  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
  37  *
  38  * This is generic Intel GTT handling code, morphed from the AGP
  39  * bridge code.
  40  */
  41
  42 #include <sys/cdefs.h>
  43 __FBSDID("$FreeBSD$");
  44
  45 #if 0
  46 #define KTR_AGP_I810    KTR_DEV
  47 #else
  48 #define KTR_AGP_I810    0
  49 #endif
  50
  51 #include <sys/param.h>
  52 #include <sys/systm.h>
  53 #include <sys/malloc.h>
  54 #include <sys/kernel.h>
  55 #include <sys/ktr.h>
  56 #include <sys/module.h>
  57 #include <sys/bus.h>
  58 #include <sys/lock.h>
  59 #include <sys/mutex.h>
  60 #include <sys/proc.h>
  61 #include <sys/rwlock.h>
  62
  63 #include <dev/agp/agppriv.h>
  64 #include <dev/agp/agpreg.h>
  65 #include <dev/agp/agp_i810.h>
  66 #include <dev/pci/pcivar.h>
  67 #include <dev/pci/pcireg.h>
  68 #include <dev/pci/pci_private.h>
  69
  70 #include <vm/vm.h>
  71 #include <vm/vm_extern.h>
  72 #include <vm/vm_kern.h>
  73 #include <vm/vm_param.h>
  74 #include <vm/vm_object.h>
  75 #include <vm/vm_page.h>
  76 #include <vm/vm_pageout.h>
  77 #include <vm/pmap.h>
  78
  79 #include <machine/bus.h>
  80 #include <machine/resource.h>
  81 #include <machine/md_var.h>
  82 #include <sys/rman.h>
  83
  84 MALLOC_DECLARE(M_AGP);
  85
  86 struct agp_i810_match;
  87
  88 static int agp_i810_check_active(device_t bridge_dev);
  89 static int agp_i830_check_active(device_t bridge_dev);
  90 static int agp_i915_check_active(device_t bridge_dev);
  91
  92 static void agp_82852_set_desc(device_t dev,
  93     const struct agp_i810_match *match);
  94 static void agp_i810_set_desc(device_t dev, const struct agp_i810_match *match);
  95
  96 static void agp_i810_dump_regs(device_t dev);
  97 static void agp_i830_dump_regs(device_t dev);
  98 static void agp_i855_dump_regs(device_t dev);
  99 static void agp_i915_dump_regs(device_t dev);
 100 static void agp_i965_dump_regs(device_t dev);
 101
 102 static int agp_i810_get_stolen_size(device_t dev);
 103 static int agp_i830_get_stolen_size(device_t dev);
 104 static int agp_i915_get_stolen_size(device_t dev);
 105
 106 static int agp_i810_get_gtt_mappable_entries(device_t dev);
 107 static int agp_i830_get_gtt_mappable_entries(device_t dev);
 108 static int agp_i915_get_gtt_mappable_entries(device_t dev);
 109
 110 static int agp_i810_get_gtt_total_entries(device_t dev);
 111 static int agp_i965_get_gtt_total_entries(device_t dev);
 112 static int agp_gen5_get_gtt_total_entries(device_t dev);
 113
 114 static int agp_i810_install_gatt(device_t dev);
 115 static int agp_i830_install_gatt(device_t dev);
 116 static int agp_i965_install_gatt(device_t dev);
 117 static int agp_g4x_install_gatt(device_t dev);
 118
 119 static void agp_i810_deinstall_gatt(device_t dev);
 120 static void agp_i830_deinstall_gatt(device_t dev);
 121
 122 static void agp_i810_install_gtt_pte(device_t dev, u_int index,
 123     vm_offset_t physical, int flags);
 124 static void agp_i830_install_gtt_pte(device_t dev, u_int index,
 125     vm_offset_t physical, int flags);
 126 static void agp_i915_install_gtt_pte(device_t dev, u_int index,
 127     vm_offset_t physical, int flags);
 128 static void agp_i965_install_gtt_pte(device_t dev, u_int index,
 129     vm_offset_t physical, int flags);
 130 static void agp_g4x_install_gtt_pte(device_t dev, u_int index,
 131     vm_offset_t physical, int flags);
 132
 133 static void agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte);
 134 static void agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte);
 135 static void agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte);
 136 static void agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte);
 137
 138 static u_int32_t agp_i810_read_gtt_pte(device_t dev, u_int index);
 139 static u_int32_t agp_i915_read_gtt_pte(device_t dev, u_int index);
 140 static u_int32_t agp_i965_read_gtt_pte(device_t dev, u_int index);
 141 static u_int32_t agp_g4x_read_gtt_pte(device_t dev, u_int index);
 142
 143 static vm_paddr_t agp_i810_read_gtt_pte_paddr(device_t dev, u_int index);
 144 static vm_paddr_t agp_i915_read_gtt_pte_paddr(device_t dev, u_int index);
 145
 146 static int agp_i810_set_aperture(device_t dev, u_int32_t aperture);
 147 static int agp_i830_set_aperture(device_t dev, u_int32_t aperture);
 148 static int agp_i915_set_aperture(device_t dev, u_int32_t aperture);
 149
 150 static int agp_i810_chipset_flush_setup(device_t dev);
 151 static int agp_i915_chipset_flush_setup(device_t dev);
 152 static int agp_i965_chipset_flush_setup(device_t dev);
 153
 154 static void agp_i810_chipset_flush_teardown(device_t dev);
 155 static void agp_i915_chipset_flush_teardown(device_t dev);
 156 static void agp_i965_chipset_flush_teardown(device_t dev);
 157
 158 static void agp_i810_chipset_flush(device_t dev);
 159 static void agp_i830_chipset_flush(device_t dev);
 160 static void agp_i915_chipset_flush(device_t dev);
 161
 162 enum {
 163         CHIP_I810,      /* i810/i815 */
 164         CHIP_I830,      /* 830M/845G */
 165         CHIP_I855,      /* 852GM/855GM/865G */
 166         CHIP_I915,      /* 915G/915GM */
 167         CHIP_I965,      /* G965 */
 168         CHIP_G33,       /* G33/Q33/Q35 */
 169         CHIP_IGD,       /* Pineview */
 170         CHIP_G4X,       /* G45/Q45 */
 171 };
 172
 173 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
 174  * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
 175  * start of the stolen memory, and should only be accessed by the OS through
 176  * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
 177  * is registers, second 512KB is GATT.
 178  */
 179 static struct resource_spec agp_i810_res_spec[] = {
 180         { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
 181         { -1, 0 }
 182 };
 183
 184 static struct resource_spec agp_i915_res_spec[] = {
 185         { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
 186         { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
 187         { -1, 0 }
 188 };
 189
 190 static struct resource_spec agp_i965_res_spec[] = {
 191         { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
 192         { SYS_RES_MEMORY, AGP_I965_APBASE, RF_ACTIVE | RF_SHAREABLE },
 193         { -1, 0 }
 194 };
 195
 196 struct agp_i810_softc {
 197         struct agp_softc agp;
 198         u_int32_t initial_aperture;     /* aperture size at startup */
 199         struct agp_gatt *gatt;
 200         u_int32_t dcache_size;          /* i810 only */
 201         u_int32_t stolen;               /* number of i830/845 gtt
 202                                            entries for stolen memory */
 203         u_int stolen_size;              /* BIOS-reserved graphics memory */
 204         u_int gtt_total_entries;        /* Total number of gtt ptes */
 205         u_int gtt_mappable_entries;     /* Number of gtt ptes mappable by CPU */
 206         device_t bdev;                  /* bridge device */
 207         void *argb_cursor;              /* contigmalloc area for ARGB cursor */
 208         struct resource *sc_res[2];
 209         const struct agp_i810_match *match;
 210         int sc_flush_page_rid;
 211         struct resource *sc_flush_page_res;
 212         void *sc_flush_page_vaddr;
 213         int sc_bios_allocated_flush_page;
 214 };
 215
 216 static device_t intel_agp;
 217
 218 struct agp_i810_driver {
 219         int chiptype;
 220         int gen;
 221         int busdma_addr_mask_sz;
 222         struct resource_spec *res_spec;
 223         int (*check_active)(device_t);
 224         void (*set_desc)(device_t, const struct agp_i810_match *);
 225         void (*dump_regs)(device_t);
 226         int (*get_stolen_size)(device_t);
 227         int (*get_gtt_total_entries)(device_t);
 228         int (*get_gtt_mappable_entries)(device_t);
 229         int (*install_gatt)(device_t);
 230         void (*deinstall_gatt)(device_t);
 231         void (*write_gtt)(device_t, u_int, uint32_t);
 232         void (*install_gtt_pte)(device_t, u_int, vm_offset_t, int);
 233         u_int32_t (*read_gtt_pte)(device_t, u_int);
 234         vm_paddr_t (*read_gtt_pte_paddr)(device_t , u_int);
 235         int (*set_aperture)(device_t, u_int32_t);
 236         int (*chipset_flush_setup)(device_t);
 237         void (*chipset_flush_teardown)(device_t);
 238         void (*chipset_flush)(device_t);
 239 };
 240
 241 static struct {
 242         struct intel_gtt base;
 243 } intel_private;
 244
 245 static const struct agp_i810_driver agp_i810_i810_driver = {
 246         .chiptype = CHIP_I810,
 247         .gen = 1,
 248         .busdma_addr_mask_sz = 32,
 249         .res_spec = agp_i810_res_spec,
 250         .check_active = agp_i810_check_active,
 251         .set_desc = agp_i810_set_desc,
 252         .dump_regs = agp_i810_dump_regs,
 253         .get_stolen_size = agp_i810_get_stolen_size,
 254         .get_gtt_mappable_entries = agp_i810_get_gtt_mappable_entries,
 255         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
 256         .install_gatt = agp_i810_install_gatt,
 257         .deinstall_gatt = agp_i810_deinstall_gatt,
 258         .write_gtt = agp_i810_write_gtt,
 259         .install_gtt_pte = agp_i810_install_gtt_pte,
 260         .read_gtt_pte = agp_i810_read_gtt_pte,
 261         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
 262         .set_aperture = agp_i810_set_aperture,
 263         .chipset_flush_setup = agp_i810_chipset_flush_setup,
 264         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
 265         .chipset_flush = agp_i810_chipset_flush,
 266 };
 267
 268 static const struct agp_i810_driver agp_i810_i815_driver = {
 269         .chiptype = CHIP_I810,
 270         .gen = 2,
 271         .busdma_addr_mask_sz = 32,
 272         .res_spec = agp_i810_res_spec,
 273         .check_active = agp_i810_check_active,
 274         .set_desc = agp_i810_set_desc,
 275         .dump_regs = agp_i810_dump_regs,
 276         .get_stolen_size = agp_i810_get_stolen_size,
 277         .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
 278         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
 279         .install_gatt = agp_i810_install_gatt,
 280         .deinstall_gatt = agp_i810_deinstall_gatt,
 281         .write_gtt = agp_i810_write_gtt,
 282         .install_gtt_pte = agp_i810_install_gtt_pte,
 283         .read_gtt_pte = agp_i810_read_gtt_pte,
 284         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
 285         .set_aperture = agp_i810_set_aperture,
 286         .chipset_flush_setup = agp_i810_chipset_flush_setup,
 287         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
 288         .chipset_flush = agp_i830_chipset_flush,
 289 };
 290
 291 static const struct agp_i810_driver agp_i810_i830_driver = {
 292         .chiptype = CHIP_I830,
 293         .gen = 2,
 294         .busdma_addr_mask_sz = 32,
 295         .res_spec = agp_i810_res_spec,
 296         .check_active = agp_i830_check_active,
 297         .set_desc = agp_i810_set_desc,
 298         .dump_regs = agp_i830_dump_regs,
 299         .get_stolen_size = agp_i830_get_stolen_size,
 300         .get_gtt_mappable_entries = agp_i830_get_gtt_mappable_entries,
 301         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
 302         .install_gatt = agp_i830_install_gatt,
 303         .deinstall_gatt = agp_i830_deinstall_gatt,
 304         .write_gtt = agp_i810_write_gtt,
 305         .install_gtt_pte = agp_i830_install_gtt_pte,
 306         .read_gtt_pte = agp_i810_read_gtt_pte,
 307         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
 308         .set_aperture = agp_i830_set_aperture,
 309         .chipset_flush_setup = agp_i810_chipset_flush_setup,
 310         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
 311         .chipset_flush = agp_i830_chipset_flush,
 312 };
 313
 314 static const struct agp_i810_driver agp_i810_i855_driver = {
 315         .chiptype = CHIP_I855,
 316         .gen = 2,
 317         .busdma_addr_mask_sz = 32,
 318         .res_spec = agp_i810_res_spec,
 319         .check_active = agp_i830_check_active,
 320         .set_desc = agp_82852_set_desc,
 321         .dump_regs = agp_i855_dump_regs,
 322         .get_stolen_size = agp_i915_get_stolen_size,
 323         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 324         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
 325         .install_gatt = agp_i830_install_gatt,
 326         .deinstall_gatt = agp_i830_deinstall_gatt,
 327         .write_gtt = agp_i810_write_gtt,
 328         .install_gtt_pte = agp_i830_install_gtt_pte,
 329         .read_gtt_pte = agp_i810_read_gtt_pte,
 330         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
 331         .set_aperture = agp_i830_set_aperture,
 332         .chipset_flush_setup = agp_i810_chipset_flush_setup,
 333         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
 334         .chipset_flush = agp_i830_chipset_flush,
 335 };
 336
 337 static const struct agp_i810_driver agp_i810_i865_driver = {
 338         .chiptype = CHIP_I855,
 339         .gen = 2,
 340         .busdma_addr_mask_sz = 32,
 341         .res_spec = agp_i810_res_spec,
 342         .check_active = agp_i830_check_active,
 343         .set_desc = agp_i810_set_desc,
 344         .dump_regs = agp_i855_dump_regs,
 345         .get_stolen_size = agp_i915_get_stolen_size,
 346         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 347         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
 348         .install_gatt = agp_i830_install_gatt,
 349         .deinstall_gatt = agp_i830_deinstall_gatt,
 350         .write_gtt = agp_i810_write_gtt,
 351         .install_gtt_pte = agp_i830_install_gtt_pte,
 352         .read_gtt_pte = agp_i810_read_gtt_pte,
 353         .read_gtt_pte_paddr = agp_i810_read_gtt_pte_paddr,
 354         .set_aperture = agp_i915_set_aperture,
 355         .chipset_flush_setup = agp_i810_chipset_flush_setup,
 356         .chipset_flush_teardown = agp_i810_chipset_flush_teardown,
 357         .chipset_flush = agp_i830_chipset_flush,
 358 };
 359
 360 static const struct agp_i810_driver agp_i810_i915_driver = {
 361         .chiptype = CHIP_I915,
 362         .gen = 3,
 363         .busdma_addr_mask_sz = 32,
 364         .res_spec = agp_i915_res_spec,
 365         .check_active = agp_i915_check_active,
 366         .set_desc = agp_i810_set_desc,
 367         .dump_regs = agp_i915_dump_regs,
 368         .get_stolen_size = agp_i915_get_stolen_size,
 369         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 370         .get_gtt_total_entries = agp_i810_get_gtt_total_entries,
 371         .install_gatt = agp_i830_install_gatt,
 372         .deinstall_gatt = agp_i830_deinstall_gatt,
 373         .write_gtt = agp_i915_write_gtt,
 374         .install_gtt_pte = agp_i915_install_gtt_pte,
 375         .read_gtt_pte = agp_i915_read_gtt_pte,
 376         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
 377         .set_aperture = agp_i915_set_aperture,
 378         .chipset_flush_setup = agp_i915_chipset_flush_setup,
 379         .chipset_flush_teardown = agp_i915_chipset_flush_teardown,
 380         .chipset_flush = agp_i915_chipset_flush,
 381 };
 382
 383 static const struct agp_i810_driver agp_i810_g33_driver = {
 384         .chiptype = CHIP_G33,
 385         .gen = 3,
 386         .busdma_addr_mask_sz = 36,
 387         .res_spec = agp_i915_res_spec,
 388         .check_active = agp_i915_check_active,
 389         .set_desc = agp_i810_set_desc,
 390         .dump_regs = agp_i965_dump_regs,
 391         .get_stolen_size = agp_i915_get_stolen_size,
 392         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 393         .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
 394         .install_gatt = agp_i830_install_gatt,
 395         .deinstall_gatt = agp_i830_deinstall_gatt,
 396         .write_gtt = agp_i915_write_gtt,
 397         .install_gtt_pte = agp_i915_install_gtt_pte,
 398         .read_gtt_pte = agp_i915_read_gtt_pte,
 399         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
 400         .set_aperture = agp_i915_set_aperture,
 401         .chipset_flush_setup = agp_i965_chipset_flush_setup,
 402         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
 403         .chipset_flush = agp_i915_chipset_flush,
 404 };
 405
 406 static const struct agp_i810_driver agp_i810_igd_driver = {
 407         .chiptype = CHIP_IGD,
 408         .gen = 3,
 409         .busdma_addr_mask_sz = 36,
 410         .res_spec = agp_i915_res_spec,
 411         .check_active = agp_i915_check_active,
 412         .set_desc = agp_i810_set_desc,
 413         .dump_regs = agp_i915_dump_regs,
 414         .get_stolen_size = agp_i915_get_stolen_size,
 415         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 416         .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
 417         .install_gatt = agp_i830_install_gatt,
 418         .deinstall_gatt = agp_i830_deinstall_gatt,
 419         .write_gtt = agp_i915_write_gtt,
 420         .install_gtt_pte = agp_i915_install_gtt_pte,
 421         .read_gtt_pte = agp_i915_read_gtt_pte,
 422         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
 423         .set_aperture = agp_i915_set_aperture,
 424         .chipset_flush_setup = agp_i965_chipset_flush_setup,
 425         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
 426         .chipset_flush = agp_i915_chipset_flush,
 427 };
 428
 429 static const struct agp_i810_driver agp_i810_g965_driver = {
 430         .chiptype = CHIP_I965,
 431         .gen = 4,
 432         .busdma_addr_mask_sz = 36,
 433         .res_spec = agp_i965_res_spec,
 434         .check_active = agp_i915_check_active,
 435         .set_desc = agp_i810_set_desc,
 436         .dump_regs = agp_i965_dump_regs,
 437         .get_stolen_size = agp_i915_get_stolen_size,
 438         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 439         .get_gtt_total_entries = agp_i965_get_gtt_total_entries,
 440         .install_gatt = agp_i965_install_gatt,
 441         .deinstall_gatt = agp_i830_deinstall_gatt,
 442         .write_gtt = agp_i965_write_gtt,
 443         .install_gtt_pte = agp_i965_install_gtt_pte,
 444         .read_gtt_pte = agp_i965_read_gtt_pte,
 445         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
 446         .set_aperture = agp_i915_set_aperture,
 447         .chipset_flush_setup = agp_i965_chipset_flush_setup,
 448         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
 449         .chipset_flush = agp_i915_chipset_flush,
 450 };
 451
 452 static const struct agp_i810_driver agp_i810_g4x_driver = {
 453         .chiptype = CHIP_G4X,
 454         .gen = 5,
 455         .busdma_addr_mask_sz = 36,
 456         .res_spec = agp_i965_res_spec,
 457         .check_active = agp_i915_check_active,
 458         .set_desc = agp_i810_set_desc,
 459         .dump_regs = agp_i965_dump_regs,
 460         .get_stolen_size = agp_i915_get_stolen_size,
 461         .get_gtt_mappable_entries = agp_i915_get_gtt_mappable_entries,
 462         .get_gtt_total_entries = agp_gen5_get_gtt_total_entries,
 463         .install_gatt = agp_g4x_install_gatt,
 464         .deinstall_gatt = agp_i830_deinstall_gatt,
 465         .write_gtt = agp_g4x_write_gtt,
 466         .install_gtt_pte = agp_g4x_install_gtt_pte,
 467         .read_gtt_pte = agp_g4x_read_gtt_pte,
 468         .read_gtt_pte_paddr = agp_i915_read_gtt_pte_paddr,
 469         .set_aperture = agp_i915_set_aperture,
 470         .chipset_flush_setup = agp_i965_chipset_flush_setup,
 471         .chipset_flush_teardown = agp_i965_chipset_flush_teardown,
 472         .chipset_flush = agp_i915_chipset_flush,
 473 };
 474
 475 /* For adding new devices, devid is the id of the graphics controller
 476  * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 477  * second head should never be added.  The bridge_offset is the offset to
 478  * subtract from devid to get the id of the hostb that the device is on.
 479  */
 480 static const struct agp_i810_match {
 481         int devid;
 482         char *name;
 483         const struct agp_i810_driver *driver;
 484 } agp_i810_matches[] = {
 485         {
 486                 .devid = 0x71218086,
 487                 .name = "Intel 82810 (i810 GMCH) SVGA controller",
 488                 .driver = &agp_i810_i810_driver
 489         },
 490         {
 491                 .devid = 0x71238086,
 492                 .name = "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller",
 493                 .driver = &agp_i810_i810_driver
 494         },
 495         {
 496                 .devid = 0x71258086,
 497                 .name = "Intel 82810E (i810E GMCH) SVGA controller",
 498                 .driver = &agp_i810_i810_driver
 499         },
 500         {
 501                 .devid = 0x11328086,
 502                 .name = "Intel 82815 (i815 GMCH) SVGA controller",
 503                 .driver = &agp_i810_i815_driver
 504         },
 505         {
 506                 .devid = 0x35778086,
 507                 .name = "Intel 82830M (830M GMCH) SVGA controller",
 508                 .driver = &agp_i810_i830_driver
 509         },
 510         {
 511                 .devid = 0x25628086,
 512                 .name = "Intel 82845M (845M GMCH) SVGA controller",
 513                 .driver = &agp_i810_i830_driver
 514         },
 515         {
 516                 .devid = 0x35828086,
 517                 .name = "Intel 82852/855GM SVGA controller",
 518                 .driver = &agp_i810_i855_driver
 519         },
 520         {
 521                 .devid = 0x25728086,
 522                 .name = "Intel 82865G (865G GMCH) SVGA controller",
 523                 .driver = &agp_i810_i865_driver
 524         },
 525         {
 526                 .devid = 0x25828086,
 527                 .name = "Intel 82915G (915G GMCH) SVGA controller",
 528                 .driver = &agp_i810_i915_driver
 529         },
 530         {
 531                 .devid = 0x258A8086,
 532                 .name = "Intel E7221 SVGA controller",
 533                 .driver = &agp_i810_i915_driver
 534         },
 535         {
 536                 .devid = 0x25928086,
 537                 .name = "Intel 82915GM (915GM GMCH) SVGA controller",
 538                 .driver = &agp_i810_i915_driver
 539         },
 540         {
 541                 .devid = 0x27728086,
 542                 .name = "Intel 82945G (945G GMCH) SVGA controller",
 543                 .driver = &agp_i810_i915_driver
 544         },
 545         {
 546                 .devid = 0x27A28086,
 547                 .name = "Intel 82945GM (945GM GMCH) SVGA controller",
 548                 .driver = &agp_i810_i915_driver
 549         },
 550         {
 551                 .devid = 0x27AE8086,
 552                 .name = "Intel 945GME SVGA controller",
 553                 .driver = &agp_i810_i915_driver
 554         },
 555         {
 556                 .devid = 0x29728086,
 557                 .name = "Intel 946GZ SVGA controller",
 558                 .driver = &agp_i810_g965_driver
 559         },
 560         {
 561                 .devid = 0x29828086,
 562                 .name = "Intel G965 SVGA controller",
 563                 .driver = &agp_i810_g965_driver
 564         },
 565         {
 566                 .devid = 0x29928086,
 567                 .name = "Intel Q965 SVGA controller",
 568                 .driver = &agp_i810_g965_driver
 569         },
 570         {
 571                 .devid = 0x29A28086,
 572                 .name = "Intel G965 SVGA controller",
 573                 .driver = &agp_i810_g965_driver
 574         },
 575         {
 576                 .devid = 0x29B28086,
 577                 .name = "Intel Q35 SVGA controller",
 578                 .driver = &agp_i810_g33_driver
 579         },
 580         {
 581                 .devid = 0x29C28086,
 582                 .name = "Intel G33 SVGA controller",
 583                 .driver = &agp_i810_g33_driver
 584         },
 585         {
 586                 .devid = 0x29D28086,
 587                 .name = "Intel Q33 SVGA controller",
 588                 .driver = &agp_i810_g33_driver
 589         },
 590         {
 591                 .devid = 0xA0018086,
 592                 .name = "Intel Pineview SVGA controller",
 593                 .driver = &agp_i810_igd_driver
 594         },
 595         {
 596                 .devid = 0xA0118086,
 597                 .name = "Intel Pineview (M) SVGA controller",
 598                 .driver = &agp_i810_igd_driver
 599         },
 600         {
 601                 .devid = 0x2A028086,
 602                 .name = "Intel GM965 SVGA controller",
 603                 .driver = &agp_i810_g965_driver
 604         },
 605         {
 606                 .devid = 0x2A128086,
 607                 .name = "Intel GME965 SVGA controller",
 608                 .driver = &agp_i810_g965_driver
 609         },
 610         {
 611                 .devid = 0x2A428086,
 612                 .name = "Intel GM45 SVGA controller",
 613                 .driver = &agp_i810_g4x_driver
 614         },
 615         {
 616                 .devid = 0x2E028086,
 617                 .name = "Intel Eaglelake SVGA controller",
 618                 .driver = &agp_i810_g4x_driver
 619         },
 620         {
 621                 .devid = 0x2E128086,
 622                 .name = "Intel Q45 SVGA controller",
 623                 .driver = &agp_i810_g4x_driver
 624         },
 625         {
 626                 .devid = 0x2E228086,
 627                 .name = "Intel G45 SVGA controller",
 628                 .driver = &agp_i810_g4x_driver
 629         },
 630         {
 631                 .devid = 0x2E328086,
 632                 .name = "Intel G41 SVGA controller",
 633                 .driver = &agp_i810_g4x_driver
 634         },
 635         {
 636                 .devid = 0x00428086,
 637                 .name = "Intel Ironlake (D) SVGA controller",
 638                 .driver = &agp_i810_g4x_driver
 639         },
 640         {
 641                 .devid = 0x00468086,
 642                 .name = "Intel Ironlake (M) SVGA controller",
 643                 .driver = &agp_i810_g4x_driver
 644         },
 645         {
 646                 .devid = 0,
 647         }
 648 };
 649
 650 static const struct agp_i810_match*
 651 agp_i810_match(device_t dev)
 652 {
 653         int i, devid;
 654
 655         if (pci_get_class(dev) != PCIC_DISPLAY
 656             || (pci_get_subclass(dev) != PCIS_DISPLAY_VGA &&
 657             pci_get_subclass(dev) != PCIS_DISPLAY_OTHER))
 658                 return (NULL);
 659
 660         devid = pci_get_devid(dev);
 661         for (i = 0; agp_i810_matches[i].devid != 0; i++) {
 662                 if (agp_i810_matches[i].devid == devid)
 663                         break;
 664         }
 665         if (agp_i810_matches[i].devid == 0)
 666                 return (NULL);
 667         else
 668                 return (&agp_i810_matches[i]);
 669 }
 670
 671 /*
 672  * Find bridge device.
 673  */
 674 static device_t
 675 agp_i810_find_bridge(device_t dev)
 676 {
 677
 678         return (pci_find_dbsf(0, 0, 0, 0));
 679 }
 680
 681 static void
 682 agp_i810_identify(driver_t *driver, device_t parent)
 683 {
 684
 685         if (device_find_child(parent, "agp", -1) == NULL &&
 686             agp_i810_match(parent))
 687                 device_add_child(parent, "agp", -1);
 688 }
 689
 690 static int
 691 agp_i810_check_active(device_t bridge_dev)
 692 {
 693         u_int8_t smram;
 694
 695         smram = pci_read_config(bridge_dev, AGP_I810_SMRAM, 1);
 696         if ((smram & AGP_I810_SMRAM_GMS) == AGP_I810_SMRAM_GMS_DISABLED)
 697                 return (ENXIO);
 698         return (0);
 699 }
 700
 701 static int
 702 agp_i830_check_active(device_t bridge_dev)
 703 {
 704         int gcc1;
 705
 706         gcc1 = pci_read_config(bridge_dev, AGP_I830_GCC1, 1);
 707         if ((gcc1 & AGP_I830_GCC1_DEV2) == AGP_I830_GCC1_DEV2_DISABLED)
 708                 return (ENXIO);
 709         return (0);
 710 }
 711
 712 static int
 713 agp_i915_check_active(device_t bridge_dev)
 714 {
 715         int deven;
 716
 717         deven = pci_read_config(bridge_dev, AGP_I915_DEVEN, 4);
 718         if ((deven & AGP_I915_DEVEN_D2F0) == AGP_I915_DEVEN_D2F0_DISABLED)
 719                 return (ENXIO);
 720         return (0);
 721 }
 722
 723 static void
 724 agp_82852_set_desc(device_t dev, const struct agp_i810_match *match)
 725 {
 726
 727         switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
 728         case AGP_I855_GME:
 729                 device_set_desc(dev,
 730                     "Intel 82855GME (855GME GMCH) SVGA controller");
 731                 break;
 732         case AGP_I855_GM:
 733                 device_set_desc(dev,
 734                     "Intel 82855GM (855GM GMCH) SVGA controller");
 735                 break;
 736         case AGP_I852_GME:
 737                 device_set_desc(dev,
 738                     "Intel 82852GME (852GME GMCH) SVGA controller");
 739                 break;
 740         case AGP_I852_GM:
 741                 device_set_desc(dev,
 742                     "Intel 82852GM (852GM GMCH) SVGA controller");
 743                 break;
 744         default:
 745                 device_set_desc(dev,
 746                     "Intel 8285xM (85xGM GMCH) SVGA controller");
 747                 break;
 748         }
 749 }
 750
 751 static void
 752 agp_i810_set_desc(device_t dev, const struct agp_i810_match *match)
 753 {
 754
 755         device_set_desc(dev, match->name);
 756 }
 757
 758 static int
 759 agp_i810_probe(device_t dev)
 760 {
 761         device_t bdev;
 762         const struct agp_i810_match *match;
 763         int err;
 764
 765         if (resource_disabled("agp", device_get_unit(dev)))
 766                 return (ENXIO);
 767         match = agp_i810_match(dev);
 768         if (match == NULL)
 769                 return (ENXIO);
 770
 771         bdev = agp_i810_find_bridge(dev);
 772         if (bdev == NULL) {
 773                 if (bootverbose)
 774                         printf("I810: can't find bridge device\n");
 775                 return (ENXIO);
 776         }
 777
 778         /*
 779          * checking whether internal graphics device has been activated.
 780          */
 781         err = match->driver->check_active(bdev);
 782         if (err != 0) {
 783                 if (bootverbose)
 784                         printf("i810: disabled, not probing\n");
 785                 return (err);
 786         }
 787
 788         match->driver->set_desc(dev, match);
 789         return (BUS_PROBE_DEFAULT);
 790 }
 791
 792 static void
 793 agp_i810_dump_regs(device_t dev)
 794 {
 795         struct agp_i810_softc *sc = device_get_softc(dev);
 796
 797         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 798             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 799         device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
 800             pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
 801 }
 802
 803 static void
 804 agp_i830_dump_regs(device_t dev)
 805 {
 806         struct agp_i810_softc *sc = device_get_softc(dev);
 807
 808         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 809             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 810         device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
 811             pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
 812 }
 813
 814 static void
 815 agp_i855_dump_regs(device_t dev)
 816 {
 817         struct agp_i810_softc *sc = device_get_softc(dev);
 818
 819         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 820             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 821         device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 822             pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 823 }
 824
 825 static void
 826 agp_i915_dump_regs(device_t dev)
 827 {
 828         struct agp_i810_softc *sc = device_get_softc(dev);
 829
 830         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 831             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 832         device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 833             pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 834         device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
 835             pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
 836 }
 837
 838 static void
 839 agp_i965_dump_regs(device_t dev)
 840 {
 841         struct agp_i810_softc *sc = device_get_softc(dev);
 842
 843         device_printf(dev, "AGP_I965_PGTBL_CTL2: %08x\n",
 844             bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2));
 845         device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 846             pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 847         device_printf(dev, "AGP_I965_MSAC: 0x%02x\n",
 848             pci_read_config(sc->bdev, AGP_I965_MSAC, 1));
 849 }
 850
 851 static int
 852 agp_i810_get_stolen_size(device_t dev)
 853 {
 854         struct agp_i810_softc *sc;
 855
 856         sc = device_get_softc(dev);
 857         sc->stolen = 0;
 858         sc->stolen_size = 0;
 859         return (0);
 860 }
 861
 862 static int
 863 agp_i830_get_stolen_size(device_t dev)
 864 {
 865         struct agp_i810_softc *sc;
 866         unsigned int gcc1;
 867
 868         sc = device_get_softc(dev);
 869
 870         gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
 871         switch (gcc1 & AGP_I830_GCC1_GMS) {
 872         case AGP_I830_GCC1_GMS_STOLEN_512:
 873                 sc->stolen = (512 - 132) * 1024 / 4096;
 874                 sc->stolen_size = 512 * 1024;
 875                 break;
 876         case AGP_I830_GCC1_GMS_STOLEN_1024:
 877                 sc->stolen = (1024 - 132) * 1024 / 4096;
 878                 sc->stolen_size = 1024 * 1024;
 879                 break;
 880         case AGP_I830_GCC1_GMS_STOLEN_8192:
 881                 sc->stolen = (8192 - 132) * 1024 / 4096;
 882                 sc->stolen_size = 8192 * 1024;
 883                 break;
 884         default:
 885                 sc->stolen = 0;
 886                 device_printf(dev,
 887                     "unknown memory configuration, disabling (GCC1 %x)\n",
 888                     gcc1);
 889                 return (EINVAL);
 890         }
 891         return (0);
 892 }
 893
 894 static int
 895 agp_i915_get_stolen_size(device_t dev)
 896 {
 897         struct agp_i810_softc *sc;
 898         unsigned int gcc1, stolen, gtt_size;
 899
 900         sc = device_get_softc(dev);
 901
 902         /*
 903          * Stolen memory is set up at the beginning of the aperture by
 904          * the BIOS, consisting of the GATT followed by 4kb for the
 905          * BIOS display.
 906          */
 907         switch (sc->match->driver->chiptype) {
 908         case CHIP_I855:
 909                 gtt_size = 128;
 910                 break;
 911         case CHIP_I915:
 912                 gtt_size = 256;
 913                 break;
 914         case CHIP_I965:
 915                 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
 916                         AGP_I810_PGTBL_SIZE_MASK) {
 917                 case AGP_I810_PGTBL_SIZE_128KB:
 918                         gtt_size = 128;
 919                         break;
 920                 case AGP_I810_PGTBL_SIZE_256KB:
 921                         gtt_size = 256;
 922                         break;
 923                 case AGP_I810_PGTBL_SIZE_512KB:
 924                         gtt_size = 512;
 925                         break;
 926                 case AGP_I965_PGTBL_SIZE_1MB:
 927                         gtt_size = 1024;
 928                         break;
 929                 case AGP_I965_PGTBL_SIZE_2MB:
 930                         gtt_size = 2048;
 931                         break;
 932                 case AGP_I965_PGTBL_SIZE_1_5MB:
 933                         gtt_size = 1024 + 512;
 934                         break;
 935                 default:
 936                         device_printf(dev, "Bad PGTBL size\n");
 937                         return (EINVAL);
 938                 }
 939                 break;
 940         case CHIP_G33:
 941                 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
 942                 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
 943                 case AGP_G33_MGGC_GGMS_SIZE_1M:
 944                         gtt_size = 1024;
 945                         break;
 946                 case AGP_G33_MGGC_GGMS_SIZE_2M:
 947                         gtt_size = 2048;
 948                         break;
 949                 default:
 950                         device_printf(dev, "Bad PGTBL size\n");
 951                         return (EINVAL);
 952                 }
 953                 break;
 954         case CHIP_IGD:
 955         case CHIP_G4X:
 956                 gtt_size = 0;
 957                 break;
 958         default:
 959                 device_printf(dev, "Bad chiptype\n");
 960                 return (EINVAL);
 961         }
 962
 963         /* GCC1 is called MGGC on i915+ */
 964         gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
 965         switch (gcc1 & AGP_I855_GCC1_GMS) {
 966         case AGP_I855_GCC1_GMS_STOLEN_1M:
 967                 stolen = 1024;
 968                 break;
 969         case AGP_I855_GCC1_GMS_STOLEN_4M:
 970                 stolen = 4 * 1024;
 971                 break;
 972         case AGP_I855_GCC1_GMS_STOLEN_8M:
 973                 stolen = 8 * 1024;
 974                 break;
 975         case AGP_I855_GCC1_GMS_STOLEN_16M:
 976                 stolen = 16 * 1024;
 977                 break;
 978         case AGP_I855_GCC1_GMS_STOLEN_32M:
 979                 stolen = 32 * 1024;
 980                 break;
 981         case AGP_I915_GCC1_GMS_STOLEN_48M:
 982                 stolen = sc->match->driver->gen > 2 ? 48 * 1024 : 0;
 983                 break;
 984         case AGP_I915_GCC1_GMS_STOLEN_64M:
 985                 stolen = sc->match->driver->gen > 2 ? 64 * 1024 : 0;
 986                 break;
 987         case AGP_G33_GCC1_GMS_STOLEN_128M:
 988                 stolen = sc->match->driver->gen > 2 ? 128 * 1024 : 0;
 989                 break;
 990         case AGP_G33_GCC1_GMS_STOLEN_256M:
 991                 stolen = sc->match->driver->gen > 2 ? 256 * 1024 : 0;
 992                 break;
 993         case AGP_G4X_GCC1_GMS_STOLEN_96M:
 994                 if (sc->match->driver->chiptype == CHIP_I965 ||
 995                     sc->match->driver->chiptype == CHIP_G4X)
 996                         stolen = 96 * 1024;
 997                 else
 998                         stolen = 0;
 999                 break;
1000         case AGP_G4X_GCC1_GMS_STOLEN_160M:
1001                 if (sc->match->driver->chiptype == CHIP_I965 ||
1002                     sc->match->driver->chiptype == CHIP_G4X)
1003                         stolen = 160 * 1024;
1004                 else
1005                         stolen = 0;
1006                 break;
1007         case AGP_G4X_GCC1_GMS_STOLEN_224M:
1008                 if (sc->match->driver->chiptype == CHIP_I965 ||
1009                     sc->match->driver->chiptype == CHIP_G4X)
1010                         stolen = 224 * 1024;
1011                 else
1012                         stolen = 0;
1013                 break;
1014         case AGP_G4X_GCC1_GMS_STOLEN_352M:
1015                 if (sc->match->driver->chiptype == CHIP_I965 ||
1016                     sc->match->driver->chiptype == CHIP_G4X)
1017                         stolen = 352 * 1024;
1018                 else
1019                         stolen = 0;
1020                 break;
1021         default:
1022                 device_printf(dev,
1023                     "unknown memory configuration, disabling (GCC1 %x)\n",
1024                     gcc1);
1025                 return (EINVAL);
1026         }
1027
1028         gtt_size += 4;
1029         sc->stolen_size = stolen * 1024;
1030         sc->stolen = (stolen - gtt_size) * 1024 / 4096;
1031
1032         return (0);
1033 }
1034
1035 static int
1036 agp_i810_get_gtt_mappable_entries(device_t dev)
1037 {
1038         struct agp_i810_softc *sc;
1039         uint32_t ap;
1040         uint16_t miscc;
1041
1042         sc = device_get_softc(dev);
1043         miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
1044         if ((miscc & AGP_I810_MISCC_WINSIZE) == AGP_I810_MISCC_WINSIZE_32)
1045                 ap = 32;
1046         else
1047                 ap = 64;
1048         sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT;
1049         return (0);
1050 }
1051
1052 static int
1053 agp_i830_get_gtt_mappable_entries(device_t dev)
1054 {
1055         struct agp_i810_softc *sc;
1056         uint32_t ap;
1057         uint16_t gmch_ctl;
1058
1059         sc = device_get_softc(dev);
1060         gmch_ctl = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1061         if ((gmch_ctl & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
1062                 ap = 64;
1063         else
1064                 ap = 128;
1065         sc->gtt_mappable_entries = (ap * 1024 * 1024) >> AGP_PAGE_SHIFT;
1066         return (0);
1067 }
1068
1069 static int
1070 agp_i915_get_gtt_mappable_entries(device_t dev)
1071 {
1072         struct agp_i810_softc *sc;
1073         uint32_t ap;
1074
1075         sc = device_get_softc(dev);
1076         ap = AGP_GET_APERTURE(dev);
1077         sc->gtt_mappable_entries = ap >> AGP_PAGE_SHIFT;
1078         return (0);
1079 }
1080
1081 static int
1082 agp_i810_get_gtt_total_entries(device_t dev)
1083 {
1084         struct agp_i810_softc *sc;
1085
1086         sc = device_get_softc(dev);
1087         sc->gtt_total_entries = sc->gtt_mappable_entries;
1088         return (0);
1089 }
1090
1091 static int
1092 agp_i965_get_gtt_total_entries(device_t dev)
1093 {
1094         struct agp_i810_softc *sc;
1095         uint32_t pgetbl_ctl;
1096         int error;
1097
1098         sc = device_get_softc(dev);
1099         error = 0;
1100         pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1101         switch (pgetbl_ctl & AGP_I810_PGTBL_SIZE_MASK) {
1102         case AGP_I810_PGTBL_SIZE_128KB:
1103                 sc->gtt_total_entries = 128 * 1024 / 4;
1104                 break;
1105         case AGP_I810_PGTBL_SIZE_256KB:
1106                 sc->gtt_total_entries = 256 * 1024 / 4;
1107                 break;
1108         case AGP_I810_PGTBL_SIZE_512KB:
1109                 sc->gtt_total_entries = 512 * 1024 / 4;
1110                 break;
1111         /* GTT pagetable sizes bigger than 512KB are not possible on G33! */
1112         case AGP_I810_PGTBL_SIZE_1MB:
1113                 sc->gtt_total_entries = 1024 * 1024 / 4;
1114                 break;
1115         case AGP_I810_PGTBL_SIZE_2MB:
1116                 sc->gtt_total_entries = 2 * 1024 * 1024 / 4;
1117                 break;
1118         case AGP_I810_PGTBL_SIZE_1_5MB:
1119                 sc->gtt_total_entries = (1024 + 512) * 1024 / 4;
1120                 break;
1121         default:
1122                 device_printf(dev, "Unknown page table size\n");
1123                 error = ENXIO;
1124         }
1125         return (error);
1126 }
1127
1128 static void
1129 agp_gen5_adjust_pgtbl_size(device_t dev, uint32_t sz)
1130 {
1131         struct agp_i810_softc *sc;
1132         uint32_t pgetbl_ctl, pgetbl_ctl2;
1133
1134         sc = device_get_softc(dev);
1135
1136         /* Disable per-process page table. */
1137         pgetbl_ctl2 = bus_read_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2);
1138         pgetbl_ctl2 &= ~AGP_I810_PGTBL_ENABLED;
1139         bus_write_4(sc->sc_res[0], AGP_I965_PGTBL_CTL2, pgetbl_ctl2);
1140
1141         /* Write the new ggtt size. */
1142         pgetbl_ctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1143         pgetbl_ctl &= ~AGP_I810_PGTBL_SIZE_MASK;
1144         pgetbl_ctl |= sz;
1145         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgetbl_ctl);
1146 }
1147
1148 static int
1149 agp_gen5_get_gtt_total_entries(device_t dev)
1150 {
1151         struct agp_i810_softc *sc;
1152         uint16_t gcc1;
1153
1154         sc = device_get_softc(dev);
1155
1156         gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1157         switch (gcc1 & AGP_G4x_GCC1_SIZE_MASK) {
1158         case AGP_G4x_GCC1_SIZE_1M:
1159         case AGP_G4x_GCC1_SIZE_VT_1M:
1160                 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1MB);
1161                 break;
1162         case AGP_G4x_GCC1_SIZE_VT_1_5M:
1163                 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_1_5MB);
1164                 break;
1165         case AGP_G4x_GCC1_SIZE_2M:
1166         case AGP_G4x_GCC1_SIZE_VT_2M:
1167                 agp_gen5_adjust_pgtbl_size(dev, AGP_I810_PGTBL_SIZE_2MB);
1168                 break;
1169         default:
1170                 device_printf(dev, "Unknown page table size\n");
1171                 return (ENXIO);
1172         }
1173
1174         return (agp_i965_get_gtt_total_entries(dev));
1175 }
1176
1177 static int
1178 agp_i810_install_gatt(device_t dev)
1179 {
1180         struct agp_i810_softc *sc;
1181
1182         sc = device_get_softc(dev);
1183
1184         /* Some i810s have on-chip memory called dcache. */
1185         if ((bus_read_1(sc->sc_res[0], AGP_I810_DRT) & AGP_I810_DRT_POPULATED)
1186             != 0)
1187                 sc->dcache_size = 4 * 1024 * 1024;
1188         else
1189                 sc->dcache_size = 0;
1190
1191         /* According to the specs the gatt on the i810 must be 64k. */
1192         sc->gatt->ag_virtual = (void *)kmem_alloc_contig(kernel_arena,
1193             64 * 1024, M_NOWAIT | M_ZERO, 0, ~0, PAGE_SIZE,
1194             0, VM_MEMATTR_WRITE_COMBINING);
1195         if (sc->gatt->ag_virtual == NULL) {
1196                 if (bootverbose)
1197                         device_printf(dev, "contiguous allocation failed\n");
1198                 return (ENOMEM);
1199         }
1200
1201         sc->gatt->ag_physical = vtophys((vm_offset_t)sc->gatt->ag_virtual);
1202         /* Install the GATT. */
1203         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1204             sc->gatt->ag_physical | 1);
1205         return (0);
1206 }
1207
1208 static void
1209 agp_i830_install_gatt_init(struct agp_i810_softc *sc)
1210 {
1211         uint32_t pgtblctl;
1212
1213         /*
1214          * The i830 automatically initializes the 128k gatt on boot.
1215          * GATT address is already in there, make sure it's enabled.
1216          */
1217         pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1218         pgtblctl |= 1;
1219         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1220
1221         sc->gatt->ag_physical = pgtblctl & ~1;
1222 }
1223
1224 static int
1225 agp_i830_install_gatt(device_t dev)
1226 {
1227         struct agp_i810_softc *sc;
1228
1229         sc = device_get_softc(dev);
1230         agp_i830_install_gatt_init(sc);
1231         return (0);
1232 }
1233
1234 static int
1235 agp_gen4_install_gatt(device_t dev, const vm_size_t gtt_offset)
1236 {
1237         struct agp_i810_softc *sc;
1238
1239         sc = device_get_softc(dev);
1240         pmap_change_attr((vm_offset_t)rman_get_virtual(sc->sc_res[0]) +
1241             gtt_offset, rman_get_size(sc->sc_res[0]) - gtt_offset,
1242             VM_MEMATTR_WRITE_COMBINING);
1243         agp_i830_install_gatt_init(sc);
1244         return (0);
1245 }
1246
1247 static int
1248 agp_i965_install_gatt(device_t dev)
1249 {
1250
1251         return (agp_gen4_install_gatt(dev, 512 * 1024));
1252 }
1253
1254 static int
1255 agp_g4x_install_gatt(device_t dev)
1256 {
1257
1258         return (agp_gen4_install_gatt(dev, 2 * 1024 * 1024));
1259 }
1260
1261 static int
1262 agp_i810_attach(device_t dev)
1263 {
1264         struct agp_i810_softc *sc;
1265         int error;
1266
1267         sc = device_get_softc(dev);
1268         sc->bdev = agp_i810_find_bridge(dev);
1269         if (sc->bdev == NULL)
1270                 return (ENOENT);
1271
1272         sc->match = agp_i810_match(dev);
1273
1274         agp_set_aperture_resource(dev, sc->match->driver->gen <= 2 ?
1275             AGP_APBASE : AGP_I915_GMADR);
1276         error = agp_generic_attach(dev);
1277         if (error)
1278                 return (error);
1279
1280         if (ptoa((vm_paddr_t)Maxmem) >
1281             (1ULL << sc->match->driver->busdma_addr_mask_sz) - 1) {
1282                 device_printf(dev, "agp_i810 does not support physical "
1283                     "memory above %ju.\n", (uintmax_t)(1ULL <<
1284                     sc->match->driver->busdma_addr_mask_sz) - 1);
1285                 return (ENOENT);
1286         }
1287
1288         if (bus_alloc_resources(dev, sc->match->driver->res_spec, sc->sc_res)) {
1289                 agp_generic_detach(dev);
1290                 return (ENODEV);
1291         }
1292
1293         sc->initial_aperture = AGP_GET_APERTURE(dev);
1294         sc->gatt = malloc(sizeof(struct agp_gatt), M_AGP, M_WAITOK);
1295         sc->gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
1296
1297         if ((error = sc->match->driver->get_stolen_size(dev)) != 0 ||
1298             (error = sc->match->driver->install_gatt(dev)) != 0 ||
1299             (error = sc->match->driver->get_gtt_mappable_entries(dev)) != 0 ||
1300             (error = sc->match->driver->get_gtt_total_entries(dev)) != 0 ||
1301             (error = sc->match->driver->chipset_flush_setup(dev)) != 0) {
1302                 bus_release_resources(dev, sc->match->driver->res_spec,
1303                     sc->sc_res);
1304                 free(sc->gatt, M_AGP);
1305                 agp_generic_detach(dev);
1306                 return (error);
1307         }
1308
1309         intel_agp = dev;
1310         device_printf(dev, "aperture size is %dM",
1311             sc->initial_aperture / 1024 / 1024);
1312         if (sc->stolen > 0)
1313                 printf(", detected %dk stolen memory\n", sc->stolen * 4);
1314         else
1315                 printf("\n");
1316         if (bootverbose) {
1317                 sc->match->driver->dump_regs(dev);
1318                 device_printf(dev, "Mappable GTT entries: %d\n",
1319                     sc->gtt_mappable_entries);
1320                 device_printf(dev, "Total GTT entries: %d\n",
1321                     sc->gtt_total_entries);
1322         }
1323         return (0);
1324 }
1325
1326 static void
1327 agp_i810_deinstall_gatt(device_t dev)
1328 {
1329         struct agp_i810_softc *sc;
1330
1331         sc = device_get_softc(dev);
1332         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
1333         kmem_free(kernel_arena, (vm_offset_t)sc->gatt->ag_virtual, 64 * 1024);
1334 }
1335
1336 static void
1337 agp_i830_deinstall_gatt(device_t dev)
1338 {
1339         struct agp_i810_softc *sc;
1340         unsigned int pgtblctl;
1341
1342         sc = device_get_softc(dev);
1343         pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
1344         pgtblctl &= ~1;
1345         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
1346 }
1347
1348 static int
1349 agp_i810_detach(device_t dev)
1350 {
1351         struct agp_i810_softc *sc;
1352
1353         sc = device_get_softc(dev);
1354         agp_free_cdev(dev);
1355
1356         /* Clear the GATT base. */
1357         sc->match->driver->deinstall_gatt(dev);
1358
1359         sc->match->driver->chipset_flush_teardown(dev);
1360
1361         /* Put the aperture back the way it started. */
1362         AGP_SET_APERTURE(dev, sc->initial_aperture);
1363
1364         free(sc->gatt, M_AGP);
1365         bus_release_resources(dev, sc->match->driver->res_spec, sc->sc_res);
1366         agp_free_res(dev);
1367
1368         return (0);
1369 }
1370
1371 static int
1372 agp_i810_resume(device_t dev)
1373 {
1374         struct agp_i810_softc *sc;
1375         sc = device_get_softc(dev);
1376
1377         AGP_SET_APERTURE(dev, sc->initial_aperture);
1378
1379         /* Install the GATT. */
1380         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
1381         sc->gatt->ag_physical | 1);
1382
1383         return (bus_generic_resume(dev));
1384 }
1385
1386 /**
1387  * Sets the PCI resource size of the aperture on i830-class and below chipsets,
1388  * while returning failure on later chipsets when an actual change is
1389  * requested.
1390  *
1391  * This whole function is likely bogus, as the kernel would probably need to
1392  * reconfigure the placement of the AGP aperture if a larger size is requested,
1393  * which doesn't happen currently.
1394  */
1395 static int
1396 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
1397 {
1398         struct agp_i810_softc *sc;
1399         u_int16_t miscc;
1400
1401         sc = device_get_softc(dev);
1402         /*
1403          * Double check for sanity.
1404          */
1405         if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
1406                 device_printf(dev, "bad aperture size %d\n", aperture);
1407                 return (EINVAL);
1408         }
1409
1410         miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
1411         miscc &= ~AGP_I810_MISCC_WINSIZE;
1412         if (aperture == 32 * 1024 * 1024)
1413                 miscc |= AGP_I810_MISCC_WINSIZE_32;
1414         else
1415                 miscc |= AGP_I810_MISCC_WINSIZE_64;
1416
1417         pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
1418         return (0);
1419 }
1420
1421 static int
1422 agp_i830_set_aperture(device_t dev, u_int32_t aperture)
1423 {
1424         struct agp_i810_softc *sc;
1425         u_int16_t gcc1;
1426
1427         sc = device_get_softc(dev);
1428
1429         if (aperture != 64 * 1024 * 1024 &&
1430             aperture != 128 * 1024 * 1024) {
1431                 device_printf(dev, "bad aperture size %d\n", aperture);
1432                 return (EINVAL);
1433         }
1434         gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
1435         gcc1 &= ~AGP_I830_GCC1_GMASIZE;
1436         if (aperture == 64 * 1024 * 1024)
1437                 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
1438         else
1439                 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
1440
1441         pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
1442         return (0);
1443 }
1444
1445 static int
1446 agp_i915_set_aperture(device_t dev, u_int32_t aperture)
1447 {
1448
1449         return (agp_generic_set_aperture(dev, aperture));
1450 }
1451
1452 static int
1453 agp_i810_method_set_aperture(device_t dev, u_int32_t aperture)
1454 {
1455         struct agp_i810_softc *sc;
1456
1457         sc = device_get_softc(dev);
1458         return (sc->match->driver->set_aperture(dev, aperture));
1459 }
1460
1461 /**
1462  * Writes a GTT entry mapping the page at the given offset from the
1463  * beginning of the aperture to the given physical address.  Setup the
1464  * caching mode according to flags.
1465  *
1466  * For gen 1, 2 and 3, GTT start is located at AGP_I810_GTT offset
1467  * from corresponding BAR start. For gen 4, offset is 512KB +
1468  * AGP_I810_GTT, for gen 5 and 6 it is 2MB + AGP_I810_GTT.
1469  *
1470  * Also, the bits of the physical page address above 4GB needs to be
1471  * placed into bits 40-32 of PTE.
1472  */
1473 static void
1474 agp_i810_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1475     int flags)
1476 {
1477         uint32_t pte;
1478
1479         pte = (u_int32_t)physical | I810_PTE_VALID;
1480         if (flags == AGP_DCACHE_MEMORY)
1481                 pte |= I810_PTE_LOCAL;
1482         else if (flags == AGP_USER_CACHED_MEMORY)
1483                 pte |= I830_PTE_SYSTEM_CACHED;
1484         agp_i810_write_gtt(dev, index, pte);
1485 }
1486
1487 static void
1488 agp_i810_write_gtt(device_t dev, u_int index, uint32_t pte)
1489 {
1490         struct agp_i810_softc *sc;
1491
1492         sc = device_get_softc(dev);
1493         bus_write_4(sc->sc_res[0], AGP_I810_GTT + index * 4, pte);
1494         CTR2(KTR_AGP_I810, "810_pte %x %x", index, pte);
1495 }
1496
1497 static void
1498 agp_i830_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1499     int flags)
1500 {
1501         uint32_t pte;
1502
1503         pte = (u_int32_t)physical | I810_PTE_VALID;
1504         if (flags == AGP_USER_CACHED_MEMORY)
1505                 pte |= I830_PTE_SYSTEM_CACHED;
1506         agp_i810_write_gtt(dev, index, pte);
1507 }
1508
1509 static void
1510 agp_i915_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1511     int flags)
1512 {
1513         uint32_t pte;
1514
1515         pte = (u_int32_t)physical | I810_PTE_VALID;
1516         if (flags == AGP_USER_CACHED_MEMORY)
1517                 pte |= I830_PTE_SYSTEM_CACHED;
1518         pte |= (physical & 0x0000000f00000000ull) >> 28;
1519         agp_i915_write_gtt(dev, index, pte);
1520 }
1521
1522 static void
1523 agp_i915_write_gtt(device_t dev, u_int index, uint32_t pte)
1524 {
1525         struct agp_i810_softc *sc;
1526
1527         sc = device_get_softc(dev);
1528         bus_write_4(sc->sc_res[1], index * 4, pte);
1529         CTR2(KTR_AGP_I810, "915_pte %x %x", index, pte);
1530 }
1531
1532 static void
1533 agp_i965_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1534     int flags)
1535 {
1536         uint32_t pte;
1537
1538         pte = (u_int32_t)physical | I810_PTE_VALID;
1539         if (flags == AGP_USER_CACHED_MEMORY)
1540                 pte |= I830_PTE_SYSTEM_CACHED;
1541         pte |= (physical & 0x0000000f00000000ull) >> 28;
1542         agp_i965_write_gtt(dev, index, pte);
1543 }
1544
1545 static void
1546 agp_i965_write_gtt(device_t dev, u_int index, uint32_t pte)
1547 {
1548         struct agp_i810_softc *sc;
1549
1550         sc = device_get_softc(dev);
1551         bus_write_4(sc->sc_res[0], index * 4 + (512 * 1024), pte);
1552         CTR2(KTR_AGP_I810, "965_pte %x %x", index, pte);
1553 }
1554
1555 static void
1556 agp_g4x_install_gtt_pte(device_t dev, u_int index, vm_offset_t physical,
1557     int flags)
1558 {
1559         uint32_t pte;
1560
1561         pte = (u_int32_t)physical | I810_PTE_VALID;
1562         if (flags == AGP_USER_CACHED_MEMORY)
1563                 pte |= I830_PTE_SYSTEM_CACHED;
1564         pte |= (physical & 0x0000000f00000000ull) >> 28;
1565         agp_g4x_write_gtt(dev, index, pte);
1566 }
1567
1568 static void
1569 agp_g4x_write_gtt(device_t dev, u_int index, uint32_t pte)
1570 {
1571         struct agp_i810_softc *sc;
1572
1573         sc = device_get_softc(dev);
1574         bus_write_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024), pte);
1575         CTR2(KTR_AGP_I810, "g4x_pte %x %x", index, pte);
1576 }
1577
1578 static int
1579 agp_i810_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
1580 {
1581         struct agp_i810_softc *sc = device_get_softc(dev);
1582         u_int index;
1583
1584         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
1585                 device_printf(dev, "failed: offset is 0x%08jx, "
1586                     "shift is %d, entries is %d\n", (intmax_t)offset,
1587                     AGP_PAGE_SHIFT, sc->gatt->ag_entries);
1588                 return (EINVAL);
1589         }
1590         index = offset >> AGP_PAGE_SHIFT;
1591         if (sc->stolen != 0 && index < sc->stolen) {
1592                 device_printf(dev, "trying to bind into stolen memory\n");
1593                 return (EINVAL);
1594         }
1595         sc->match->driver->install_gtt_pte(dev, index, physical, 0);
1596         return (0);
1597 }
1598
1599 static int
1600 agp_i810_unbind_page(device_t dev, vm_offset_t offset)
1601 {
1602         struct agp_i810_softc *sc;
1603         u_int index;
1604
1605         sc = device_get_softc(dev);
1606         if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
1607                 return (EINVAL);
1608         index = offset >> AGP_PAGE_SHIFT;
1609         if (sc->stolen != 0 && index < sc->stolen) {
1610                 device_printf(dev, "trying to unbind from stolen memory\n");
1611                 return (EINVAL);
1612         }
1613         sc->match->driver->install_gtt_pte(dev, index, 0, 0);
1614         return (0);
1615 }
1616
1617 static u_int32_t
1618 agp_i810_read_gtt_pte(device_t dev, u_int index)
1619 {
1620         struct agp_i810_softc *sc;
1621         u_int32_t pte;
1622
1623         sc = device_get_softc(dev);
1624         pte = bus_read_4(sc->sc_res[0], AGP_I810_GTT + index * 4);
1625         return (pte);
1626 }
1627
1628 static u_int32_t
1629 agp_i915_read_gtt_pte(device_t dev, u_int index)
1630 {
1631         struct agp_i810_softc *sc;
1632         u_int32_t pte;
1633
1634         sc = device_get_softc(dev);
1635         pte = bus_read_4(sc->sc_res[1], index * 4);
1636         return (pte);
1637 }
1638
1639 static u_int32_t
1640 agp_i965_read_gtt_pte(device_t dev, u_int index)
1641 {
1642         struct agp_i810_softc *sc;
1643         u_int32_t pte;
1644
1645         sc = device_get_softc(dev);
1646         pte = bus_read_4(sc->sc_res[0], index * 4 + (512 * 1024));
1647         return (pte);
1648 }
1649
1650 static u_int32_t
1651 agp_g4x_read_gtt_pte(device_t dev, u_int index)
1652 {
1653         struct agp_i810_softc *sc;
1654         u_int32_t pte;
1655
1656         sc = device_get_softc(dev);
1657         pte = bus_read_4(sc->sc_res[0], index * 4 + (2 * 1024 * 1024));
1658         return (pte);
1659 }
1660
1661 static vm_paddr_t
1662 agp_i810_read_gtt_pte_paddr(device_t dev, u_int index)
1663 {
1664         struct agp_i810_softc *sc;
1665         u_int32_t pte;
1666         vm_paddr_t res;
1667
1668         sc = device_get_softc(dev);
1669         pte = sc->match->driver->read_gtt_pte(dev, index);
1670         res = pte & ~PAGE_MASK;
1671         return (res);
1672 }
1673
1674 static vm_paddr_t
1675 agp_i915_read_gtt_pte_paddr(device_t dev, u_int index)
1676 {
1677         struct agp_i810_softc *sc;
1678         u_int32_t pte;
1679         vm_paddr_t res;
1680
1681         sc = device_get_softc(dev);
1682         pte = sc->match->driver->read_gtt_pte(dev, index);
1683         res = (pte & ~PAGE_MASK) | ((pte & 0xf0) << 28);
1684         return (res);
1685 }
1686
1687 /*
1688  * Writing via memory mapped registers already flushes all TLBs.
1689  */
1690 static void
1691 agp_i810_flush_tlb(device_t dev)
1692 {
1693 }
1694
1695 static int
1696 agp_i810_enable(device_t dev, u_int32_t mode)
1697 {
1698
1699         return (0);
1700 }
1701
1702 static struct agp_memory *
1703 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
1704 {
1705         struct agp_i810_softc *sc;
1706         struct agp_memory *mem;
1707         vm_page_t m;
1708
1709         sc = device_get_softc(dev);
1710
1711         if ((size & (AGP_PAGE_SIZE - 1)) != 0 ||
1712             sc->agp.as_allocated + size > sc->agp.as_maxmem)
1713                 return (0);
1714
1715         if (type == 1) {
1716                 /*
1717                  * Mapping local DRAM into GATT.
1718                  */
1719                 if (sc->match->driver->chiptype != CHIP_I810)
1720                         return (0);
1721                 if (size != sc->dcache_size)
1722                         return (0);
1723         } else if (type == 2) {
1724                 /*
1725                  * Type 2 is the contiguous physical memory type, that hands
1726                  * back a physical address.  This is used for cursors on i810.
1727                  * Hand back as many single pages with physical as the user
1728                  * wants, but only allow one larger allocation (ARGB cursor)
1729                  * for simplicity.
1730                  */
1731                 if (size != AGP_PAGE_SIZE) {
1732                         if (sc->argb_cursor != NULL)
1733                                 return (0);
1734
1735                         /* Allocate memory for ARGB cursor, if we can. */
1736                         sc->argb_cursor = contigmalloc(size, M_AGP,
1737                            0, 0, ~0, PAGE_SIZE, 0);
1738                         if (sc->argb_cursor == NULL)
1739                                 return (0);
1740                 }
1741         }
1742
1743         mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
1744         mem->am_id = sc->agp.as_nextid++;
1745         mem->am_size = size;
1746         mem->am_type = type;
1747         if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
1748                 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
1749                     atop(round_page(size)));
1750         else
1751                 mem->am_obj = 0;
1752
1753         if (type == 2) {
1754                 if (size == AGP_PAGE_SIZE) {
1755                         /*
1756                          * Allocate and wire down the page now so that we can
1757                          * get its physical address.
1758                          */
1759                         VM_OBJECT_WLOCK(mem->am_obj);
1760                         m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
1761                             VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1762                         VM_OBJECT_WUNLOCK(mem->am_obj);
1763                         mem->am_physical = VM_PAGE_TO_PHYS(m);
1764                 } else {
1765                         /* Our allocation is already nicely wired down for us.
1766                          * Just grab the physical address.
1767                          */
1768                         mem->am_physical = vtophys(sc->argb_cursor);
1769                 }
1770         } else
1771                 mem->am_physical = 0;
1772
1773         mem->am_offset = 0;
1774         mem->am_is_bound = 0;
1775         TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
1776         sc->agp.as_allocated += size;
1777
1778         return (mem);
1779 }
1780
1781 static int
1782 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
1783 {
1784         struct agp_i810_softc *sc;
1785         vm_page_t m;
1786
1787         if (mem->am_is_bound)
1788                 return (EBUSY);
1789
1790         sc = device_get_softc(dev);
1791
1792         if (mem->am_type == 2) {
1793                 if (mem->am_size == AGP_PAGE_SIZE) {
1794                         /*
1795                          * Unwire the page which we wired in alloc_memory.
1796                          */
1797                         VM_OBJECT_WLOCK(mem->am_obj);
1798                         m = vm_page_lookup(mem->am_obj, 0);
1799                         vm_page_lock(m);
1800                         vm_page_unwire(m, PQ_INACTIVE);
1801                         vm_page_unlock(m);
1802                         VM_OBJECT_WUNLOCK(mem->am_obj);
1803                 } else {
1804                         contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1805                         sc->argb_cursor = NULL;
1806                 }
1807         }
1808
1809         sc->agp.as_allocated -= mem->am_size;
1810         TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1811         if (mem->am_obj)
1812                 vm_object_deallocate(mem->am_obj);
1813         free(mem, M_AGP);
1814         return (0);
1815 }
1816
1817 static int
1818 agp_i810_bind_memory(device_t dev, struct agp_memory *mem, vm_offset_t offset)
1819 {
1820         struct agp_i810_softc *sc;
1821         vm_offset_t i;
1822
1823         /* Do some sanity checks first. */
1824         if ((offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1825             offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1826                 device_printf(dev, "binding memory at bad offset %#x\n",
1827                     (int)offset);
1828                 return (EINVAL);
1829         }
1830
1831         sc = device_get_softc(dev);
1832         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1833                 mtx_lock(&sc->agp.as_lock);
1834                 if (mem->am_is_bound) {
1835                         mtx_unlock(&sc->agp.as_lock);
1836                         return (EINVAL);
1837                 }
1838                 /* The memory's already wired down, just stick it in the GTT. */
1839                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1840                         sc->match->driver->install_gtt_pte(dev, (offset + i) >>
1841                             AGP_PAGE_SHIFT, mem->am_physical + i, 0);
1842                 }
1843                 mem->am_offset = offset;
1844                 mem->am_is_bound = 1;
1845                 mtx_unlock(&sc->agp.as_lock);
1846                 return (0);
1847         }
1848
1849         if (mem->am_type != 1)
1850                 return (agp_generic_bind_memory(dev, mem, offset));
1851
1852         /*
1853          * Mapping local DRAM into GATT.
1854          */
1855         if (sc->match->driver->chiptype != CHIP_I810)
1856                 return (EINVAL);
1857         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
1858                 bus_write_4(sc->sc_res[0],
1859                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1860
1861         return (0);
1862 }
1863
1864 static int
1865 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1866 {
1867         struct agp_i810_softc *sc;
1868         vm_offset_t i;
1869
1870         sc = device_get_softc(dev);
1871
1872         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1873                 mtx_lock(&sc->agp.as_lock);
1874                 if (!mem->am_is_bound) {
1875                         mtx_unlock(&sc->agp.as_lock);
1876                         return (EINVAL);
1877                 }
1878
1879                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1880                         sc->match->driver->install_gtt_pte(dev,
1881                             (mem->am_offset + i) >> AGP_PAGE_SHIFT, 0, 0);
1882                 }
1883                 mem->am_is_bound = 0;
1884                 mtx_unlock(&sc->agp.as_lock);
1885                 return (0);
1886         }
1887
1888         if (mem->am_type != 1)
1889                 return (agp_generic_unbind_memory(dev, mem));
1890
1891         if (sc->match->driver->chiptype != CHIP_I810)
1892                 return (EINVAL);
1893         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1894                 sc->match->driver->install_gtt_pte(dev, i >> AGP_PAGE_SHIFT,
1895                     0, 0);
1896         }
1897         return (0);
1898 }
1899
1900 static device_method_t agp_i810_methods[] = {
1901         /* Device interface */
1902         DEVMETHOD(device_identify,      agp_i810_identify),
1903         DEVMETHOD(device_probe,         agp_i810_probe),
1904         DEVMETHOD(device_attach,        agp_i810_attach),
1905         DEVMETHOD(device_detach,        agp_i810_detach),
1906         DEVMETHOD(device_suspend,       bus_generic_suspend),
1907         DEVMETHOD(device_resume,        agp_i810_resume),
1908
1909         /* AGP interface */
1910         DEVMETHOD(agp_get_aperture,     agp_generic_get_aperture),
1911         DEVMETHOD(agp_set_aperture,     agp_i810_method_set_aperture),
1912         DEVMETHOD(agp_bind_page,        agp_i810_bind_page),
1913         DEVMETHOD(agp_unbind_page,      agp_i810_unbind_page),
1914         DEVMETHOD(agp_flush_tlb,        agp_i810_flush_tlb),
1915         DEVMETHOD(agp_enable,           agp_i810_enable),
1916         DEVMETHOD(agp_alloc_memory,     agp_i810_alloc_memory),
1917         DEVMETHOD(agp_free_memory,      agp_i810_free_memory),
1918         DEVMETHOD(agp_bind_memory,      agp_i810_bind_memory),
1919         DEVMETHOD(agp_unbind_memory,    agp_i810_unbind_memory),
1920         DEVMETHOD(agp_chipset_flush,    agp_intel_gtt_chipset_flush),
1921
1922         { 0, 0 }
1923 };
1924
1925 static driver_t agp_i810_driver = {
1926         "agp",
1927         agp_i810_methods,
1928         sizeof(struct agp_i810_softc),
1929 };
1930
1931 static devclass_t agp_devclass;
1932
1933 DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1934 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1935 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
1936
1937 void
1938 agp_intel_gtt_clear_range(device_t dev, u_int first_entry, u_int num_entries)
1939 {
1940         struct agp_i810_softc *sc;
1941         u_int i;
1942
1943         sc = device_get_softc(dev);
1944         for (i = 0; i < num_entries; i++)
1945                 sc->match->driver->install_gtt_pte(dev, first_entry + i,
1946                     VM_PAGE_TO_PHYS(bogus_page), 0);
1947         sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1);
1948 }
1949
1950 void
1951 agp_intel_gtt_insert_pages(device_t dev, u_int first_entry, u_int num_entries,
1952     vm_page_t *pages, u_int flags)
1953 {
1954         struct agp_i810_softc *sc;
1955         u_int i;
1956
1957         sc = device_get_softc(dev);
1958         for (i = 0; i < num_entries; i++) {
1959                 MPASS(pages[i]->valid == VM_PAGE_BITS_ALL);
1960                 MPASS(pages[i]->wire_count > 0);
1961                 sc->match->driver->install_gtt_pte(dev, first_entry + i,
1962                     VM_PAGE_TO_PHYS(pages[i]), flags);
1963         }
1964         sc->match->driver->read_gtt_pte(dev, first_entry + num_entries - 1);
1965 }
1966
1967 struct intel_gtt
1968 agp_intel_gtt_get(device_t dev)
1969 {
1970         struct agp_i810_softc *sc;
1971         struct intel_gtt res;
1972
1973         sc = device_get_softc(dev);
1974         res.stolen_size = sc->stolen_size;
1975         res.gtt_total_entries = sc->gtt_total_entries;
1976         res.gtt_mappable_entries = sc->gtt_mappable_entries;
1977         res.do_idle_maps = 0;
1978         res.scratch_page_dma = VM_PAGE_TO_PHYS(bogus_page);
1979         if (sc->agp.as_aperture != NULL)
1980                 res.gma_bus_addr = rman_get_start(sc->agp.as_aperture);
1981         else
1982                 res.gma_bus_addr = 0;
1983         return (res);
1984 }
1985
1986 static int
1987 agp_i810_chipset_flush_setup(device_t dev)
1988 {
1989
1990         return (0);
1991 }
1992
1993 static void
1994 agp_i810_chipset_flush_teardown(device_t dev)
1995 {
1996
1997         /* Nothing to do. */
1998 }
1999
2000 static void
2001 agp_i810_chipset_flush(device_t dev)
2002 {
2003
2004         /* Nothing to do. */
2005 }
2006
2007 static void
2008 agp_i830_chipset_flush(device_t dev)
2009 {
2010         struct agp_i810_softc *sc;
2011         uint32_t hic;
2012         int i;
2013
2014         sc = device_get_softc(dev);
2015         pmap_invalidate_cache();
2016         hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
2017         bus_write_4(sc->sc_res[0], AGP_I830_HIC, hic | (1U << 31));
2018         for (i = 0; i < 20000 /* 1 sec */; i++) {
2019                 hic = bus_read_4(sc->sc_res[0], AGP_I830_HIC);
2020                 if ((hic & (1U << 31)) == 0)
2021                         break;
2022                 DELAY(50);
2023         }
2024 }
2025
2026 static int
2027 agp_i915_chipset_flush_alloc_page(device_t dev, uint64_t start, uint64_t end)
2028 {
2029         struct agp_i810_softc *sc;
2030         device_t vga;
2031
2032         sc = device_get_softc(dev);
2033         vga = device_get_parent(dev);
2034         sc->sc_flush_page_rid = 100;
2035         sc->sc_flush_page_res = BUS_ALLOC_RESOURCE(device_get_parent(vga), dev,
2036             SYS_RES_MEMORY, &sc->sc_flush_page_rid, start, end, PAGE_SIZE,
2037             RF_ACTIVE);
2038         if (sc->sc_flush_page_res == NULL) {
2039                 device_printf(dev, "Failed to allocate flush page at 0x%jx\n",
2040                     (uintmax_t)start);
2041                 return (EINVAL);
2042         }
2043         sc->sc_flush_page_vaddr = rman_get_virtual(sc->sc_flush_page_res);
2044         if (bootverbose) {
2045                 device_printf(dev, "Allocated flush page phys 0x%jx virt %p\n",
2046                     (uintmax_t)rman_get_start(sc->sc_flush_page_res),
2047                     sc->sc_flush_page_vaddr);
2048         }
2049         return (0);
2050 }
2051
2052 static void
2053 agp_i915_chipset_flush_free_page(device_t dev)
2054 {
2055         struct agp_i810_softc *sc;
2056         device_t vga;
2057
2058         sc = device_get_softc(dev);
2059         vga = device_get_parent(dev);
2060         if (sc->sc_flush_page_res == NULL)
2061                 return;
2062         BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY,
2063             sc->sc_flush_page_rid, sc->sc_flush_page_res);
2064         BUS_RELEASE_RESOURCE(device_get_parent(vga), dev, SYS_RES_MEMORY,
2065             sc->sc_flush_page_rid, sc->sc_flush_page_res);
2066 }
2067
2068 static int
2069 agp_i915_chipset_flush_setup(device_t dev)
2070 {
2071         struct agp_i810_softc *sc;
2072         uint32_t temp;
2073         int error;
2074
2075         sc = device_get_softc(dev);
2076         temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
2077         if ((temp & 1) != 0) {
2078                 temp &= ~1;
2079                 if (bootverbose)
2080                         device_printf(dev,
2081                             "Found already configured flush page at 0x%jx\n",
2082                             (uintmax_t)temp);
2083                 sc->sc_bios_allocated_flush_page = 1;
2084                 /*
2085                  * In the case BIOS initialized the flush pointer (?)
2086                  * register, expect that BIOS also set up the resource
2087                  * for the page.
2088                  */
2089                 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2090                     temp + PAGE_SIZE - 1);
2091                 if (error != 0)
2092                         return (error);
2093         } else {
2094                 sc->sc_bios_allocated_flush_page = 0;
2095                 error = agp_i915_chipset_flush_alloc_page(dev, 0, 0xffffffff);
2096                 if (error != 0)
2097                         return (error);
2098                 temp = rman_get_start(sc->sc_flush_page_res);
2099                 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp | 1, 4);
2100         }
2101         return (0);
2102 }
2103
2104 static void
2105 agp_i915_chipset_flush_teardown(device_t dev)
2106 {
2107         struct agp_i810_softc *sc;
2108         uint32_t temp;
2109
2110         sc = device_get_softc(dev);
2111         if (sc->sc_flush_page_res == NULL)
2112                 return;
2113         if (!sc->sc_bios_allocated_flush_page) {
2114                 temp = pci_read_config(sc->bdev, AGP_I915_IFPADDR, 4);
2115                 temp &= ~1;
2116                 pci_write_config(sc->bdev, AGP_I915_IFPADDR, temp, 4);
2117         }
2118         agp_i915_chipset_flush_free_page(dev);
2119 }
2120
2121 static int
2122 agp_i965_chipset_flush_setup(device_t dev)
2123 {
2124         struct agp_i810_softc *sc;
2125         uint64_t temp;
2126         uint32_t temp_hi, temp_lo;
2127         int error;
2128
2129         sc = device_get_softc(dev);
2130
2131         temp_hi = pci_read_config(sc->bdev, AGP_I965_IFPADDR + 4, 4);
2132         temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2133
2134         if ((temp_lo & 1) != 0) {
2135                 temp = ((uint64_t)temp_hi << 32) | (temp_lo & ~1);
2136                 if (bootverbose)
2137                         device_printf(dev,
2138                             "Found already configured flush page at 0x%jx\n",
2139                             (uintmax_t)temp);
2140                 sc->sc_bios_allocated_flush_page = 1;
2141                 /*
2142                  * In the case BIOS initialized the flush pointer (?)
2143                  * register, expect that BIOS also set up the resource
2144                  * for the page.
2145                  */
2146                 error = agp_i915_chipset_flush_alloc_page(dev, temp,
2147                     temp + PAGE_SIZE - 1);
2148                 if (error != 0)
2149                         return (error);
2150         } else {
2151                 sc->sc_bios_allocated_flush_page = 0;
2152                 error = agp_i915_chipset_flush_alloc_page(dev, 0, ~0);
2153                 if (error != 0)
2154                         return (error);
2155                 temp = rman_get_start(sc->sc_flush_page_res);
2156                 pci_write_config(sc->bdev, AGP_I965_IFPADDR + 4,
2157                     (temp >> 32) & UINT32_MAX, 4);
2158                 pci_write_config(sc->bdev, AGP_I965_IFPADDR,
2159                     (temp & UINT32_MAX) | 1, 4);
2160         }
2161         return (0);
2162 }
2163
2164 static void
2165 agp_i965_chipset_flush_teardown(device_t dev)
2166 {
2167         struct agp_i810_softc *sc;
2168         uint32_t temp_lo;
2169
2170         sc = device_get_softc(dev);
2171         if (sc->sc_flush_page_res == NULL)
2172                 return;
2173         if (!sc->sc_bios_allocated_flush_page) {
2174                 temp_lo = pci_read_config(sc->bdev, AGP_I965_IFPADDR, 4);
2175                 temp_lo &= ~1;
2176                 pci_write_config(sc->bdev, AGP_I965_IFPADDR, temp_lo, 4);
2177         }
2178         agp_i915_chipset_flush_free_page(dev);
2179 }
2180
2181 static void
2182 agp_i915_chipset_flush(device_t dev)
2183 {
2184         struct agp_i810_softc *sc;
2185
2186         sc = device_get_softc(dev);
2187         *(uint32_t *)sc->sc_flush_page_vaddr = 1;
2188 }
2189
2190 int
2191 agp_intel_gtt_chipset_flush(device_t dev)
2192 {
2193         struct agp_i810_softc *sc;
2194
2195         sc = device_get_softc(dev);
2196         sc->match->driver->chipset_flush(dev);
2197         return (0);
2198 }
2199
2200 void
2201 agp_intel_gtt_unmap_memory(device_t dev, struct sglist *sg_list)
2202 {
2203 }
2204
2205 int
2206 agp_intel_gtt_map_memory(device_t dev, vm_page_t *pages, u_int num_entries,
2207     struct sglist **sg_list)
2208 {
2209         struct agp_i810_softc *sc;
2210         struct sglist *sg;
2211         int i;
2212 #if 0
2213         int error;
2214         bus_dma_tag_t dmat;
2215 #endif
2216
2217         if (*sg_list != NULL)
2218                 return (0);
2219         sc = device_get_softc(dev);
2220         sg = sglist_alloc(num_entries, M_WAITOK /* XXXKIB */);
2221         for (i = 0; i < num_entries; i++) {
2222                 sg->sg_segs[i].ss_paddr = VM_PAGE_TO_PHYS(pages[i]);
2223                 sg->sg_segs[i].ss_len = PAGE_SIZE;
2224         }
2225
2226 #if 0
2227         error = bus_dma_tag_create(bus_get_dma_tag(dev),
2228             1 /* alignment */, 0 /* boundary */,
2229             1ULL << sc->match->busdma_addr_mask_sz /* lowaddr */,
2230             BUS_SPACE_MAXADDR /* highaddr */,
2231             NULL /* filtfunc */, NULL /* filtfuncarg */,
2232             BUS_SPACE_MAXADDR /* maxsize */,
2233             BUS_SPACE_UNRESTRICTED /* nsegments */,
2234             BUS_SPACE_MAXADDR /* maxsegsz */,
2235             0 /* flags */, NULL /* lockfunc */, NULL /* lockfuncarg */,
2236             &dmat);
2237         if (error != 0) {
2238                 sglist_free(sg);
2239                 return (error);
2240         }
2241         /* XXXKIB */
2242 #endif
2243         *sg_list = sg;
2244         return (0);
2245 }
2246
2247 static void
2248 agp_intel_gtt_install_pte(device_t dev, u_int index, vm_paddr_t addr,
2249     u_int flags)
2250 {
2251         struct agp_i810_softc *sc;
2252
2253         sc = device_get_softc(dev);
2254         sc->match->driver->install_gtt_pte(dev, index, addr, flags);
2255 }
2256
2257 void
2258 agp_intel_gtt_insert_sg_entries(device_t dev, struct sglist *sg_list,
2259     u_int first_entry, u_int flags)
2260 {
2261         struct agp_i810_softc *sc;
2262         vm_paddr_t spaddr;
2263         size_t slen;
2264         u_int i, j;
2265
2266         sc = device_get_softc(dev);
2267         for (i = j = 0; j < sg_list->sg_nseg; j++) {
2268                 spaddr = sg_list->sg_segs[i].ss_paddr;
2269                 slen = sg_list->sg_segs[i].ss_len;
2270                 for (; slen > 0; i++) {
2271                         sc->match->driver->install_gtt_pte(dev, first_entry + i,
2272                             spaddr, flags);
2273                         spaddr += AGP_PAGE_SIZE;
2274                         slen -= AGP_PAGE_SIZE;
2275                 }
2276         }
2277         sc->match->driver->read_gtt_pte(dev, first_entry + i - 1);
2278 }
2279
2280 void
2281 intel_gtt_clear_range(u_int first_entry, u_int num_entries)
2282 {
2283
2284         agp_intel_gtt_clear_range(intel_agp, first_entry, num_entries);
2285 }
2286
2287 void
2288 intel_gtt_insert_pages(u_int first_entry, u_int num_entries, vm_page_t *pages,
2289     u_int flags)
2290 {
2291
2292         agp_intel_gtt_insert_pages(intel_agp, first_entry, num_entries,
2293             pages, flags);
2294 }
2295
2296 struct intel_gtt *
2297 intel_gtt_get(void)
2298 {
2299
2300         intel_private.base = agp_intel_gtt_get(intel_agp);
2301         return (&intel_private.base);
2302 }
2303
2304 int
2305 intel_gtt_chipset_flush(void)
2306 {
2307
2308         return (agp_intel_gtt_chipset_flush(intel_agp));
2309 }
2310
2311 void
2312 intel_gtt_unmap_memory(struct sglist *sg_list)
2313 {
2314
2315         agp_intel_gtt_unmap_memory(intel_agp, sg_list);
2316 }
2317
2318 int
2319 intel_gtt_map_memory(vm_page_t *pages, u_int num_entries,
2320     struct sglist **sg_list)
2321 {
2322
2323         return (agp_intel_gtt_map_memory(intel_agp, pages, num_entries,
2324             sg_list));
2325 }
2326
2327 void
2328 intel_gtt_insert_sg_entries(struct sglist *sg_list, u_int first_entry,
2329     u_int flags)
2330 {
2331
2332         agp_intel_gtt_insert_sg_entries(intel_agp, sg_list, first_entry, flags);
2333 }
2334
2335 void
2336 intel_gtt_install_pte(u_int index, vm_paddr_t addr, u_int flags)
2337 {
2338
2339         agp_intel_gtt_install_pte(intel_agp, index, addr, flags);
2340 }
2341
2342 device_t
2343 intel_gtt_get_bridge_device(void)
2344 {
2345         struct agp_i810_softc *sc;
2346
2347         sc = device_get_softc(intel_agp);
2348         return (sc->bdev);
2349 }
2350
2351 vm_paddr_t
2352 intel_gtt_read_pte_paddr(u_int entry)
2353 {
2354         struct agp_i810_softc *sc;
2355
2356         sc = device_get_softc(intel_agp);
2357         return (sc->match->driver->read_gtt_pte_paddr(intel_agp, entry));
2358 }
2359
2360 u_int32_t
2361 intel_gtt_read_pte(u_int entry)
2362 {
2363         struct agp_i810_softc *sc;
2364
2365         sc = device_get_softc(intel_agp);
2366         return (sc->match->driver->read_gtt_pte(intel_agp, entry));
2367 }
2368
2369 void
2370 intel_gtt_write(u_int entry, uint32_t val)
2371 {
2372         struct agp_i810_softc *sc;
2373
2374         sc = device_get_softc(intel_agp);
2375         return (sc->match->driver->write_gtt(intel_agp, entry, val));
2376 }