2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2000 Doug Rabson
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
39 #include <sys/mutex.h>
42 #include <dev/agp/agppriv.h>
43 #include <dev/agp/agpreg.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
48 #include <vm/vm_object.h>
51 #define MAX_APSIZE 0x3f /* 256 MB */
53 struct agp_intel_softc {
55 u_int32_t initial_aperture; /* aperture size at startup */
56 struct agp_gatt *gatt;
58 u_int32_t current_aperture; /* current aperture size */
62 agp_intel_match(device_t dev)
64 if (pci_get_class(dev) != PCIC_BRIDGE
65 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
68 if (agp_find_caps(dev) == 0)
71 switch (pci_get_devid(dev)) {
72 /* Intel -- vendor 0x8086 */
74 return ("Intel 82443LX (440 LX) host to PCI bridge");
76 return ("Intel 82443BX (440 BX) host to PCI bridge");
78 return ("Intel 82443GX host to PCI bridge");
80 return ("Intel 82443GX host to AGP bridge");
82 return ("Intel 82815 (i815 GMCH) host to PCI bridge");
85 return ("Intel 82820 host to AGP bridge");
87 return ("Intel 82830 host to AGP bridge");
89 return ("Intel 82840 host to AGP bridge");
91 return ("Intel 82845 host to AGP bridge");
93 return ("Intel 82850 host to AGP bridge");
95 return ("Intel 82855 host to AGP bridge");
97 return ("Intel 82860 host to AGP bridge");
99 return ("Intel 82865 host to AGP bridge");
101 return ("Intel E7205 host to AGP bridge");
103 return ("Intel E7505 host to AGP bridge");
105 return ("Intel 82875P host to AGP bridge");
107 return ("Intel 82845G host to AGP bridge");
109 return ("Intel 82855GM host to AGP bridge");
116 agp_intel_probe(device_t dev)
120 if (resource_disabled("agp", device_get_unit(dev)))
122 desc = agp_intel_match(dev);
124 device_set_desc(dev, desc);
125 return (BUS_PROBE_DEFAULT);
132 agp_intel_commit_gatt(device_t dev)
134 struct agp_intel_softc *sc;
138 sc = device_get_softc(dev);
139 type = pci_get_devid(dev);
141 /* Install the gatt. */
142 pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4);
144 /* Enable the GLTB and setup the control register. */
146 case 0x71908086: /* 440LX/EX */
147 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4);
149 case 0x71808086: /* 440BX */
151 * XXX: Should be 0xa080? Bit 9 is undefined, and
152 * bit 13 being on and bit 15 being clear is illegal.
154 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4);
157 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
158 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4);
161 /* Enable aperture accesses. */
163 case 0x25008086: /* i820 */
164 case 0x25018086: /* i820 */
165 pci_write_config(dev, AGP_INTEL_I820_RDCR,
166 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1)
169 case 0x1a308086: /* i845 */
170 case 0x25608086: /* i845G */
171 case 0x33408086: /* i855 */
172 case 0x35808086: /* i855GM */
173 case 0x25708086: /* i865 */
174 case 0x25788086: /* i875P */
175 pci_write_config(dev, AGP_INTEL_I845_AGPM,
176 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1)
179 case 0x1a218086: /* i840 */
180 case 0x25308086: /* i850 */
181 case 0x25318086: /* i860 */
182 case 0x255d8086: /* E7205 */
183 case 0x25508086: /* E7505 */
184 pci_write_config(dev, AGP_INTEL_MCHCFG,
185 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2)
188 default: /* Intel Generic (maybe) */
189 pci_write_config(dev, AGP_INTEL_NBXCFG,
190 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4)
191 & ~(1 << 10)) | (1 << 9), 4);
196 case 0x1a218086: /* i840 */
197 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2);
199 case 0x25008086: /* i820 */
200 case 0x25018086: /* i820 */
201 case 0x1a308086: /* i845 */
202 case 0x25608086: /* i845G */
203 case 0x25308086: /* i850 */
204 case 0x33408086: /* i855 */
205 case 0x25318086: /* i860 */
206 case 0x25708086: /* i865 */
207 case 0x25788086: /* i875P */
208 case 0x255d8086: /* E7205 */
209 case 0x25508086: /* E7505 */
210 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2);
212 default: /* Intel Generic (maybe) */
213 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1);
218 agp_intel_attach(device_t dev)
220 struct agp_intel_softc *sc;
221 struct agp_gatt *gatt;
225 sc = device_get_softc(dev);
227 error = agp_generic_attach(dev);
231 /* Determine maximum supported aperture size. */
232 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1);
233 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1);
234 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) &
236 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1);
237 sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev);
240 gatt = agp_alloc_gatt(dev);
245 * Probably contigmalloc failure. Try reducing the
246 * aperture so that the gatt size reduces.
248 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
249 agp_generic_detach(dev);
255 agp_intel_commit_gatt(dev);
261 agp_intel_detach(device_t dev)
263 struct agp_intel_softc *sc;
266 sc = device_get_softc(dev);
270 /* Disable aperture accesses. */
271 switch (pci_get_devid(dev)) {
272 case 0x25008086: /* i820 */
273 case 0x25018086: /* i820 */
274 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1);
275 printf("%s: set RDCR to %02x\n", __func__, reg & 0xff);
276 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1);
278 case 0x1a308086: /* i845 */
279 case 0x25608086: /* i845G */
280 case 0x33408086: /* i855 */
281 case 0x35808086: /* i855GM */
282 case 0x25708086: /* i865 */
283 case 0x25788086: /* i875P */
284 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1);
285 printf("%s: set AGPM to %02x\n", __func__, reg & 0xff);
286 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1);
288 case 0x1a218086: /* i840 */
289 case 0x25308086: /* i850 */
290 case 0x25318086: /* i860 */
291 case 0x255d8086: /* E7205 */
292 case 0x25508086: /* E7505 */
293 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9);
294 printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff);
295 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2);
297 default: /* Intel Generic (maybe) */
298 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9);
299 printf("%s: set NBXCFG to %08x\n", __func__, reg);
300 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4);
302 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4);
303 AGP_SET_APERTURE(dev, sc->initial_aperture);
304 agp_free_gatt(sc->gatt);
311 agp_intel_resume(device_t dev)
313 struct agp_intel_softc *sc;
314 sc = device_get_softc(dev);
316 AGP_SET_APERTURE(dev, sc->current_aperture);
317 agp_intel_commit_gatt(dev);
318 return (bus_generic_resume(dev));
322 agp_intel_get_aperture(device_t dev)
324 struct agp_intel_softc *sc;
327 sc = device_get_softc(dev);
329 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask;
332 * The size is determined by the number of low bits of
333 * register APBASE which are forced to zero. The low 22 bits
334 * are always forced to zero and each zero bit in the apsize
335 * field just read forces the corresponding bit in the 27:22
336 * to be zero. We calculate the aperture size accordingly.
338 return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1);
342 agp_intel_set_aperture(device_t dev, u_int32_t aperture)
344 struct agp_intel_softc *sc;
347 sc = device_get_softc(dev);
350 * Reverse the magic from get_aperture.
352 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask;
355 * Double check for sanity.
357 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture)
360 sc->current_aperture = apsize;
362 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1);
368 agp_intel_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
370 struct agp_intel_softc *sc;
372 sc = device_get_softc(dev);
374 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
377 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17;
382 agp_intel_unbind_page(device_t dev, vm_offset_t offset)
384 struct agp_intel_softc *sc;
386 sc = device_get_softc(dev);
388 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
391 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
396 agp_intel_flush_tlb(device_t dev)
400 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4);
401 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4);
402 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4);
405 static device_method_t agp_intel_methods[] = {
406 /* Device interface */
407 DEVMETHOD(device_probe, agp_intel_probe),
408 DEVMETHOD(device_attach, agp_intel_attach),
409 DEVMETHOD(device_detach, agp_intel_detach),
410 DEVMETHOD(device_shutdown, bus_generic_shutdown),
411 DEVMETHOD(device_suspend, bus_generic_suspend),
412 DEVMETHOD(device_resume, agp_intel_resume),
415 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture),
416 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture),
417 DEVMETHOD(agp_bind_page, agp_intel_bind_page),
418 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page),
419 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb),
420 DEVMETHOD(agp_enable, agp_generic_enable),
421 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
422 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
423 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
424 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
429 static driver_t agp_intel_driver = {
432 sizeof(struct agp_intel_softc),
435 static devclass_t agp_devclass;
437 DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0);
438 MODULE_DEPEND(agp_intel, agp, 1, 1, 1);
439 MODULE_DEPEND(agp_intel, pci, 1, 1, 1);