2 * Generic register and struct definitions for the Adaptech 1540, 1542,
3 * 1640, 1642 SCSI host adapters. Product specific probe and attach
4 * routines can be found in:
7 * Derived from bt.c written by:
9 * Copyright (c) 1998 Justin T. Gibbs.
10 * All rights reserved.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions, and the following disclaimer,
17 * without modification, immediately at the beginning of the file.
18 * 2. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 #include <sys/queue.h>
40 #include <cam/scsi/scsi_all.h>
42 #define AHA_MAXTRANSFER_SIZE 0xffffff /* limited by 24bit counter */
43 #define AHA_NSEG 17 /* The number of dma segments
45 #define ALL_TARGETS (~0)
48 * Control Register pp. 1-8, 1-9 (Write Only)
50 #define CONTROL_REG 0x00
51 #define HARD_RESET 0x80 /* Hard Reset - return to POST state */
52 #define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */
53 #define RESET_INTR 0x20 /* Reset/Ack Interrupt */
54 #define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */
57 * Status Register pp. 1-9, 1-10 (Read Only)
59 #define STATUS_REG 0x00
60 #define DIAG_ACTIVE 0x80 /* Performing Internal Diags */
61 #define DIAG_FAIL 0x40 /* Internal Diags failed */
62 #define INIT_REQUIRED 0x20 /* MBOXes need initialization */
63 #define HA_READY 0x10 /* HA ready for new commands */
64 #define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */
65 #define DATAIN_REG_READY 0x04 /* Data-in Byte available */
66 #define STATUS_REG_RSVD 0x02
67 #define CMD_INVALID 0x01 /* Invalid Command detected */
70 * Command/Parameter Register pp. 1-10, 1-11 (Write Only)
72 #define COMMAND_REG 0x01
75 * Data in Register p. 1-11 (Read Only)
77 #define DATAIN_REG 0x01
80 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
82 #define INTSTAT_REG 0x02
83 #define INTR_PENDING 0x80 /* There is a pending INTR */
84 #define INTSTAT_REG_RSVD 0x70
85 #define SCSI_BUS_RESET 0x08 /* Bus Reset detected */
86 #define CMD_COMPLETE 0x04
87 #define OMB_READY 0x02 /* Outgoin Mailbox Ready */
88 #define IMB_LOADED 0x01 /* Incoming Mailbox loaded */
91 * Definitions for the "undocumented" geometry register, we just need
94 #define GEOMETRY_REG 0x03
99 * Opcodes for Adapter commands.
103 AOP_INITIALIZE_MBOX = 0x01,
104 AOP_START_MBOX = 0x02,
105 AOP_EXECUTE_BIOS_CMD = 0x03,
106 AOP_INQUIRE_BOARD_ID = 0x04,
107 AOP_ENABLE_OMBR_INT = 0x05,
108 AOP_SET_SEL_TIMOUT = 0x06,
109 AOP_SET_TIME_ON_BUS = 0x07,
110 AOP_SET_TIME_OFF_BUS = 0x08,
111 AOP_SET_BUS_TRANS_RATE = 0x09,
112 AOP_INQUIRE_INST_LDEVS = 0x0A,
113 AOP_INQUIRE_CONFIG = 0x0B,
114 AOP_ENABLE_TARGET_MODE = 0x0C,
115 AOP_INQUIRE_SETUP_INFO = 0x0D,
116 AOP_WRITE_LRAM = 0x1A,
117 AOP_READ_LRAM = 0x1B,
118 AOP_WRITE_CHIP_FIFO = 0x1C,
119 AOP_READ_CHIP_FIFO = 0x1D,
120 AOP_ECHO_DATA_BYTE = 0x1F,
121 AOP_ADAPTER_DIAGNOSTICS = 0x20,
122 AOP_SET_ADAPTER_OPTIONS = 0x21,
123 AOP_SET_EEPROM = 0x22,
124 AOP_RETURN_EEPROM = 0x23,
125 AOP_ENABLE_SHADOW_RAM = 0x24,
126 AOP_INIT_BIOS_MBOX = 0x25,
127 AOP_SET_BIOS_BANK_1 = 0x26,
128 AOP_SET_BIOS_BANK_2 = 0x27,
129 AOP_RETURN_EXT_BIOS_INFO= 0x28,
130 AOP_MBOX_IF_ENABLE = 0x29,
131 AOP_SCSI_TERM_STATUS = 0x2C,
132 AOP_INQUIRE_SCAM_DEV = 0x2D,
133 AOP_SCSI_DEV_TABLE = 0x2E,
135 AOP_START_BIOS_CMD = 0x82,
136 AOP_INQUIRE_ESETUP_INFO = 0x8D
139 /************** Definitions of Multi-byte commands and responses ************/
143 uint8_t flags; /* Bit 3 == 1 extended bios enabled */
144 uint8_t mailboxlock; /* mail box lock code to unlock it */
149 uint8_t base_addr[3];
150 } init_24b_mbox_params_t;
154 /* These values are mostly from the aha-1540CP technical reference, but */
155 /* with other values from the old aha1542.c driver. The values from the */
156 /* aha-1540CP technical manual are used where conflicts arise */
157 #define BOARD_1540_16HEAD_BIOS 0x00
158 #define BOARD_1540_64HEAD_BIOS 0x30
159 #define BOARD_1542 0x41 /* aha-1540/1542 w/64-h bios */
160 #define BOARD_1640 0x42 /* aha-1640 */
161 #define BOARD_1740 0x43 /* aha-1740A/1742A/1744 */
162 #define BOARD_1542C 0x44 /* aha-1542C */
163 #define BOARD_1542CF 0x45 /* aha-1542CF */
164 #define BOARD_1542CP 0x46 /* aha-1542CP, plug and play */
165 uint8_t cust_features;
166 #define FEATURES_STANDARD 0x30
167 uint8_t firmware_rev_major;
168 uint8_t firmware_rev_minor;
173 #define DMA_CHAN_5 0x20
174 #define DMA_CHAN_6 0x40
175 #define DMA_CHAN_7 0x80
188 } target_mode_params_t;
197 uint8_t initiate_sync : 1,
201 uint8_t bus_transfer_rate;
203 uint8_t time_off_bus;
205 uint8_t mbox_base_addr[3];
206 targ_syncinfo_t syncinfo[8];
208 uint8_t customer_sig[20];
210 uint8_t board_switches;
211 uint8_t firmware_cksum[2];
212 uint8_t bios_mbox_addr[3];
215 struct aha_isa_port {
217 uint8_t bio; /* board IO offset */
220 #define AHA_NUM_ISAPORTS 6
234 uint8_t sync_rate[16]; /* Sync in 10ns units */
235 } target_sync_info_data_t;
242 /********************** Mail Box definitions *******************************/
245 AMBO_FREE = 0x0, /* MBO intry is free */
246 AMBO_START = 0x1, /* MBO activate entry */
247 AMBO_ABORT = 0x2 /* MBO abort entry */
248 } aha_mbo_action_code_t;
250 typedef struct aha_mbox_out {
256 AMBI_FREE = 0x0, /* MBI entry is free */
257 AMBI_OK = 0x1, /* completed without error */
258 AMBI_ABORT = 0x2, /* aborted ccb */
259 AMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */
260 AMBI_ERROR = 0x4 /* Completed with error */
261 } aha_mbi_comp_code_t;
263 typedef struct aha_mbox_in {
268 /****************** Hardware CCB definition *********************************/
270 INITIATOR_CCB = 0x00,
271 INITIATOR_SG_CCB = 0x02,
272 INITIATOR_CCB_WRESID = 0x03,
273 INITIATOR_SG_CCB_WRESID = 0x04,
274 INITIATOR_BUS_DEV_RESET = 0x81
278 AHASTAT_NOERROR = 0x00,
279 AHASTAT_SELTIMEOUT = 0x11,
280 AHASTAT_DATARUN_ERROR = 0x12,
281 AHASTAT_UNEXPECTED_BUSFREE = 0x13,
282 AHASTAT_INVALID_PHASE = 0x14,
283 AHASTAT_INVALID_ACTION_CODE = 0x15,
284 AHASTAT_INVALID_OPCODE = 0x16,
285 AHASTAT_LINKED_CCB_LUN_MISMATCH = 0x17,
286 AHASTAT_INVALID_CCB_OR_SG_PARAM = 0x1A,
287 AHASTAT_HA_SCSI_BUS_RESET = 0x22, /* stolen from bt */
288 AHASTAT_HA_BDR = 0x25 /* Stolen from bt */
292 uint8_t opcode; /* 0 */
293 uint8_t lun : 3, /* 1 */
297 uint8_t cmd_len; /* 2 */
298 uint8_t sense_len; /* 3 */
299 uint8_t data_len[3]; /* 4 */
300 uint8_t data_addr[3]; /* 7 */
301 uint8_t link_ptr[3]; /* 10 */
302 uint8_t link_id; /* 13 */
303 uint8_t ahastat; /* 14 */
304 uint8_t sdstat; /* 15 */
305 uint8_t reserved1; /* 16 */
306 uint8_t reserved2; /* 17 */
307 uint8_t scsi_cdb[16]; /* 18 */
308 uint8_t sense_data[SSD_FULL_SIZE];
314 ACCB_DEVICE_RESET = 0x2,
315 ACCB_RELEASE_SIMQ = 0x4
319 struct aha_hccb hccb; /* hccb assumed to be at 0 */
320 SLIST_ENTRY(aha_ccb) links;
325 uint32_t sg_list_phys;
329 bus_dmamap_t sg_dmamap;
330 bus_addr_t sg_physaddr;
332 SLIST_ENTRY(sg_map_node) links;
337 bus_space_handle_t bsh;
339 struct cam_path *path;
340 aha_mbox_out_t *cur_outbox;
341 aha_mbox_in_t *cur_inbox;
342 aha_mbox_out_t *last_outbox;
343 aha_mbox_in_t *last_inbox;
344 struct aha_ccb *aha_ccb_array;
345 SLIST_HEAD(,aha_ccb) free_aha_ccbs;
346 LIST_HEAD(,ccb_hdr) pending_ccbs;
348 uint32_t aha_ccb_physbase;
349 aha_ccb_opcode_t ccb_sg_opcode;
350 aha_ccb_opcode_t ccb_ccb_opcode;
351 aha_mbox_in_t *in_boxes;
352 aha_mbox_out_t *out_boxes;
353 struct scsi_sense_data *sense_buffers;
354 uint32_t sense_buffers_physbase;
355 struct aha_ccb *recovery_accb;
357 bus_dma_tag_t parent_dmat; /*
358 * All dmat's derive from
359 * the dmat defined by our
362 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
363 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */
364 bus_dmamap_t mailbox_dmamap;
365 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */
366 bus_dmamap_t ccb_dmamap;
367 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
368 SLIST_HEAD(, sg_map_node) sg_maps;
369 bus_addr_t mailbox_physbase;
370 u_int num_ccbs; /* Number of CCBs malloc'd */
371 u_int max_ccbs; /* Maximum allocatable CCBs */
375 uint32_t extended_trans :1,
382 uint16_t disc_permitted;
383 uint16_t sync_permitted;
385 volatile uint8_t command_cmp;
386 volatile uint8_t latched_status;
392 struct resource *irq;
393 struct resource *port;
394 struct resource *drq;
402 void aha_alloc(struct aha_softc *, int, bus_space_tag_t, bus_space_handle_t);
403 int aha_attach(struct aha_softc *);
404 int aha_cmd(struct aha_softc *, aha_op_t, uint8_t *, u_int, uint8_t *, u_int,
406 int aha_detach(struct aha_softc *);
407 int aha_fetch_adapter_info(struct aha_softc *);
408 void aha_find_probe_range(int, int *, int *);
409 void aha_free(struct aha_softc *);
410 int aha_init(struct aha_softc *);
411 void aha_intr(void *);
412 int aha_iop_from_bio(isa_compat_io_t);
413 int aha_probe(struct aha_softc *);
415 #define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */
417 #define aha_inb(aha, port) \
418 bus_space_read_1((aha)->tag, (aha)->bsh, port)
420 #define aha_outb(aha, port, value) \
421 bus_space_write_1((aha)->tag, (aha)->bsh, port, value)
423 #define ADP0100_PNP 0x00019004 /* ADP0100 */
424 #define AHA1540_PNP 0x40159004 /* ADP1540 */
425 #define AHA1542_PNP 0x42159004 /* ADP1542 */
426 #define AHA1542_PNPCOMPAT 0xA000D040 /* PNP00A0 */
427 #define ICU0091_PNP 0X91005AA4 /* ICU0091 */
429 #endif /* _AHAREG_H_ */