2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
42 #include <sys/sysctl.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
50 #include <cam/cam_ccb.h>
51 #include <cam/cam_sim.h>
52 #include <cam/cam_xpt_sim.h>
53 #include <cam/cam_debug.h>
55 /* local prototypes */
56 static void ahci_intr(void *data);
57 static void ahci_intr_one(void *data);
58 static void ahci_intr_one_edge(void *data);
59 static int ahci_ch_init(device_t dev);
60 static int ahci_ch_deinit(device_t dev);
61 static int ahci_ch_suspend(device_t dev);
62 static int ahci_ch_resume(device_t dev);
63 static void ahci_ch_pm(void *arg);
64 static void ahci_ch_intr(void *arg);
65 static void ahci_ch_intr_direct(void *arg);
66 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
67 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
68 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
69 static void ahci_execute_transaction(struct ahci_slot *slot);
70 static void ahci_timeout(void *arg);
71 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
72 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
73 static void ahci_dmainit(device_t dev);
74 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
75 static void ahci_dmafini(device_t dev);
76 static void ahci_slotsalloc(device_t dev);
77 static void ahci_slotsfree(device_t dev);
78 static void ahci_reset(struct ahci_channel *ch);
79 static void ahci_start(struct ahci_channel *ch, int fbs);
80 static void ahci_stop(struct ahci_channel *ch);
81 static void ahci_clo(struct ahci_channel *ch);
82 static void ahci_start_fr(struct ahci_channel *ch);
83 static void ahci_stop_fr(struct ahci_channel *ch);
84 static int ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr);
85 static uint32_t ahci_ch_detval(struct ahci_channel *ch, uint32_t val);
87 static int ahci_sata_connect(struct ahci_channel *ch);
88 static int ahci_sata_phy_reset(struct ahci_channel *ch);
89 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
91 static void ahci_issue_recovery(struct ahci_channel *ch);
92 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
93 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
95 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
96 static void ahcipoll(struct cam_sim *sim);
98 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
100 #define recovery_type spriv_field0
101 #define RECOVERY_NONE 0
102 #define RECOVERY_READ_LOG 1
103 #define RECOVERY_REQUEST_SENSE 2
104 #define recovery_slot spriv_field1
107 ahci_ch_detval(struct ahci_channel *ch, uint32_t val)
110 return ch->disablephy ? ATA_SC_DET_DISABLE : val;
114 ahci_ctlr_setup(device_t dev)
116 struct ahci_controller *ctlr = device_get_softc(dev);
117 /* Clear interrupts */
118 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
121 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
122 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
123 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
124 (4 << AHCI_CCCC_CC_SHIFT) |
126 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
127 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
130 "CCC with %dms/4cmd enabled on vector %d\n",
131 ctlr->ccc, ctlr->cccv);
134 /* Enable AHCI interrupts */
135 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
136 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
141 ahci_ctlr_reset(device_t dev)
143 struct ahci_controller *ctlr = device_get_softc(dev);
147 /* BIOS/OS Handoff */
148 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
149 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
150 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
151 /* Request OS ownership. */
152 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS);
154 /* Wait up to 2s for BIOS ownership release. */
155 for (timeout = 0; timeout < 80; timeout++) {
157 v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
158 if ((v & AHCI_BOHC_BOS) == 0)
160 if ((v & AHCI_BOHC_BB) == 0)
165 /* Enable AHCI mode */
166 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
167 /* Reset AHCI controller */
168 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
169 for (timeout = 1000; timeout > 0; timeout--) {
171 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
175 device_printf(dev, "AHCI controller reset failure\n");
178 /* Reenable AHCI mode */
179 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
181 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
183 * Restore capability field.
184 * This is write to a read-only register to restore its state.
185 * On fully standard-compliant hardware this is not needed and
186 * this operation shall not take place. See ahci_pci.c for
187 * platforms using this quirk.
189 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
196 ahci_attach(device_t dev)
198 struct ahci_controller *ctlr = device_get_softc(dev);
199 int error, i, speed, unit;
205 resource_int_value(device_get_name(dev),
206 device_get_unit(dev), "ccc", &ctlr->ccc);
207 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF);
209 /* Setup our own memory management for channels. */
210 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
211 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
212 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
213 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
214 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
218 if ((error = rman_manage_region(&ctlr->sc_iomem,
219 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
221 rman_fini(&ctlr->sc_iomem);
224 /* Get the HW capabilities */
225 version = ATA_INL(ctlr->r_mem, AHCI_VS);
226 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
227 if (version >= 0x00010200)
228 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
229 if (ctlr->caps & AHCI_CAP_EMS)
230 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
232 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
235 * The spec says that BIOS sets up bits corresponding to
236 * available ports. On platforms where this information
237 * is missing, the driver can define available ports on its own.
239 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
240 int nmask = (1 << nports) - 1;
242 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
243 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n",
247 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
249 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
250 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
251 (ctlr->caps & AHCI_CAP_SPM) == 0)
252 ctlr->quirks |= AHCI_Q_NOBSYRES;
254 if (ctlr->quirks & AHCI_Q_1CH) {
255 ctlr->caps &= ~AHCI_CAP_NPMASK;
256 ctlr->ichannels &= 0x01;
258 if (ctlr->quirks & AHCI_Q_2CH) {
259 ctlr->caps &= ~AHCI_CAP_NPMASK;
261 ctlr->ichannels &= 0x03;
263 if (ctlr->quirks & AHCI_Q_4CH) {
264 ctlr->caps &= ~AHCI_CAP_NPMASK;
266 ctlr->ichannels &= 0x0f;
268 ctlr->channels = MAX(flsl(ctlr->ichannels),
269 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
270 if (ctlr->quirks & AHCI_Q_NOPMP)
271 ctlr->caps &= ~AHCI_CAP_SPM;
272 if (ctlr->quirks & AHCI_Q_NONCQ)
273 ctlr->caps &= ~AHCI_CAP_SNCQ;
274 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
276 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
278 /* Create controller-wide DMA tag. */
279 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
280 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
281 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
282 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
283 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
286 rman_fini(&ctlr->sc_iomem);
290 ahci_ctlr_setup(dev);
292 /* Setup interrupts. */
293 if ((error = ahci_setup_interrupt(dev)) != 0) {
294 bus_dma_tag_destroy(ctlr->dma_tag);
296 rman_fini(&ctlr->sc_iomem);
301 for (u = ctlr->ichannels; u != 0; u >>= 1)
303 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
304 resource_int_value(device_get_name(dev), device_get_unit(dev),
305 "direct", &ctlr->direct);
306 /* Announce HW capabilities. */
307 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
309 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
310 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
311 ((version >> 4) & 0xf0) + (version & 0x0f),
312 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
313 ((speed == 1) ? "1.5":((speed == 2) ? "3":
314 ((speed == 3) ? "6":"?"))),
315 (ctlr->caps & AHCI_CAP_SPM) ?
316 "supported" : "not supported",
317 (ctlr->caps & AHCI_CAP_FBSS) ?
319 if (ctlr->quirks != 0) {
320 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
324 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
325 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
326 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
327 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
328 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
329 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
330 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
331 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
332 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
333 ((speed == 1) ? "1.5":((speed == 2) ? "3":
334 ((speed == 3) ? "6":"?"))));
335 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
336 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
337 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
338 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
339 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
340 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
341 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
342 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
343 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
344 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
345 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
346 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
348 if (bootverbose && version >= 0x00010200) {
349 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
350 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
351 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
352 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
353 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
354 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
355 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
357 /* Attach all channels on this controller */
358 for (unit = 0; unit < ctlr->channels; unit++) {
359 child = device_add_child(dev, "ahcich", -1);
361 device_printf(dev, "failed to add channel device\n");
364 device_set_ivars(child, (void *)(intptr_t)unit);
365 if ((ctlr->ichannels & (1 << unit)) == 0)
366 device_disable(child);
368 /* Attach any remapped NVME device */
369 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
370 child = device_add_child(dev, "nvme", -1);
372 device_printf(dev, "failed to add remapped NVMe device");
375 device_set_ivars(child, (void *)(intptr_t)(unit | AHCI_REMAPPED_UNIT));
378 if (ctlr->caps & AHCI_CAP_EMS) {
379 child = device_add_child(dev, "ahciem", -1);
381 device_printf(dev, "failed to add enclosure device\n");
383 device_set_ivars(child, (void *)(intptr_t)AHCI_EM_UNIT);
385 bus_generic_attach(dev);
390 ahci_detach(device_t dev)
392 struct ahci_controller *ctlr = device_get_softc(dev);
395 /* Detach & delete all children */
396 device_delete_children(dev);
398 /* Free interrupts. */
399 for (i = 0; i < ctlr->numirqs; i++) {
400 if (ctlr->irqs[i].r_irq) {
401 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
402 ctlr->irqs[i].handle);
403 bus_release_resource(dev, SYS_RES_IRQ,
404 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
407 bus_dma_tag_destroy(ctlr->dma_tag);
409 rman_fini(&ctlr->sc_iomem);
411 mtx_destroy(&ctlr->ch_mtx);
416 ahci_free_mem(device_t dev)
418 struct ahci_controller *ctlr = device_get_softc(dev);
420 /* Release memory resources */
422 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
423 if (ctlr->r_msix_table)
424 bus_release_resource(dev, SYS_RES_MEMORY,
425 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
426 if (ctlr->r_msix_pba)
427 bus_release_resource(dev, SYS_RES_MEMORY,
428 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
430 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
434 ahci_setup_interrupt(device_t dev)
436 struct ahci_controller *ctlr = device_get_softc(dev);
439 /* Check for single MSI vector fallback. */
440 if (ctlr->numirqs > 1 &&
441 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
442 device_printf(dev, "Falling back to one MSI\n");
446 /* Ensure we don't overrun irqs. */
447 if (ctlr->numirqs > AHCI_MAX_IRQS) {
448 device_printf(dev, "Too many irqs %d > %d (clamping)\n",
449 ctlr->numirqs, AHCI_MAX_IRQS);
450 ctlr->numirqs = AHCI_MAX_IRQS;
453 /* Allocate all IRQs. */
454 for (i = 0; i < ctlr->numirqs; i++) {
455 ctlr->irqs[i].ctlr = ctlr;
456 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
457 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
458 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
459 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
460 (ctlr->ccc && i == ctlr->cccv))
461 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
462 else if (ctlr->channels > ctlr->numirqs &&
463 i == ctlr->numirqs - 1)
464 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
466 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
467 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
468 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
469 device_printf(dev, "unable to map interrupt\n");
472 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
473 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
474 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
476 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
477 /* SOS XXX release r_irq */
478 device_printf(dev, "unable to setup interrupt\n");
481 if (ctlr->numirqs > 1) {
482 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
483 ctlr->irqs[i].handle,
484 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
492 * Common case interrupt handler.
495 ahci_intr(void *data)
497 struct ahci_controller_irq *irq = data;
498 struct ahci_controller *ctlr = irq->ctlr;
499 u_int32_t is, ise = 0;
503 if (irq->mode == AHCI_IRQ_MODE_ALL) {
506 is = ctlr->ichannels;
508 is = ATA_INL(ctlr->r_mem, AHCI_IS);
509 } else { /* AHCI_IRQ_MODE_AFTER */
510 unit = irq->r_irq_rid - 1;
511 is = ATA_INL(ctlr->r_mem, AHCI_IS);
512 is &= (0xffffffff << unit);
514 /* CCC interrupt is edge triggered. */
516 ise = 1 << ctlr->cccv;
517 /* Some controllers have edge triggered IS. */
518 if (ctlr->quirks & AHCI_Q_EDGEIS)
521 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
522 for (; unit < ctlr->channels; unit++) {
523 if ((is & (1 << unit)) != 0 &&
524 (arg = ctlr->interrupt[unit].argument)) {
525 ctlr->interrupt[unit].function(arg);
528 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
529 if ((arg = ctlr->interrupt[unit].argument)) {
530 ctlr->interrupt[unit].function(arg);
534 /* AHCI declares level triggered IS. */
535 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
536 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
537 ATA_RBL(ctlr->r_mem, AHCI_IS);
541 * Simplified interrupt handler for multivector MSI mode.
544 ahci_intr_one(void *data)
546 struct ahci_controller_irq *irq = data;
547 struct ahci_controller *ctlr = irq->ctlr;
551 unit = irq->r_irq_rid - 1;
552 if ((arg = ctlr->interrupt[unit].argument))
553 ctlr->interrupt[unit].function(arg);
554 /* AHCI declares level triggered IS. */
555 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
556 ATA_RBL(ctlr->r_mem, AHCI_IS);
560 ahci_intr_one_edge(void *data)
562 struct ahci_controller_irq *irq = data;
563 struct ahci_controller *ctlr = irq->ctlr;
567 unit = irq->r_irq_rid - 1;
568 /* Some controllers have edge triggered IS. */
569 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
570 if ((arg = ctlr->interrupt[unit].argument))
571 ctlr->interrupt[unit].function(arg);
572 ATA_RBL(ctlr->r_mem, AHCI_IS);
576 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
577 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
579 struct ahci_controller *ctlr = device_get_softc(dev);
580 struct resource *res;
582 int offset, size, unit;
583 bool is_em, is_remapped;
585 unit = (intptr_t)device_get_ivars(child);
586 is_em = is_remapped = false;
587 if (unit & AHCI_REMAPPED_UNIT) {
589 unit -= ctlr->channels;
591 } else if (unit & AHCI_EM_UNIT) {
599 offset = ctlr->remap_offset + unit * ctlr->remap_size;
600 size = ctlr->remap_size;
602 offset = AHCI_OFFSET + (unit << 7);
604 } else if (*rid == 0) {
605 offset = AHCI_EM_CTL;
608 offset = (ctlr->emloc & 0xffff0000) >> 14;
609 size = (ctlr->emloc & 0x0000ffff) << 2;
611 if (*rid == 2 && (ctlr->capsem &
612 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
618 st = rman_get_start(ctlr->r_mem);
619 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
620 st + offset + size - 1, size, RF_ACTIVE, child);
622 bus_space_handle_t bsh;
624 bsh = rman_get_bushandle(ctlr->r_mem);
625 bst = rman_get_bustag(ctlr->r_mem);
626 bus_space_subregion(bst, bsh, offset, 128, &bsh);
627 rman_set_bushandle(res, bsh);
628 rman_set_bustag(res, bst);
632 if (*rid == ATA_IRQ_RID)
633 res = ctlr->irqs[0].r_irq;
640 ahci_release_resource(device_t dev, device_t child, int type, int rid,
646 rman_release_resource(r);
649 if (rid != ATA_IRQ_RID)
657 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
658 int flags, driver_filter_t *filter, driver_intr_t *function,
659 void *argument, void **cookiep)
661 struct ahci_controller *ctlr = device_get_softc(dev);
662 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT;
664 if (filter != NULL) {
665 printf("ahci.c: we cannot use a filter here\n");
668 ctlr->interrupt[unit].function = function;
669 ctlr->interrupt[unit].argument = argument;
674 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
677 struct ahci_controller *ctlr = device_get_softc(dev);
678 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT;
680 ctlr->interrupt[unit].function = NULL;
681 ctlr->interrupt[unit].argument = NULL;
686 ahci_print_child(device_t dev, device_t child)
691 retval = bus_print_child_header(dev, child);
692 ivars = (intptr_t)device_get_ivars(child);
693 if ((ivars & AHCI_EM_UNIT) == 0)
694 retval += printf(" at channel %d", (int)ivars & AHCI_UNIT);
695 retval += bus_print_child_footer(dev, child);
700 ahci_child_location_str(device_t dev, device_t child, char *buf,
705 ivars = (intptr_t)device_get_ivars(child);
706 if ((ivars & AHCI_EM_UNIT) == 0)
707 snprintf(buf, buflen, "channel=%d", (int)ivars & AHCI_UNIT);
712 ahci_get_dma_tag(device_t dev, device_t child)
714 struct ahci_controller *ctlr = device_get_softc(dev);
716 return (ctlr->dma_tag);
720 ahci_attached(device_t dev, struct ahci_channel *ch)
722 struct ahci_controller *ctlr = device_get_softc(dev);
724 mtx_lock(&ctlr->ch_mtx);
725 ctlr->ch[ch->unit] = ch;
726 mtx_unlock(&ctlr->ch_mtx);
730 ahci_detached(device_t dev, struct ahci_channel *ch)
732 struct ahci_controller *ctlr = device_get_softc(dev);
734 mtx_lock(&ctlr->ch_mtx);
736 ctlr->ch[ch->unit] = NULL;
737 mtx_unlock(&ch->mtx);
738 mtx_unlock(&ctlr->ch_mtx);
741 struct ahci_channel *
742 ahci_getch(device_t dev, int n)
744 struct ahci_controller *ctlr = device_get_softc(dev);
745 struct ahci_channel *ch;
747 KASSERT(n >= 0 && n < AHCI_MAX_PORTS, ("Bad channel number %d", n));
748 mtx_lock(&ctlr->ch_mtx);
752 mtx_unlock(&ctlr->ch_mtx);
757 ahci_putch(struct ahci_channel *ch)
760 mtx_unlock(&ch->mtx);
764 ahci_ch_probe(device_t dev)
767 device_set_desc_copy(dev, "AHCI channel");
768 return (BUS_PROBE_DEFAULT);
772 ahci_ch_disablephy_proc(SYSCTL_HANDLER_ARGS)
774 struct ahci_channel *ch;
778 value = ch->disablephy;
779 error = sysctl_handle_int(oidp, &value, 0, req);
780 if (error != 0 || req->newptr == NULL || (value != 0 && value != 1))
784 ch->disablephy = value;
786 ahci_ch_deinit(ch->dev);
788 ahci_ch_init(ch->dev);
789 ahci_phy_check_events(ch, ATA_SE_PHY_CHANGED | ATA_SE_EXCHANGED);
791 mtx_unlock(&ch->mtx);
797 ahci_ch_attach(device_t dev)
799 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
800 struct ahci_channel *ch = device_get_softc(dev);
801 struct cam_devq *devq;
802 struct sysctl_ctx_list *ctx;
803 struct sysctl_oid *tree;
804 int rid, error, i, sata_rev = 0;
808 ch->unit = (intptr_t)device_get_ivars(dev);
809 ch->caps = ctlr->caps;
810 ch->caps2 = ctlr->caps2;
811 ch->start = ctlr->ch_start;
812 ch->quirks = ctlr->quirks;
813 ch->vendorid = ctlr->vendorid;
814 ch->deviceid = ctlr->deviceid;
815 ch->subvendorid = ctlr->subvendorid;
816 ch->subdeviceid = ctlr->subdeviceid;
817 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
818 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
820 resource_int_value(device_get_name(dev),
821 device_get_unit(dev), "pm_level", &ch->pm_level);
822 STAILQ_INIT(&ch->doneq);
823 if (ch->pm_level > 3)
824 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
825 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
826 /* JMicron external ports (0) sometimes limited */
827 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
829 if (ch->quirks & AHCI_Q_SATA2)
831 resource_int_value(device_get_name(dev),
832 device_get_unit(dev), "sata_rev", &sata_rev);
833 for (i = 0; i < 16; i++) {
834 ch->user[i].revision = sata_rev;
835 ch->user[i].mode = 0;
836 ch->user[i].bytecount = 8192;
837 ch->user[i].tags = ch->numslots;
838 ch->user[i].caps = 0;
839 ch->curr[i] = ch->user[i];
841 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
842 CTS_SATA_CAPS_H_APST |
843 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
845 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
849 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
852 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
853 version = ATA_INL(ctlr->r_mem, AHCI_VS);
854 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
855 ch->chcaps |= AHCI_P_CMD_FBSCP;
856 if (ch->caps2 & AHCI_CAP2_SDS)
857 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
859 device_printf(dev, "Caps:%s%s%s%s%s%s\n",
860 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
861 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
862 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
863 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
864 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
865 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
868 ahci_slotsalloc(dev);
872 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
873 &rid, RF_SHAREABLE | RF_ACTIVE))) {
874 device_printf(dev, "Unable to map interrupt\n");
878 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
879 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
881 device_printf(dev, "Unable to setup interrupt\n");
885 /* Create the device queue for our SIM. */
886 devq = cam_simq_alloc(ch->numslots);
888 device_printf(dev, "Unable to allocate simq\n");
892 /* Construct SIM entry */
893 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
894 device_get_unit(dev), (struct mtx *)&ch->mtx,
895 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
896 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
898 if (ch->sim == NULL) {
900 device_printf(dev, "unable to allocate sim\n");
904 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
905 device_printf(dev, "unable to register xpt bus\n");
909 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
910 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
911 device_printf(dev, "unable to create path\n");
915 if (ch->pm_level > 3) {
916 callout_reset(&ch->pm_timer,
917 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
920 mtx_unlock(&ch->mtx);
921 ahci_attached(device_get_parent(dev), ch);
922 ctx = device_get_sysctl_ctx(dev);
923 tree = device_get_sysctl_tree(dev);
924 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "disable_phy",
925 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_NEEDGIANT, ch,
926 0, ahci_ch_disablephy_proc, "IU", "Disable PHY");
930 xpt_bus_deregister(cam_sim_path(ch->sim));
932 cam_sim_free(ch->sim, /*free_devq*/TRUE);
934 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
936 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
937 mtx_unlock(&ch->mtx);
938 mtx_destroy(&ch->mtx);
943 ahci_ch_detach(device_t dev)
945 struct ahci_channel *ch = device_get_softc(dev);
947 ahci_detached(device_get_parent(dev), ch);
949 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
950 /* Forget about reset. */
953 xpt_release_simq(ch->sim, TRUE);
955 xpt_free_path(ch->path);
956 xpt_bus_deregister(cam_sim_path(ch->sim));
957 cam_sim_free(ch->sim, /*free_devq*/TRUE);
958 mtx_unlock(&ch->mtx);
960 if (ch->pm_level > 3)
961 callout_drain(&ch->pm_timer);
962 callout_drain(&ch->reset_timer);
963 bus_teardown_intr(dev, ch->r_irq, ch->ih);
964 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
970 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
971 mtx_destroy(&ch->mtx);
976 ahci_ch_init(device_t dev)
978 struct ahci_channel *ch = device_get_softc(dev);
981 /* Disable port interrupts */
982 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
983 /* Setup work areas */
984 work = ch->dma.work_bus + AHCI_CL_OFFSET;
985 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
986 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
987 work = ch->dma.rfis_bus;
988 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
989 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
990 /* Activate the channel and power/spin up device */
991 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
992 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
993 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
994 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1001 ahci_ch_deinit(device_t dev)
1003 struct ahci_channel *ch = device_get_softc(dev);
1005 /* Disable port interrupts. */
1006 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1007 /* Reset command register. */
1010 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1011 /* Allow everything, including partial and slumber modes. */
1012 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1013 /* Request slumber mode transition and give some time to get there. */
1014 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1017 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1022 ahci_ch_suspend(device_t dev)
1024 struct ahci_channel *ch = device_get_softc(dev);
1027 xpt_freeze_simq(ch->sim, 1);
1028 /* Forget about reset. */
1029 if (ch->resetting) {
1031 callout_stop(&ch->reset_timer);
1032 xpt_release_simq(ch->sim, TRUE);
1035 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1036 ahci_ch_deinit(dev);
1037 mtx_unlock(&ch->mtx);
1042 ahci_ch_resume(device_t dev)
1044 struct ahci_channel *ch = device_get_softc(dev);
1049 xpt_release_simq(ch->sim, TRUE);
1050 mtx_unlock(&ch->mtx);
1054 devclass_t ahcich_devclass;
1055 static device_method_t ahcich_methods[] = {
1056 DEVMETHOD(device_probe, ahci_ch_probe),
1057 DEVMETHOD(device_attach, ahci_ch_attach),
1058 DEVMETHOD(device_detach, ahci_ch_detach),
1059 DEVMETHOD(device_suspend, ahci_ch_suspend),
1060 DEVMETHOD(device_resume, ahci_ch_resume),
1063 static driver_t ahcich_driver = {
1066 sizeof(struct ahci_channel)
1068 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
1070 struct ahci_dc_cb_args {
1076 ahci_dmainit(device_t dev)
1078 struct ahci_channel *ch = device_get_softc(dev);
1079 struct ahci_dc_cb_args dcba;
1084 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1085 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1086 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1087 0, NULL, NULL, &ch->dma.work_tag);
1090 error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1091 BUS_DMA_ZERO, &ch->dma.work_map);
1094 error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1095 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT);
1096 if (error != 0 || (error = dcba.error) != 0) {
1097 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1100 ch->dma.work_bus = dcba.maddr;
1101 /* FIS receive area. */
1102 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1106 error = bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1107 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1108 NULL, NULL, rfsize, 1, rfsize,
1109 0, NULL, NULL, &ch->dma.rfis_tag);
1112 error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1116 error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1117 rfsize, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT);
1118 if (error != 0 || (error = dcba.error) != 0) {
1119 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1122 ch->dma.rfis_bus = dcba.maddr;
1124 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1125 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1127 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
1128 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1129 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag);
1135 device_printf(dev, "WARNING - DMA initialization failed, error %d\n",
1141 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1143 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1145 if (!(dcba->error = error))
1146 dcba->maddr = segs[0].ds_addr;
1150 ahci_dmafini(device_t dev)
1152 struct ahci_channel *ch = device_get_softc(dev);
1154 if (ch->dma.data_tag) {
1155 bus_dma_tag_destroy(ch->dma.data_tag);
1156 ch->dma.data_tag = NULL;
1158 if (ch->dma.rfis_bus) {
1159 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1160 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1161 ch->dma.rfis_bus = 0;
1162 ch->dma.rfis = NULL;
1164 if (ch->dma.work_bus) {
1165 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1166 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1167 ch->dma.work_bus = 0;
1168 ch->dma.work = NULL;
1170 if (ch->dma.work_tag) {
1171 bus_dma_tag_destroy(ch->dma.work_tag);
1172 ch->dma.work_tag = NULL;
1177 ahci_slotsalloc(device_t dev)
1179 struct ahci_channel *ch = device_get_softc(dev);
1182 /* Alloc and setup command/dma slots */
1183 bzero(ch->slot, sizeof(ch->slot));
1184 for (i = 0; i < ch->numslots; i++) {
1185 struct ahci_slot *slot = &ch->slot[i];
1189 slot->state = AHCI_SLOT_EMPTY;
1191 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1193 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1194 device_printf(ch->dev, "FAILURE - create data_map\n");
1199 ahci_slotsfree(device_t dev)
1201 struct ahci_channel *ch = device_get_softc(dev);
1204 /* Free all dma slots */
1205 for (i = 0; i < ch->numslots; i++) {
1206 struct ahci_slot *slot = &ch->slot[i];
1208 callout_drain(&slot->timeout);
1209 if (slot->dma.data_map) {
1210 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1211 slot->dma.data_map = NULL;
1217 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1220 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1221 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1222 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1226 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1227 device_printf(ch->dev, "CONNECT requested\n");
1229 device_printf(ch->dev, "DISCONNECT requested\n");
1232 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1234 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1235 cam_sim_path(ch->sim),
1236 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1247 ahci_cpd_check_events(struct ahci_channel *ch)
1253 if (ch->pm_level == 0)
1256 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1257 if ((status & AHCI_P_CMD_CPD) == 0)
1262 if (status & AHCI_P_CMD_CPS) {
1263 device_printf(dev, "COLD CONNECT requested\n");
1265 device_printf(dev, "COLD DISCONNECT requested\n");
1268 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1270 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1271 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1279 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1281 struct cam_path *dpath;
1284 if (ch->caps & AHCI_CAP_SSNTF)
1285 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1287 device_printf(ch->dev, "SNTF 0x%04x\n", status);
1288 for (i = 0; i < 16; i++) {
1289 if ((status & (1 << i)) == 0)
1291 if (xpt_create_path(&dpath, NULL,
1292 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1293 xpt_async(AC_SCSI_AEN, dpath, NULL);
1294 xpt_free_path(dpath);
1300 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1303 mtx_assert(&ch->mtx, MA_OWNED);
1304 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1310 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1314 ahci_ch_intr(void *arg)
1316 struct ahci_channel *ch = (struct ahci_channel *)arg;
1319 /* Read interrupt statuses. */
1320 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1323 ahci_ch_intr_main(ch, istatus);
1324 mtx_unlock(&ch->mtx);
1328 ahci_ch_intr_direct(void *arg)
1330 struct ahci_channel *ch = (struct ahci_channel *)arg;
1331 struct ccb_hdr *ccb_h;
1333 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1335 /* Read interrupt statuses. */
1336 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1340 ahci_ch_intr_main(ch, istatus);
1343 * Prevent the possibility of issues caused by processing the queue
1344 * while unlocked below by moving the contents to a local queue.
1346 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1347 mtx_unlock(&ch->mtx);
1348 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1349 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1350 xpt_done_direct((union ccb *)ccb_h);
1355 ahci_ch_pm(void *arg)
1357 struct ahci_channel *ch = (struct ahci_channel *)arg;
1360 if (ch->numrslots != 0)
1362 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1363 if (ch->pm_level == 4)
1364 work |= AHCI_P_CMD_PARTIAL;
1366 work |= AHCI_P_CMD_SLUMBER;
1367 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1371 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1373 uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1374 enum ahci_err_type et;
1375 int i, ccs, port, reset = 0;
1377 /* Clear interrupt statuses. */
1378 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1379 /* Read command statuses. */
1380 if (ch->numtslots != 0)
1381 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1384 if (ch->numrslots != ch->numtslots)
1385 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1386 /* Read SNTF in one of possible ways. */
1387 if ((istatus & AHCI_P_IX_SDB) &&
1388 (ch->pm_present || ch->curr[0].atapi != 0)) {
1389 if (ch->caps & AHCI_CAP_SSNTF)
1390 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1391 else if (ch->fbs_enabled) {
1392 u_int8_t *fis = ch->dma.rfis + 0x58;
1394 for (i = 0; i < 16; i++) {
1395 if (fis[1] & 0x80) {
1402 u_int8_t *fis = ch->dma.rfis + 0x58;
1405 sntf = (1 << (fis[1] & 0x0f));
1408 /* Process PHY events */
1409 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1410 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1411 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1413 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1414 reset = ahci_phy_check_events(ch, serr);
1417 /* Process cold presence detection events */
1418 if ((istatus & AHCI_P_IX_CPD) && !reset)
1419 ahci_cpd_check_events(ch);
1420 /* Process command errors */
1421 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1422 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1423 if (ch->quirks & AHCI_Q_NOCCS) {
1425 * ASMedia chips sometimes report failed commands as
1426 * completed. Count all running commands as failed.
1428 cstatus |= ch->rslots;
1430 /* They also report wrong CCS, so try to guess one. */
1431 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1433 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1434 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
1436 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1437 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1438 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1440 if (ch->fbs_enabled) {
1441 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1442 if (fbs & AHCI_P_FBS_SDE) {
1443 port = (fbs & AHCI_P_FBS_DWE)
1444 >> AHCI_P_FBS_DWE_SHIFT;
1446 for (i = 0; i < 16; i++) {
1447 if (ch->numrslotspd[i] == 0)
1451 else if (port != i) {
1458 err = ch->rslots & cstatus;
1464 /* Complete all successful commands. */
1465 ok = ch->rslots & ~cstatus;
1466 for (i = 0; i < ch->numslots; i++) {
1468 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1470 /* On error, complete the rest of commands with error statuses. */
1473 union ccb *fccb = ch->frozen;
1475 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1476 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1477 xpt_freeze_devq(fccb->ccb_h.path, 1);
1478 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1480 ahci_done(ch, fccb);
1482 for (i = 0; i < ch->numslots; i++) {
1483 /* XXX: reqests in loading state. */
1484 if (((err >> i) & 1) == 0)
1487 ch->slot[i].ccb->ccb_h.target_id != port)
1489 if (istatus & AHCI_P_IX_TFE) {
1491 /* Task File Error */
1492 if (ch->numtslotspd[
1493 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1494 /* Untagged operation. */
1498 et = AHCI_ERR_INNOCENT;
1500 /* Tagged operation. */
1507 } else if (istatus & AHCI_P_IX_IF) {
1508 if (ch->numtslots == 0 && i != ccs && port != -2)
1509 et = AHCI_ERR_INNOCENT;
1513 et = AHCI_ERR_INVALID;
1514 ahci_end_transaction(&ch->slot[i], et);
1517 * We can't reinit port if there are some other
1518 * commands active, use resume to complete them.
1520 if (ch->rslots != 0 && !ch->recoverycmd)
1521 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1523 /* Process NOTIFY events */
1525 ahci_notify_events(ch, sntf);
1528 /* Must be called with channel locked. */
1530 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1532 int t = ccb->ccb_h.target_id;
1534 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1535 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1536 /* Tagged command while we have no supported tag free. */
1537 if (((~ch->oslots) & (0xffffffff >> (32 -
1538 ch->curr[t].tags))) == 0)
1540 /* If we have FBS */
1541 if (ch->fbs_enabled) {
1542 /* Tagged command while untagged are active. */
1543 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1546 /* Tagged command while untagged are active. */
1547 if (ch->numrslots != 0 && ch->numtslots == 0)
1549 /* Tagged command while tagged to other target is active. */
1550 if (ch->numtslots != 0 &&
1551 ch->taggedtarget != ccb->ccb_h.target_id)
1555 /* If we have FBS */
1556 if (ch->fbs_enabled) {
1557 /* Untagged command while tagged are active. */
1558 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1561 /* Untagged command while tagged are active. */
1562 if (ch->numrslots != 0 && ch->numtslots != 0)
1566 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1567 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1568 /* Atomic command while anything active. */
1569 if (ch->numrslots != 0)
1572 /* We have some atomic command running. */
1573 if (ch->aslots != 0)
1578 /* Must be called with channel locked. */
1580 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1582 struct ahci_slot *slot;
1585 /* Choose empty slot. */
1586 tags = ch->numslots;
1587 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1588 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1589 tags = ch->curr[ccb->ccb_h.target_id].tags;
1590 if (ch->lastslot + 1 < tags)
1591 tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1594 if (tag == 0 || tag + ch->lastslot >= tags)
1595 tag = ffs(~ch->oslots) - 1;
1597 tag += ch->lastslot;
1599 /* Occupy chosen slot. */
1600 slot = &ch->slot[tag];
1602 /* Stop PM timer. */
1603 if (ch->numrslots == 0 && ch->pm_level > 3)
1604 callout_stop(&ch->pm_timer);
1605 /* Update channel stats. */
1606 ch->oslots |= (1 << tag);
1608 ch->numrslotspd[ccb->ccb_h.target_id]++;
1609 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1610 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1612 ch->numtslotspd[ccb->ccb_h.target_id]++;
1613 ch->taggedtarget = ccb->ccb_h.target_id;
1615 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1616 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1617 ch->aslots |= (1 << tag);
1618 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1619 slot->state = AHCI_SLOT_LOADING;
1620 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1621 ahci_dmasetprd, slot, 0);
1623 slot->dma.nsegs = 0;
1624 ahci_execute_transaction(slot);
1628 /* Locked by busdma engine. */
1630 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1632 struct ahci_slot *slot = arg;
1633 struct ahci_channel *ch = slot->ch;
1634 struct ahci_cmd_tab *ctp;
1635 struct ahci_dma_prd *prd;
1639 device_printf(ch->dev, "DMA load error\n");
1640 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1643 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1644 /* Get a piece of the workspace for this request */
1645 ctp = (struct ahci_cmd_tab *)
1646 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1647 /* Fill S/G table */
1648 prd = &ctp->prd_tab[0];
1649 for (i = 0; i < nsegs; i++) {
1650 prd[i].dba = htole64(segs[i].ds_addr);
1651 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1653 slot->dma.nsegs = nsegs;
1654 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1655 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1656 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1657 ahci_execute_transaction(slot);
1660 /* Must be called with channel locked. */
1662 ahci_execute_transaction(struct ahci_slot *slot)
1664 struct ahci_channel *ch = slot->ch;
1665 struct ahci_cmd_tab *ctp;
1666 struct ahci_cmd_list *clp;
1667 union ccb *ccb = slot->ccb;
1668 int port = ccb->ccb_h.target_id & 0x0f;
1669 int fis_size, i, softreset;
1670 uint8_t *fis = ch->dma.rfis + 0x40;
1674 /* Get a piece of the workspace for this request */
1675 ctp = (struct ahci_cmd_tab *)
1676 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1677 /* Setup the FIS for this request */
1678 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1679 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1680 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1683 /* Setup the command list entry */
1684 clp = (struct ahci_cmd_list *)
1685 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1687 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1688 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1689 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1690 (fis_size / sizeof(u_int32_t)) |
1692 clp->prd_length = htole16(slot->dma.nsegs);
1693 /* Special handling for Soft Reset command. */
1694 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1695 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1696 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1698 /* Kick controller into sane state */
1702 cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1705 /* Prepare FIS receive area for check. */
1706 for (i = 0; i < 20; i++)
1712 clp->cmd_flags = htole16(cmd_flags);
1713 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1714 (AHCI_CT_SIZE * slot->slot));
1715 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1717 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1718 BUS_DMASYNC_PREREAD);
1719 /* Set ACTIVE bit for NCQ commands. */
1720 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1721 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1722 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1724 /* If FBS is enabled, set PMP port. */
1725 if (ch->fbs_enabled) {
1726 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1727 (port << AHCI_P_FBS_DEV_SHIFT));
1729 /* Issue command to the controller. */
1730 slot->state = AHCI_SLOT_RUNNING;
1731 ch->rslots |= (1 << slot->slot);
1732 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1733 /* Device reset commands doesn't interrupt. Poll them. */
1734 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1735 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1736 int count, timeout = ccb->ccb_h.timeout * 100;
1737 enum ahci_err_type et = AHCI_ERR_NONE;
1739 for (count = 0; count < timeout; count++) {
1741 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1743 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1746 device_printf(ch->dev,
1747 "Poll error on slot %d, TFD: %04x\n",
1748 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1753 /* Workaround for ATI SB600/SB700 chipsets. */
1754 if (ccb->ccb_h.target_id == 15 &&
1755 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1756 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1757 et = AHCI_ERR_TIMEOUT;
1763 * Some Marvell controllers require additional time
1764 * after soft reset to work properly. Setup delay
1765 * to 50ms after soft reset.
1767 if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
1771 * Marvell HBAs with non-RAID firmware do not wait for
1772 * readiness after soft reset, so we have to wait here.
1773 * Marvell RAIDs do not have this problem, but instead
1774 * sometimes forget to update FIS receive area, breaking
1777 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1778 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1779 softreset == 2 && et == AHCI_ERR_NONE) {
1780 for ( ; count < timeout; count++) {
1781 bus_dmamap_sync(ch->dma.rfis_tag,
1782 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1784 bus_dmamap_sync(ch->dma.rfis_tag,
1785 ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1786 if ((val & ATA_S_BUSY) == 0)
1792 if (timeout && (count >= timeout)) {
1793 device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1795 device_printf(ch->dev, "is %08x cs %08x ss %08x "
1796 "rs %08x tfd %02x serr %08x cmd %08x\n",
1797 ATA_INL(ch->r_mem, AHCI_P_IS),
1798 ATA_INL(ch->r_mem, AHCI_P_CI),
1799 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1800 ATA_INL(ch->r_mem, AHCI_P_TFD),
1801 ATA_INL(ch->r_mem, AHCI_P_SERR),
1802 ATA_INL(ch->r_mem, AHCI_P_CMD));
1803 et = AHCI_ERR_TIMEOUT;
1806 /* Kick controller into sane state and enable FBS. */
1808 ch->eslots |= (1 << slot->slot);
1809 ahci_end_transaction(slot, et);
1812 /* Start command execution timeout */
1813 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1814 0, ahci_timeout, slot, 0);
1818 /* Must be called with channel locked. */
1820 ahci_process_timeout(struct ahci_channel *ch)
1824 mtx_assert(&ch->mtx, MA_OWNED);
1825 /* Handle the rest of commands. */
1826 for (i = 0; i < ch->numslots; i++) {
1827 /* Do we have a running request on slot? */
1828 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1830 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1834 /* Must be called with channel locked. */
1836 ahci_rearm_timeout(struct ahci_channel *ch)
1840 mtx_assert(&ch->mtx, MA_OWNED);
1841 for (i = 0; i < ch->numslots; i++) {
1842 struct ahci_slot *slot = &ch->slot[i];
1844 /* Do we have a running request on slot? */
1845 if (slot->state < AHCI_SLOT_RUNNING)
1847 if ((ch->toslots & (1 << i)) == 0)
1849 callout_reset_sbt(&slot->timeout,
1850 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1851 ahci_timeout, slot, 0);
1855 /* Locked by callout mechanism. */
1857 ahci_timeout(void *arg)
1859 struct ahci_slot *slot = arg;
1860 struct ahci_channel *ch = slot->ch;
1861 device_t dev = ch->dev;
1866 /* Check for stale timeout. */
1867 if (slot->state < AHCI_SLOT_RUNNING)
1870 /* Check if slot was not being executed last time we checked. */
1871 if (slot->state < AHCI_SLOT_EXECUTING) {
1872 /* Check if slot started executing. */
1873 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1874 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1875 >> AHCI_P_CMD_CCS_SHIFT;
1876 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1877 ch->fbs_enabled || ch->wrongccs)
1878 slot->state = AHCI_SLOT_EXECUTING;
1879 else if ((ch->rslots & (1 << ccs)) == 0) {
1881 slot->state = AHCI_SLOT_EXECUTING;
1884 callout_reset_sbt(&slot->timeout,
1885 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1886 ahci_timeout, slot, 0);
1890 device_printf(dev, "Timeout on slot %d port %d\n",
1891 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1892 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1893 "serr %08x cmd %08x\n",
1894 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1895 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1896 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1897 ATA_INL(ch->r_mem, AHCI_P_CMD));
1899 /* Handle frozen command. */
1901 union ccb *fccb = ch->frozen;
1903 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1904 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1905 xpt_freeze_devq(fccb->ccb_h.path, 1);
1906 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1908 ahci_done(ch, fccb);
1910 if (!ch->fbs_enabled && !ch->wrongccs) {
1911 /* Without FBS we know real timeout source. */
1913 /* Handle command with timeout. */
1914 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1915 /* Handle the rest of commands. */
1916 for (i = 0; i < ch->numslots; i++) {
1917 /* Do we have a running request on slot? */
1918 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1920 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1923 /* With FBS we wait for other commands timeout and pray. */
1924 if (ch->toslots == 0)
1925 xpt_freeze_simq(ch->sim, 1);
1926 ch->toslots |= (1 << slot->slot);
1927 if ((ch->rslots & ~ch->toslots) == 0)
1928 ahci_process_timeout(ch);
1930 device_printf(dev, " ... waiting for slots %08x\n",
1931 ch->rslots & ~ch->toslots);
1935 /* Must be called with channel locked. */
1937 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1939 struct ahci_channel *ch = slot->ch;
1940 union ccb *ccb = slot->ccb;
1941 struct ahci_cmd_list *clp;
1945 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1946 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1947 clp = (struct ahci_cmd_list *)
1948 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1949 /* Read result registers to the result struct
1950 * May be incorrect if several commands finished same time,
1951 * so read only when sure or have to.
1953 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1954 struct ata_res *res = &ccb->ataio.res;
1956 if ((et == AHCI_ERR_TFE) ||
1957 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1958 u_int8_t *fis = ch->dma.rfis + 0x40;
1960 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1961 BUS_DMASYNC_POSTREAD);
1962 if (ch->fbs_enabled) {
1963 fis += ccb->ccb_h.target_id * 256;
1964 res->status = fis[2];
1965 res->error = fis[3];
1967 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1970 res->error = tfd >> 8;
1972 res->lba_low = fis[4];
1973 res->lba_mid = fis[5];
1974 res->lba_high = fis[6];
1975 res->device = fis[7];
1976 res->lba_low_exp = fis[8];
1977 res->lba_mid_exp = fis[9];
1978 res->lba_high_exp = fis[10];
1979 res->sector_count = fis[12];
1980 res->sector_count_exp = fis[13];
1983 * Some weird controllers do not return signature in
1984 * FIS receive area. Read it from PxSIG register.
1986 if ((ch->quirks & AHCI_Q_ALTSIG) &&
1987 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1988 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1989 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
1990 res->lba_high = sig >> 24;
1991 res->lba_mid = sig >> 16;
1992 res->lba_low = sig >> 8;
1993 res->sector_count = sig;
1996 bzero(res, sizeof(*res));
1997 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
1998 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1999 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2001 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2004 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2005 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2007 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2010 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2011 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2012 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2013 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2014 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2016 if (et != AHCI_ERR_NONE)
2017 ch->eslots |= (1 << slot->slot);
2018 /* In case of error, freeze device for proper recovery. */
2019 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2020 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2021 xpt_freeze_devq(ccb->ccb_h.path, 1);
2022 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2024 /* Set proper result status. */
2025 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2028 ccb->ccb_h.status |= CAM_REQ_CMP;
2029 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2030 ccb->csio.scsi_status = SCSI_STATUS_OK;
2032 case AHCI_ERR_INVALID:
2034 ccb->ccb_h.status |= CAM_REQ_INVALID;
2036 case AHCI_ERR_INNOCENT:
2037 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2041 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2042 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2043 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2045 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2050 if (!ch->recoverycmd) {
2051 xpt_freeze_simq(ch->sim, 1);
2052 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2053 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2055 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2057 case AHCI_ERR_TIMEOUT:
2058 if (!ch->recoverycmd) {
2059 xpt_freeze_simq(ch->sim, 1);
2060 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2061 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2063 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2067 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2070 ch->oslots &= ~(1 << slot->slot);
2071 ch->rslots &= ~(1 << slot->slot);
2072 ch->aslots &= ~(1 << slot->slot);
2073 slot->state = AHCI_SLOT_EMPTY;
2075 /* Update channel stats. */
2077 ch->numrslotspd[ccb->ccb_h.target_id]--;
2078 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2079 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2081 ch->numtslotspd[ccb->ccb_h.target_id]--;
2083 /* Cancel timeout state if request completed normally. */
2084 if (et != AHCI_ERR_TIMEOUT) {
2085 lastto = (ch->toslots == (1 << slot->slot));
2086 ch->toslots &= ~(1 << slot->slot);
2088 xpt_release_simq(ch->sim, TRUE);
2090 /* If it was first request of reset sequence and there is no error,
2091 * proceed to second request. */
2092 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2093 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2094 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2095 et == AHCI_ERR_NONE) {
2096 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2097 ahci_begin_transaction(ch, ccb);
2100 /* If it was our READ LOG command - process it. */
2101 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2102 ahci_process_read_log(ch, ccb);
2103 /* If it was our REQUEST SENSE command - process it. */
2104 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2105 ahci_process_request_sense(ch, ccb);
2106 /* If it was NCQ or ATAPI command error, put result on hold. */
2107 } else if (et == AHCI_ERR_NCQ ||
2108 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2109 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2110 ch->hold[slot->slot] = ccb;
2114 /* If we have no other active commands, ... */
2115 if (ch->rslots == 0) {
2116 /* if there was fatal error - reset port. */
2117 if (ch->toslots != 0 || ch->fatalerr) {
2120 /* if we have slots in error, we can reinit port. */
2121 if (ch->eslots != 0) {
2126 /* if there commands on hold, we can do READ LOG. */
2127 if (!ch->recoverycmd && ch->numhslots)
2128 ahci_issue_recovery(ch);
2130 /* If all the rest of commands are in timeout - give them chance. */
2131 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2132 et != AHCI_ERR_TIMEOUT)
2133 ahci_rearm_timeout(ch);
2134 /* Unfreeze frozen command. */
2135 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
2136 union ccb *fccb = ch->frozen;
2138 ahci_begin_transaction(ch, fccb);
2139 xpt_release_simq(ch->sim, TRUE);
2141 /* Start PM timer. */
2142 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2143 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2144 callout_schedule(&ch->pm_timer,
2145 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2150 ahci_issue_recovery(struct ahci_channel *ch)
2153 struct ccb_ataio *ataio;
2154 struct ccb_scsiio *csio;
2157 /* Find some held command. */
2158 for (i = 0; i < ch->numslots; i++) {
2162 ccb = xpt_alloc_ccb_nowait();
2164 device_printf(ch->dev, "Unable to allocate recovery command\n");
2166 /* We can't do anything -- complete held commands. */
2167 for (i = 0; i < ch->numslots; i++) {
2168 if (ch->hold[i] == NULL)
2170 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2171 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2172 ahci_done(ch, ch->hold[i]);
2179 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2180 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2182 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2183 ccb->ccb_h.func_code = XPT_ATA_IO;
2184 ccb->ccb_h.flags = CAM_DIR_IN;
2185 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2186 ataio = &ccb->ataio;
2187 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2188 if (ataio->data_ptr == NULL) {
2190 device_printf(ch->dev,
2191 "Unable to allocate memory for READ LOG command\n");
2194 ataio->dxfer_len = 512;
2195 bzero(&ataio->cmd, sizeof(ataio->cmd));
2196 ataio->cmd.flags = CAM_ATAIO_48BIT;
2197 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2198 ataio->cmd.sector_count = 1;
2199 ataio->cmd.sector_count_exp = 0;
2200 ataio->cmd.lba_low = 0x10;
2201 ataio->cmd.lba_mid = 0;
2202 ataio->cmd.lba_mid_exp = 0;
2205 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2206 ccb->ccb_h.recovery_slot = i;
2207 ccb->ccb_h.func_code = XPT_SCSI_IO;
2208 ccb->ccb_h.flags = CAM_DIR_IN;
2209 ccb->ccb_h.status = 0;
2210 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2212 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2213 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2215 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2216 csio->cdb_io.cdb_bytes[0] = 0x03;
2217 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2219 /* Freeze SIM while doing recovery. */
2220 ch->recoverycmd = 1;
2221 xpt_freeze_simq(ch->sim, 1);
2222 ahci_begin_transaction(ch, ccb);
2226 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
2229 struct ata_res *res;
2232 ch->recoverycmd = 0;
2234 data = ccb->ataio.data_ptr;
2235 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2236 (data[0] & 0x80) == 0) {
2237 for (i = 0; i < ch->numslots; i++) {
2240 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2242 if ((data[0] & 0x1F) == i) {
2243 res = &ch->hold[i]->ataio.res;
2244 res->status = data[2];
2245 res->error = data[3];
2246 res->lba_low = data[4];
2247 res->lba_mid = data[5];
2248 res->lba_high = data[6];
2249 res->device = data[7];
2250 res->lba_low_exp = data[8];
2251 res->lba_mid_exp = data[9];
2252 res->lba_high_exp = data[10];
2253 res->sector_count = data[12];
2254 res->sector_count_exp = data[13];
2256 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2257 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2259 ahci_done(ch, ch->hold[i]);
2264 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2265 device_printf(ch->dev, "Error while READ LOG EXT\n");
2266 else if ((data[0] & 0x80) == 0) {
2267 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2269 for (i = 0; i < ch->numslots; i++) {
2272 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2274 ahci_done(ch, ch->hold[i]);
2279 free(ccb->ataio.data_ptr, M_AHCI);
2281 xpt_release_simq(ch->sim, TRUE);
2285 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2289 ch->recoverycmd = 0;
2291 i = ccb->ccb_h.recovery_slot;
2292 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2293 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2295 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2296 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2298 ahci_done(ch, ch->hold[i]);
2302 xpt_release_simq(ch->sim, TRUE);
2306 ahci_start(struct ahci_channel *ch, int fbs)
2310 /* Run the channel start callback, if any. */
2314 /* Clear SATA error register */
2315 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2316 /* Clear any interrupts pending on this channel */
2317 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2318 /* Configure FIS-based switching if supported. */
2319 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2320 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2321 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2322 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2324 /* Start operations on this channel */
2325 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2326 cmd &= ~AHCI_P_CMD_PMA;
2327 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2328 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2332 ahci_stop(struct ahci_channel *ch)
2337 /* Kill all activity on this channel */
2338 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2339 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2340 /* Wait for activity stop. */
2344 if (timeout++ > 50000) {
2345 device_printf(ch->dev, "stopping AHCI engine failed\n");
2348 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2353 ahci_clo(struct ahci_channel *ch)
2358 /* Issue Command List Override if supported */
2359 if (ch->caps & AHCI_CAP_SCLO) {
2360 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2361 cmd |= AHCI_P_CMD_CLO;
2362 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2366 if (timeout++ > 50000) {
2367 device_printf(ch->dev, "executing CLO failed\n");
2370 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2375 ahci_stop_fr(struct ahci_channel *ch)
2380 /* Kill all FIS reception on this channel */
2381 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2382 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2383 /* Wait for FIS reception stop. */
2387 if (timeout++ > 50000) {
2388 device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2391 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2395 ahci_start_fr(struct ahci_channel *ch)
2399 /* Start FIS reception on this channel */
2400 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2401 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2405 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2410 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2411 (ATA_S_BUSY | ATA_S_DRQ)) {
2414 device_printf(ch->dev,
2415 "AHCI reset: device not ready after %dms "
2417 MAX(t, 0) + t0, val);
2425 device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2431 ahci_reset_to(void *arg)
2433 struct ahci_channel *ch = arg;
2435 if (ch->resetting == 0)
2438 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2439 (310 - ch->resetting) * 100) == 0) {
2442 xpt_release_simq(ch->sim, TRUE);
2445 if (ch->resetting == 0) {
2448 xpt_release_simq(ch->sim, TRUE);
2451 callout_schedule(&ch->reset_timer, hz / 10);
2455 ahci_reset(struct ahci_channel *ch)
2457 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2460 xpt_freeze_simq(ch->sim, 1);
2462 device_printf(ch->dev, "AHCI reset...\n");
2463 /* Forget about previous reset. */
2464 if (ch->resetting) {
2466 callout_stop(&ch->reset_timer);
2467 xpt_release_simq(ch->sim, TRUE);
2469 /* Requeue freezed command. */
2471 union ccb *fccb = ch->frozen;
2473 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2474 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2475 xpt_freeze_devq(fccb->ccb_h.path, 1);
2476 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2478 ahci_done(ch, fccb);
2480 /* Kill the engine and requeue all running commands. */
2482 for (i = 0; i < ch->numslots; i++) {
2483 /* Do we have a running request on slot? */
2484 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2486 /* XXX; Commands in loading state. */
2487 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2489 for (i = 0; i < ch->numslots; i++) {
2492 ahci_done(ch, ch->hold[i]);
2496 if (ch->toslots != 0)
2497 xpt_release_simq(ch->sim, TRUE);
2502 /* Tell the XPT about the event */
2503 xpt_async(AC_BUS_RESET, ch->path, NULL);
2504 /* Disable port interrupts */
2505 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2506 /* Reset and reconnect PHY, */
2507 if (!ahci_sata_phy_reset(ch)) {
2509 device_printf(ch->dev,
2510 "AHCI reset: device not found\n");
2512 /* Enable wanted port interrupts */
2513 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2514 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2515 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2516 xpt_release_simq(ch->sim, TRUE);
2520 device_printf(ch->dev, "AHCI reset: device found\n");
2521 /* Wait for clearing busy status. */
2522 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2526 ch->resetting = 310;
2529 /* Enable wanted port interrupts */
2530 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2531 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2532 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2533 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2534 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2535 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2536 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2538 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2541 xpt_release_simq(ch->sim, TRUE);
2546 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2548 u_int8_t *fis = &ctp->cfis[0];
2551 fis[0] = 0x27; /* host to device */
2552 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2553 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2555 fis[2] = ATA_PACKET_CMD;
2556 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2557 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2560 fis[5] = ccb->csio.dxfer_len;
2561 fis[6] = ccb->csio.dxfer_len >> 8;
2564 fis[15] = ATA_A_4BIT;
2565 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2566 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2567 ctp->acmd, ccb->csio.cdb_len);
2568 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2569 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2571 fis[2] = ccb->ataio.cmd.command;
2572 fis[3] = ccb->ataio.cmd.features;
2573 fis[4] = ccb->ataio.cmd.lba_low;
2574 fis[5] = ccb->ataio.cmd.lba_mid;
2575 fis[6] = ccb->ataio.cmd.lba_high;
2576 fis[7] = ccb->ataio.cmd.device;
2577 fis[8] = ccb->ataio.cmd.lba_low_exp;
2578 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2579 fis[10] = ccb->ataio.cmd.lba_high_exp;
2580 fis[11] = ccb->ataio.cmd.features_exp;
2581 fis[12] = ccb->ataio.cmd.sector_count;
2582 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2584 fis[12] |= tag << 3;
2586 fis[13] = ccb->ataio.cmd.sector_count_exp;
2587 fis[15] = ATA_A_4BIT;
2589 fis[15] = ccb->ataio.cmd.control;
2591 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2592 fis[16] = ccb->ataio.aux & 0xff;
2593 fis[17] = (ccb->ataio.aux >> 8) & 0xff;
2594 fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2595 fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2601 ahci_sata_connect(struct ahci_channel *ch)
2604 int timeout, found = 0;
2606 /* Wait up to 100ms for "connect well" */
2607 for (timeout = 0; timeout < 1000 ; timeout++) {
2608 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2609 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2611 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2612 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2613 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2615 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2617 device_printf(ch->dev, "SATA offline status=%08x\n",
2622 if (found == 0 && timeout >= 100)
2626 if (timeout >= 1000 || !found) {
2628 device_printf(ch->dev,
2629 "SATA connect timeout time=%dus status=%08x\n",
2630 timeout * 100, status);
2635 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2636 timeout * 100, status);
2638 /* Clear SATA error register */
2639 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2644 ahci_sata_phy_reset(struct ahci_channel *ch)
2647 uint32_t val, detval;
2649 if (ch->listening) {
2650 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2651 val |= AHCI_P_CMD_SUD;
2652 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2655 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2657 val = ATA_SC_SPD_SPEED_GEN1;
2658 else if (sata_rev == 2)
2659 val = ATA_SC_SPD_SPEED_GEN2;
2660 else if (sata_rev == 3)
2661 val = ATA_SC_SPD_SPEED_GEN3;
2664 detval = ahci_ch_detval(ch, ATA_SC_DET_RESET);
2665 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2667 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2669 detval = ahci_ch_detval(ch, ATA_SC_DET_IDLE);
2670 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2671 detval | val | ((ch->pm_level > 0) ? 0 :
2672 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2673 if (!ahci_sata_connect(ch)) {
2674 if (ch->caps & AHCI_CAP_SSS) {
2675 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2676 val &= ~AHCI_P_CMD_SUD;
2677 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2679 } else if (ch->pm_level > 0)
2680 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2687 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2690 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2691 ccb->ccb_h.status = CAM_TID_INVALID;
2695 if (ccb->ccb_h.target_lun != 0) {
2696 ccb->ccb_h.status = CAM_LUN_INVALID;
2704 ahciaction(struct cam_sim *sim, union ccb *ccb)
2706 struct ahci_channel *ch;
2708 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2709 ccb->ccb_h.func_code));
2711 ch = (struct ahci_channel *)cam_sim_softc(sim);
2712 switch (ccb->ccb_h.func_code) {
2713 /* Common cases first */
2714 case XPT_ATA_IO: /* Execute the requested I/O operation */
2716 if (ahci_check_ids(ch, ccb))
2718 if (ch->devices == 0 ||
2719 (ch->pm_present == 0 &&
2720 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2721 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2724 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2725 /* Check for command collision. */
2726 if (ahci_check_collision(ch, ccb)) {
2727 /* Freeze command. */
2729 /* We have only one frozen slot, so freeze simq also. */
2730 xpt_freeze_simq(ch->sim, 1);
2733 ahci_begin_transaction(ch, ccb);
2735 case XPT_ABORT: /* Abort the specified CCB */
2737 ccb->ccb_h.status = CAM_REQ_INVALID;
2739 case XPT_SET_TRAN_SETTINGS:
2741 struct ccb_trans_settings *cts = &ccb->cts;
2742 struct ahci_device *d;
2744 if (ahci_check_ids(ch, ccb))
2746 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2747 d = &ch->curr[ccb->ccb_h.target_id];
2749 d = &ch->user[ccb->ccb_h.target_id];
2750 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2751 d->revision = cts->xport_specific.sata.revision;
2752 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2753 d->mode = cts->xport_specific.sata.mode;
2754 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2755 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2757 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2759 ch->pm_present = cts->xport_specific.sata.pm_present;
2760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2761 d->atapi = cts->xport_specific.sata.atapi;
2762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2763 d->caps = cts->xport_specific.sata.caps;
2764 ccb->ccb_h.status = CAM_REQ_CMP;
2767 case XPT_GET_TRAN_SETTINGS:
2768 /* Get default/user set transfer settings for the target */
2770 struct ccb_trans_settings *cts = &ccb->cts;
2771 struct ahci_device *d;
2774 if (ahci_check_ids(ch, ccb))
2776 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2777 d = &ch->curr[ccb->ccb_h.target_id];
2779 d = &ch->user[ccb->ccb_h.target_id];
2780 cts->protocol = PROTO_UNSPECIFIED;
2781 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2782 cts->transport = XPORT_SATA;
2783 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2784 cts->proto_specific.valid = 0;
2785 cts->xport_specific.sata.valid = 0;
2786 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2787 (ccb->ccb_h.target_id == 15 ||
2788 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2789 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2790 if (status & 0x0f0) {
2791 cts->xport_specific.sata.revision =
2792 (status & 0x0f0) >> 4;
2793 cts->xport_specific.sata.valid |=
2794 CTS_SATA_VALID_REVISION;
2796 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2798 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2799 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2800 if (ch->caps2 & AHCI_CAP2_APST)
2801 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2803 if ((ch->caps & AHCI_CAP_SNCQ) &&
2804 (ch->quirks & AHCI_Q_NOAA) == 0)
2805 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2806 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2807 cts->xport_specific.sata.caps &=
2808 ch->user[ccb->ccb_h.target_id].caps;
2809 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2811 cts->xport_specific.sata.revision = d->revision;
2812 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2813 cts->xport_specific.sata.caps = d->caps;
2814 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2816 cts->xport_specific.sata.mode = d->mode;
2817 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2818 cts->xport_specific.sata.bytecount = d->bytecount;
2819 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2820 cts->xport_specific.sata.pm_present = ch->pm_present;
2821 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2822 cts->xport_specific.sata.tags = d->tags;
2823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2824 cts->xport_specific.sata.atapi = d->atapi;
2825 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2826 ccb->ccb_h.status = CAM_REQ_CMP;
2829 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2830 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2832 ccb->ccb_h.status = CAM_REQ_CMP;
2834 case XPT_TERM_IO: /* Terminate the I/O process */
2836 ccb->ccb_h.status = CAM_REQ_INVALID;
2838 case XPT_PATH_INQ: /* Path routing inquiry */
2840 struct ccb_pathinq *cpi = &ccb->cpi;
2842 cpi->version_num = 1; /* XXX??? */
2843 cpi->hba_inquiry = PI_SDTR_ABLE;
2844 if (ch->caps & AHCI_CAP_SNCQ)
2845 cpi->hba_inquiry |= PI_TAG_ABLE;
2846 if (ch->caps & AHCI_CAP_SPM)
2847 cpi->hba_inquiry |= PI_SATAPM;
2848 cpi->target_sprt = 0;
2849 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2850 if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2851 cpi->hba_misc |= PIM_ATA_EXT;
2852 cpi->hba_eng_cnt = 0;
2853 if (ch->caps & AHCI_CAP_SPM)
2854 cpi->max_target = 15;
2856 cpi->max_target = 0;
2858 cpi->initiator_id = 0;
2859 cpi->bus_id = cam_sim_bus(sim);
2860 cpi->base_transfer_speed = 150000;
2861 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2862 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2863 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2864 cpi->unit_number = cam_sim_unit(sim);
2865 cpi->transport = XPORT_SATA;
2866 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2867 cpi->protocol = PROTO_ATA;
2868 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2869 cpi->maxio = MAXPHYS;
2870 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2871 if (ch->quirks & AHCI_Q_MAXIO_64K)
2872 cpi->maxio = min(cpi->maxio, 128 * 512);
2873 cpi->hba_vendor = ch->vendorid;
2874 cpi->hba_device = ch->deviceid;
2875 cpi->hba_subvendor = ch->subvendorid;
2876 cpi->hba_subdevice = ch->subdeviceid;
2877 cpi->ccb_h.status = CAM_REQ_CMP;
2881 ccb->ccb_h.status = CAM_REQ_INVALID;
2888 ahcipoll(struct cam_sim *sim)
2890 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2893 /* Read interrupt statuses and process if any. */
2894 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2896 ahci_ch_intr_main(ch, istatus);
2897 if (ch->resetting != 0 &&
2898 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2899 ch->resetpolldiv = 1000;
2904 devclass_t ahci_devclass;
2906 MODULE_VERSION(ahci, 1);
2907 MODULE_DEPEND(ahci, cam, 1, 1, 1);