2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/sysctl.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
51 #include <cam/cam_ccb.h>
52 #include <cam/cam_sim.h>
53 #include <cam/cam_xpt_sim.h>
54 #include <cam/cam_debug.h>
56 /* local prototypes */
57 static void ahci_intr(void *data);
58 static void ahci_intr_one(void *data);
59 static void ahci_intr_one_edge(void *data);
60 static int ahci_ch_init(device_t dev);
61 static int ahci_ch_deinit(device_t dev);
62 static int ahci_ch_suspend(device_t dev);
63 static int ahci_ch_resume(device_t dev);
64 static void ahci_ch_pm(void *arg);
65 static void ahci_ch_intr(void *arg);
66 static void ahci_ch_intr_direct(void *arg);
67 static void ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus);
68 static void ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb);
69 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
70 static void ahci_execute_transaction(struct ahci_slot *slot);
71 static void ahci_timeout(void *arg);
72 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
73 static int ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
74 static void ahci_dmainit(device_t dev);
75 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
76 static void ahci_dmafini(device_t dev);
77 static void ahci_slotsalloc(device_t dev);
78 static void ahci_slotsfree(device_t dev);
79 static void ahci_reset(struct ahci_channel *ch);
80 static void ahci_start(struct ahci_channel *ch, int fbs);
81 static void ahci_stop(struct ahci_channel *ch);
82 static void ahci_clo(struct ahci_channel *ch);
83 static void ahci_start_fr(struct ahci_channel *ch);
84 static void ahci_stop_fr(struct ahci_channel *ch);
85 static int ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr);
86 static uint32_t ahci_ch_detval(struct ahci_channel *ch, uint32_t val);
88 static int ahci_sata_connect(struct ahci_channel *ch);
89 static int ahci_sata_phy_reset(struct ahci_channel *ch);
90 static int ahci_wait_ready(struct ahci_channel *ch, int t, int t0);
92 static void ahci_issue_recovery(struct ahci_channel *ch);
93 static void ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb);
94 static void ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb);
96 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
97 static void ahcipoll(struct cam_sim *sim);
99 static MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
101 #define recovery_type spriv_field0
102 #define RECOVERY_NONE 0
103 #define RECOVERY_READ_LOG 1
104 #define RECOVERY_REQUEST_SENSE 2
105 #define recovery_slot spriv_field1
108 ahci_ch_detval(struct ahci_channel *ch, uint32_t val)
111 return ch->disablephy ? ATA_SC_DET_DISABLE : val;
115 ahci_ctlr_setup(device_t dev)
117 struct ahci_controller *ctlr = device_get_softc(dev);
118 /* Clear interrupts */
119 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
122 ATA_OUTL(ctlr->r_mem, AHCI_CCCP, ATA_INL(ctlr->r_mem, AHCI_PI));
123 ATA_OUTL(ctlr->r_mem, AHCI_CCCC,
124 (ctlr->ccc << AHCI_CCCC_TV_SHIFT) |
125 (4 << AHCI_CCCC_CC_SHIFT) |
127 ctlr->cccv = (ATA_INL(ctlr->r_mem, AHCI_CCCC) &
128 AHCI_CCCC_INT_MASK) >> AHCI_CCCC_INT_SHIFT;
131 "CCC with %dms/4cmd enabled on vector %d\n",
132 ctlr->ccc, ctlr->cccv);
135 /* Enable AHCI interrupts */
136 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
137 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
142 ahci_ctlr_reset(device_t dev)
144 struct ahci_controller *ctlr = device_get_softc(dev);
148 /* BIOS/OS Handoff */
149 if ((ATA_INL(ctlr->r_mem, AHCI_VS) >= 0x00010200) &&
150 (ATA_INL(ctlr->r_mem, AHCI_CAP2) & AHCI_CAP2_BOH) &&
151 ((v = ATA_INL(ctlr->r_mem, AHCI_BOHC)) & AHCI_BOHC_OOS) == 0) {
152 /* Request OS ownership. */
153 ATA_OUTL(ctlr->r_mem, AHCI_BOHC, v | AHCI_BOHC_OOS);
155 /* Wait up to 2s for BIOS ownership release. */
156 for (timeout = 0; timeout < 80; timeout++) {
158 v = ATA_INL(ctlr->r_mem, AHCI_BOHC);
159 if ((v & AHCI_BOHC_BOS) == 0)
161 if ((v & AHCI_BOHC_BB) == 0)
166 /* Enable AHCI mode */
167 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
168 /* Reset AHCI controller */
169 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
170 for (timeout = 1000; timeout > 0; timeout--) {
172 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
176 device_printf(dev, "AHCI controller reset failure\n");
179 /* Reenable AHCI mode */
180 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
182 if (ctlr->quirks & AHCI_Q_RESTORE_CAP) {
184 * Restore capability field.
185 * This is write to a read-only register to restore its state.
186 * On fully standard-compliant hardware this is not needed and
187 * this operation shall not take place. See ahci_pci.c for
188 * platforms using this quirk.
190 ATA_OUTL(ctlr->r_mem, AHCI_CAP, ctlr->caps);
197 ahci_attach(device_t dev)
199 struct ahci_controller *ctlr = device_get_softc(dev);
200 int error, i, speed, unit;
206 resource_int_value(device_get_name(dev),
207 device_get_unit(dev), "ccc", &ctlr->ccc);
208 mtx_init(&ctlr->ch_mtx, "AHCI channels lock", NULL, MTX_DEF);
210 /* Setup our own memory management for channels. */
211 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
212 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
213 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
214 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
215 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
219 if ((error = rman_manage_region(&ctlr->sc_iomem,
220 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
222 rman_fini(&ctlr->sc_iomem);
225 /* Get the HW capabilities */
226 version = ATA_INL(ctlr->r_mem, AHCI_VS);
227 ctlr->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
228 if (version >= 0x00010200)
229 ctlr->caps2 = ATA_INL(ctlr->r_mem, AHCI_CAP2);
230 if (ctlr->caps & AHCI_CAP_EMS)
231 ctlr->capsem = ATA_INL(ctlr->r_mem, AHCI_EM_CTL);
233 if (ctlr->quirks & AHCI_Q_FORCE_PI) {
236 * The spec says that BIOS sets up bits corresponding to
237 * available ports. On platforms where this information
238 * is missing, the driver can define available ports on its own.
240 int nports = (ctlr->caps & AHCI_CAP_NPMASK) + 1;
241 int nmask = (1 << nports) - 1;
243 ATA_OUTL(ctlr->r_mem, AHCI_PI, nmask);
244 device_printf(dev, "Forcing PI to %d ports (mask = %x)\n",
248 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
250 /* Identify and set separate quirks for HBA and RAID f/w Marvells. */
251 if ((ctlr->quirks & AHCI_Q_ALTSIG) &&
252 (ctlr->caps & AHCI_CAP_SPM) == 0)
253 ctlr->quirks |= AHCI_Q_NOBSYRES;
255 if (ctlr->quirks & AHCI_Q_1CH) {
256 ctlr->caps &= ~AHCI_CAP_NPMASK;
257 ctlr->ichannels &= 0x01;
259 if (ctlr->quirks & AHCI_Q_2CH) {
260 ctlr->caps &= ~AHCI_CAP_NPMASK;
262 ctlr->ichannels &= 0x03;
264 if (ctlr->quirks & AHCI_Q_4CH) {
265 ctlr->caps &= ~AHCI_CAP_NPMASK;
267 ctlr->ichannels &= 0x0f;
269 ctlr->channels = MAX(flsl(ctlr->ichannels),
270 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
271 if (ctlr->quirks & AHCI_Q_NOPMP)
272 ctlr->caps &= ~AHCI_CAP_SPM;
273 if (ctlr->quirks & AHCI_Q_NONCQ)
274 ctlr->caps &= ~AHCI_CAP_SNCQ;
275 if ((ctlr->caps & AHCI_CAP_CCCS) == 0)
277 ctlr->emloc = ATA_INL(ctlr->r_mem, AHCI_EM_LOC);
279 /* Create controller-wide DMA tag. */
280 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
281 (ctlr->caps & AHCI_CAP_64BIT) ? BUS_SPACE_MAXADDR :
282 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
283 BUS_SPACE_MAXSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE,
284 ctlr->dma_coherent ? BUS_DMA_COHERENT : 0, NULL, NULL,
287 rman_fini(&ctlr->sc_iomem);
291 ahci_ctlr_setup(dev);
293 /* Setup interrupts. */
294 if ((error = ahci_setup_interrupt(dev)) != 0) {
295 bus_dma_tag_destroy(ctlr->dma_tag);
297 rman_fini(&ctlr->sc_iomem);
302 for (u = ctlr->ichannels; u != 0; u >>= 1)
304 ctlr->direct = (ctlr->msi && (ctlr->numirqs > 1 || i <= 3));
305 resource_int_value(device_get_name(dev), device_get_unit(dev),
306 "direct", &ctlr->direct);
307 /* Announce HW capabilities. */
308 speed = (ctlr->caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
310 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s%s\n",
311 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
312 ((version >> 4) & 0xf0) + (version & 0x0f),
313 (ctlr->caps & AHCI_CAP_NPMASK) + 1,
314 ((speed == 1) ? "1.5":((speed == 2) ? "3":
315 ((speed == 3) ? "6":"?"))),
316 (ctlr->caps & AHCI_CAP_SPM) ?
317 "supported" : "not supported",
318 (ctlr->caps & AHCI_CAP_FBSS) ?
320 if (ctlr->quirks != 0) {
321 device_printf(dev, "quirks=0x%b\n", ctlr->quirks,
325 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
326 (ctlr->caps & AHCI_CAP_64BIT) ? " 64bit":"",
327 (ctlr->caps & AHCI_CAP_SNCQ) ? " NCQ":"",
328 (ctlr->caps & AHCI_CAP_SSNTF) ? " SNTF":"",
329 (ctlr->caps & AHCI_CAP_SMPS) ? " MPS":"",
330 (ctlr->caps & AHCI_CAP_SSS) ? " SS":"",
331 (ctlr->caps & AHCI_CAP_SALP) ? " ALP":"",
332 (ctlr->caps & AHCI_CAP_SAL) ? " AL":"",
333 (ctlr->caps & AHCI_CAP_SCLO) ? " CLO":"",
334 ((speed == 1) ? "1.5":((speed == 2) ? "3":
335 ((speed == 3) ? "6":"?"))));
336 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
337 (ctlr->caps & AHCI_CAP_SAM) ? " AM":"",
338 (ctlr->caps & AHCI_CAP_SPM) ? " PM":"",
339 (ctlr->caps & AHCI_CAP_FBSS) ? " FBS":"",
340 (ctlr->caps & AHCI_CAP_PMD) ? " PMD":"",
341 (ctlr->caps & AHCI_CAP_SSC) ? " SSC":"",
342 (ctlr->caps & AHCI_CAP_PSC) ? " PSC":"",
343 ((ctlr->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
344 (ctlr->caps & AHCI_CAP_CCCS) ? " CCC":"",
345 (ctlr->caps & AHCI_CAP_EMS) ? " EM":"",
346 (ctlr->caps & AHCI_CAP_SXS) ? " eSATA":"",
347 (ctlr->caps & AHCI_CAP_NPMASK) + 1);
349 if (bootverbose && version >= 0x00010200) {
350 device_printf(dev, "Caps2:%s%s%s%s%s%s\n",
351 (ctlr->caps2 & AHCI_CAP2_DESO) ? " DESO":"",
352 (ctlr->caps2 & AHCI_CAP2_SADM) ? " SADM":"",
353 (ctlr->caps2 & AHCI_CAP2_SDS) ? " SDS":"",
354 (ctlr->caps2 & AHCI_CAP2_APST) ? " APST":"",
355 (ctlr->caps2 & AHCI_CAP2_NVMP) ? " NVMP":"",
356 (ctlr->caps2 & AHCI_CAP2_BOH) ? " BOH":"");
358 /* Attach all channels on this controller */
359 for (unit = 0; unit < ctlr->channels; unit++) {
360 child = device_add_child(dev, "ahcich", -1);
362 device_printf(dev, "failed to add channel device\n");
365 device_set_ivars(child, (void *)(intptr_t)unit);
366 if ((ctlr->ichannels & (1 << unit)) == 0)
367 device_disable(child);
369 /* Attach any remapped NVME device */
370 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
371 child = device_add_child(dev, "nvme", -1);
373 device_printf(dev, "failed to add remapped NVMe device");
376 device_set_ivars(child, (void *)(intptr_t)(unit | AHCI_REMAPPED_UNIT));
379 int em = (ctlr->caps & AHCI_CAP_EMS) != 0;
380 resource_int_value(device_get_name(dev), device_get_unit(dev),
383 child = device_add_child(dev, "ahciem", -1);
385 device_printf(dev, "failed to add enclosure device\n");
387 device_set_ivars(child, (void *)(intptr_t)AHCI_EM_UNIT);
389 bus_generic_attach(dev);
394 ahci_detach(device_t dev)
396 struct ahci_controller *ctlr = device_get_softc(dev);
399 /* Detach & delete all children */
400 device_delete_children(dev);
402 /* Free interrupts. */
403 for (i = 0; i < ctlr->numirqs; i++) {
404 if (ctlr->irqs[i].r_irq) {
405 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
406 ctlr->irqs[i].handle);
407 bus_release_resource(dev, SYS_RES_IRQ,
408 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
411 bus_dma_tag_destroy(ctlr->dma_tag);
413 rman_fini(&ctlr->sc_iomem);
415 mtx_destroy(&ctlr->ch_mtx);
420 ahci_free_mem(device_t dev)
422 struct ahci_controller *ctlr = device_get_softc(dev);
424 /* Release memory resources */
426 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
427 if (ctlr->r_msix_table)
428 bus_release_resource(dev, SYS_RES_MEMORY,
429 ctlr->r_msix_tab_rid, ctlr->r_msix_table);
430 if (ctlr->r_msix_pba)
431 bus_release_resource(dev, SYS_RES_MEMORY,
432 ctlr->r_msix_pba_rid, ctlr->r_msix_pba);
434 ctlr->r_msix_pba = ctlr->r_mem = ctlr->r_msix_table = NULL;
438 ahci_setup_interrupt(device_t dev)
440 struct ahci_controller *ctlr = device_get_softc(dev);
443 /* Check for single MSI vector fallback. */
444 if (ctlr->numirqs > 1 &&
445 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
446 device_printf(dev, "Falling back to one MSI\n");
450 /* Ensure we don't overrun irqs. */
451 if (ctlr->numirqs > AHCI_MAX_IRQS) {
452 device_printf(dev, "Too many irqs %d > %d (clamping)\n",
453 ctlr->numirqs, AHCI_MAX_IRQS);
454 ctlr->numirqs = AHCI_MAX_IRQS;
457 /* Allocate all IRQs. */
458 for (i = 0; i < ctlr->numirqs; i++) {
459 ctlr->irqs[i].ctlr = ctlr;
460 ctlr->irqs[i].r_irq_rid = i + (ctlr->msi ? 1 : 0);
461 if (ctlr->channels == 1 && !ctlr->ccc && ctlr->msi)
462 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
463 else if (ctlr->numirqs == 1 || i >= ctlr->channels ||
464 (ctlr->ccc && i == ctlr->cccv))
465 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
466 else if (ctlr->channels > ctlr->numirqs &&
467 i == ctlr->numirqs - 1)
468 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
470 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
471 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
472 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
473 device_printf(dev, "unable to map interrupt\n");
476 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
477 (ctlr->irqs[i].mode != AHCI_IRQ_MODE_ONE) ? ahci_intr :
478 ((ctlr->quirks & AHCI_Q_EDGEIS) ? ahci_intr_one_edge :
480 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
481 /* SOS XXX release r_irq */
482 device_printf(dev, "unable to setup interrupt\n");
485 if (ctlr->numirqs > 1) {
486 bus_describe_intr(dev, ctlr->irqs[i].r_irq,
487 ctlr->irqs[i].handle,
488 ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
496 * Common case interrupt handler.
499 ahci_intr(void *data)
501 struct ahci_controller_irq *irq = data;
502 struct ahci_controller *ctlr = irq->ctlr;
503 u_int32_t is, ise = 0;
507 if (irq->mode == AHCI_IRQ_MODE_ALL) {
510 is = ctlr->ichannels;
512 is = ATA_INL(ctlr->r_mem, AHCI_IS);
513 } else { /* AHCI_IRQ_MODE_AFTER */
514 unit = irq->r_irq_rid - 1;
515 is = ATA_INL(ctlr->r_mem, AHCI_IS);
516 is &= (0xffffffff << unit);
518 /* CCC interrupt is edge triggered. */
520 ise = 1 << ctlr->cccv;
521 /* Some controllers have edge triggered IS. */
522 if (ctlr->quirks & AHCI_Q_EDGEIS)
525 ATA_OUTL(ctlr->r_mem, AHCI_IS, ise);
526 for (; unit < ctlr->channels; unit++) {
527 if ((is & (1 << unit)) != 0 &&
528 (arg = ctlr->interrupt[unit].argument)) {
529 ctlr->interrupt[unit].function(arg);
532 for (; unit < ctlr->channels + ctlr->remapped_devices; unit++) {
533 if ((arg = ctlr->interrupt[unit].argument)) {
534 ctlr->interrupt[unit].function(arg);
538 /* AHCI declares level triggered IS. */
539 if (!(ctlr->quirks & AHCI_Q_EDGEIS))
540 ATA_OUTL(ctlr->r_mem, AHCI_IS, is);
541 ATA_RBL(ctlr->r_mem, AHCI_IS);
545 * Simplified interrupt handler for multivector MSI mode.
548 ahci_intr_one(void *data)
550 struct ahci_controller_irq *irq = data;
551 struct ahci_controller *ctlr = irq->ctlr;
555 unit = irq->r_irq_rid - 1;
556 if ((arg = ctlr->interrupt[unit].argument))
557 ctlr->interrupt[unit].function(arg);
558 /* AHCI declares level triggered IS. */
559 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
560 ATA_RBL(ctlr->r_mem, AHCI_IS);
564 ahci_intr_one_edge(void *data)
566 struct ahci_controller_irq *irq = data;
567 struct ahci_controller *ctlr = irq->ctlr;
571 unit = irq->r_irq_rid - 1;
572 /* Some controllers have edge triggered IS. */
573 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
574 if ((arg = ctlr->interrupt[unit].argument))
575 ctlr->interrupt[unit].function(arg);
576 ATA_RBL(ctlr->r_mem, AHCI_IS);
580 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
581 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
583 struct ahci_controller *ctlr = device_get_softc(dev);
584 struct resource *res;
586 int offset, size, unit;
587 bool is_em, is_remapped;
589 unit = (intptr_t)device_get_ivars(child);
590 is_em = is_remapped = false;
591 if (unit & AHCI_REMAPPED_UNIT) {
593 unit -= ctlr->channels;
595 } else if (unit & AHCI_EM_UNIT) {
603 offset = ctlr->remap_offset + unit * ctlr->remap_size;
604 size = ctlr->remap_size;
606 offset = AHCI_OFFSET + (unit << 7);
608 } else if ((ctlr->caps & AHCI_CAP_EMS) == 0) {
610 } else if (*rid == 0) {
611 offset = AHCI_EM_CTL;
614 offset = (ctlr->emloc & 0xffff0000) >> 14;
615 size = (ctlr->emloc & 0x0000ffff) << 2;
617 if (*rid == 2 && (ctlr->capsem &
618 (AHCI_EM_XMT | AHCI_EM_SMB)) == 0)
624 st = rman_get_start(ctlr->r_mem);
625 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
626 st + offset + size - 1, size, RF_ACTIVE, child);
628 bus_space_handle_t bsh;
630 bsh = rman_get_bushandle(ctlr->r_mem);
631 bst = rman_get_bustag(ctlr->r_mem);
632 bus_space_subregion(bst, bsh, offset, 128, &bsh);
633 rman_set_bushandle(res, bsh);
634 rman_set_bustag(res, bst);
638 if (*rid == ATA_IRQ_RID)
639 res = ctlr->irqs[0].r_irq;
646 ahci_release_resource(device_t dev, device_t child, int type, int rid,
652 rman_release_resource(r);
655 if (rid != ATA_IRQ_RID)
663 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
664 int flags, driver_filter_t *filter, driver_intr_t *function,
665 void *argument, void **cookiep)
667 struct ahci_controller *ctlr = device_get_softc(dev);
668 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT;
670 if (filter != NULL) {
671 printf("ahci.c: we cannot use a filter here\n");
674 ctlr->interrupt[unit].function = function;
675 ctlr->interrupt[unit].argument = argument;
680 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
683 struct ahci_controller *ctlr = device_get_softc(dev);
684 int unit = (intptr_t)device_get_ivars(child) & AHCI_UNIT;
686 ctlr->interrupt[unit].function = NULL;
687 ctlr->interrupt[unit].argument = NULL;
692 ahci_print_child(device_t dev, device_t child)
697 retval = bus_print_child_header(dev, child);
698 ivars = (intptr_t)device_get_ivars(child);
699 if ((ivars & AHCI_EM_UNIT) == 0)
700 retval += printf(" at channel %d", (int)ivars & AHCI_UNIT);
701 retval += bus_print_child_footer(dev, child);
706 ahci_child_location(device_t dev, device_t child, struct sbuf *sb)
710 ivars = (intptr_t)device_get_ivars(child);
711 if ((ivars & AHCI_EM_UNIT) == 0)
712 sbuf_printf(sb, "channel=%d", (int)ivars & AHCI_UNIT);
717 ahci_get_dma_tag(device_t dev, device_t child)
719 struct ahci_controller *ctlr = device_get_softc(dev);
721 return (ctlr->dma_tag);
725 ahci_attached(device_t dev, struct ahci_channel *ch)
727 struct ahci_controller *ctlr = device_get_softc(dev);
729 mtx_lock(&ctlr->ch_mtx);
730 ctlr->ch[ch->unit] = ch;
731 mtx_unlock(&ctlr->ch_mtx);
735 ahci_detached(device_t dev, struct ahci_channel *ch)
737 struct ahci_controller *ctlr = device_get_softc(dev);
739 mtx_lock(&ctlr->ch_mtx);
741 ctlr->ch[ch->unit] = NULL;
742 mtx_unlock(&ch->mtx);
743 mtx_unlock(&ctlr->ch_mtx);
746 struct ahci_channel *
747 ahci_getch(device_t dev, int n)
749 struct ahci_controller *ctlr = device_get_softc(dev);
750 struct ahci_channel *ch;
752 KASSERT(n >= 0 && n < AHCI_MAX_PORTS, ("Bad channel number %d", n));
753 mtx_lock(&ctlr->ch_mtx);
757 mtx_unlock(&ctlr->ch_mtx);
762 ahci_putch(struct ahci_channel *ch)
765 mtx_unlock(&ch->mtx);
769 ahci_ch_probe(device_t dev)
772 device_set_desc_copy(dev, "AHCI channel");
773 return (BUS_PROBE_DEFAULT);
777 ahci_ch_disablephy_proc(SYSCTL_HANDLER_ARGS)
779 struct ahci_channel *ch;
783 value = ch->disablephy;
784 error = sysctl_handle_int(oidp, &value, 0, req);
785 if (error != 0 || req->newptr == NULL || (value != 0 && value != 1))
789 ch->disablephy = value;
791 ahci_ch_deinit(ch->dev);
793 ahci_ch_init(ch->dev);
794 ahci_phy_check_events(ch, ATA_SE_PHY_CHANGED | ATA_SE_EXCHANGED);
796 mtx_unlock(&ch->mtx);
802 ahci_ch_attach(device_t dev)
804 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
805 struct ahci_channel *ch = device_get_softc(dev);
806 struct cam_devq *devq;
807 struct sysctl_ctx_list *ctx;
808 struct sysctl_oid *tree;
809 int rid, error, i, sata_rev = 0;
813 ch->unit = (intptr_t)device_get_ivars(dev);
814 ch->caps = ctlr->caps;
815 ch->caps2 = ctlr->caps2;
816 ch->start = ctlr->ch_start;
817 ch->quirks = ctlr->quirks;
818 ch->vendorid = ctlr->vendorid;
819 ch->deviceid = ctlr->deviceid;
820 ch->subvendorid = ctlr->subvendorid;
821 ch->subdeviceid = ctlr->subdeviceid;
822 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1;
823 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
825 resource_int_value(device_get_name(dev),
826 device_get_unit(dev), "pm_level", &ch->pm_level);
827 STAILQ_INIT(&ch->doneq);
828 if (ch->pm_level > 3)
829 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
830 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
831 /* JMicron external ports (0) sometimes limited */
832 if ((ctlr->quirks & AHCI_Q_SATA1_UNIT0) && ch->unit == 0)
834 if (ch->quirks & AHCI_Q_SATA2)
836 resource_int_value(device_get_name(dev),
837 device_get_unit(dev), "sata_rev", &sata_rev);
838 for (i = 0; i < 16; i++) {
839 ch->user[i].revision = sata_rev;
840 ch->user[i].mode = 0;
841 ch->user[i].bytecount = 8192;
842 ch->user[i].tags = ch->numslots;
843 ch->user[i].caps = 0;
844 ch->curr[i] = ch->user[i];
846 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
847 CTS_SATA_CAPS_H_APST |
848 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
850 ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA |
854 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
857 ch->chcaps = ATA_INL(ch->r_mem, AHCI_P_CMD);
858 version = ATA_INL(ctlr->r_mem, AHCI_VS);
859 if (version < 0x00010200 && (ctlr->caps & AHCI_CAP_FBSS))
860 ch->chcaps |= AHCI_P_CMD_FBSCP;
861 if (ch->caps2 & AHCI_CAP2_SDS)
862 ch->chscaps = ATA_INL(ch->r_mem, AHCI_P_DEVSLP);
864 device_printf(dev, "Caps:%s%s%s%s%s%s\n",
865 (ch->chcaps & AHCI_P_CMD_HPCP) ? " HPCP":"",
866 (ch->chcaps & AHCI_P_CMD_MPSP) ? " MPSP":"",
867 (ch->chcaps & AHCI_P_CMD_CPD) ? " CPD":"",
868 (ch->chcaps & AHCI_P_CMD_ESP) ? " ESP":"",
869 (ch->chcaps & AHCI_P_CMD_FBSCP) ? " FBSCP":"",
870 (ch->chscaps & AHCI_P_DEVSLP_DSP) ? " DSP":"");
873 ahci_slotsalloc(dev);
877 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
878 &rid, RF_SHAREABLE | RF_ACTIVE))) {
879 device_printf(dev, "Unable to map interrupt\n");
883 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
884 ctlr->direct ? ahci_ch_intr_direct : ahci_ch_intr,
886 device_printf(dev, "Unable to setup interrupt\n");
890 /* Create the device queue for our SIM. */
891 devq = cam_simq_alloc(ch->numslots);
893 device_printf(dev, "Unable to allocate simq\n");
897 /* Construct SIM entry */
898 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
899 device_get_unit(dev), (struct mtx *)&ch->mtx,
900 (ch->quirks & AHCI_Q_NOCCS) ? 1 : min(2, ch->numslots),
901 (ch->caps & AHCI_CAP_SNCQ) ? ch->numslots : 0,
903 if (ch->sim == NULL) {
905 device_printf(dev, "unable to allocate sim\n");
909 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
910 device_printf(dev, "unable to register xpt bus\n");
914 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
915 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
916 device_printf(dev, "unable to create path\n");
920 if (ch->pm_level > 3) {
921 callout_reset(&ch->pm_timer,
922 (ch->pm_level == 4) ? hz / 1000 : hz / 8,
925 mtx_unlock(&ch->mtx);
926 ahci_attached(device_get_parent(dev), ch);
927 ctx = device_get_sysctl_ctx(dev);
928 tree = device_get_sysctl_tree(dev);
929 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "disable_phy",
930 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, ch,
931 0, ahci_ch_disablephy_proc, "IU", "Disable PHY");
935 xpt_bus_deregister(cam_sim_path(ch->sim));
937 cam_sim_free(ch->sim, /*free_devq*/TRUE);
939 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
941 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
942 mtx_unlock(&ch->mtx);
943 mtx_destroy(&ch->mtx);
948 ahci_ch_detach(device_t dev)
950 struct ahci_channel *ch = device_get_softc(dev);
952 ahci_detached(device_get_parent(dev), ch);
954 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
955 /* Forget about reset. */
958 xpt_release_simq(ch->sim, TRUE);
960 xpt_free_path(ch->path);
961 xpt_bus_deregister(cam_sim_path(ch->sim));
962 cam_sim_free(ch->sim, /*free_devq*/TRUE);
963 mtx_unlock(&ch->mtx);
965 if (ch->pm_level > 3)
966 callout_drain(&ch->pm_timer);
967 callout_drain(&ch->reset_timer);
968 bus_teardown_intr(dev, ch->r_irq, ch->ih);
969 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
975 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
976 mtx_destroy(&ch->mtx);
981 ahci_ch_init(device_t dev)
983 struct ahci_channel *ch = device_get_softc(dev);
986 /* Disable port interrupts */
987 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
988 /* Setup work areas */
989 work = ch->dma.work_bus + AHCI_CL_OFFSET;
990 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
991 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
992 work = ch->dma.rfis_bus;
993 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
994 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
995 /* Activate the channel and power/spin up device */
996 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
997 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
998 ((ch->pm_level == 2 || ch->pm_level == 3) ? AHCI_P_CMD_ALPE : 0) |
999 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
1006 ahci_ch_deinit(device_t dev)
1008 struct ahci_channel *ch = device_get_softc(dev);
1010 /* Disable port interrupts. */
1011 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1012 /* Reset command register. */
1015 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
1016 /* Allow everything, including partial and slumber modes. */
1017 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
1018 /* Request slumber mode transition and give some time to get there. */
1019 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
1022 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
1027 ahci_ch_suspend(device_t dev)
1029 struct ahci_channel *ch = device_get_softc(dev);
1032 xpt_freeze_simq(ch->sim, 1);
1033 /* Forget about reset. */
1034 if (ch->resetting) {
1036 callout_stop(&ch->reset_timer);
1037 xpt_release_simq(ch->sim, TRUE);
1040 msleep(ch, &ch->mtx, PRIBIO, "ahcisusp", hz/100);
1041 ahci_ch_deinit(dev);
1042 mtx_unlock(&ch->mtx);
1047 ahci_ch_resume(device_t dev)
1049 struct ahci_channel *ch = device_get_softc(dev);
1054 xpt_release_simq(ch->sim, TRUE);
1055 mtx_unlock(&ch->mtx);
1059 devclass_t ahcich_devclass;
1060 static device_method_t ahcich_methods[] = {
1061 DEVMETHOD(device_probe, ahci_ch_probe),
1062 DEVMETHOD(device_attach, ahci_ch_attach),
1063 DEVMETHOD(device_detach, ahci_ch_detach),
1064 DEVMETHOD(device_suspend, ahci_ch_suspend),
1065 DEVMETHOD(device_resume, ahci_ch_resume),
1068 static driver_t ahcich_driver = {
1071 sizeof(struct ahci_channel)
1073 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahcich_devclass, NULL, NULL);
1075 struct ahci_dc_cb_args {
1081 ahci_dmainit(device_t dev)
1083 struct ahci_channel *ch = device_get_softc(dev);
1084 struct ahci_dc_cb_args dcba;
1089 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
1090 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1091 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
1092 0, NULL, NULL, &ch->dma.work_tag);
1095 error = bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work,
1096 BUS_DMA_ZERO, &ch->dma.work_map);
1099 error = bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
1100 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT);
1101 if (error != 0 || (error = dcba.error) != 0) {
1102 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1105 ch->dma.work_bus = dcba.maddr;
1106 /* FIS receive area. */
1107 if (ch->chcaps & AHCI_P_CMD_FBSCP)
1111 error = bus_dma_tag_create(bus_get_dma_tag(dev), rfsize, 0,
1112 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1113 NULL, NULL, rfsize, 1, rfsize,
1114 0, NULL, NULL, &ch->dma.rfis_tag);
1117 error = bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
1121 error = bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
1122 rfsize, ahci_dmasetupc_cb, &dcba, BUS_DMA_NOWAIT);
1123 if (error != 0 || (error = dcba.error) != 0) {
1124 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1127 ch->dma.rfis_bus = dcba.maddr;
1129 error = bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
1130 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1132 AHCI_SG_ENTRIES * PAGE_SIZE, AHCI_SG_ENTRIES, AHCI_PRD_MAX,
1133 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag);
1139 device_printf(dev, "WARNING - DMA initialization failed, error %d\n",
1145 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
1147 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
1149 if (!(dcba->error = error))
1150 dcba->maddr = segs[0].ds_addr;
1154 ahci_dmafini(device_t dev)
1156 struct ahci_channel *ch = device_get_softc(dev);
1158 if (ch->dma.data_tag) {
1159 bus_dma_tag_destroy(ch->dma.data_tag);
1160 ch->dma.data_tag = NULL;
1162 if (ch->dma.rfis_bus) {
1163 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
1164 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
1165 ch->dma.rfis_bus = 0;
1166 ch->dma.rfis = NULL;
1168 if (ch->dma.work_bus) {
1169 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
1170 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
1171 ch->dma.work_bus = 0;
1172 ch->dma.work = NULL;
1174 if (ch->dma.work_tag) {
1175 bus_dma_tag_destroy(ch->dma.work_tag);
1176 ch->dma.work_tag = NULL;
1181 ahci_slotsalloc(device_t dev)
1183 struct ahci_channel *ch = device_get_softc(dev);
1186 /* Alloc and setup command/dma slots */
1187 bzero(ch->slot, sizeof(ch->slot));
1188 for (i = 0; i < ch->numslots; i++) {
1189 struct ahci_slot *slot = &ch->slot[i];
1193 slot->state = AHCI_SLOT_EMPTY;
1194 slot->ct_offset = AHCI_CT_OFFSET + AHCI_CT_SIZE * i;
1196 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
1198 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
1199 device_printf(ch->dev, "FAILURE - create data_map\n");
1204 ahci_slotsfree(device_t dev)
1206 struct ahci_channel *ch = device_get_softc(dev);
1209 /* Free all dma slots */
1210 for (i = 0; i < ch->numslots; i++) {
1211 struct ahci_slot *slot = &ch->slot[i];
1213 callout_drain(&slot->timeout);
1214 if (slot->dma.data_map) {
1215 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
1216 slot->dma.data_map = NULL;
1222 ahci_phy_check_events(struct ahci_channel *ch, u_int32_t serr)
1225 if (((ch->pm_level == 0) && (serr & ATA_SE_PHY_CHANGED)) ||
1226 ((ch->pm_level != 0 || ch->listening) && (serr & ATA_SE_EXCHANGED))) {
1227 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1231 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
1232 device_printf(ch->dev, "CONNECT requested\n");
1234 device_printf(ch->dev, "DISCONNECT requested\n");
1237 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1239 if (xpt_create_path(&ccb->ccb_h.path, NULL,
1240 cam_sim_path(ch->sim),
1241 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1252 ahci_cpd_check_events(struct ahci_channel *ch)
1258 if (ch->pm_level == 0)
1261 status = ATA_INL(ch->r_mem, AHCI_P_CMD);
1262 if ((status & AHCI_P_CMD_CPD) == 0)
1267 if (status & AHCI_P_CMD_CPS) {
1268 device_printf(dev, "COLD CONNECT requested\n");
1270 device_printf(dev, "COLD DISCONNECT requested\n");
1273 if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
1275 if (xpt_create_path(&ccb->ccb_h.path, NULL, cam_sim_path(ch->sim),
1276 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
1284 ahci_notify_events(struct ahci_channel *ch, u_int32_t status)
1286 struct cam_path *dpath;
1289 if (ch->caps & AHCI_CAP_SSNTF)
1290 ATA_OUTL(ch->r_mem, AHCI_P_SNTF, status);
1292 device_printf(ch->dev, "SNTF 0x%04x\n", status);
1293 for (i = 0; i < 16; i++) {
1294 if ((status & (1 << i)) == 0)
1296 if (xpt_create_path(&dpath, NULL,
1297 xpt_path_path_id(ch->path), i, 0) == CAM_REQ_CMP) {
1298 xpt_async(AC_SCSI_AEN, dpath, NULL);
1299 xpt_free_path(dpath);
1305 ahci_done(struct ahci_channel *ch, union ccb *ccb)
1308 mtx_assert(&ch->mtx, MA_OWNED);
1309 if ((ccb->ccb_h.func_code & XPT_FC_QUEUED) == 0 ||
1315 STAILQ_INSERT_TAIL(&ch->doneq, &ccb->ccb_h, sim_links.stqe);
1319 ahci_ch_intr(void *arg)
1321 struct ahci_channel *ch = (struct ahci_channel *)arg;
1324 /* Read interrupt statuses. */
1325 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1328 ahci_ch_intr_main(ch, istatus);
1329 mtx_unlock(&ch->mtx);
1333 ahci_ch_intr_direct(void *arg)
1335 struct ahci_channel *ch = (struct ahci_channel *)arg;
1336 struct ccb_hdr *ccb_h;
1338 STAILQ_HEAD(, ccb_hdr) tmp_doneq = STAILQ_HEAD_INITIALIZER(tmp_doneq);
1340 /* Read interrupt statuses. */
1341 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
1345 ahci_ch_intr_main(ch, istatus);
1348 * Prevent the possibility of issues caused by processing the queue
1349 * while unlocked below by moving the contents to a local queue.
1351 STAILQ_CONCAT(&tmp_doneq, &ch->doneq);
1352 mtx_unlock(&ch->mtx);
1353 while ((ccb_h = STAILQ_FIRST(&tmp_doneq)) != NULL) {
1354 STAILQ_REMOVE_HEAD(&tmp_doneq, sim_links.stqe);
1355 xpt_done_direct((union ccb *)ccb_h);
1360 ahci_ch_pm(void *arg)
1362 struct ahci_channel *ch = (struct ahci_channel *)arg;
1365 if (ch->numrslots != 0)
1367 work = ATA_INL(ch->r_mem, AHCI_P_CMD);
1368 if (ch->pm_level == 4)
1369 work |= AHCI_P_CMD_PARTIAL;
1371 work |= AHCI_P_CMD_SLUMBER;
1372 ATA_OUTL(ch->r_mem, AHCI_P_CMD, work);
1376 ahci_ch_intr_main(struct ahci_channel *ch, uint32_t istatus)
1378 uint32_t cstatus, serr = 0, sntf = 0, ok, err;
1379 enum ahci_err_type et;
1380 int i, ccs, port, reset = 0;
1382 /* Clear interrupt statuses. */
1383 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
1384 /* Read command statuses. */
1385 if (ch->numtslots != 0)
1386 cstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1389 if (ch->numrslots != ch->numtslots)
1390 cstatus |= ATA_INL(ch->r_mem, AHCI_P_CI);
1391 /* Read SNTF in one of possible ways. */
1392 if ((istatus & AHCI_P_IX_SDB) &&
1393 (ch->pm_present || ch->curr[0].atapi != 0)) {
1394 if (ch->caps & AHCI_CAP_SSNTF)
1395 sntf = ATA_INL(ch->r_mem, AHCI_P_SNTF);
1396 else if (ch->fbs_enabled) {
1397 u_int8_t *fis = ch->dma.rfis + 0x58;
1399 for (i = 0; i < 16; i++) {
1400 if (fis[1] & 0x80) {
1407 u_int8_t *fis = ch->dma.rfis + 0x58;
1410 sntf = (1 << (fis[1] & 0x0f));
1413 /* Process PHY events */
1414 if (istatus & (AHCI_P_IX_PC | AHCI_P_IX_PRC | AHCI_P_IX_OF |
1415 AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1416 serr = ATA_INL(ch->r_mem, AHCI_P_SERR);
1418 ATA_OUTL(ch->r_mem, AHCI_P_SERR, serr);
1419 reset = ahci_phy_check_events(ch, serr);
1422 /* Process cold presence detection events */
1423 if ((istatus & AHCI_P_IX_CPD) && !reset)
1424 ahci_cpd_check_events(ch);
1425 /* Process command errors */
1426 if (istatus & (AHCI_P_IX_OF | AHCI_P_IX_IF |
1427 AHCI_P_IX_HBD | AHCI_P_IX_HBF | AHCI_P_IX_TFE)) {
1428 if (ch->quirks & AHCI_Q_NOCCS) {
1430 * ASMedia chips sometimes report failed commands as
1431 * completed. Count all running commands as failed.
1433 cstatus |= ch->rslots;
1435 /* They also report wrong CCS, so try to guess one. */
1436 ccs = powerof2(cstatus) ? ffs(cstatus) - 1 : -1;
1438 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) &
1439 AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT;
1441 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x fbs %08x ccs %d\n",
1442 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
1443 // serr, ATA_INL(ch->r_mem, AHCI_P_FBS), ccs);
1445 if (ch->fbs_enabled) {
1446 uint32_t fbs = ATA_INL(ch->r_mem, AHCI_P_FBS);
1447 if (fbs & AHCI_P_FBS_SDE) {
1448 port = (fbs & AHCI_P_FBS_DWE)
1449 >> AHCI_P_FBS_DWE_SHIFT;
1451 for (i = 0; i < 16; i++) {
1452 if (ch->numrslotspd[i] == 0)
1456 else if (port != i) {
1463 err = ch->rslots & cstatus;
1469 /* Complete all successful commands. */
1470 ok = ch->rslots & ~cstatus;
1471 for (i = 0; i < ch->numslots; i++) {
1473 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
1475 /* On error, complete the rest of commands with error statuses. */
1478 union ccb *fccb = ch->frozen;
1480 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1481 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1482 xpt_freeze_devq(fccb->ccb_h.path, 1);
1483 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1485 ahci_done(ch, fccb);
1487 for (i = 0; i < ch->numslots; i++) {
1488 /* XXX: reqests in loading state. */
1489 if (((err >> i) & 1) == 0)
1492 ch->slot[i].ccb->ccb_h.target_id != port)
1494 if (istatus & AHCI_P_IX_TFE) {
1496 /* Task File Error */
1497 if (ch->numtslotspd[
1498 ch->slot[i].ccb->ccb_h.target_id] == 0) {
1499 /* Untagged operation. */
1503 et = AHCI_ERR_INNOCENT;
1505 /* Tagged operation. */
1512 } else if (istatus & AHCI_P_IX_IF) {
1513 if (ch->numtslots == 0 && i != ccs && port != -2)
1514 et = AHCI_ERR_INNOCENT;
1518 et = AHCI_ERR_INVALID;
1519 ahci_end_transaction(&ch->slot[i], et);
1522 * We can't reinit port if there are some other
1523 * commands active, use resume to complete them.
1525 if (ch->rslots != 0 && !ch->recoverycmd)
1526 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN | AHCI_P_FBS_DEC);
1528 /* Process NOTIFY events */
1530 ahci_notify_events(ch, sntf);
1533 /* Must be called with channel locked. */
1535 ahci_check_collision(struct ahci_channel *ch, union ccb *ccb)
1537 int t = ccb->ccb_h.target_id;
1539 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1540 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1541 /* Tagged command while we have no supported tag free. */
1542 if (((~ch->oslots) & (0xffffffff >> (32 -
1543 ch->curr[t].tags))) == 0)
1545 /* If we have FBS */
1546 if (ch->fbs_enabled) {
1547 /* Tagged command while untagged are active. */
1548 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] == 0)
1551 /* Tagged command while untagged are active. */
1552 if (ch->numrslots != 0 && ch->numtslots == 0)
1554 /* Tagged command while tagged to other target is active. */
1555 if (ch->numtslots != 0 &&
1556 ch->taggedtarget != ccb->ccb_h.target_id)
1560 /* If we have FBS */
1561 if (ch->fbs_enabled) {
1562 /* Untagged command while tagged are active. */
1563 if (ch->numrslotspd[t] != 0 && ch->numtslotspd[t] != 0)
1566 /* Untagged command while tagged are active. */
1567 if (ch->numrslots != 0 && ch->numtslots != 0)
1571 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1572 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
1573 /* Atomic command while anything active. */
1574 if (ch->numrslots != 0)
1577 /* We have some atomic command running. */
1578 if (ch->aslots != 0)
1583 /* Must be called with channel locked. */
1585 ahci_begin_transaction(struct ahci_channel *ch, union ccb *ccb)
1587 struct ahci_slot *slot;
1590 /* Choose empty slot. */
1591 tags = ch->numslots;
1592 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1593 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA))
1594 tags = ch->curr[ccb->ccb_h.target_id].tags;
1595 if (ch->lastslot + 1 < tags)
1596 tag = ffs(~(ch->oslots >> (ch->lastslot + 1)));
1599 if (tag == 0 || tag + ch->lastslot >= tags)
1600 tag = ffs(~ch->oslots) - 1;
1602 tag += ch->lastslot;
1604 /* Occupy chosen slot. */
1605 slot = &ch->slot[tag];
1607 /* Stop PM timer. */
1608 if (ch->numrslots == 0 && ch->pm_level > 3)
1609 callout_stop(&ch->pm_timer);
1610 /* Update channel stats. */
1611 ch->oslots |= (1 << tag);
1613 ch->numrslotspd[ccb->ccb_h.target_id]++;
1614 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1615 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1617 ch->numtslotspd[ccb->ccb_h.target_id]++;
1618 ch->taggedtarget = ccb->ccb_h.target_id;
1620 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1621 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1622 ch->aslots |= (1 << tag);
1623 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1624 slot->state = AHCI_SLOT_LOADING;
1625 bus_dmamap_load_ccb(ch->dma.data_tag, slot->dma.data_map, ccb,
1626 ahci_dmasetprd, slot, 0);
1628 slot->dma.nsegs = 0;
1629 ahci_execute_transaction(slot);
1633 /* Locked by busdma engine. */
1635 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1637 struct ahci_slot *slot = arg;
1638 struct ahci_channel *ch = slot->ch;
1639 struct ahci_cmd_tab *ctp;
1640 struct ahci_dma_prd *prd;
1644 device_printf(ch->dev, "DMA load error\n");
1645 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1648 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1649 /* Get a piece of the workspace for this request */
1650 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset);
1651 /* Fill S/G table */
1652 prd = &ctp->prd_tab[0];
1653 for (i = 0; i < nsegs; i++) {
1654 prd[i].dba = htole64(segs[i].ds_addr);
1655 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1657 slot->dma.nsegs = nsegs;
1658 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1659 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1660 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1661 ahci_execute_transaction(slot);
1664 /* Must be called with channel locked. */
1666 ahci_execute_transaction(struct ahci_slot *slot)
1668 struct ahci_channel *ch = slot->ch;
1669 struct ahci_cmd_tab *ctp;
1670 struct ahci_cmd_list *clp;
1671 union ccb *ccb = slot->ccb;
1672 int port = ccb->ccb_h.target_id & 0x0f;
1673 int fis_size, i, softreset;
1674 uint8_t *fis = ch->dma.rfis + 0x40;
1678 /* Get a piece of the workspace for this request */
1679 ctp = (struct ahci_cmd_tab *)(ch->dma.work + slot->ct_offset);
1680 /* Setup the FIS for this request */
1681 if (!(fis_size = ahci_setup_fis(ch, ctp, ccb, slot->slot))) {
1682 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1683 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1686 /* Setup the command list entry */
1687 clp = (struct ahci_cmd_list *)
1688 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1690 (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1691 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1692 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1693 (fis_size / sizeof(u_int32_t)) |
1695 clp->prd_length = htole16(slot->dma.nsegs);
1696 /* Special handling for Soft Reset command. */
1697 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1698 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1699 if (ccb->ataio.cmd.control & ATA_A_RESET) {
1701 /* Kick controller into sane state */
1705 cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1708 /* Prepare FIS receive area for check. */
1709 for (i = 0; i < 20; i++)
1715 clp->cmd_flags = htole16(cmd_flags);
1716 clp->cmd_table_phys = htole64(ch->dma.work_bus + slot->ct_offset);
1717 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1718 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1719 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1720 BUS_DMASYNC_PREREAD);
1721 /* Set ACTIVE bit for NCQ commands. */
1722 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1723 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1724 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1726 /* If FBS is enabled, set PMP port. */
1727 if (ch->fbs_enabled) {
1728 ATA_OUTL(ch->r_mem, AHCI_P_FBS, AHCI_P_FBS_EN |
1729 (port << AHCI_P_FBS_DEV_SHIFT));
1731 /* Issue command to the controller. */
1732 slot->state = AHCI_SLOT_RUNNING;
1733 ch->rslots |= (1 << slot->slot);
1734 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1735 /* Device reset commands doesn't interrupt. Poll them. */
1736 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1737 (ccb->ataio.cmd.command == ATA_DEVICE_RESET || softreset)) {
1738 int count, timeout = ccb->ccb_h.timeout * 100;
1739 enum ahci_err_type et = AHCI_ERR_NONE;
1741 for (count = 0; count < timeout; count++) {
1743 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1745 if ((ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) &&
1748 device_printf(ch->dev,
1749 "Poll error on slot %d, TFD: %04x\n",
1750 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1755 /* Workaround for ATI SB600/SB700 chipsets. */
1756 if (ccb->ccb_h.target_id == 15 &&
1757 (ch->quirks & AHCI_Q_ATI_PMP_BUG) &&
1758 (ATA_INL(ch->r_mem, AHCI_P_IS) & AHCI_P_IX_IPM)) {
1759 et = AHCI_ERR_TIMEOUT;
1765 * Some Marvell controllers require additional time
1766 * after soft reset to work properly. Setup delay
1767 * to 50ms after soft reset.
1769 if (ch->quirks & AHCI_Q_MRVL_SR_DEL)
1773 * Marvell HBAs with non-RAID firmware do not wait for
1774 * readiness after soft reset, so we have to wait here.
1775 * Marvell RAIDs do not have this problem, but instead
1776 * sometimes forget to update FIS receive area, breaking
1779 if ((ch->quirks & AHCI_Q_NOBSYRES) == 0 &&
1780 (ch->quirks & AHCI_Q_ATI_PMP_BUG) == 0 &&
1781 softreset == 2 && et == AHCI_ERR_NONE) {
1782 for ( ; count < timeout; count++) {
1783 bus_dmamap_sync(ch->dma.rfis_tag,
1784 ch->dma.rfis_map, BUS_DMASYNC_POSTREAD);
1786 bus_dmamap_sync(ch->dma.rfis_tag,
1787 ch->dma.rfis_map, BUS_DMASYNC_PREREAD);
1788 if ((val & ATA_S_BUSY) == 0)
1794 if (timeout && (count >= timeout)) {
1795 device_printf(ch->dev, "Poll timeout on slot %d port %d\n",
1797 device_printf(ch->dev, "is %08x cs %08x ss %08x "
1798 "rs %08x tfd %02x serr %08x cmd %08x\n",
1799 ATA_INL(ch->r_mem, AHCI_P_IS),
1800 ATA_INL(ch->r_mem, AHCI_P_CI),
1801 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1802 ATA_INL(ch->r_mem, AHCI_P_TFD),
1803 ATA_INL(ch->r_mem, AHCI_P_SERR),
1804 ATA_INL(ch->r_mem, AHCI_P_CMD));
1805 et = AHCI_ERR_TIMEOUT;
1808 /* Kick controller into sane state and enable FBS. */
1810 ch->eslots |= (1 << slot->slot);
1811 ahci_end_transaction(slot, et);
1814 /* Start command execution timeout */
1815 callout_reset_sbt(&slot->timeout, SBT_1MS * ccb->ccb_h.timeout / 2,
1816 0, ahci_timeout, slot, 0);
1820 /* Must be called with channel locked. */
1822 ahci_process_timeout(struct ahci_channel *ch)
1826 mtx_assert(&ch->mtx, MA_OWNED);
1827 /* Handle the rest of commands. */
1828 for (i = 0; i < ch->numslots; i++) {
1829 /* Do we have a running request on slot? */
1830 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1832 ahci_end_transaction(&ch->slot[i], AHCI_ERR_TIMEOUT);
1836 /* Must be called with channel locked. */
1838 ahci_rearm_timeout(struct ahci_channel *ch)
1842 mtx_assert(&ch->mtx, MA_OWNED);
1843 for (i = 0; i < ch->numslots; i++) {
1844 struct ahci_slot *slot = &ch->slot[i];
1846 /* Do we have a running request on slot? */
1847 if (slot->state < AHCI_SLOT_RUNNING)
1849 if ((ch->toslots & (1 << i)) == 0)
1851 callout_reset_sbt(&slot->timeout,
1852 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1853 ahci_timeout, slot, 0);
1857 /* Locked by callout mechanism. */
1859 ahci_timeout(void *arg)
1861 struct ahci_slot *slot = arg;
1862 struct ahci_channel *ch = slot->ch;
1863 device_t dev = ch->dev;
1868 /* Check for stale timeout. */
1869 if (slot->state < AHCI_SLOT_RUNNING)
1872 /* Check if slot was not being executed last time we checked. */
1873 if (slot->state < AHCI_SLOT_EXECUTING) {
1874 /* Check if slot started executing. */
1875 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
1876 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
1877 >> AHCI_P_CMD_CCS_SHIFT;
1878 if ((sstatus & (1 << slot->slot)) != 0 || ccs == slot->slot ||
1879 ch->fbs_enabled || ch->wrongccs)
1880 slot->state = AHCI_SLOT_EXECUTING;
1881 else if ((ch->rslots & (1 << ccs)) == 0) {
1883 slot->state = AHCI_SLOT_EXECUTING;
1886 callout_reset_sbt(&slot->timeout,
1887 SBT_1MS * slot->ccb->ccb_h.timeout / 2, 0,
1888 ahci_timeout, slot, 0);
1892 device_printf(dev, "Timeout on slot %d port %d\n",
1893 slot->slot, slot->ccb->ccb_h.target_id & 0x0f);
1894 device_printf(dev, "is %08x cs %08x ss %08x rs %08x tfd %02x "
1895 "serr %08x cmd %08x\n",
1896 ATA_INL(ch->r_mem, AHCI_P_IS), ATA_INL(ch->r_mem, AHCI_P_CI),
1897 ATA_INL(ch->r_mem, AHCI_P_SACT), ch->rslots,
1898 ATA_INL(ch->r_mem, AHCI_P_TFD), ATA_INL(ch->r_mem, AHCI_P_SERR),
1899 ATA_INL(ch->r_mem, AHCI_P_CMD));
1901 /* Handle frozen command. */
1903 union ccb *fccb = ch->frozen;
1905 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1906 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1907 xpt_freeze_devq(fccb->ccb_h.path, 1);
1908 fccb->ccb_h.status |= CAM_DEV_QFRZN;
1910 ahci_done(ch, fccb);
1912 if (!ch->fbs_enabled && !ch->wrongccs) {
1913 /* Without FBS we know real timeout source. */
1915 /* Handle command with timeout. */
1916 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1917 /* Handle the rest of commands. */
1918 for (i = 0; i < ch->numslots; i++) {
1919 /* Do we have a running request on slot? */
1920 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1922 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1925 /* With FBS we wait for other commands timeout and pray. */
1926 if (ch->toslots == 0)
1927 xpt_freeze_simq(ch->sim, 1);
1928 ch->toslots |= (1 << slot->slot);
1929 if ((ch->rslots & ~ch->toslots) == 0)
1930 ahci_process_timeout(ch);
1932 device_printf(dev, " ... waiting for slots %08x\n",
1933 ch->rslots & ~ch->toslots);
1937 /* Must be called with channel locked. */
1939 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1941 struct ahci_channel *ch = slot->ch;
1942 union ccb *ccb = slot->ccb;
1943 struct ahci_cmd_list *clp;
1947 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1948 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1949 clp = (struct ahci_cmd_list *)
1950 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1951 /* Read result registers to the result struct
1952 * May be incorrect if several commands finished same time,
1953 * so read only when sure or have to.
1955 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1956 struct ata_res *res = &ccb->ataio.res;
1958 if ((et == AHCI_ERR_TFE) ||
1959 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1960 u_int8_t *fis = ch->dma.rfis + 0x40;
1962 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1963 BUS_DMASYNC_POSTREAD);
1964 if (ch->fbs_enabled) {
1965 fis += ccb->ccb_h.target_id * 256;
1966 res->status = fis[2];
1967 res->error = fis[3];
1969 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1972 res->error = tfd >> 8;
1974 res->lba_low = fis[4];
1975 res->lba_mid = fis[5];
1976 res->lba_high = fis[6];
1977 res->device = fis[7];
1978 res->lba_low_exp = fis[8];
1979 res->lba_mid_exp = fis[9];
1980 res->lba_high_exp = fis[10];
1981 res->sector_count = fis[12];
1982 res->sector_count_exp = fis[13];
1985 * Some weird controllers do not return signature in
1986 * FIS receive area. Read it from PxSIG register.
1988 if ((ch->quirks & AHCI_Q_ALTSIG) &&
1989 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1990 (ccb->ataio.cmd.control & ATA_A_RESET) == 0) {
1991 sig = ATA_INL(ch->r_mem, AHCI_P_SIG);
1992 res->lba_high = sig >> 24;
1993 res->lba_mid = sig >> 16;
1994 res->lba_low = sig >> 8;
1995 res->sector_count = sig;
1998 bzero(res, sizeof(*res));
1999 if ((ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) == 0 &&
2000 (ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2001 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2003 ccb->ataio.dxfer_len - le32toh(clp->bytecount);
2006 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2007 (ch->quirks & AHCI_Q_NOCOUNT) == 0) {
2009 ccb->csio.dxfer_len - le32toh(clp->bytecount);
2012 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
2013 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
2014 (ccb->ccb_h.flags & CAM_DIR_IN) ?
2015 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
2016 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
2018 if (et != AHCI_ERR_NONE)
2019 ch->eslots |= (1 << slot->slot);
2020 /* In case of error, freeze device for proper recovery. */
2021 if ((et != AHCI_ERR_NONE) && (!ch->recoverycmd) &&
2022 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
2023 xpt_freeze_devq(ccb->ccb_h.path, 1);
2024 ccb->ccb_h.status |= CAM_DEV_QFRZN;
2026 /* Set proper result status. */
2027 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2030 ccb->ccb_h.status |= CAM_REQ_CMP;
2031 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
2032 ccb->csio.scsi_status = SCSI_STATUS_OK;
2034 case AHCI_ERR_INVALID:
2036 ccb->ccb_h.status |= CAM_REQ_INVALID;
2038 case AHCI_ERR_INNOCENT:
2039 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
2043 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2044 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2045 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2047 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2052 if (!ch->recoverycmd) {
2053 xpt_freeze_simq(ch->sim, 1);
2054 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2055 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2057 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
2059 case AHCI_ERR_TIMEOUT:
2060 if (!ch->recoverycmd) {
2061 xpt_freeze_simq(ch->sim, 1);
2062 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2063 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2065 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2069 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
2072 ch->oslots &= ~(1 << slot->slot);
2073 ch->rslots &= ~(1 << slot->slot);
2074 ch->aslots &= ~(1 << slot->slot);
2075 slot->state = AHCI_SLOT_EMPTY;
2077 /* Update channel stats. */
2079 ch->numrslotspd[ccb->ccb_h.target_id]--;
2080 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2081 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
2083 ch->numtslotspd[ccb->ccb_h.target_id]--;
2085 /* Cancel timeout state if request completed normally. */
2086 if (et != AHCI_ERR_TIMEOUT) {
2087 lastto = (ch->toslots == (1 << slot->slot));
2088 ch->toslots &= ~(1 << slot->slot);
2090 xpt_release_simq(ch->sim, TRUE);
2092 /* If it was first request of reset sequence and there is no error,
2093 * proceed to second request. */
2094 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
2095 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
2096 (ccb->ataio.cmd.control & ATA_A_RESET) &&
2097 et == AHCI_ERR_NONE) {
2098 ccb->ataio.cmd.control &= ~ATA_A_RESET;
2099 ahci_begin_transaction(ch, ccb);
2102 /* If it was our READ LOG command - process it. */
2103 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
2104 ahci_process_read_log(ch, ccb);
2105 /* If it was our REQUEST SENSE command - process it. */
2106 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
2107 ahci_process_request_sense(ch, ccb);
2108 /* If it was NCQ or ATAPI command error, put result on hold. */
2109 } else if (et == AHCI_ERR_NCQ ||
2110 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
2111 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
2112 ch->hold[slot->slot] = ccb;
2116 /* If we have no other active commands, ... */
2117 if (ch->rslots == 0) {
2118 /* if there was fatal error - reset port. */
2119 if (ch->toslots != 0 || ch->fatalerr) {
2122 /* if we have slots in error, we can reinit port. */
2123 if (ch->eslots != 0) {
2128 /* if there commands on hold, we can do READ LOG. */
2129 if (!ch->recoverycmd && ch->numhslots)
2130 ahci_issue_recovery(ch);
2132 /* If all the rest of commands are in timeout - give them chance. */
2133 } else if ((ch->rslots & ~ch->toslots) == 0 &&
2134 et != AHCI_ERR_TIMEOUT)
2135 ahci_rearm_timeout(ch);
2136 /* Unfreeze frozen command. */
2137 if (ch->frozen && !ahci_check_collision(ch, ch->frozen)) {
2138 union ccb *fccb = ch->frozen;
2140 ahci_begin_transaction(ch, fccb);
2141 xpt_release_simq(ch->sim, TRUE);
2143 /* Start PM timer. */
2144 if (ch->numrslots == 0 && ch->pm_level > 3 &&
2145 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
2146 callout_schedule(&ch->pm_timer,
2147 (ch->pm_level == 4) ? hz / 1000 : hz / 8);
2152 ahci_issue_recovery(struct ahci_channel *ch)
2155 struct ccb_ataio *ataio;
2156 struct ccb_scsiio *csio;
2159 /* Find some held command. */
2160 for (i = 0; i < ch->numslots; i++) {
2164 ccb = xpt_alloc_ccb_nowait();
2166 device_printf(ch->dev, "Unable to allocate recovery command\n");
2168 /* We can't do anything -- complete held commands. */
2169 for (i = 0; i < ch->numslots; i++) {
2170 if (ch->hold[i] == NULL)
2172 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2173 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
2174 ahci_done(ch, ch->hold[i]);
2181 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
2182 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
2184 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
2185 ccb->ccb_h.func_code = XPT_ATA_IO;
2186 ccb->ccb_h.flags = CAM_DIR_IN;
2187 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2188 ataio = &ccb->ataio;
2189 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
2190 if (ataio->data_ptr == NULL) {
2192 device_printf(ch->dev,
2193 "Unable to allocate memory for READ LOG command\n");
2196 ataio->dxfer_len = 512;
2197 bzero(&ataio->cmd, sizeof(ataio->cmd));
2198 ataio->cmd.flags = CAM_ATAIO_48BIT;
2199 ataio->cmd.command = 0x2F; /* READ LOG EXT */
2200 ataio->cmd.sector_count = 1;
2201 ataio->cmd.sector_count_exp = 0;
2202 ataio->cmd.lba_low = 0x10;
2203 ataio->cmd.lba_mid = 0;
2204 ataio->cmd.lba_mid_exp = 0;
2207 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
2208 ccb->ccb_h.recovery_slot = i;
2209 ccb->ccb_h.func_code = XPT_SCSI_IO;
2210 ccb->ccb_h.flags = CAM_DIR_IN;
2211 ccb->ccb_h.status = 0;
2212 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
2214 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
2215 csio->dxfer_len = ch->hold[i]->csio.sense_len;
2217 bzero(&csio->cdb_io, sizeof(csio->cdb_io));
2218 csio->cdb_io.cdb_bytes[0] = 0x03;
2219 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
2221 /* Freeze SIM while doing recovery. */
2222 ch->recoverycmd = 1;
2223 xpt_freeze_simq(ch->sim, 1);
2224 ahci_begin_transaction(ch, ccb);
2228 ahci_process_read_log(struct ahci_channel *ch, union ccb *ccb)
2231 struct ata_res *res;
2234 ch->recoverycmd = 0;
2236 data = ccb->ataio.data_ptr;
2237 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
2238 (data[0] & 0x80) == 0) {
2239 for (i = 0; i < ch->numslots; i++) {
2242 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2244 if ((data[0] & 0x1F) == i) {
2245 res = &ch->hold[i]->ataio.res;
2246 res->status = data[2];
2247 res->error = data[3];
2248 res->lba_low = data[4];
2249 res->lba_mid = data[5];
2250 res->lba_high = data[6];
2251 res->device = data[7];
2252 res->lba_low_exp = data[8];
2253 res->lba_mid_exp = data[9];
2254 res->lba_high_exp = data[10];
2255 res->sector_count = data[12];
2256 res->sector_count_exp = data[13];
2258 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2259 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
2261 ahci_done(ch, ch->hold[i]);
2266 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
2267 device_printf(ch->dev, "Error while READ LOG EXT\n");
2268 else if ((data[0] & 0x80) == 0) {
2269 device_printf(ch->dev, "Non-queued command error in READ LOG EXT\n");
2271 for (i = 0; i < ch->numslots; i++) {
2274 if (ch->hold[i]->ccb_h.func_code != XPT_ATA_IO)
2276 ahci_done(ch, ch->hold[i]);
2281 free(ccb->ataio.data_ptr, M_AHCI);
2283 xpt_release_simq(ch->sim, TRUE);
2287 ahci_process_request_sense(struct ahci_channel *ch, union ccb *ccb)
2291 ch->recoverycmd = 0;
2293 i = ccb->ccb_h.recovery_slot;
2294 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
2295 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
2297 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
2298 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
2300 ahci_done(ch, ch->hold[i]);
2304 xpt_release_simq(ch->sim, TRUE);
2308 ahci_start(struct ahci_channel *ch, int fbs)
2312 /* Run the channel start callback, if any. */
2316 /* Clear SATA error register */
2317 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
2318 /* Clear any interrupts pending on this channel */
2319 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
2320 /* Configure FIS-based switching if supported. */
2321 if (ch->chcaps & AHCI_P_CMD_FBSCP) {
2322 ch->fbs_enabled = (fbs && ch->pm_present) ? 1 : 0;
2323 ATA_OUTL(ch->r_mem, AHCI_P_FBS,
2324 ch->fbs_enabled ? AHCI_P_FBS_EN : 0);
2326 /* Start operations on this channel */
2327 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2328 cmd &= ~AHCI_P_CMD_PMA;
2329 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
2330 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
2334 ahci_stop(struct ahci_channel *ch)
2339 /* Kill all activity on this channel */
2340 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2341 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
2342 /* Wait for activity stop. */
2346 if (timeout++ > 50000) {
2347 device_printf(ch->dev, "stopping AHCI engine failed\n");
2350 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
2355 ahci_clo(struct ahci_channel *ch)
2360 /* Issue Command List Override if supported */
2361 if (ch->caps & AHCI_CAP_SCLO) {
2362 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2363 cmd |= AHCI_P_CMD_CLO;
2364 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
2368 if (timeout++ > 50000) {
2369 device_printf(ch->dev, "executing CLO failed\n");
2372 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
2377 ahci_stop_fr(struct ahci_channel *ch)
2382 /* Kill all FIS reception on this channel */
2383 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2384 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
2385 /* Wait for FIS reception stop. */
2389 if (timeout++ > 50000) {
2390 device_printf(ch->dev, "stopping AHCI FR engine failed\n");
2393 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
2397 ahci_start_fr(struct ahci_channel *ch)
2401 /* Start FIS reception on this channel */
2402 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
2403 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
2407 ahci_wait_ready(struct ahci_channel *ch, int t, int t0)
2412 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
2413 (ATA_S_BUSY | ATA_S_DRQ)) {
2416 device_printf(ch->dev,
2417 "AHCI reset: device not ready after %dms "
2419 MAX(t, 0) + t0, val);
2427 device_printf(ch->dev, "AHCI reset: device ready after %dms\n",
2433 ahci_reset_to(void *arg)
2435 struct ahci_channel *ch = arg;
2437 if (ch->resetting == 0)
2440 if (ahci_wait_ready(ch, ch->resetting == 0 ? -1 : 0,
2441 (310 - ch->resetting) * 100) == 0) {
2444 xpt_release_simq(ch->sim, TRUE);
2447 if (ch->resetting == 0) {
2450 xpt_release_simq(ch->sim, TRUE);
2453 callout_schedule(&ch->reset_timer, hz / 10);
2457 ahci_reset(struct ahci_channel *ch)
2459 struct ahci_controller *ctlr = device_get_softc(device_get_parent(ch->dev));
2462 xpt_freeze_simq(ch->sim, 1);
2464 device_printf(ch->dev, "AHCI reset...\n");
2465 /* Forget about previous reset. */
2466 if (ch->resetting) {
2468 callout_stop(&ch->reset_timer);
2469 xpt_release_simq(ch->sim, TRUE);
2471 /* Requeue freezed command. */
2473 union ccb *fccb = ch->frozen;
2475 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
2476 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
2477 xpt_freeze_devq(fccb->ccb_h.path, 1);
2478 fccb->ccb_h.status |= CAM_DEV_QFRZN;
2480 ahci_done(ch, fccb);
2482 /* Kill the engine and requeue all running commands. */
2484 for (i = 0; i < ch->numslots; i++) {
2485 /* Do we have a running request on slot? */
2486 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
2488 /* XXX; Commands in loading state. */
2489 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
2491 for (i = 0; i < ch->numslots; i++) {
2494 ahci_done(ch, ch->hold[i]);
2498 if (ch->toslots != 0)
2499 xpt_release_simq(ch->sim, TRUE);
2504 /* Tell the XPT about the event */
2505 xpt_async(AC_BUS_RESET, ch->path, NULL);
2506 /* Disable port interrupts */
2507 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
2508 /* Reset and reconnect PHY, */
2509 if (!ahci_sata_phy_reset(ch)) {
2511 device_printf(ch->dev,
2512 "AHCI reset: device not found\n");
2514 /* Enable wanted port interrupts */
2515 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2516 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2517 AHCI_P_IX_PRC | AHCI_P_IX_PC));
2518 xpt_release_simq(ch->sim, TRUE);
2522 device_printf(ch->dev, "AHCI reset: device found\n");
2523 /* Wait for clearing busy status. */
2524 if (ahci_wait_ready(ch, dumping ? 31000 : 0, 0)) {
2528 ch->resetting = 310;
2531 /* Enable wanted port interrupts */
2532 ATA_OUTL(ch->r_mem, AHCI_P_IE,
2533 (((ch->pm_level != 0) ? AHCI_P_IX_CPD | AHCI_P_IX_MP : 0) |
2534 AHCI_P_IX_TFE | AHCI_P_IX_HBF |
2535 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
2536 ((ch->pm_level == 0) ? AHCI_P_IX_PRC : 0) | AHCI_P_IX_PC |
2537 AHCI_P_IX_DP | AHCI_P_IX_UF | (ctlr->ccc ? 0 : AHCI_P_IX_SDB) |
2538 AHCI_P_IX_DS | AHCI_P_IX_PS | (ctlr->ccc ? 0 : AHCI_P_IX_DHR)));
2540 callout_reset(&ch->reset_timer, hz / 10, ahci_reset_to, ch);
2543 xpt_release_simq(ch->sim, TRUE);
2548 ahci_setup_fis(struct ahci_channel *ch, struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
2550 u_int8_t *fis = &ctp->cfis[0];
2553 fis[0] = 0x27; /* host to device */
2554 fis[1] = (ccb->ccb_h.target_id & 0x0f);
2555 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
2557 fis[2] = ATA_PACKET_CMD;
2558 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
2559 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA)
2562 fis[5] = ccb->csio.dxfer_len;
2563 fis[6] = ccb->csio.dxfer_len >> 8;
2566 fis[15] = ATA_A_4BIT;
2567 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
2568 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
2569 ctp->acmd, ccb->csio.cdb_len);
2570 bzero(ctp->acmd + ccb->csio.cdb_len, 32 - ccb->csio.cdb_len);
2571 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
2573 fis[2] = ccb->ataio.cmd.command;
2574 fis[3] = ccb->ataio.cmd.features;
2575 fis[4] = ccb->ataio.cmd.lba_low;
2576 fis[5] = ccb->ataio.cmd.lba_mid;
2577 fis[6] = ccb->ataio.cmd.lba_high;
2578 fis[7] = ccb->ataio.cmd.device;
2579 fis[8] = ccb->ataio.cmd.lba_low_exp;
2580 fis[9] = ccb->ataio.cmd.lba_mid_exp;
2581 fis[10] = ccb->ataio.cmd.lba_high_exp;
2582 fis[11] = ccb->ataio.cmd.features_exp;
2583 fis[12] = ccb->ataio.cmd.sector_count;
2584 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
2586 fis[12] |= tag << 3;
2588 fis[13] = ccb->ataio.cmd.sector_count_exp;
2589 if (ccb->ataio.ata_flags & ATA_FLAG_ICC)
2590 fis[14] = ccb->ataio.icc;
2591 fis[15] = ATA_A_4BIT;
2592 if (ccb->ataio.ata_flags & ATA_FLAG_AUX) {
2593 fis[16] = ccb->ataio.aux & 0xff;
2594 fis[17] = (ccb->ataio.aux >> 8) & 0xff;
2595 fis[18] = (ccb->ataio.aux >> 16) & 0xff;
2596 fis[19] = (ccb->ataio.aux >> 24) & 0xff;
2599 fis[15] = ccb->ataio.cmd.control;
2605 ahci_sata_connect(struct ahci_channel *ch)
2608 int timeout, found = 0;
2610 /* Wait up to 100ms for "connect well" */
2611 for (timeout = 0; timeout < 1000 ; timeout++) {
2612 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
2613 if ((status & ATA_SS_DET_MASK) != ATA_SS_DET_NO_DEVICE)
2615 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
2616 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
2617 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
2619 if ((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_OFFLINE) {
2621 device_printf(ch->dev, "SATA offline status=%08x\n",
2626 if (found == 0 && timeout >= 100)
2630 if (timeout >= 1000 || !found) {
2632 device_printf(ch->dev,
2633 "SATA connect timeout time=%dus status=%08x\n",
2634 timeout * 100, status);
2639 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2640 timeout * 100, status);
2642 /* Clear SATA error register */
2643 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
2648 ahci_sata_phy_reset(struct ahci_channel *ch)
2651 uint32_t val, detval;
2653 if (ch->listening) {
2654 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2655 val |= AHCI_P_CMD_SUD;
2656 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2659 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2661 val = ATA_SC_SPD_SPEED_GEN1;
2662 else if (sata_rev == 2)
2663 val = ATA_SC_SPD_SPEED_GEN2;
2664 else if (sata_rev == 3)
2665 val = ATA_SC_SPD_SPEED_GEN3;
2668 detval = ahci_ch_detval(ch, ATA_SC_DET_RESET);
2669 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2671 ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER);
2673 detval = ahci_ch_detval(ch, ATA_SC_DET_IDLE);
2674 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
2675 detval | val | ((ch->pm_level > 0) ? 0 :
2676 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
2677 if (!ahci_sata_connect(ch)) {
2678 if (ch->caps & AHCI_CAP_SSS) {
2679 val = ATA_INL(ch->r_mem, AHCI_P_CMD);
2680 val &= ~AHCI_P_CMD_SUD;
2681 ATA_OUTL(ch->r_mem, AHCI_P_CMD, val);
2683 } else if (ch->pm_level > 0)
2684 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
2691 ahci_check_ids(struct ahci_channel *ch, union ccb *ccb)
2694 if (ccb->ccb_h.target_id > ((ch->caps & AHCI_CAP_SPM) ? 15 : 0)) {
2695 ccb->ccb_h.status = CAM_TID_INVALID;
2699 if (ccb->ccb_h.target_lun != 0) {
2700 ccb->ccb_h.status = CAM_LUN_INVALID;
2708 ahciaction(struct cam_sim *sim, union ccb *ccb)
2710 struct ahci_channel *ch;
2712 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
2713 ccb->ccb_h.func_code));
2715 ch = (struct ahci_channel *)cam_sim_softc(sim);
2716 switch (ccb->ccb_h.func_code) {
2717 /* Common cases first */
2718 case XPT_ATA_IO: /* Execute the requested I/O operation */
2720 if (ahci_check_ids(ch, ccb))
2722 if (ch->devices == 0 ||
2723 (ch->pm_present == 0 &&
2724 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2725 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2728 ccb->ccb_h.recovery_type = RECOVERY_NONE;
2729 /* Check for command collision. */
2730 if (ahci_check_collision(ch, ccb)) {
2731 /* Freeze command. */
2733 /* We have only one frozen slot, so freeze simq also. */
2734 xpt_freeze_simq(ch->sim, 1);
2737 ahci_begin_transaction(ch, ccb);
2739 case XPT_ABORT: /* Abort the specified CCB */
2741 ccb->ccb_h.status = CAM_REQ_INVALID;
2743 case XPT_SET_TRAN_SETTINGS:
2745 struct ccb_trans_settings *cts = &ccb->cts;
2746 struct ahci_device *d;
2748 if (ahci_check_ids(ch, ccb))
2750 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2751 d = &ch->curr[ccb->ccb_h.target_id];
2753 d = &ch->user[ccb->ccb_h.target_id];
2754 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2755 d->revision = cts->xport_specific.sata.revision;
2756 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2757 d->mode = cts->xport_specific.sata.mode;
2758 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT)
2759 d->bytecount = min(8192, cts->xport_specific.sata.bytecount);
2760 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2761 d->tags = min(ch->numslots, cts->xport_specific.sata.tags);
2762 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2763 ch->pm_present = cts->xport_specific.sata.pm_present;
2764 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2765 d->atapi = cts->xport_specific.sata.atapi;
2766 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2767 d->caps = cts->xport_specific.sata.caps;
2768 ccb->ccb_h.status = CAM_REQ_CMP;
2771 case XPT_GET_TRAN_SETTINGS:
2772 /* Get default/user set transfer settings for the target */
2774 struct ccb_trans_settings *cts = &ccb->cts;
2775 struct ahci_device *d;
2778 if (ahci_check_ids(ch, ccb))
2780 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2781 d = &ch->curr[ccb->ccb_h.target_id];
2783 d = &ch->user[ccb->ccb_h.target_id];
2784 cts->protocol = PROTO_UNSPECIFIED;
2785 cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2786 cts->transport = XPORT_SATA;
2787 cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2788 cts->proto_specific.valid = 0;
2789 cts->xport_specific.sata.valid = 0;
2790 if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2791 (ccb->ccb_h.target_id == 15 ||
2792 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2793 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
2794 if (status & 0x0f0) {
2795 cts->xport_specific.sata.revision =
2796 (status & 0x0f0) >> 4;
2797 cts->xport_specific.sata.valid |=
2798 CTS_SATA_VALID_REVISION;
2800 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2802 if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
2803 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2804 if (ch->caps2 & AHCI_CAP2_APST)
2805 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
2807 if ((ch->caps & AHCI_CAP_SNCQ) &&
2808 (ch->quirks & AHCI_Q_NOAA) == 0)
2809 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
2810 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2811 cts->xport_specific.sata.caps &=
2812 ch->user[ccb->ccb_h.target_id].caps;
2813 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2815 cts->xport_specific.sata.revision = d->revision;
2816 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2817 cts->xport_specific.sata.caps = d->caps;
2818 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2820 cts->xport_specific.sata.mode = d->mode;
2821 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2822 cts->xport_specific.sata.bytecount = d->bytecount;
2823 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2824 cts->xport_specific.sata.pm_present = ch->pm_present;
2825 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2826 cts->xport_specific.sata.tags = d->tags;
2827 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2828 cts->xport_specific.sata.atapi = d->atapi;
2829 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2830 ccb->ccb_h.status = CAM_REQ_CMP;
2833 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
2834 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
2836 ccb->ccb_h.status = CAM_REQ_CMP;
2838 case XPT_TERM_IO: /* Terminate the I/O process */
2840 ccb->ccb_h.status = CAM_REQ_INVALID;
2842 case XPT_PATH_INQ: /* Path routing inquiry */
2844 struct ccb_pathinq *cpi = &ccb->cpi;
2846 cpi->version_num = 1; /* XXX??? */
2847 cpi->hba_inquiry = PI_SDTR_ABLE;
2848 if (ch->caps & AHCI_CAP_SNCQ)
2849 cpi->hba_inquiry |= PI_TAG_ABLE;
2850 if (ch->caps & AHCI_CAP_SPM)
2851 cpi->hba_inquiry |= PI_SATAPM;
2852 cpi->target_sprt = 0;
2853 cpi->hba_misc = PIM_SEQSCAN | PIM_UNMAPPED;
2854 if ((ch->quirks & AHCI_Q_NOAUX) == 0)
2855 cpi->hba_misc |= PIM_ATA_EXT;
2856 cpi->hba_eng_cnt = 0;
2857 if (ch->caps & AHCI_CAP_SPM)
2858 cpi->max_target = 15;
2860 cpi->max_target = 0;
2862 cpi->initiator_id = 0;
2863 cpi->bus_id = cam_sim_bus(sim);
2864 cpi->base_transfer_speed = 150000;
2865 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2866 strlcpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
2867 strlcpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2868 cpi->unit_number = cam_sim_unit(sim);
2869 cpi->transport = XPORT_SATA;
2870 cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2871 cpi->protocol = PROTO_ATA;
2872 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2873 cpi->maxio = ctob(AHCI_SG_ENTRIES - 1);
2874 /* ATI SB600 can't handle 256 sectors with FPDMA (NCQ). */
2875 if (ch->quirks & AHCI_Q_MAXIO_64K)
2876 cpi->maxio = min(cpi->maxio, 128 * 512);
2877 cpi->hba_vendor = ch->vendorid;
2878 cpi->hba_device = ch->deviceid;
2879 cpi->hba_subvendor = ch->subvendorid;
2880 cpi->hba_subdevice = ch->subdeviceid;
2881 cpi->ccb_h.status = CAM_REQ_CMP;
2885 ccb->ccb_h.status = CAM_REQ_INVALID;
2892 ahcipoll(struct cam_sim *sim)
2894 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
2897 /* Read interrupt statuses and process if any. */
2898 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
2900 ahci_ch_intr_main(ch, istatus);
2901 if (ch->resetting != 0 &&
2902 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2903 ch->resetpolldiv = 1000;
2908 devclass_t ahci_devclass;
2910 MODULE_VERSION(ahci, 1);
2911 MODULE_DEPEND(ahci, cam, 1, 1, 1);