2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 /* ATA register defines */
31 #define ATA_DATA 0 /* (RW) data */
33 #define ATA_FEATURE 1 /* (W) feature */
34 #define ATA_F_DMA 0x01 /* enable DMA */
35 #define ATA_F_OVL 0x02 /* enable overlap */
37 #define ATA_COUNT 2 /* (W) sector count */
39 #define ATA_SECTOR 3 /* (RW) sector # */
40 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
41 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
42 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
43 #define ATA_D_LBA 0x40 /* use LBA addressing */
44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
46 #define ATA_COMMAND 7 /* (W) command */
48 #define ATA_ERROR 8 /* (R) error */
49 #define ATA_E_ILI 0x01 /* illegal length */
50 #define ATA_E_NM 0x02 /* no media */
51 #define ATA_E_ABORT 0x04 /* command aborted */
52 #define ATA_E_MCR 0x08 /* media change request */
53 #define ATA_E_IDNF 0x10 /* ID not found */
54 #define ATA_E_MC 0x20 /* media changed */
55 #define ATA_E_UNC 0x40 /* uncorrectable data */
56 #define ATA_E_ICRC 0x80 /* UDMA crc error */
57 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
59 #define ATA_IREASON 9 /* (R) interrupt reason */
60 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
61 #define ATA_I_IN 0x02 /* read (1) | write (0) */
62 #define ATA_I_RELEASE 0x04 /* released bus (1) */
63 #define ATA_I_TAGMASK 0xf8 /* tag mask */
65 #define ATA_STATUS 10 /* (R) status */
66 #define ATA_ALTSTAT 11 /* (R) alternate status */
67 #define ATA_S_ERROR 0x01 /* error */
68 #define ATA_S_INDEX 0x02 /* index */
69 #define ATA_S_CORR 0x04 /* data corrected */
70 #define ATA_S_DRQ 0x08 /* data request */
71 #define ATA_S_DSC 0x10 /* drive seek completed */
72 #define ATA_S_SERVICE 0x10 /* drive needs service */
73 #define ATA_S_DWF 0x20 /* drive write fault */
74 #define ATA_S_DMA 0x20 /* DMA ready */
75 #define ATA_S_READY 0x40 /* drive ready */
76 #define ATA_S_BUSY 0x80 /* busy */
78 #define ATA_CONTROL 12 /* (W) control */
79 #define ATA_A_IDS 0x02 /* disable interrupts */
80 #define ATA_A_RESET 0x04 /* RESET controller */
81 #define ATA_A_4BIT 0x08 /* 4 head bits */
82 #define ATA_A_HOB 0x80 /* High Order Byte enable */
84 /* SATA register defines */
85 #define ATA_SSTATUS 13
86 #define ATA_SS_DET_MASK 0x0000000f
87 #define ATA_SS_DET_NO_DEVICE 0x00000000
88 #define ATA_SS_DET_DEV_PRESENT 0x00000001
89 #define ATA_SS_DET_PHY_ONLINE 0x00000003
90 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
92 #define ATA_SS_SPD_MASK 0x000000f0
93 #define ATA_SS_SPD_NO_SPEED 0x00000000
94 #define ATA_SS_SPD_GEN1 0x00000010
95 #define ATA_SS_SPD_GEN2 0x00000020
96 #define ATA_SS_SPD_GEN3 0x00000040
98 #define ATA_SS_IPM_MASK 0x00000f00
99 #define ATA_SS_IPM_NO_DEVICE 0x00000000
100 #define ATA_SS_IPM_ACTIVE 0x00000100
101 #define ATA_SS_IPM_PARTIAL 0x00000200
102 #define ATA_SS_IPM_SLUMBER 0x00000600
104 #define ATA_SERROR 14
105 #define ATA_SE_DATA_CORRECTED 0x00000001
106 #define ATA_SE_COMM_CORRECTED 0x00000002
107 #define ATA_SE_DATA_ERR 0x00000100
108 #define ATA_SE_COMM_ERR 0x00000200
109 #define ATA_SE_PROT_ERR 0x00000400
110 #define ATA_SE_HOST_ERR 0x00000800
111 #define ATA_SE_PHY_CHANGED 0x00010000
112 #define ATA_SE_PHY_IERROR 0x00020000
113 #define ATA_SE_COMM_WAKE 0x00040000
114 #define ATA_SE_DECODE_ERR 0x00080000
115 #define ATA_SE_PARITY_ERR 0x00100000
116 #define ATA_SE_CRC_ERR 0x00200000
117 #define ATA_SE_HANDSHAKE_ERR 0x00400000
118 #define ATA_SE_LINKSEQ_ERR 0x00800000
119 #define ATA_SE_TRANSPORT_ERR 0x01000000
120 #define ATA_SE_UNKNOWN_FIS 0x02000000
122 #define ATA_SCONTROL 15
123 #define ATA_SC_DET_MASK 0x0000000f
124 #define ATA_SC_DET_IDLE 0x00000000
125 #define ATA_SC_DET_RESET 0x00000001
126 #define ATA_SC_DET_DISABLE 0x00000004
128 #define ATA_SC_SPD_MASK 0x000000f0
129 #define ATA_SC_SPD_NO_SPEED 0x00000000
130 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
131 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
132 #define ATA_SC_SPD_SPEED_GEN3 0x00000040
134 #define ATA_SC_IPM_MASK 0x00000f00
135 #define ATA_SC_IPM_NONE 0x00000000
136 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
137 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
139 #define ATA_SACTIVE 16
141 #define AHCI_MAX_PORTS 32
142 #define AHCI_MAX_SLOTS 32
144 /* SATA AHCI v1.0 register defines */
145 #define AHCI_CAP 0x00
146 #define AHCI_CAP_NPMASK 0x0000001f
147 #define AHCI_CAP_SXS 0x00000020
148 #define AHCI_CAP_EMS 0x00000040
149 #define AHCI_CAP_CCCS 0x00000080
150 #define AHCI_CAP_NCS 0x00001F00
151 #define AHCI_CAP_NCS_SHIFT 8
152 #define AHCI_CAP_PSC 0x00002000
153 #define AHCI_CAP_SSC 0x00004000
154 #define AHCI_CAP_PMD 0x00008000
155 #define AHCI_CAP_FBSS 0x00010000
156 #define AHCI_CAP_SPM 0x00020000
157 #define AHCI_CAP_SAM 0x00080000
158 #define AHCI_CAP_ISS 0x00F00000
159 #define AHCI_CAP_ISS_SHIFT 20
160 #define AHCI_CAP_SCLO 0x01000000
161 #define AHCI_CAP_SAL 0x02000000
162 #define AHCI_CAP_SALP 0x04000000
163 #define AHCI_CAP_SSS 0x08000000
164 #define AHCI_CAP_SMPS 0x10000000
165 #define AHCI_CAP_SSNTF 0x20000000
166 #define AHCI_CAP_SNCQ 0x40000000
167 #define AHCI_CAP_64BIT 0x80000000
169 #define AHCI_GHC 0x04
170 #define AHCI_GHC_AE 0x80000000
171 #define AHCI_GHC_MRSM 0x00000004
172 #define AHCI_GHC_IE 0x00000002
173 #define AHCI_GHC_HR 0x00000001
179 #define AHCI_CCCC 0x14
180 #define AHCI_CCCC_TV_MASK 0xffff0000
181 #define AHCI_CCCC_TV_SHIFT 16
182 #define AHCI_CCCC_CC_MASK 0x0000ff00
183 #define AHCI_CCCC_CC_SHIFT 8
184 #define AHCI_CCCC_INT_MASK 0x000000f8
185 #define AHCI_CCCC_INT_SHIFT 3
186 #define AHCI_CCCC_EN 0x00000001
187 #define AHCI_CCCP 0x18
189 #define AHCI_EM_LOC 0x1C
190 #define AHCI_EM_CTL 0x20
191 #define AHCI_EM_MR 0x00000001
192 #define AHCI_EM_TM 0x00000100
193 #define AHCI_EM_RST 0x00000200
194 #define AHCI_EM_LED 0x00010000
195 #define AHCI_EM_SAFTE 0x00020000
196 #define AHCI_EM_SES2 0x00040000
197 #define AHCI_EM_SGPIO 0x00080000
198 #define AHCI_EM_SMB 0x01000000
199 #define AHCI_EM_XMT 0x02000000
200 #define AHCI_EM_ALHD 0x04000000
201 #define AHCI_EM_PM 0x08000000
203 #define AHCI_CAP2 0x24
204 #define AHCI_CAP2_BOH 0x00000001
205 #define AHCI_CAP2_NVMP 0x00000002
206 #define AHCI_CAP2_APST 0x00000004
208 #define AHCI_OFFSET 0x100
209 #define AHCI_STEP 0x80
211 #define AHCI_P_CLB 0x00
212 #define AHCI_P_CLBU 0x04
213 #define AHCI_P_FB 0x08
214 #define AHCI_P_FBU 0x0c
215 #define AHCI_P_IS 0x10
216 #define AHCI_P_IE 0x14
217 #define AHCI_P_IX_DHR 0x00000001
218 #define AHCI_P_IX_PS 0x00000002
219 #define AHCI_P_IX_DS 0x00000004
220 #define AHCI_P_IX_SDB 0x00000008
221 #define AHCI_P_IX_UF 0x00000010
222 #define AHCI_P_IX_DP 0x00000020
223 #define AHCI_P_IX_PC 0x00000040
224 #define AHCI_P_IX_DI 0x00000080
226 #define AHCI_P_IX_PRC 0x00400000
227 #define AHCI_P_IX_IPM 0x00800000
228 #define AHCI_P_IX_OF 0x01000000
229 #define AHCI_P_IX_INF 0x04000000
230 #define AHCI_P_IX_IF 0x08000000
231 #define AHCI_P_IX_HBD 0x10000000
232 #define AHCI_P_IX_HBF 0x20000000
233 #define AHCI_P_IX_TFE 0x40000000
234 #define AHCI_P_IX_CPD 0x80000000
236 #define AHCI_P_CMD 0x18
237 #define AHCI_P_CMD_ST 0x00000001
238 #define AHCI_P_CMD_SUD 0x00000002
239 #define AHCI_P_CMD_POD 0x00000004
240 #define AHCI_P_CMD_CLO 0x00000008
241 #define AHCI_P_CMD_FRE 0x00000010
242 #define AHCI_P_CMD_CCS_MASK 0x00001f00
243 #define AHCI_P_CMD_CCS_SHIFT 8
244 #define AHCI_P_CMD_ISS 0x00002000
245 #define AHCI_P_CMD_FR 0x00004000
246 #define AHCI_P_CMD_CR 0x00008000
247 #define AHCI_P_CMD_CPS 0x00010000
248 #define AHCI_P_CMD_PMA 0x00020000
249 #define AHCI_P_CMD_HPCP 0x00040000
250 #define AHCI_P_CMD_MPSP 0x00080000
251 #define AHCI_P_CMD_CPD 0x00100000
252 #define AHCI_P_CMD_ESP 0x00200000
253 #define AHCI_P_CMD_FBSCP 0x00400000
254 #define AHCI_P_CMD_APSTE 0x00800000
255 #define AHCI_P_CMD_ATAPI 0x01000000
256 #define AHCI_P_CMD_DLAE 0x02000000
257 #define AHCI_P_CMD_ALPE 0x04000000
258 #define AHCI_P_CMD_ASP 0x08000000
259 #define AHCI_P_CMD_ICC_MASK 0xf0000000
260 #define AHCI_P_CMD_NOOP 0x00000000
261 #define AHCI_P_CMD_ACTIVE 0x10000000
262 #define AHCI_P_CMD_PARTIAL 0x20000000
263 #define AHCI_P_CMD_SLUMBER 0x60000000
265 #define AHCI_P_TFD 0x20
266 #define AHCI_P_SIG 0x24
267 #define AHCI_P_SSTS 0x28
268 #define AHCI_P_SCTL 0x2c
269 #define AHCI_P_SERR 0x30
270 #define AHCI_P_SACT 0x34
271 #define AHCI_P_CI 0x38
272 #define AHCI_P_SNTF 0x3C
273 #define AHCI_P_FBS 0x40
274 #define AHCI_P_FBS_EN 0x00000001
275 #define AHCI_P_FBS_DEC 0x00000002
276 #define AHCI_P_FBS_SDE 0x00000004
277 #define AHCI_P_FBS_DEV 0x00000f00
278 #define AHCI_P_FBS_DEV_SHIFT 8
279 #define AHCI_P_FBS_ADO 0x0000f000
280 #define AHCI_P_FBS_ADO_SHIFT 12
281 #define AHCI_P_FBS_DWE 0x000f0000
282 #define AHCI_P_FBS_DWE_SHIFT 16
284 /* Just to be sure, if building as module. */
285 #if MAXPHYS < 512 * 1024
287 #define MAXPHYS 512 * 1024
289 /* Pessimistic prognosis on number of required S/G entries */
290 #define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
291 /* Command list. 32 commands. First, 1Kbyte aligned. */
292 #define AHCI_CL_OFFSET 0
293 #define AHCI_CL_SIZE 32
294 /* Command tables. Up to 32 commands, Each, 128byte aligned. */
295 #define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
296 #define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
297 /* Total main work area. */
298 #define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
300 struct ahci_dma_prd {
303 u_int32_t dbc; /* 0 based */
304 #define AHCI_PRD_MASK 0x003fffff /* max 4MB */
305 #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1)
306 #define AHCI_PRD_IPC (1 << 31)
309 struct ahci_cmd_tab {
312 u_int8_t reserved[32];
313 struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES];
316 struct ahci_cmd_list {
318 #define AHCI_CMD_ATAPI 0x0020
319 #define AHCI_CMD_WRITE 0x0040
320 #define AHCI_CMD_PREFETCH 0x0080
321 #define AHCI_CMD_RESET 0x0100
322 #define AHCI_CMD_BIST 0x0200
323 #define AHCI_CMD_CLR_BUSY 0x0400
325 u_int16_t prd_length; /* PRD entries */
327 u_int64_t cmd_table_phys; /* 128byte aligned */
331 #define ATA_IRQ_RID 0
332 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
335 bus_dmamap_t data_map; /* data DMA map */
336 int nsegs; /* Number of segs loaded */
339 /* structure holding DMA related information */
341 bus_dma_tag_t work_tag; /* workspace DMA tag */
342 bus_dmamap_t work_map; /* workspace DMA map */
343 uint8_t *work; /* workspace */
344 bus_addr_t work_bus; /* bus address of work */
345 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */
346 bus_dmamap_t rfis_map; /* RFIS list DMA map */
347 uint8_t *rfis; /* FIS receive area */
348 bus_addr_t rfis_bus; /* bus address of rfis */
349 bus_dma_tag_t data_tag; /* data DMA tag */
350 u_int64_t max_address; /* highest DMA'able address */
353 enum ahci_slot_states {
361 device_t dev; /* Device handle */
362 u_int8_t slot; /* Number of this slot */
363 enum ahci_slot_states state; /* Slot state */
364 union ccb *ccb; /* CCB occupying slot */
365 struct ata_dmaslot dma; /* DMA data of this slot */
366 struct callout timeout; /* Execution timeout */
378 /* structure describing an ATA channel */
379 struct ahci_channel {
380 device_t dev; /* Device handle */
381 int unit; /* Physical channel */
382 struct resource *r_mem; /* Memory of this channel */
383 struct resource *r_irq; /* Interrupt of this channel */
384 void *ih; /* Interrupt handle */
385 struct ata_dma dma; /* DMA data */
387 struct cam_path *path;
388 uint32_t caps; /* Controller capabilities */
389 uint32_t caps2; /* Controller capabilities */
390 uint32_t chcaps; /* Channel capabilities */
392 int numslots; /* Number of present slots */
393 int pm_level; /* power management level */
395 struct ahci_slot slot[AHCI_MAX_SLOTS];
396 union ccb *hold[AHCI_MAX_SLOTS];
397 struct mtx mtx; /* state lock */
398 int devices; /* What is present */
399 int pm_present; /* PM presence reported */
400 int fbs_enabled; /* FIS-based switching enabled */
401 uint32_t oslots; /* Occupied slots */
402 uint32_t rslots; /* Running slots */
403 uint32_t aslots; /* Slots with atomic commands */
404 uint32_t eslots; /* Slots in error */
405 uint32_t toslots; /* Slots in timeout */
406 int numrslots; /* Number of running slots */
407 int numrslotspd[16];/* Number of running slots per dev */
408 int numtslots; /* Number of tagged slots */
409 int numtslotspd[16];/* Number of tagged slots per dev */
410 int numhslots; /* Number of holden slots */
411 int readlog; /* Our READ LOG active */
412 int fatalerr; /* Fatal error happend */
413 int lastslot; /* Last used slot */
414 int taggedtarget; /* Last tagged target */
415 union ccb *frozen; /* Frozen command */
416 struct callout pm_timer; /* Power management events */
418 struct ahci_device user[16]; /* User-specified settings */
419 struct ahci_device curr[16]; /* Current settings */
422 /* structure describing a AHCI controller */
423 struct ahci_controller {
426 struct resource *r_mem;
427 struct rman sc_iomem;
428 struct ahci_controller_irq {
429 struct ahci_controller *ctlr;
430 struct resource *r_irq;
434 #define AHCI_IRQ_MODE_ALL 0
435 #define AHCI_IRQ_MODE_AFTER 1
436 #define AHCI_IRQ_MODE_ONE 2
438 uint32_t caps; /* Controller capabilities */
439 uint32_t caps2; /* Controller capabilities */
440 uint32_t capsem; /* Controller capabilities */
445 int ccc; /* CCC timeout */
446 int cccv; /* CCC vector */
448 void (*function)(void *);
450 } interrupt[AHCI_MAX_PORTS];
454 AHCI_ERR_NONE, /* No error */
455 AHCI_ERR_INVALID, /* Error detected by us before submitting. */
456 AHCI_ERR_INNOCENT, /* Innocent victim. */
457 AHCI_ERR_TFE, /* Task File Error. */
458 AHCI_ERR_SATA, /* SATA error. */
459 AHCI_ERR_TIMEOUT, /* Command execution timeout. */
460 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold
461 * until READ LOG executed to reveal error. */
464 /* macros to hide busspace uglyness */
465 #define ATA_INB(res, offset) \
466 bus_read_1((res), (offset))
467 #define ATA_INW(res, offset) \
468 bus_read_2((res), (offset))
469 #define ATA_INL(res, offset) \
470 bus_read_4((res), (offset))
471 #define ATA_INSW(res, offset, addr, count) \
472 bus_read_multi_2((res), (offset), (addr), (count))
473 #define ATA_INSW_STRM(res, offset, addr, count) \
474 bus_read_multi_stream_2((res), (offset), (addr), (count))
475 #define ATA_INSL(res, offset, addr, count) \
476 bus_read_multi_4((res), (offset), (addr), (count))
477 #define ATA_INSL_STRM(res, offset, addr, count) \
478 bus_read_multi_stream_4((res), (offset), (addr), (count))
479 #define ATA_OUTB(res, offset, value) \
480 bus_write_1((res), (offset), (value))
481 #define ATA_OUTW(res, offset, value) \
482 bus_write_2((res), (offset), (value))
483 #define ATA_OUTL(res, offset, value) \
484 bus_write_4((res), (offset), (value))
485 #define ATA_OUTSW(res, offset, addr, count) \
486 bus_write_multi_2((res), (offset), (addr), (count))
487 #define ATA_OUTSW_STRM(res, offset, addr, count) \
488 bus_write_multi_stream_2((res), (offset), (addr), (count))
489 #define ATA_OUTSL(res, offset, addr, count) \
490 bus_write_multi_4((res), (offset), (addr), (count))
491 #define ATA_OUTSL_STRM(res, offset, addr, count) \
492 bus_write_multi_stream_4((res), (offset), (addr), (count))