2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 /* ATA register defines */
31 #define ATA_DATA 0 /* (RW) data */
33 #define ATA_FEATURE 1 /* (W) feature */
34 #define ATA_F_DMA 0x01 /* enable DMA */
35 #define ATA_F_OVL 0x02 /* enable overlap */
37 #define ATA_COUNT 2 /* (W) sector count */
39 #define ATA_SECTOR 3 /* (RW) sector # */
40 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */
41 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */
42 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */
43 #define ATA_D_LBA 0x40 /* use LBA addressing */
44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
46 #define ATA_COMMAND 7 /* (W) command */
48 #define ATA_ERROR 8 /* (R) error */
49 #define ATA_E_ILI 0x01 /* illegal length */
50 #define ATA_E_NM 0x02 /* no media */
51 #define ATA_E_ABORT 0x04 /* command aborted */
52 #define ATA_E_MCR 0x08 /* media change request */
53 #define ATA_E_IDNF 0x10 /* ID not found */
54 #define ATA_E_MC 0x20 /* media changed */
55 #define ATA_E_UNC 0x40 /* uncorrectable data */
56 #define ATA_E_ICRC 0x80 /* UDMA crc error */
57 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
59 #define ATA_IREASON 9 /* (R) interrupt reason */
60 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
61 #define ATA_I_IN 0x02 /* read (1) | write (0) */
62 #define ATA_I_RELEASE 0x04 /* released bus (1) */
63 #define ATA_I_TAGMASK 0xf8 /* tag mask */
65 #define ATA_STATUS 10 /* (R) status */
66 #define ATA_ALTSTAT 11 /* (R) alternate status */
67 #define ATA_S_ERROR 0x01 /* error */
68 #define ATA_S_INDEX 0x02 /* index */
69 #define ATA_S_CORR 0x04 /* data corrected */
70 #define ATA_S_DRQ 0x08 /* data request */
71 #define ATA_S_DSC 0x10 /* drive seek completed */
72 #define ATA_S_SERVICE 0x10 /* drive needs service */
73 #define ATA_S_DWF 0x20 /* drive write fault */
74 #define ATA_S_DMA 0x20 /* DMA ready */
75 #define ATA_S_READY 0x40 /* drive ready */
76 #define ATA_S_BUSY 0x80 /* busy */
78 #define ATA_CONTROL 12 /* (W) control */
79 #define ATA_A_IDS 0x02 /* disable interrupts */
80 #define ATA_A_RESET 0x04 /* RESET controller */
81 #define ATA_A_4BIT 0x08 /* 4 head bits */
82 #define ATA_A_HOB 0x80 /* High Order Byte enable */
84 /* SATA register defines */
85 #define ATA_SSTATUS 13
86 #define ATA_SS_DET_MASK 0x0000000f
87 #define ATA_SS_DET_NO_DEVICE 0x00000000
88 #define ATA_SS_DET_DEV_PRESENT 0x00000001
89 #define ATA_SS_DET_PHY_ONLINE 0x00000003
90 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
92 #define ATA_SS_SPD_MASK 0x000000f0
93 #define ATA_SS_SPD_NO_SPEED 0x00000000
94 #define ATA_SS_SPD_GEN1 0x00000010
95 #define ATA_SS_SPD_GEN2 0x00000020
96 #define ATA_SS_SPD_GEN3 0x00000040
98 #define ATA_SS_IPM_MASK 0x00000f00
99 #define ATA_SS_IPM_NO_DEVICE 0x00000000
100 #define ATA_SS_IPM_ACTIVE 0x00000100
101 #define ATA_SS_IPM_PARTIAL 0x00000200
102 #define ATA_SS_IPM_SLUMBER 0x00000600
103 #define ATA_SS_IPM_DEVSLEEP 0x00000800
105 #define ATA_SERROR 14
106 #define ATA_SE_DATA_CORRECTED 0x00000001
107 #define ATA_SE_COMM_CORRECTED 0x00000002
108 #define ATA_SE_DATA_ERR 0x00000100
109 #define ATA_SE_COMM_ERR 0x00000200
110 #define ATA_SE_PROT_ERR 0x00000400
111 #define ATA_SE_HOST_ERR 0x00000800
112 #define ATA_SE_PHY_CHANGED 0x00010000
113 #define ATA_SE_PHY_IERROR 0x00020000
114 #define ATA_SE_COMM_WAKE 0x00040000
115 #define ATA_SE_DECODE_ERR 0x00080000
116 #define ATA_SE_PARITY_ERR 0x00100000
117 #define ATA_SE_CRC_ERR 0x00200000
118 #define ATA_SE_HANDSHAKE_ERR 0x00400000
119 #define ATA_SE_LINKSEQ_ERR 0x00800000
120 #define ATA_SE_TRANSPORT_ERR 0x01000000
121 #define ATA_SE_UNKNOWN_FIS 0x02000000
122 #define ATA_SE_EXCHANGED 0x04000000
124 #define ATA_SCONTROL 15
125 #define ATA_SC_DET_MASK 0x0000000f
126 #define ATA_SC_DET_IDLE 0x00000000
127 #define ATA_SC_DET_RESET 0x00000001
128 #define ATA_SC_DET_DISABLE 0x00000004
130 #define ATA_SC_SPD_MASK 0x000000f0
131 #define ATA_SC_SPD_NO_SPEED 0x00000000
132 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
133 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
134 #define ATA_SC_SPD_SPEED_GEN3 0x00000040
136 #define ATA_SC_IPM_MASK 0x00000f00
137 #define ATA_SC_IPM_NONE 0x00000000
138 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
139 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
141 #define ATA_SACTIVE 16
143 #define AHCI_MAX_PORTS 32
144 #define AHCI_MAX_SLOTS 32
146 /* SATA AHCI v1.0 register defines */
147 #define AHCI_CAP 0x00
148 #define AHCI_CAP_NPMASK 0x0000001f
149 #define AHCI_CAP_SXS 0x00000020
150 #define AHCI_CAP_EMS 0x00000040
151 #define AHCI_CAP_CCCS 0x00000080
152 #define AHCI_CAP_NCS 0x00001F00
153 #define AHCI_CAP_NCS_SHIFT 8
154 #define AHCI_CAP_PSC 0x00002000
155 #define AHCI_CAP_SSC 0x00004000
156 #define AHCI_CAP_PMD 0x00008000
157 #define AHCI_CAP_FBSS 0x00010000
158 #define AHCI_CAP_SPM 0x00020000
159 #define AHCI_CAP_SAM 0x00080000
160 #define AHCI_CAP_ISS 0x00F00000
161 #define AHCI_CAP_ISS_SHIFT 20
162 #define AHCI_CAP_SCLO 0x01000000
163 #define AHCI_CAP_SAL 0x02000000
164 #define AHCI_CAP_SALP 0x04000000
165 #define AHCI_CAP_SSS 0x08000000
166 #define AHCI_CAP_SMPS 0x10000000
167 #define AHCI_CAP_SSNTF 0x20000000
168 #define AHCI_CAP_SNCQ 0x40000000
169 #define AHCI_CAP_64BIT 0x80000000
171 #define AHCI_GHC 0x04
172 #define AHCI_GHC_AE 0x80000000
173 #define AHCI_GHC_MRSM 0x00000004
174 #define AHCI_GHC_IE 0x00000002
175 #define AHCI_GHC_HR 0x00000001
181 #define AHCI_CCCC 0x14
182 #define AHCI_CCCC_TV_MASK 0xffff0000
183 #define AHCI_CCCC_TV_SHIFT 16
184 #define AHCI_CCCC_CC_MASK 0x0000ff00
185 #define AHCI_CCCC_CC_SHIFT 8
186 #define AHCI_CCCC_INT_MASK 0x000000f8
187 #define AHCI_CCCC_INT_SHIFT 3
188 #define AHCI_CCCC_EN 0x00000001
189 #define AHCI_CCCP 0x18
191 #define AHCI_EM_LOC 0x1C
192 #define AHCI_EM_CTL 0x20
193 #define AHCI_EM_MR 0x00000001
194 #define AHCI_EM_TM 0x00000100
195 #define AHCI_EM_RST 0x00000200
196 #define AHCI_EM_LED 0x00010000
197 #define AHCI_EM_SAFTE 0x00020000
198 #define AHCI_EM_SES2 0x00040000
199 #define AHCI_EM_SGPIO 0x00080000
200 #define AHCI_EM_SMB 0x01000000
201 #define AHCI_EM_XMT 0x02000000
202 #define AHCI_EM_ALHD 0x04000000
203 #define AHCI_EM_PM 0x08000000
205 #define AHCI_CAP2 0x24
206 #define AHCI_CAP2_BOH 0x00000001
207 #define AHCI_CAP2_NVMP 0x00000002
208 #define AHCI_CAP2_APST 0x00000004
209 #define AHCI_CAP2_SDS 0x00000008
210 #define AHCI_CAP2_SADM 0x00000010
211 #define AHCI_CAP2_DESO 0x00000020
213 #define AHCI_OFFSET 0x100
214 #define AHCI_STEP 0x80
216 #define AHCI_P_CLB 0x00
217 #define AHCI_P_CLBU 0x04
218 #define AHCI_P_FB 0x08
219 #define AHCI_P_FBU 0x0c
220 #define AHCI_P_IS 0x10
221 #define AHCI_P_IE 0x14
222 #define AHCI_P_IX_DHR 0x00000001
223 #define AHCI_P_IX_PS 0x00000002
224 #define AHCI_P_IX_DS 0x00000004
225 #define AHCI_P_IX_SDB 0x00000008
226 #define AHCI_P_IX_UF 0x00000010
227 #define AHCI_P_IX_DP 0x00000020
228 #define AHCI_P_IX_PC 0x00000040
229 #define AHCI_P_IX_MP 0x00000080
231 #define AHCI_P_IX_PRC 0x00400000
232 #define AHCI_P_IX_IPM 0x00800000
233 #define AHCI_P_IX_OF 0x01000000
234 #define AHCI_P_IX_INF 0x04000000
235 #define AHCI_P_IX_IF 0x08000000
236 #define AHCI_P_IX_HBD 0x10000000
237 #define AHCI_P_IX_HBF 0x20000000
238 #define AHCI_P_IX_TFE 0x40000000
239 #define AHCI_P_IX_CPD 0x80000000
241 #define AHCI_P_CMD 0x18
242 #define AHCI_P_CMD_ST 0x00000001
243 #define AHCI_P_CMD_SUD 0x00000002
244 #define AHCI_P_CMD_POD 0x00000004
245 #define AHCI_P_CMD_CLO 0x00000008
246 #define AHCI_P_CMD_FRE 0x00000010
247 #define AHCI_P_CMD_CCS_MASK 0x00001f00
248 #define AHCI_P_CMD_CCS_SHIFT 8
249 #define AHCI_P_CMD_ISS 0x00002000
250 #define AHCI_P_CMD_FR 0x00004000
251 #define AHCI_P_CMD_CR 0x00008000
252 #define AHCI_P_CMD_CPS 0x00010000
253 #define AHCI_P_CMD_PMA 0x00020000
254 #define AHCI_P_CMD_HPCP 0x00040000
255 #define AHCI_P_CMD_MPSP 0x00080000
256 #define AHCI_P_CMD_CPD 0x00100000
257 #define AHCI_P_CMD_ESP 0x00200000
258 #define AHCI_P_CMD_FBSCP 0x00400000
259 #define AHCI_P_CMD_APSTE 0x00800000
260 #define AHCI_P_CMD_ATAPI 0x01000000
261 #define AHCI_P_CMD_DLAE 0x02000000
262 #define AHCI_P_CMD_ALPE 0x04000000
263 #define AHCI_P_CMD_ASP 0x08000000
264 #define AHCI_P_CMD_ICC_MASK 0xf0000000
265 #define AHCI_P_CMD_NOOP 0x00000000
266 #define AHCI_P_CMD_ACTIVE 0x10000000
267 #define AHCI_P_CMD_PARTIAL 0x20000000
268 #define AHCI_P_CMD_SLUMBER 0x60000000
269 #define AHCI_P_CMD_DEVSLEEP 0x80000000
271 #define AHCI_P_TFD 0x20
272 #define AHCI_P_SIG 0x24
273 #define AHCI_P_SSTS 0x28
274 #define AHCI_P_SCTL 0x2c
275 #define AHCI_P_SERR 0x30
276 #define AHCI_P_SACT 0x34
277 #define AHCI_P_CI 0x38
278 #define AHCI_P_SNTF 0x3C
279 #define AHCI_P_FBS 0x40
280 #define AHCI_P_FBS_EN 0x00000001
281 #define AHCI_P_FBS_DEC 0x00000002
282 #define AHCI_P_FBS_SDE 0x00000004
283 #define AHCI_P_FBS_DEV 0x00000f00
284 #define AHCI_P_FBS_DEV_SHIFT 8
285 #define AHCI_P_FBS_ADO 0x0000f000
286 #define AHCI_P_FBS_ADO_SHIFT 12
287 #define AHCI_P_FBS_DWE 0x000f0000
288 #define AHCI_P_FBS_DWE_SHIFT 16
290 /* Just to be sure, if building as module. */
291 #if MAXPHYS < 512 * 1024
293 #define MAXPHYS 512 * 1024
295 /* Pessimistic prognosis on number of required S/G entries */
296 #define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8))
297 /* Command list. 32 commands. First, 1Kbyte aligned. */
298 #define AHCI_CL_OFFSET 0
299 #define AHCI_CL_SIZE 32
300 /* Command tables. Up to 32 commands, Each, 128byte aligned. */
301 #define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS)
302 #define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16)
303 /* Total main work area. */
304 #define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots)
306 struct ahci_dma_prd {
309 u_int32_t dbc; /* 0 based */
310 #define AHCI_PRD_MASK 0x003fffff /* max 4MB */
311 #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1)
312 #define AHCI_PRD_IPC (1 << 31)
315 struct ahci_cmd_tab {
318 u_int8_t reserved[32];
319 struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES];
322 struct ahci_cmd_list {
324 #define AHCI_CMD_ATAPI 0x0020
325 #define AHCI_CMD_WRITE 0x0040
326 #define AHCI_CMD_PREFETCH 0x0080
327 #define AHCI_CMD_RESET 0x0100
328 #define AHCI_CMD_BIST 0x0200
329 #define AHCI_CMD_CLR_BUSY 0x0400
331 u_int16_t prd_length; /* PRD entries */
333 u_int64_t cmd_table_phys; /* 128byte aligned */
337 #define ATA_IRQ_RID 0
338 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY)
341 bus_dmamap_t data_map; /* data DMA map */
342 int nsegs; /* Number of segs loaded */
345 /* structure holding DMA related information */
347 bus_dma_tag_t work_tag; /* workspace DMA tag */
348 bus_dmamap_t work_map; /* workspace DMA map */
349 uint8_t *work; /* workspace */
350 bus_addr_t work_bus; /* bus address of work */
351 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */
352 bus_dmamap_t rfis_map; /* RFIS list DMA map */
353 uint8_t *rfis; /* FIS receive area */
354 bus_addr_t rfis_bus; /* bus address of rfis */
355 bus_dma_tag_t data_tag; /* data DMA tag */
358 enum ahci_slot_states {
366 device_t dev; /* Device handle */
367 u_int8_t slot; /* Number of this slot */
368 enum ahci_slot_states state; /* Slot state */
369 union ccb *ccb; /* CCB occupying slot */
370 struct ata_dmaslot dma; /* DMA data of this slot */
371 struct callout timeout; /* Execution timeout */
384 device_t dev; /* Device handle */
386 uint8_t num; /* Number of this led */
387 uint8_t state; /* State of this led */
390 #define AHCI_NUM_LEDS 3
392 /* structure describing an ATA channel */
393 struct ahci_channel {
394 device_t dev; /* Device handle */
395 int unit; /* Physical channel */
396 struct resource *r_mem; /* Memory of this channel */
397 struct resource *r_irq; /* Interrupt of this channel */
398 void *ih; /* Interrupt handle */
399 struct ata_dma dma; /* DMA data */
401 struct cam_path *path;
402 uint32_t caps; /* Controller capabilities */
403 uint32_t caps2; /* Controller capabilities */
404 uint32_t chcaps; /* Channel capabilities */
406 int numslots; /* Number of present slots */
407 int pm_level; /* power management level */
409 struct ahci_slot slot[AHCI_MAX_SLOTS];
410 union ccb *hold[AHCI_MAX_SLOTS];
411 struct mtx mtx; /* state lock */
412 int devices; /* What is present */
413 int pm_present; /* PM presence reported */
414 int fbs_enabled; /* FIS-based switching enabled */
415 uint32_t oslots; /* Occupied slots */
416 uint32_t rslots; /* Running slots */
417 uint32_t aslots; /* Slots with atomic commands */
418 uint32_t eslots; /* Slots in error */
419 uint32_t toslots; /* Slots in timeout */
420 int numrslots; /* Number of running slots */
421 int numrslotspd[16];/* Number of running slots per dev */
422 int numtslots; /* Number of tagged slots */
423 int numtslotspd[16];/* Number of tagged slots per dev */
424 int numhslots; /* Number of held slots */
425 int recoverycmd; /* Our READ LOG active */
426 int fatalerr; /* Fatal error happend */
427 int lastslot; /* Last used slot */
428 int taggedtarget; /* Last tagged target */
429 int resetting; /* Hard-reset in progress. */
430 int resetpolldiv; /* Hard-reset poll divider. */
431 int listening; /* SUD bit is cleared. */
432 int wrongccs; /* CCS field in CMD was wrong */
433 union ccb *frozen; /* Frozen command */
434 struct callout pm_timer; /* Power management events */
435 struct callout reset_timer; /* Hard-reset timeout */
437 struct ahci_device user[16]; /* User-specified settings */
438 struct ahci_device curr[16]; /* Current settings */
441 struct ahci_enclosure {
442 device_t dev; /* Device handle */
443 struct resource *r_memc; /* Control register */
444 struct resource *r_memt; /* Transmit buffer */
445 struct resource *r_memr; /* Recieve buffer */
447 struct cam_path *path;
448 struct mtx mtx; /* state lock */
449 struct ahci_led leds[AHCI_MAX_PORTS * 3];
450 uint32_t capsem; /* Controller capabilities */
451 uint8_t status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */
457 /* structure describing a AHCI controller */
458 struct ahci_controller {
460 bus_dma_tag_t dma_tag;
462 struct resource *r_mem;
463 struct rman sc_iomem;
464 struct ahci_controller_irq {
465 struct ahci_controller *ctlr;
466 struct resource *r_irq;
470 #define AHCI_IRQ_MODE_ALL 0
471 #define AHCI_IRQ_MODE_AFTER 1
472 #define AHCI_IRQ_MODE_ONE 2
474 uint32_t caps; /* Controller capabilities */
475 uint32_t caps2; /* Controller capabilities */
476 uint32_t capsem; /* Controller capabilities */
477 uint32_t emloc; /* EM buffer location */
482 int ccc; /* CCC timeout */
483 int cccv; /* CCC vector */
485 void (*function)(void *);
487 } interrupt[AHCI_MAX_PORTS];
491 AHCI_ERR_NONE, /* No error */
492 AHCI_ERR_INVALID, /* Error detected by us before submitting. */
493 AHCI_ERR_INNOCENT, /* Innocent victim. */
494 AHCI_ERR_TFE, /* Task File Error. */
495 AHCI_ERR_SATA, /* SATA error. */
496 AHCI_ERR_TIMEOUT, /* Command execution timeout. */
497 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold
498 * until READ LOG executed to reveal error. */
501 /* macros to hide busspace uglyness */
502 #define ATA_INB(res, offset) \
503 bus_read_1((res), (offset))
504 #define ATA_INW(res, offset) \
505 bus_read_2((res), (offset))
506 #define ATA_INL(res, offset) \
507 bus_read_4((res), (offset))
508 #define ATA_INSW(res, offset, addr, count) \
509 bus_read_multi_2((res), (offset), (addr), (count))
510 #define ATA_INSW_STRM(res, offset, addr, count) \
511 bus_read_multi_stream_2((res), (offset), (addr), (count))
512 #define ATA_INSL(res, offset, addr, count) \
513 bus_read_multi_4((res), (offset), (addr), (count))
514 #define ATA_INSL_STRM(res, offset, addr, count) \
515 bus_read_multi_stream_4((res), (offset), (addr), (count))
516 #define ATA_OUTB(res, offset, value) \
517 bus_write_1((res), (offset), (value))
518 #define ATA_OUTW(res, offset, value) \
519 bus_write_2((res), (offset), (value))
520 #define ATA_OUTL(res, offset, value) \
521 bus_write_4((res), (offset), (value))
522 #define ATA_OUTSW(res, offset, addr, count) \
523 bus_write_multi_2((res), (offset), (addr), (count))
524 #define ATA_OUTSW_STRM(res, offset, addr, count) \
525 bus_write_multi_stream_2((res), (offset), (addr), (count))
526 #define ATA_OUTSL(res, offset, addr, count) \
527 bus_write_multi_4((res), (offset), (addr), (count))
528 #define ATA_OUTSL_STRM(res, offset, addr, count) \
529 bus_write_multi_stream_4((res), (offset), (addr), (count))