2 * Core routines and tables shareable across OS platforms.
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
7 * Copyright (c) 2000-2003 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
46 #include "aic79xx_osm.h"
47 #include "aic79xx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 #include <dev/aic7xxx/aic79xx_osm.h>
53 #include <dev/aic7xxx/aic79xx_inline.h>
54 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
57 /******************************** Globals *************************************/
58 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
59 uint32_t ahd_attach_to_HostRAID_controllers = 1;
61 /***************************** Lookup Tables **********************************/
62 char *ahd_chip_names[] =
71 * Hardware error codes.
73 struct ahd_hard_error_entry {
78 static struct ahd_hard_error_entry ahd_hard_errors[] = {
79 { DSCTMOUT, "Discard Timer has timed out" },
80 { ILLOPCODE, "Illegal Opcode in sequencer program" },
81 { SQPARERR, "Sequencer Parity Error" },
82 { DPARERR, "Data-path Parity Error" },
83 { MPARERR, "Scratch or SCB Memory Parity Error" },
84 { CIOPARERR, "CIOBUS Parity Error" },
86 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
88 static struct ahd_phase_table_entry ahd_phase_table[] =
90 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
91 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
92 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
93 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
94 { P_COMMAND, MSG_NOOP, "in Command phase" },
95 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
96 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
97 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
98 { P_BUSFREE, MSG_NOOP, "while idle" },
99 { 0, MSG_NOOP, "in unknown phase" }
103 * In most cases we only wish to itterate over real phases, so
104 * exclude the last element from the count.
106 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
108 /* Our Sequencer Program */
109 #include "aic79xx_seq.h"
111 /**************************** Function Declarations ***************************/
112 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
113 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
115 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
117 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
118 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
119 static void ahd_force_renegotiation(struct ahd_softc *ahd,
120 struct ahd_devinfo *devinfo);
122 static struct ahd_tmode_tstate*
123 ahd_alloc_tstate(struct ahd_softc *ahd,
124 u_int scsi_id, char channel);
125 #ifdef AHD_TARGET_MODE
126 static void ahd_free_tstate(struct ahd_softc *ahd,
127 u_int scsi_id, char channel, int force);
129 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
130 struct ahd_initiator_tinfo *,
134 static void ahd_update_neg_table(struct ahd_softc *ahd,
135 struct ahd_devinfo *devinfo,
136 struct ahd_transinfo *tinfo);
137 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
138 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
139 struct ahd_devinfo *devinfo);
140 static void ahd_scb_devinfo(struct ahd_softc *ahd,
141 struct ahd_devinfo *devinfo,
143 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
144 struct ahd_devinfo *devinfo,
146 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
147 struct ahd_devinfo *devinfo);
148 static void ahd_construct_sdtr(struct ahd_softc *ahd,
149 struct ahd_devinfo *devinfo,
150 u_int period, u_int offset);
151 static void ahd_construct_wdtr(struct ahd_softc *ahd,
152 struct ahd_devinfo *devinfo,
154 static void ahd_construct_ppr(struct ahd_softc *ahd,
155 struct ahd_devinfo *devinfo,
156 u_int period, u_int offset,
157 u_int bus_width, u_int ppr_options);
158 static void ahd_clear_msg_state(struct ahd_softc *ahd);
159 static void ahd_handle_message_phase(struct ahd_softc *ahd);
165 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
166 u_int msgval, int full);
167 static int ahd_parse_msg(struct ahd_softc *ahd,
168 struct ahd_devinfo *devinfo);
169 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
170 struct ahd_devinfo *devinfo);
171 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
172 struct ahd_devinfo *devinfo);
173 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
174 static void ahd_handle_devreset(struct ahd_softc *ahd,
175 struct ahd_devinfo *devinfo,
176 u_int lun, cam_status status,
177 char *message, int verbose_level);
178 #ifdef AHD_TARGET_MODE
179 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
180 struct ahd_devinfo *devinfo,
184 static u_int ahd_sglist_size(struct ahd_softc *ahd);
185 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
186 static bus_dmamap_callback_t
188 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
189 static int ahd_init_scbdata(struct ahd_softc *ahd);
190 static void ahd_fini_scbdata(struct ahd_softc *ahd);
191 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
192 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
193 static void ahd_add_col_list(struct ahd_softc *ahd,
194 struct scb *scb, u_int col_idx);
195 static void ahd_rem_col_list(struct ahd_softc *ahd,
197 static void ahd_chip_init(struct ahd_softc *ahd);
198 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
199 struct scb *prev_scb,
201 static int ahd_qinfifo_count(struct ahd_softc *ahd);
202 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
203 char channel, int lun, u_int tag,
204 role_t role, uint32_t status,
205 ahd_search_action action,
206 u_int *list_head, u_int *list_tail,
208 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
209 u_int tid_prev, u_int tid_cur,
211 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
213 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
214 u_int prev, u_int next, u_int tid);
215 static void ahd_reset_current_bus(struct ahd_softc *ahd);
216 static ahd_callback_t ahd_reset_poll;
217 static ahd_callback_t ahd_stat_timer;
219 static void ahd_dumpseq(struct ahd_softc *ahd);
221 static void ahd_loadseq(struct ahd_softc *ahd);
222 static int ahd_check_patch(struct ahd_softc *ahd,
223 struct patch **start_patch,
224 u_int start_instr, u_int *skip_addr);
225 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
227 static void ahd_download_instr(struct ahd_softc *ahd,
228 u_int instrptr, uint8_t *dconsts);
229 static int ahd_probe_stack_size(struct ahd_softc *ahd);
230 static int ahd_other_scb_timeout(struct ahd_softc *ahd,
232 struct scb *other_scb);
233 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
235 static void ahd_run_data_fifo(struct ahd_softc *ahd,
238 #ifdef AHD_TARGET_MODE
239 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
240 struct ahd_tmode_lstate *lstate,
244 static void ahd_update_scsiid(struct ahd_softc *ahd,
246 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
247 struct target_cmd *cmd);
250 /******************************** Private Inlines *****************************/
251 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
252 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
253 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
256 ahd_assert_atn(struct ahd_softc *ahd)
258 ahd_outb(ahd, SCSISIGO, ATNO);
262 * Determine if the current connection has a packetized
263 * agreement. This does not necessarily mean that we
264 * are currently in a packetized transfer. We could
265 * just as easily be sending or receiving a message.
268 ahd_currently_packetized(struct ahd_softc *ahd)
270 ahd_mode_state saved_modes;
273 saved_modes = ahd_save_modes(ahd);
274 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
276 * The packetized bit refers to the last
277 * connection, not the current one. Check
278 * for non-zero LQISTATE instead.
280 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
281 packetized = ahd_inb(ahd, LQISTATE) != 0;
283 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
284 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
286 ahd_restore_modes(ahd, saved_modes);
291 ahd_set_active_fifo(struct ahd_softc *ahd)
295 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
296 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
297 switch (active_fifo) {
300 ahd_set_modes(ahd, active_fifo, active_fifo);
307 /************************* Sequencer Execution Control ************************/
309 * Restart the sequencer program from address zero
312 ahd_restart(struct ahd_softc *ahd)
317 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
319 /* No more pending messages */
320 ahd_clear_msg_state(ahd);
321 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
322 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
323 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
324 ahd_outb(ahd, SEQINTCTL, 0);
325 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
326 ahd_outb(ahd, SEQ_FLAGS, 0);
327 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
328 ahd_outb(ahd, SAVED_LUN, 0xFF);
331 * Ensure that the sequencer's idea of TQINPOS
332 * matches our own. The sequencer increments TQINPOS
333 * only after it sees a DMA complete and a reset could
334 * occur before the increment leaving the kernel to believe
335 * the command arrived but the sequencer to not.
337 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
339 /* Always allow reselection */
340 ahd_outb(ahd, SCSISEQ1,
341 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
342 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
345 * Clear any pending sequencer interrupt. It is no
346 * longer relevant since we're resetting the Program
349 ahd_outb(ahd, CLRINT, CLRSEQINT);
351 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
356 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
358 ahd_mode_state saved_modes;
361 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
362 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
364 saved_modes = ahd_save_modes(ahd);
365 ahd_set_modes(ahd, fifo, fifo);
366 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
367 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
368 ahd_outb(ahd, CCSGCTL, CCSGRESET);
369 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
370 ahd_outb(ahd, SG_STATE, 0);
371 ahd_restore_modes(ahd, saved_modes);
374 /************************* Input/Output Queues ********************************/
376 * Flush and completed commands that are sitting in the command
377 * complete queues down on the chip but have yet to be dma'ed back up.
380 ahd_flush_qoutfifo(struct ahd_softc *ahd)
383 ahd_mode_state saved_modes;
389 saved_modes = ahd_save_modes(ahd);
392 * Flush the good status FIFO for completed packetized commands.
394 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
395 saved_scbptr = ahd_get_scbptr(ahd);
396 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
400 scbid = ahd_inw(ahd, GSFIFO);
401 scb = ahd_lookup_scb(ahd, scbid);
403 printf("%s: Warning - GSFIFO SCB %d invalid\n",
404 ahd_name(ahd), scbid);
405 AHD_CORRECTABLE_ERROR(ahd);
409 * Determine if this transaction is still active in
410 * any FIFO. If it is, we must flush that FIFO to
411 * the host before completing the command.
415 for (i = 0; i < 2; i++) {
416 /* Toggle to the other mode. */
418 ahd_set_modes(ahd, fifo_mode, fifo_mode);
420 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
423 ahd_run_data_fifo(ahd, scb);
426 * Running this FIFO may cause a CFG4DATA for
427 * this same transaction to assert in the other
428 * FIFO or a new snapshot SAVEPTRS interrupt
429 * in this FIFO. Even running a FIFO may not
430 * clear the transaction if we are still waiting
431 * for data to drain to the host. We must loop
432 * until the transaction is not active in either
433 * FIFO just to be sure. Reset our loop counter
434 * so we will visit both FIFOs again before
435 * declaring this transaction finished. We
436 * also delay a bit so that status has a chance
437 * to change before we look at this FIFO again.
442 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
443 ahd_set_scbptr(ahd, scbid);
444 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
445 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
446 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
447 & SG_LIST_NULL) != 0)) {
451 * The transfer completed with a residual.
452 * Place this SCB on the complete DMA list
453 * so that we update our in-core copy of the
454 * SCB before completing the command.
456 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
457 ahd_outb(ahd, SCB_SGPTR,
458 ahd_inb_scbram(ahd, SCB_SGPTR)
460 ahd_outw(ahd, SCB_TAG, scbid);
461 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
462 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
463 if (SCBID_IS_NULL(comp_head)) {
464 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
465 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
469 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
470 ahd_set_scbptr(ahd, tail);
471 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
472 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
473 ahd_set_scbptr(ahd, scbid);
476 ahd_complete_scb(ahd, scb);
478 ahd_set_scbptr(ahd, saved_scbptr);
481 * Setup for command channel portion of flush.
483 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
486 * Wait for any inprogress DMA to complete and clear DMA state
487 * if this if for an SCB in the qinfifo.
489 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
490 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
491 if ((ccscbctl & ARRDONE) != 0)
493 } else if ((ccscbctl & CCSCBDONE) != 0)
498 * We leave the sequencer to cleanup in the case of DMA's to
499 * update the qoutfifo. In all other cases (DMA's to the
500 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
501 * we disable the DMA engine so that the sequencer will not
502 * attempt to handle the DMA completion.
504 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
505 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
508 * Complete any SCBs that just finished
509 * being DMA'ed into the qoutfifo.
511 ahd_run_qoutfifo(ahd);
513 saved_scbptr = ahd_get_scbptr(ahd);
515 * Manually update/complete any completed SCBs that are waiting to be
516 * DMA'ed back up to the host.
518 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
519 while (!SCBID_IS_NULL(scbid)) {
523 ahd_set_scbptr(ahd, scbid);
524 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
525 scb = ahd_lookup_scb(ahd, scbid);
527 printf("%s: Warning - DMA-up and complete "
528 "SCB %d invalid\n", ahd_name(ahd), scbid);
529 AHD_CORRECTABLE_ERROR(ahd);
532 hscb_ptr = (uint8_t *)scb->hscb;
533 for (i = 0; i < sizeof(struct hardware_scb); i++)
534 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
536 ahd_complete_scb(ahd, scb);
539 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
540 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
542 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
543 while (!SCBID_IS_NULL(scbid)) {
544 ahd_set_scbptr(ahd, scbid);
545 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
546 scb = ahd_lookup_scb(ahd, scbid);
548 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
549 ahd_name(ahd), scbid);
550 AHD_CORRECTABLE_ERROR(ahd);
554 ahd_complete_scb(ahd, scb);
557 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
559 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
560 while (!SCBID_IS_NULL(scbid)) {
561 ahd_set_scbptr(ahd, scbid);
562 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
563 scb = ahd_lookup_scb(ahd, scbid);
565 printf("%s: Warning - Complete SCB %d invalid\n",
566 ahd_name(ahd), scbid);
567 AHD_CORRECTABLE_ERROR(ahd);
571 ahd_complete_scb(ahd, scb);
574 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
579 ahd_set_scbptr(ahd, saved_scbptr);
580 ahd_restore_modes(ahd, saved_modes);
581 ahd->flags |= AHD_UPDATE_PEND_CMDS;
585 * Determine if an SCB for a packetized transaction
586 * is active in a FIFO.
589 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
593 * The FIFO is only active for our transaction if
594 * the SCBPTR matches the SCB's ID and the firmware
595 * has installed a handler for the FIFO or we have
596 * a pending SAVEPTRS or CFG4DATA interrupt.
598 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
599 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
600 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
607 * Run a data fifo to completion for a transaction we know
608 * has completed across the SCSI bus (good status has been
609 * received). We are already set to the correct FIFO mode
610 * on entry to this routine.
612 * This function attempts to operate exactly as the firmware
613 * would when running this FIFO. Care must be taken to update
614 * this routine any time the firmware's FIFO algorithm is
618 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
622 seqintsrc = ahd_inb(ahd, SEQINTSRC);
623 if ((seqintsrc & CFG4DATA) != 0) {
628 * Clear full residual flag.
630 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
631 ahd_outb(ahd, SCB_SGPTR, sgptr);
634 * Load datacnt and address.
636 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
637 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
639 ahd_outb(ahd, SG_STATE, 0);
641 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
642 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
643 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
644 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
645 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
648 * Initialize Residual Fields.
650 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
651 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
654 * Mark the SCB as having a FIFO in use.
656 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
657 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
660 * Install a "fake" handler for this FIFO.
662 ahd_outw(ahd, LONGJMP_ADDR, 0);
665 * Notify the hardware that we have satisfied
666 * this sequencer interrupt.
668 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
669 } else if ((seqintsrc & SAVEPTRS) != 0) {
673 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
675 * Snapshot Save Pointers. All that
676 * is necessary to clear the snapshot
683 * Disable S/G fetch so the DMA engine
684 * is available to future users.
686 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
687 ahd_outb(ahd, CCSGCTL, 0);
688 ahd_outb(ahd, SG_STATE, 0);
691 * Flush the data FIFO. Strickly only
692 * necessary for Rev A parts.
694 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
697 * Calculate residual.
699 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
700 resid = ahd_inl(ahd, SHCNT);
701 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
702 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
703 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
705 * Must back up to the correct S/G element.
706 * Typically this just means resetting our
707 * low byte to the offset in the SG_CACHE,
708 * but if we wrapped, we have to correct
709 * the other bytes of the sgptr too.
711 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
712 && (sgptr & 0x80) == 0)
715 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
717 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
718 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
719 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
720 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
721 sgptr | SG_LIST_NULL);
726 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
727 ahd_outl(ahd, SCB_DATACNT, resid);
728 ahd_outl(ahd, SCB_SGPTR, sgptr);
729 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
730 ahd_outb(ahd, SEQIMODE,
731 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
733 * If the data is to the SCSI bus, we are
734 * done, otherwise wait for FIFOEMP.
736 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
738 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
745 * Disable S/G fetch so the DMA engine
746 * is available to future users. We won't
747 * be using the DMA engine to load segments.
749 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
750 ahd_outb(ahd, CCSGCTL, 0);
751 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
755 * Wait for the DMA engine to notice that the
756 * host transfer is enabled and that there is
757 * space in the S/G FIFO for new segments before
758 * loading more segments.
760 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
761 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
763 * Determine the offset of the next S/G
766 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
767 sgptr &= SG_PTR_MASK;
768 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
769 struct ahd_dma64_seg *sg;
771 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
772 data_addr = sg->addr;
774 sgptr += sizeof(*sg);
776 struct ahd_dma_seg *sg;
778 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
779 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
781 data_addr |= sg->addr;
783 sgptr += sizeof(*sg);
787 * Update residual information.
789 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
790 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
795 if (data_len & AHD_DMA_LAST_SEG) {
797 ahd_outb(ahd, SG_STATE, 0);
799 ahd_outq(ahd, HADDR, data_addr);
800 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
801 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
804 * Advertise the segment to the hardware.
806 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
807 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
809 * Use SCSIENWRDIS so that SCSIEN
810 * is never modified by this
813 dfcntrl |= SCSIENWRDIS;
815 ahd_outb(ahd, DFCNTRL, dfcntrl);
817 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
819 * Transfer completed to the end of SG list
820 * and has flushed to the host.
822 ahd_outb(ahd, SCB_SGPTR,
823 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
825 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
828 * Clear any handler for this FIFO, decrement
829 * the FIFO use count for the SCB, and release
832 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
833 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
834 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
835 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
840 * Look for entries in the QoutFIFO that have completed.
841 * The valid_tag completion field indicates the validity
842 * of the entry - the valid value toggles each time through
843 * the queue. We use the sg_status field in the completion
844 * entry to avoid referencing the hscb if the completion
845 * occurred with no errors and no residual. sg_status is
846 * a copy of the first byte (little endian) of the sgptr
850 ahd_run_qoutfifo(struct ahd_softc *ahd)
852 struct ahd_completion *completion;
856 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
857 panic("ahd_run_qoutfifo recursion");
858 ahd->flags |= AHD_RUNNING_QOUTFIFO;
859 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
861 completion = &ahd->qoutfifo[ahd->qoutfifonext];
863 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
866 scb_index = aic_le16toh(completion->tag);
867 scb = ahd_lookup_scb(ahd, scb_index);
869 printf("%s: WARNING no command for scb %d "
870 "(cmdcmplt)\nQOUTPOS = %d\n",
871 ahd_name(ahd), scb_index,
873 AHD_CORRECTABLE_ERROR(ahd);
874 ahd_dump_card_state(ahd);
875 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
876 ahd_handle_scb_status(ahd, scb);
881 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
882 if (ahd->qoutfifonext == 0)
883 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
885 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
888 /************************* Interrupt Handling *********************************/
890 ahd_handle_hwerrint(struct ahd_softc *ahd)
893 * Some catastrophic hardware error has occurred.
894 * Print it for the user and disable the controller.
899 error = ahd_inb(ahd, ERROR);
900 for (i = 0; i < num_errors; i++) {
901 if ((error & ahd_hard_errors[i].errno) != 0) {
902 printf("%s: hwerrint, %s\n",
903 ahd_name(ahd), ahd_hard_errors[i].errmesg);
904 AHD_UNCORRECTABLE_ERROR(ahd);
908 ahd_dump_card_state(ahd);
911 /* Tell everyone that this HBA is no longer available */
912 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
913 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
916 /* Tell the system that this controller has gone away. */
921 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
926 * Save the sequencer interrupt code and clear the SEQINT
927 * bit. We will unpause the sequencer, if appropriate,
928 * after servicing the request.
930 seqintcode = ahd_inb(ahd, SEQINTCODE);
931 ahd_outb(ahd, CLRINT, CLRSEQINT);
932 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
934 * Unpause the sequencer and let it clear
935 * SEQINT by writing NO_SEQINT to it. This
936 * will cause the sequencer to be paused again,
937 * which is the expected state of this routine.
940 while (!ahd_is_paused(ahd))
942 ahd_outb(ahd, CLRINT, CLRSEQINT);
944 ahd_update_modes(ahd);
946 if ((ahd_debug & AHD_SHOW_MISC) != 0)
947 printf("%s: Handle Seqint Called for code %d\n",
948 ahd_name(ahd), seqintcode);
950 switch (seqintcode) {
951 case ENTERING_NONPACK:
956 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
957 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
958 scbid = ahd_get_scbptr(ahd);
959 scb = ahd_lookup_scb(ahd, scbid);
962 * Somehow need to know if this
963 * is from a selection or reselection.
964 * From that, we can determine target
965 * ID so we at least have an I_T nexus.
968 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
969 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
970 ahd_outb(ahd, SEQ_FLAGS, 0x0);
972 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
973 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
975 * Phase change after read stream with
976 * CRC error with P0 asserted on last
980 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
981 printf("%s: Assuming LQIPHASE_NLQ with "
982 "P0 assertion\n", ahd_name(ahd));
986 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
987 printf("%s: Entering NONPACK\n", ahd_name(ahd));
992 printf("%s: Invalid Sequencer interrupt occurred.\n",
994 ahd_dump_card_state(ahd);
995 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
996 AHD_UNCORRECTABLE_ERROR(ahd);
1003 scbid = ahd_get_scbptr(ahd);
1004 scb = ahd_lookup_scb(ahd, scbid);
1006 ahd_print_path(ahd, scb);
1008 printf("%s: ", ahd_name(ahd));
1009 printf("SCB %d Packetized Status Overrun", scbid);
1010 ahd_dump_card_state(ahd);
1011 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1012 AHD_UNCORRECTABLE_ERROR(ahd);
1015 case CFG4ISTAT_INTR:
1020 scbid = ahd_get_scbptr(ahd);
1021 scb = ahd_lookup_scb(ahd, scbid);
1023 ahd_dump_card_state(ahd);
1024 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1025 AHD_FATAL_ERROR(ahd);
1026 panic("For safety");
1028 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1029 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1030 ahd_outb(ahd, HCNT + 2, 0);
1031 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1032 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1039 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1040 printf("%s: ILLEGAL_PHASE 0x%x\n",
1041 ahd_name(ahd), bus_phase);
1043 switch (bus_phase) {
1051 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1052 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1053 AHD_UNCORRECTABLE_ERROR(ahd);
1057 struct ahd_devinfo devinfo;
1059 struct ahd_tmode_tstate *tstate;
1063 * If a target takes us into the command phase
1064 * assume that it has been externally reset and
1065 * has thus lost our previous packetized negotiation
1066 * agreement. Since we have not sent an identify
1067 * message and may not have fully qualified the
1068 * connection, we change our command to TUR, assert
1069 * ATN and ABORT the task when we go to message in
1070 * phase. The OSM will see the REQUEUE_REQUEST
1071 * status and retry the command.
1073 scbid = ahd_get_scbptr(ahd);
1074 scb = ahd_lookup_scb(ahd, scbid);
1076 AHD_CORRECTABLE_ERROR(ahd);
1077 printf("Invalid phase with no valid SCB. "
1078 "Resetting bus.\n");
1079 ahd_reset_channel(ahd, 'A',
1080 /*Initiate Reset*/TRUE);
1083 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1084 SCB_GET_TARGET(ahd, scb),
1086 SCB_GET_CHANNEL(ahd, scb),
1088 ahd_fetch_transinfo(ahd,
1093 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1094 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1095 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1096 /*offset*/0, /*ppr_options*/0,
1097 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1098 ahd_outb(ahd, SCB_CDB_STORE, 0);
1099 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1100 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1101 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1102 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1103 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1104 ahd_outb(ahd, SCB_CDB_LEN, 6);
1105 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1106 scb->hscb->control |= MK_MESSAGE;
1107 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1108 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1109 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1111 * The lun is 0, regardless of the SCB's lun
1112 * as we have not sent an identify message.
1114 ahd_outb(ahd, SAVED_LUN, 0);
1115 ahd_outb(ahd, SEQ_FLAGS, 0);
1116 ahd_assert_atn(ahd);
1117 scb->flags &= ~SCB_PACKETIZED;
1118 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1119 ahd_freeze_devq(ahd, scb);
1120 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
1121 aic_freeze_scb(scb);
1124 * Allow the sequencer to continue with
1125 * non-pack processing.
1127 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1128 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1129 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1130 ahd_outb(ahd, CLRLQOINT1, 0);
1133 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1134 ahd_print_path(ahd, scb);
1135 AHD_CORRECTABLE_ERROR(ahd);
1136 printf("Unexpected command phase from "
1137 "packetized target\n");
1151 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1152 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1153 ahd_inb(ahd, MODE_PTR));
1156 scb_index = ahd_get_scbptr(ahd);
1157 scb = ahd_lookup_scb(ahd, scb_index);
1160 * Attempt to transfer to an SCB that is
1163 ahd_assert_atn(ahd);
1164 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1165 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1166 ahd->msgout_len = 1;
1167 ahd->msgout_index = 0;
1168 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1170 * Clear status received flag to prevent any
1171 * attempt to complete this bogus SCB.
1173 ahd_outb(ahd, SCB_CONTROL,
1174 ahd_inb_scbram(ahd, SCB_CONTROL)
1179 case DUMP_CARD_STATE:
1181 ahd_dump_card_state(ahd);
1187 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1188 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1189 "SG_CACHE_SHADOW = 0x%x\n",
1190 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1191 ahd_inb(ahd, SG_CACHE_SHADOW));
1194 ahd_reinitialize_dataptrs(ahd);
1199 struct ahd_devinfo devinfo;
1202 * The sequencer has encountered a message phase
1203 * that requires host assistance for completion.
1204 * While handling the message phase(s), we will be
1205 * notified by the sequencer after each byte is
1206 * transferred so we can track bus phase changes.
1208 * If this is the first time we've seen a HOST_MSG_LOOP
1209 * interrupt, initialize the state of the host message
1212 ahd_fetch_devinfo(ahd, &devinfo);
1213 if (ahd->msg_type == MSG_TYPE_NONE) {
1218 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1219 if (bus_phase != P_MESGIN
1220 && bus_phase != P_MESGOUT) {
1221 printf("ahd_intr: HOST_MSG_LOOP bad "
1222 "phase 0x%x\n", bus_phase);
1223 AHD_CORRECTABLE_ERROR(ahd);
1225 * Probably transitioned to bus free before
1226 * we got here. Just punt the message.
1228 ahd_dump_card_state(ahd);
1229 ahd_clear_intstat(ahd);
1234 scb_index = ahd_get_scbptr(ahd);
1235 scb = ahd_lookup_scb(ahd, scb_index);
1236 if (devinfo.role == ROLE_INITIATOR) {
1237 if (bus_phase == P_MESGOUT)
1238 ahd_setup_initiator_msgout(ahd,
1243 MSG_TYPE_INITIATOR_MSGIN;
1244 ahd->msgin_index = 0;
1247 #ifdef AHD_TARGET_MODE
1249 if (bus_phase == P_MESGOUT) {
1251 MSG_TYPE_TARGET_MSGOUT;
1252 ahd->msgin_index = 0;
1255 ahd_setup_target_msgin(ahd,
1262 ahd_handle_message_phase(ahd);
1267 /* Ensure we don't leave the selection hardware on */
1268 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1269 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1271 printf("%s:%c:%d: no active SCB for reconnecting "
1272 "target - issuing BUS DEVICE RESET\n",
1273 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1274 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1275 "REG0 == 0x%x ACCUM = 0x%x\n",
1276 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1277 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1278 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1280 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1281 ahd_find_busy_tcl(ahd,
1282 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1283 ahd_inb(ahd, SAVED_LUN))),
1284 ahd_inw(ahd, SINDEX));
1285 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1286 "SCB_CONTROL == 0x%x\n",
1287 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1288 ahd_inb_scbram(ahd, SCB_LUN),
1289 ahd_inb_scbram(ahd, SCB_CONTROL));
1290 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1291 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1292 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1293 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1294 ahd_dump_card_state(ahd);
1295 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1296 ahd->msgout_len = 1;
1297 ahd->msgout_index = 0;
1298 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1299 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1300 ahd_assert_atn(ahd);
1303 case PROTO_VIOLATION:
1305 ahd_handle_proto_violation(ahd);
1310 struct ahd_devinfo devinfo;
1312 ahd_fetch_devinfo(ahd, &devinfo);
1313 ahd_handle_ign_wide_residue(ahd, &devinfo);
1320 lastphase = ahd_inb(ahd, LASTPHASE);
1321 printf("%s:%c:%d: unknown scsi bus phase %x, "
1322 "lastphase = 0x%x. Attempting to continue\n",
1324 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1325 lastphase, ahd_inb(ahd, SCSISIGI));
1326 AHD_CORRECTABLE_ERROR(ahd);
1329 case MISSED_BUSFREE:
1333 lastphase = ahd_inb(ahd, LASTPHASE);
1334 printf("%s:%c:%d: Missed busfree. "
1335 "Lastphase = 0x%x, Curphase = 0x%x\n",
1337 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1338 lastphase, ahd_inb(ahd, SCSISIGI));
1339 AHD_CORRECTABLE_ERROR(ahd);
1346 * When the sequencer detects an overrun, it
1347 * places the controller in "BITBUCKET" mode
1348 * and allows the target to complete its transfer.
1349 * Unfortunately, none of the counters get updated
1350 * when the controller is in this mode, so we have
1351 * no way of knowing how large the overrun was.
1359 scbindex = ahd_get_scbptr(ahd);
1360 scb = ahd_lookup_scb(ahd, scbindex);
1362 lastphase = ahd_inb(ahd, LASTPHASE);
1363 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1364 ahd_print_path(ahd, scb);
1365 printf("data overrun detected %s. Tag == 0x%x.\n",
1366 ahd_lookup_phase_entry(lastphase)->phasemsg,
1368 ahd_print_path(ahd, scb);
1369 printf("%s seen Data Phase. Length = %ld. "
1371 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1372 ? "Have" : "Haven't",
1373 aic_get_transfer_length(scb), scb->sg_count);
1374 ahd_dump_sglist(scb);
1379 * Set this and it will take effect when the
1380 * target does a command complete.
1382 ahd_freeze_devq(ahd, scb);
1383 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1384 aic_freeze_scb(scb);
1389 struct ahd_devinfo devinfo;
1393 ahd_fetch_devinfo(ahd, &devinfo);
1394 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1395 ahd_name(ahd), devinfo.channel, devinfo.target,
1397 scbid = ahd_get_scbptr(ahd);
1398 scb = ahd_lookup_scb(ahd, scbid);
1399 AHD_CORRECTABLE_ERROR(ahd);
1401 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1403 * Ensure that we didn't put a second instance of this
1404 * SCB into the QINFIFO.
1406 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1407 SCB_GET_CHANNEL(ahd, scb),
1408 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1409 ROLE_INITIATOR, /*status*/0,
1411 ahd_outb(ahd, SCB_CONTROL,
1412 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1415 case TASKMGMT_FUNC_COMPLETE:
1420 scbid = ahd_get_scbptr(ahd);
1421 scb = ahd_lookup_scb(ahd, scbid);
1427 ahd_print_path(ahd, scb);
1428 printf("Task Management Func 0x%x Complete\n",
1429 scb->hscb->task_management);
1430 lun = CAM_LUN_WILDCARD;
1431 tag = SCB_LIST_NULL;
1433 switch (scb->hscb->task_management) {
1434 case SIU_TASKMGMT_ABORT_TASK:
1435 tag = SCB_GET_TAG(scb);
1436 case SIU_TASKMGMT_ABORT_TASK_SET:
1437 case SIU_TASKMGMT_CLEAR_TASK_SET:
1438 lun = scb->hscb->lun;
1439 error = CAM_REQ_ABORTED;
1440 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1441 'A', lun, tag, ROLE_INITIATOR,
1444 case SIU_TASKMGMT_LUN_RESET:
1445 lun = scb->hscb->lun;
1446 case SIU_TASKMGMT_TARGET_RESET:
1448 struct ahd_devinfo devinfo;
1450 ahd_scb_devinfo(ahd, &devinfo, scb);
1451 error = CAM_BDR_SENT;
1452 ahd_handle_devreset(ahd, &devinfo, lun,
1454 lun != CAM_LUN_WILDCARD
1457 /*verbose_level*/0);
1461 panic("Unexpected TaskMgmt Func\n");
1467 case TASKMGMT_CMD_CMPLT_OKAY:
1473 * An ABORT TASK TMF failed to be delivered before
1474 * the targeted command completed normally.
1476 scbid = ahd_get_scbptr(ahd);
1477 scb = ahd_lookup_scb(ahd, scbid);
1480 * Remove the second instance of this SCB from
1481 * the QINFIFO if it is still there.
1483 ahd_print_path(ahd, scb);
1484 printf("SCB completes before TMF\n");
1486 * Handle losing the race. Wait until any
1487 * current selection completes. We will then
1488 * set the TMF back to zero in this SCB so that
1489 * the sequencer doesn't bother to issue another
1490 * sequencer interrupt for its completion.
1492 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1493 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1494 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1496 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1497 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1498 SCB_GET_CHANNEL(ahd, scb),
1499 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1500 ROLE_INITIATOR, /*status*/0,
1509 printf("%s: Tracepoint %d\n", ahd_name(ahd),
1510 seqintcode - TRACEPOINT0);
1515 ahd_handle_hwerrint(ahd);
1518 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1523 * The sequencer is paused immediately on
1524 * a SEQINT, so we should restart it when
1531 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1542 ahd_update_modes(ahd);
1543 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1545 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1546 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1547 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1548 lqistat1 = ahd_inb(ahd, LQISTAT1);
1549 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1550 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1551 if ((status0 & (SELDI|SELDO)) != 0) {
1554 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1555 simode0 = ahd_inb(ahd, SIMODE0);
1556 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1557 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1559 scbid = ahd_get_scbptr(ahd);
1560 scb = ahd_lookup_scb(ahd, scbid);
1562 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1565 if ((status0 & IOERR) != 0) {
1568 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1569 printf("%s: Transceiver State Has Changed to %s mode\n",
1570 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1571 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1573 * A change in I/O mode is equivalent to a bus reset.
1575 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1577 ahd_setup_iocell_workaround(ahd);
1579 } else if ((status0 & OVERRUN) != 0) {
1580 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1582 AHD_CORRECTABLE_ERROR(ahd);
1583 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1584 } else if ((status & SCSIRSTI) != 0) {
1585 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1586 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1587 AHD_UNCORRECTABLE_ERROR(ahd);
1588 } else if ((status & SCSIPERR) != 0) {
1589 /* Make sure the sequencer is in a safe location. */
1590 ahd_clear_critical_section(ahd);
1592 ahd_handle_transmission_error(ahd);
1593 } else if (lqostat0 != 0) {
1594 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1595 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1596 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1597 ahd_outb(ahd, CLRLQOINT1, 0);
1598 } else if ((status & SELTO) != 0) {
1601 /* Stop the selection */
1602 ahd_outb(ahd, SCSISEQ0, 0);
1604 /* Make sure the sequencer is in a safe location. */
1605 ahd_clear_critical_section(ahd);
1607 /* No more pending messages */
1608 ahd_clear_msg_state(ahd);
1610 /* Clear interrupt state */
1611 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1614 * Although the driver does not care about the
1615 * 'Selection in Progress' status bit, the busy
1616 * LED does. SELINGO is only cleared by a successful
1617 * selection, so we must manually clear it to insure
1618 * the LED turns off just incase no future successful
1619 * selections occur (e.g. no devices on the bus).
1621 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1623 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1624 scb = ahd_lookup_scb(ahd, scbid);
1626 printf("%s: ahd_intr - referenced scb not "
1627 "valid during SELTO scb(0x%x)\n",
1628 ahd_name(ahd), scbid);
1629 ahd_dump_card_state(ahd);
1630 AHD_UNCORRECTABLE_ERROR(ahd);
1632 struct ahd_devinfo devinfo;
1634 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1635 ahd_print_path(ahd, scb);
1636 printf("Saw Selection Timeout for SCB 0x%x\n",
1640 ahd_scb_devinfo(ahd, &devinfo, scb);
1641 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1642 ahd_freeze_devq(ahd, scb);
1645 * Cancel any pending transactions on the device
1646 * now that it seems to be missing. This will
1647 * also revert us to async/narrow transfers until
1648 * we can renegotiate with the device.
1650 ahd_handle_devreset(ahd, &devinfo,
1653 "Selection Timeout",
1654 /*verbose_level*/1);
1656 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1657 ahd_iocell_first_selection(ahd);
1659 } else if ((status0 & (SELDI|SELDO)) != 0) {
1660 ahd_iocell_first_selection(ahd);
1662 } else if (status3 != 0) {
1663 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1664 ahd_name(ahd), status3);
1665 AHD_CORRECTABLE_ERROR(ahd);
1666 ahd_outb(ahd, CLRSINT3, status3);
1667 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1668 /* Make sure the sequencer is in a safe location. */
1669 ahd_clear_critical_section(ahd);
1671 ahd_handle_lqiphase_error(ahd, lqistat1);
1672 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1674 * This status can be delayed during some
1675 * streaming operations. The SCSIPHASE
1676 * handler has already dealt with this case
1677 * so just clear the error.
1679 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1680 } else if ((status & BUSFREE) != 0
1681 || (lqistat1 & LQOBUSFREE) != 0) {
1689 * Clear our selection hardware as soon as possible.
1690 * We may have an entry in the waiting Q for this target,
1691 * that is affected by this busfree and we don't want to
1692 * go about selecting the target while we handle the event.
1694 ahd_outb(ahd, SCSISEQ0, 0);
1696 /* Make sure the sequencer is in a safe location. */
1697 ahd_clear_critical_section(ahd);
1700 * Determine what we were up to at the time of
1703 mode = AHD_MODE_SCSI;
1704 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1705 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1706 switch (busfreetime) {
1713 mode = busfreetime == BUSFREE_DFF0
1714 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1715 ahd_set_modes(ahd, mode, mode);
1716 scbid = ahd_get_scbptr(ahd);
1717 scb = ahd_lookup_scb(ahd, scbid);
1719 printf("%s: Invalid SCB %d in DFF%d "
1720 "during unexpected busfree\n",
1721 ahd_name(ahd), scbid, mode);
1723 AHD_CORRECTABLE_ERROR(ahd);
1725 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1735 packetized = (lqostat1 & LQOBUSFREE) != 0;
1737 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1738 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1739 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1740 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1742 * Assume packetized if we are not
1743 * on the bus in a non-packetized
1744 * capacity and any pending selection
1745 * was a packetized selection.
1752 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1753 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1757 * Busfrees that occur in non-packetized phases are
1758 * handled by the nonpkt_busfree handler.
1760 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1761 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1764 restart = ahd_handle_nonpkt_busfree(ahd);
1767 * Clear the busfree interrupt status. The setting of
1768 * the interrupt is a pulse, so in a perfect world, we
1769 * would not need to muck with the ENBUSFREE logic. This
1770 * would ensure that if the bus moves on to another
1771 * connection, busfree protection is still in force. If
1772 * BUSFREEREV is broken, however, we must manually clear
1773 * the ENBUSFREE if the busfree occurred during a non-pack
1774 * connection so that we don't get false positives during
1775 * future, packetized, connections.
1777 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1779 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1780 ahd_outb(ahd, SIMODE1,
1781 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1784 ahd_clear_fifo(ahd, mode);
1786 ahd_clear_msg_state(ahd);
1787 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1794 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1795 ahd_name(ahd), status);
1796 ahd_dump_card_state(ahd);
1797 ahd_clear_intstat(ahd);
1803 ahd_handle_transmission_error(struct ahd_softc *ahd)
1816 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1817 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1818 ahd_inb(ahd, LQISTAT2);
1819 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1820 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1823 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1824 lqistate = ahd_inb(ahd, LQISTATE);
1825 if ((lqistate >= 0x1E && lqistate <= 0x24)
1826 || (lqistate == 0x29)) {
1828 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1829 printf("%s: NLQCRC found via LQISTATE\n",
1833 lqistat1 |= LQICRCI_NLQ;
1835 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1838 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1839 lastphase = ahd_inb(ahd, LASTPHASE);
1840 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1841 perrdiag = ahd_inb(ahd, PERRDIAG);
1842 msg_out = MSG_INITIATOR_DET_ERR;
1843 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1846 * Try to find the SCB associated with this error.
1850 || (lqistat1 & LQICRCI_NLQ) != 0) {
1851 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1852 ahd_set_active_fifo(ahd);
1853 scbid = ahd_get_scbptr(ahd);
1854 scb = ahd_lookup_scb(ahd, scbid);
1855 if (scb != NULL && SCB_IS_SILENT(scb))
1860 if (silent == FALSE) {
1861 printf("%s: Transmission error detected\n", ahd_name(ahd));
1862 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1863 ahd_lastphase_print(lastphase, &cur_col, 50);
1864 ahd_scsisigi_print(curphase, &cur_col, 50);
1865 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1867 AHD_CORRECTABLE_ERROR(ahd);
1868 ahd_dump_card_state(ahd);
1871 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1872 if (silent == FALSE) {
1873 printf("%s: Gross protocol error during incoming "
1874 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1875 ahd_name(ahd), lqistat1);
1876 AHD_UNCORRECTABLE_ERROR(ahd);
1878 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1880 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1882 * A CRC error has been detected on an incoming LQ.
1883 * The bus is currently hung on the last ACK.
1884 * Hit LQIRETRY to release the last ack, and
1885 * wait for the sequencer to determine that ATNO
1886 * is asserted while in message out to take us
1887 * to our host message loop. No NONPACKREQ or
1888 * LQIPHASE type errors will occur in this
1889 * scenario. After this first LQIRETRY, the LQI
1890 * manager will be in ISELO where it will
1891 * happily sit until another packet phase begins.
1892 * Unexpected bus free detection is enabled
1893 * through any phases that occur after we release
1894 * this last ack until the LQI manager sees a
1895 * packet phase. This implies we may have to
1896 * ignore a perfectly valid "unexected busfree"
1897 * after our "initiator detected error" message is
1898 * sent. A busfree is the expected response after
1899 * we tell the target that it's L_Q was corrupted.
1900 * (SPI4R09 10.7.3.3.3)
1902 ahd_outb(ahd, LQCTL2, LQIRETRY);
1903 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1904 AHD_CORRECTABLE_ERROR(ahd);
1905 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1907 * We detected a CRC error in a NON-LQ packet.
1908 * The hardware has varying behavior in this situation
1909 * depending on whether this packet was part of a
1913 * The hardware has already acked the complete packet.
1914 * If the target honors our outstanding ATN condition,
1915 * we should be (or soon will be) in MSGOUT phase.
1916 * This will trigger the LQIPHASE_LQ status bit as the
1917 * hardware was expecting another LQ. Unexpected
1918 * busfree detection is enabled. Once LQIPHASE_LQ is
1919 * true (first entry into host message loop is much
1920 * the same), we must clear LQIPHASE_LQ and hit
1921 * LQIRETRY so the hardware is ready to handle
1922 * a future LQ. NONPACKREQ will not be asserted again
1923 * once we hit LQIRETRY until another packet is
1924 * processed. The target may either go busfree
1925 * or start another packet in response to our message.
1927 * Read Streaming P0 asserted:
1928 * If we raise ATN and the target completes the entire
1929 * stream (P0 asserted during the last packet), the
1930 * hardware will ack all data and return to the ISTART
1931 * state. When the target reponds to our ATN condition,
1932 * LQIPHASE_LQ will be asserted. We should respond to
1933 * this with an LQIRETRY to prepare for any future
1934 * packets. NONPACKREQ will not be asserted again
1935 * once we hit LQIRETRY until another packet is
1936 * processed. The target may either go busfree or
1937 * start another packet in response to our message.
1938 * Busfree detection is enabled.
1940 * Read Streaming P0 not asserted:
1941 * If we raise ATN and the target transitions to
1942 * MSGOUT in or after a packet where P0 is not
1943 * asserted, the hardware will assert LQIPHASE_NLQ.
1944 * We should respond to the LQIPHASE_NLQ with an
1945 * LQIRETRY. Should the target stay in a non-pkt
1946 * phase after we send our message, the hardware
1947 * will assert LQIPHASE_LQ. Recovery is then just as
1948 * listed above for the read streaming with P0 asserted.
1949 * Busfree detection is enabled.
1951 if (silent == FALSE)
1952 printf("LQICRC_NLQ\n");
1954 printf("%s: No SCB valid for LQICRC_NLQ. "
1955 "Resetting bus\n", ahd_name(ahd));
1956 AHD_UNCORRECTABLE_ERROR(ahd);
1957 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1960 } else if ((lqistat1 & LQIBADLQI) != 0) {
1961 printf("Need to handle BADLQI!\n");
1962 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1964 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1965 if ((curphase & ~P_DATAIN_DT) != 0) {
1966 /* Ack the byte. So we can continue. */
1967 if (silent == FALSE)
1968 printf("Acking %s to clear perror\n",
1969 ahd_lookup_phase_entry(curphase)->phasemsg);
1970 ahd_inb(ahd, SCSIDAT);
1973 if (curphase == P_MESGIN)
1974 msg_out = MSG_PARITY_ERROR;
1978 * We've set the hardware to assert ATN if we
1979 * get a parity error on "in" phases, so all we
1980 * need to do is stuff the message buffer with
1981 * the appropriate message. "In" phases have set
1982 * mesg_out to something other than MSG_NOP.
1984 ahd->send_msg_perror = msg_out;
1985 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1986 scb->flags |= SCB_TRANSMISSION_ERROR;
1987 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1988 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1993 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1996 * Clear the sources of the interrupts.
1998 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1999 ahd_outb(ahd, CLRLQIINT1, lqistat1);
2002 * If the "illegal" phase changes were in response
2003 * to our ATN to flag a CRC error, AND we ended up
2004 * on packet boundaries, clear the error, restart the
2005 * LQI manager as appropriate, and go on our merry
2006 * way toward sending the message. Otherwise, reset
2007 * the bus to clear the error.
2009 ahd_set_active_fifo(ahd);
2010 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
2011 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
2012 if ((lqistat1 & LQIPHASE_LQ) != 0) {
2013 printf("LQIRETRY for LQIPHASE_LQ\n");
2014 AHD_CORRECTABLE_ERROR(ahd);
2015 ahd_outb(ahd, LQCTL2, LQIRETRY);
2016 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
2017 printf("LQIRETRY for LQIPHASE_NLQ\n");
2018 AHD_CORRECTABLE_ERROR(ahd);
2019 ahd_outb(ahd, LQCTL2, LQIRETRY);
2021 panic("ahd_handle_lqiphase_error: No phase errors\n");
2022 ahd_dump_card_state(ahd);
2023 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2026 printf("Reseting Channel for LQI Phase error\n");
2027 AHD_CORRECTABLE_ERROR(ahd);
2028 ahd_dump_card_state(ahd);
2029 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2034 * Packetized unexpected or expected busfree.
2035 * Entered in mode based on busfreetime.
2038 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2042 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2043 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2044 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2045 if ((lqostat1 & LQOBUSFREE) != 0) {
2054 * The LQO manager detected an unexpected busfree
2057 * 1) During an outgoing LQ.
2058 * 2) After an outgoing LQ but before the first
2059 * REQ of the command packet.
2060 * 3) During an outgoing command packet.
2062 * In all cases, CURRSCB is pointing to the
2063 * SCB that encountered the failure. Clean
2064 * up the queue, clear SELDO and LQOBUSFREE,
2065 * and allow the sequencer to restart the select
2066 * out at its lesure.
2068 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2069 scbid = ahd_inw(ahd, CURRSCB);
2070 scb = ahd_lookup_scb(ahd, scbid);
2072 panic("SCB not valid during LQOBUSFREE");
2076 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2077 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2078 ahd_outb(ahd, CLRLQOINT1, 0);
2079 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2080 ahd_flush_device_writes(ahd);
2081 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2084 * Return the LQO manager to its idle loop. It will
2085 * not do this automatically if the busfree occurs
2086 * after the first REQ of either the LQ or command
2087 * packet or between the LQ and command packet.
2089 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2092 * Update the waiting for selection queue so
2093 * we restart on the correct SCB.
2095 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2096 saved_scbptr = ahd_get_scbptr(ahd);
2097 if (waiting_h != scbid) {
2098 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2099 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2100 if (waiting_t == waiting_h) {
2101 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2102 next = SCB_LIST_NULL;
2104 ahd_set_scbptr(ahd, waiting_h);
2105 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2107 ahd_set_scbptr(ahd, scbid);
2108 ahd_outw(ahd, SCB_NEXT2, next);
2110 ahd_set_scbptr(ahd, saved_scbptr);
2111 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2112 if (SCB_IS_SILENT(scb) == FALSE) {
2113 ahd_print_path(ahd, scb);
2114 printf("Probable outgoing LQ CRC error. "
2115 "Retrying command\n");
2116 AHD_CORRECTABLE_ERROR(ahd);
2118 scb->crc_retry_count++;
2120 aic_set_transaction_status(scb, CAM_UNCOR_PARITY);
2121 aic_freeze_scb(scb);
2122 ahd_freeze_devq(ahd, scb);
2124 /* Return unpausing the sequencer. */
2126 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2128 * Ignore what are really parity errors that
2129 * occur on the last REQ of a free running
2130 * clock prior to going busfree. Some drives
2131 * do not properly active negate just before
2132 * going busfree resulting in a parity glitch.
2134 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2136 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2137 printf("%s: Parity on last REQ detected "
2138 "during busfree phase.\n",
2141 /* Return unpausing the sequencer. */
2144 if (ahd->src_mode != AHD_MODE_SCSI) {
2148 scbid = ahd_get_scbptr(ahd);
2149 scb = ahd_lookup_scb(ahd, scbid);
2150 ahd_print_path(ahd, scb);
2151 printf("Unexpected PKT busfree condition\n");
2152 AHD_UNCORRECTABLE_ERROR(ahd);
2153 ahd_dump_card_state(ahd);
2154 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2155 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2156 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2158 /* Return restarting the sequencer. */
2161 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2162 AHD_UNCORRECTABLE_ERROR(ahd);
2163 ahd_dump_card_state(ahd);
2164 /* Restart the sequencer. */
2169 * Non-packetized unexpected or expected busfree.
2172 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2174 struct ahd_devinfo devinfo;
2180 u_int initiator_role_id;
2186 * Look at what phase we were last in. If its message out,
2187 * chances are pretty good that the busfree was in response
2188 * to one of our abort requests.
2190 lastphase = ahd_inb(ahd, LASTPHASE);
2191 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2192 saved_lun = ahd_inb(ahd, SAVED_LUN);
2193 target = SCSIID_TARGET(ahd, saved_scsiid);
2194 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2195 ahd_compile_devinfo(&devinfo, initiator_role_id,
2196 target, saved_lun, 'A', ROLE_INITIATOR);
2199 scbid = ahd_get_scbptr(ahd);
2200 scb = ahd_lookup_scb(ahd, scbid);
2202 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2205 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2206 if (lastphase == P_MESGOUT) {
2209 tag = SCB_LIST_NULL;
2210 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2211 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2216 ahd_print_devinfo(ahd, &devinfo);
2217 printf("Abort for unidentified "
2218 "connection completed.\n");
2219 /* restart the sequencer. */
2222 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2223 ahd_print_path(ahd, scb);
2224 printf("SCB %d - Abort%s Completed.\n",
2226 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2228 if (sent_msg == MSG_ABORT_TAG)
2229 tag = SCB_GET_TAG(scb);
2231 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2233 * This abort is in response to an
2234 * unexpected switch to command phase
2235 * for a packetized connection. Since
2236 * the identify message was never sent,
2237 * "saved lun" is 0. We really want to
2238 * abort only the SCB that encountered
2239 * this error, which could have a different
2240 * lun. The SCB will be retried so the OS
2241 * will see the UA after renegotiating to
2244 tag = SCB_GET_TAG(scb);
2245 saved_lun = scb->hscb->lun;
2247 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2248 tag, ROLE_INITIATOR,
2250 printf("found == 0x%x\n", found);
2252 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2253 MSG_BUS_DEV_RESET, TRUE)) {
2256 * Don't mark the user's request for this BDR
2257 * as completing with CAM_BDR_SENT. CAM3
2258 * specifies CAM_REQ_CMP.
2261 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2262 && ahd_match_scb(ahd, scb, target, 'A',
2263 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2265 aic_set_transaction_status(scb, CAM_REQ_CMP);
2267 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2268 CAM_BDR_SENT, "Bus Device Reset",
2269 /*verbose_level*/0);
2271 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2272 && ppr_busfree == 0) {
2273 struct ahd_initiator_tinfo *tinfo;
2274 struct ahd_tmode_tstate *tstate;
2279 * If the previous negotiation was packetized,
2280 * this could be because the device has been
2281 * reset without our knowledge. Force our
2282 * current negotiation to async and retry the
2283 * negotiation. Otherwise retry the command
2284 * with non-ppr negotiation.
2287 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2288 printf("PPR negotiation rejected busfree.\n");
2290 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2292 devinfo.target, &tstate);
2293 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2294 ahd_set_width(ahd, &devinfo,
2295 MSG_EXT_WDTR_BUS_8_BIT,
2298 ahd_set_syncrate(ahd, &devinfo,
2299 /*period*/0, /*offset*/0,
2304 * The expect PPR busfree handler below
2305 * will effect the retry and necessary
2309 tinfo->curr.transport_version = 2;
2310 tinfo->goal.transport_version = 2;
2311 tinfo->goal.ppr_options = 0;
2313 * Remove any SCBs in the waiting for selection
2314 * queue that may also be for this target so
2315 * that command ordering is preserved.
2317 ahd_freeze_devq(ahd, scb);
2318 ahd_qinfifo_requeue_tail(ahd, scb);
2321 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2322 && ppr_busfree == 0) {
2324 * Negotiation Rejected. Go-narrow and
2328 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2329 printf("WDTR negotiation rejected busfree.\n");
2331 ahd_set_width(ahd, &devinfo,
2332 MSG_EXT_WDTR_BUS_8_BIT,
2333 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2336 * Remove any SCBs in the waiting for selection
2337 * queue that may also be for this target so that
2338 * command ordering is preserved.
2340 ahd_freeze_devq(ahd, scb);
2341 ahd_qinfifo_requeue_tail(ahd, scb);
2343 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2344 && ppr_busfree == 0) {
2346 * Negotiation Rejected. Go-async and
2350 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2351 printf("SDTR negotiation rejected busfree.\n");
2353 ahd_set_syncrate(ahd, &devinfo,
2354 /*period*/0, /*offset*/0,
2356 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2359 * Remove any SCBs in the waiting for selection
2360 * queue that may also be for this target so that
2361 * command ordering is preserved.
2363 ahd_freeze_devq(ahd, scb);
2364 ahd_qinfifo_requeue_tail(ahd, scb);
2366 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2367 && ahd_sent_msg(ahd, AHDMSG_1B,
2368 MSG_INITIATOR_DET_ERR, TRUE)) {
2370 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2371 printf("Expected IDE Busfree\n");
2374 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2375 && ahd_sent_msg(ahd, AHDMSG_1B,
2376 MSG_MESSAGE_REJECT, TRUE)) {
2378 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2379 printf("Expected QAS Reject Busfree\n");
2386 * The busfree required flag is honored at the end of
2387 * the message phases. We check it last in case we
2388 * had to send some other message that caused a busfree.
2391 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2392 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2393 ahd_freeze_devq(ahd, scb);
2394 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
2395 aic_freeze_scb(scb);
2396 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2397 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2398 SCB_GET_CHANNEL(ahd, scb),
2399 SCB_GET_LUN(scb), SCB_LIST_NULL,
2400 ROLE_INITIATOR, CAM_REQ_ABORTED);
2403 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2404 printf("PPR Negotiation Busfree.\n");
2410 if (printerror != 0) {
2417 if ((scb->hscb->control & TAG_ENB) != 0)
2418 tag = SCB_GET_TAG(scb);
2420 tag = SCB_LIST_NULL;
2421 ahd_print_path(ahd, scb);
2422 aborted = ahd_abort_scbs(ahd, target, 'A',
2423 SCB_GET_LUN(scb), tag,
2428 * We had not fully identified this connection,
2429 * so we cannot abort anything.
2431 printf("%s: ", ahd_name(ahd));
2433 printf("Unexpected busfree %s, %d SCBs aborted, "
2434 "PRGMCNT == 0x%x\n",
2435 ahd_lookup_phase_entry(lastphase)->phasemsg,
2437 ahd_inw(ahd, PRGMCNT));
2438 AHD_UNCORRECTABLE_ERROR(ahd);
2439 ahd_dump_card_state(ahd);
2440 if (lastphase != P_BUSFREE)
2441 ahd_force_renegotiation(ahd, &devinfo);
2443 /* Always restart the sequencer. */
2448 ahd_handle_proto_violation(struct ahd_softc *ahd)
2450 struct ahd_devinfo devinfo;
2458 ahd_fetch_devinfo(ahd, &devinfo);
2459 scbid = ahd_get_scbptr(ahd);
2460 scb = ahd_lookup_scb(ahd, scbid);
2461 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2462 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2463 lastphase = ahd_inb(ahd, LASTPHASE);
2464 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2466 * The reconnecting target either did not send an
2467 * identify message, or did, but we didn't find an SCB
2470 ahd_print_devinfo(ahd, &devinfo);
2471 printf("Target did not send an IDENTIFY message. "
2472 "LASTPHASE = 0x%x.\n", lastphase);
2473 AHD_UNCORRECTABLE_ERROR(ahd);
2475 } else if (scb == NULL) {
2477 * We don't seem to have an SCB active for this
2478 * transaction. Print an error and reset the bus.
2480 ahd_print_devinfo(ahd, &devinfo);
2481 printf("No SCB found during protocol violation\n");
2482 AHD_UNCORRECTABLE_ERROR(ahd);
2483 goto proto_violation_reset;
2485 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2486 if ((seq_flags & NO_CDB_SENT) != 0) {
2487 ahd_print_path(ahd, scb);
2488 printf("No or incomplete CDB sent to device.\n");
2489 AHD_UNCORRECTABLE_ERROR(ahd);
2490 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2491 & STATUS_RCVD) == 0) {
2493 * The target never bothered to provide status to
2494 * us prior to completing the command. Since we don't
2495 * know the disposition of this command, we must attempt
2496 * to abort it. Assert ATN and prepare to send an abort
2499 ahd_print_path(ahd, scb);
2500 printf("Completed command without status.\n");
2502 ahd_print_path(ahd, scb);
2503 printf("Unknown protocol violation.\n");
2504 AHD_UNCORRECTABLE_ERROR(ahd);
2505 ahd_dump_card_state(ahd);
2508 if ((lastphase & ~P_DATAIN_DT) == 0
2509 || lastphase == P_COMMAND) {
2510 proto_violation_reset:
2512 * Target either went directly to data
2513 * phase or didn't respond to our ATN.
2514 * The only safe thing to do is to blow
2515 * it away with a bus reset.
2517 found = ahd_reset_channel(ahd, 'A', TRUE);
2518 printf("%s: Issued Channel %c Bus Reset. "
2519 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2520 AHD_UNCORRECTABLE_ERROR(ahd);
2523 * Leave the selection hardware off in case
2524 * this abort attempt will affect yet to
2527 ahd_outb(ahd, SCSISEQ0,
2528 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2529 ahd_assert_atn(ahd);
2530 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2532 ahd_print_devinfo(ahd, &devinfo);
2533 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2534 ahd->msgout_len = 1;
2535 ahd->msgout_index = 0;
2536 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2538 ahd_print_path(ahd, scb);
2539 scb->flags |= SCB_ABORT;
2541 printf("Protocol violation %s. Attempting to abort.\n",
2542 ahd_lookup_phase_entry(curphase)->phasemsg);
2543 AHD_UNCORRECTABLE_ERROR(ahd);
2548 * Force renegotiation to occur the next time we initiate
2549 * a command to the current device.
2552 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2554 struct ahd_initiator_tinfo *targ_info;
2555 struct ahd_tmode_tstate *tstate;
2558 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2559 ahd_print_devinfo(ahd, devinfo);
2560 printf("Forcing renegotiation\n");
2563 targ_info = ahd_fetch_transinfo(ahd,
2565 devinfo->our_scsiid,
2568 ahd_update_neg_request(ahd, devinfo, tstate,
2569 targ_info, AHD_NEG_IF_NON_ASYNC);
2572 #define AHD_MAX_STEPS 2000
2574 ahd_clear_critical_section(struct ahd_softc *ahd)
2576 ahd_mode_state saved_modes;
2588 if (ahd->num_critical_sections == 0)
2601 saved_modes = ahd_save_modes(ahd);
2607 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2608 seqaddr = ahd_inw(ahd, CURADDR);
2610 cs = ahd->critical_sections;
2611 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2613 if (cs->begin < seqaddr && cs->end >= seqaddr)
2617 if (i == ahd->num_critical_sections)
2620 if (steps > AHD_MAX_STEPS) {
2621 printf("%s: Infinite loop in critical section\n"
2622 "%s: First Instruction 0x%x now 0x%x\n",
2623 ahd_name(ahd), ahd_name(ahd), first_instr,
2625 AHD_FATAL_ERROR(ahd);
2626 ahd_dump_card_state(ahd);
2627 panic("critical section loop");
2632 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2633 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2636 if (stepping == FALSE) {
2637 first_instr = seqaddr;
2638 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2639 simode0 = ahd_inb(ahd, SIMODE0);
2640 simode3 = ahd_inb(ahd, SIMODE3);
2641 lqimode0 = ahd_inb(ahd, LQIMODE0);
2642 lqimode1 = ahd_inb(ahd, LQIMODE1);
2643 lqomode0 = ahd_inb(ahd, LQOMODE0);
2644 lqomode1 = ahd_inb(ahd, LQOMODE1);
2645 ahd_outb(ahd, SIMODE0, 0);
2646 ahd_outb(ahd, SIMODE3, 0);
2647 ahd_outb(ahd, LQIMODE0, 0);
2648 ahd_outb(ahd, LQIMODE1, 0);
2649 ahd_outb(ahd, LQOMODE0, 0);
2650 ahd_outb(ahd, LQOMODE1, 0);
2651 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2652 simode1 = ahd_inb(ahd, SIMODE1);
2654 * We don't clear ENBUSFREE. Unfortunately
2655 * we cannot re-enable busfree detection within
2656 * the current connection, so we must leave it
2657 * on while single stepping.
2659 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2660 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2663 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2664 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2665 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2666 ahd_outb(ahd, HCNTRL, ahd->unpause);
2667 while (!ahd_is_paused(ahd))
2669 ahd_update_modes(ahd);
2672 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2673 ahd_outb(ahd, SIMODE0, simode0);
2674 ahd_outb(ahd, SIMODE3, simode3);
2675 ahd_outb(ahd, LQIMODE0, lqimode0);
2676 ahd_outb(ahd, LQIMODE1, lqimode1);
2677 ahd_outb(ahd, LQOMODE0, lqomode0);
2678 ahd_outb(ahd, LQOMODE1, lqomode1);
2679 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2680 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2681 ahd_outb(ahd, SIMODE1, simode1);
2683 * SCSIINT seems to glitch occasionally when
2684 * the interrupt masks are restored. Clear SCSIINT
2685 * one more time so that only persistent errors
2686 * are seen as a real interrupt.
2688 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2690 ahd_restore_modes(ahd, saved_modes);
2694 * Clear any pending interrupt status.
2697 ahd_clear_intstat(struct ahd_softc *ahd)
2699 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2700 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2701 /* Clear any interrupt conditions this may have caused */
2702 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2703 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2704 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2705 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2706 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2707 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2708 |CLRLQOATNPKT|CLRLQOTCRC);
2709 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2710 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2711 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2712 ahd_outb(ahd, CLRLQOINT0, 0);
2713 ahd_outb(ahd, CLRLQOINT1, 0);
2715 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2716 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2717 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2718 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2719 |CLRIOERR|CLROVERRUN);
2720 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2723 /**************************** Debugging Routines ******************************/
2725 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2728 ahd_print_scb(struct scb *scb)
2730 struct hardware_scb *hscb;
2734 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2740 printf("Shared Data: ");
2741 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2742 printf("%#02x", hscb->shared_data.idata.cdb[i]);
2743 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2744 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2745 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2746 aic_le32toh(hscb->datacnt),
2747 aic_le32toh(hscb->sgptr),
2749 ahd_dump_sglist(scb);
2753 ahd_dump_sglist(struct scb *scb)
2757 if (scb->sg_count > 0) {
2758 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2759 struct ahd_dma64_seg *sg_list;
2761 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2762 for (i = 0; i < scb->sg_count; i++) {
2765 addr = aic_le64toh(sg_list[i].addr);
2766 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2768 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2769 (uint32_t)(addr & 0xFFFFFFFF),
2770 sg_list[i].len & AHD_SG_LEN_MASK,
2771 (sg_list[i].len & AHD_DMA_LAST_SEG)
2775 struct ahd_dma_seg *sg_list;
2777 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2778 for (i = 0; i < scb->sg_count; i++) {
2781 len = aic_le32toh(sg_list[i].len);
2782 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2784 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2785 aic_le32toh(sg_list[i].addr),
2786 len & AHD_SG_LEN_MASK,
2787 len & AHD_DMA_LAST_SEG ? " Last" : "");
2793 /************************* Transfer Negotiation *******************************/
2795 * Allocate per target mode instance (ID we respond to as a target)
2796 * transfer negotiation data structures.
2798 static struct ahd_tmode_tstate *
2799 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2801 struct ahd_tmode_tstate *master_tstate;
2802 struct ahd_tmode_tstate *tstate;
2805 master_tstate = ahd->enabled_targets[ahd->our_id];
2806 if (ahd->enabled_targets[scsi_id] != NULL
2807 && ahd->enabled_targets[scsi_id] != master_tstate)
2808 panic("%s: ahd_alloc_tstate - Target already allocated",
2810 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
2815 * If we have allocated a master tstate, copy user settings from
2816 * the master tstate (taken from SRAM or the EEPROM) for this
2817 * channel, but reset our current and goal settings to async/narrow
2818 * until an initiator talks to us.
2820 if (master_tstate != NULL) {
2821 memcpy(tstate, master_tstate, sizeof(*tstate));
2822 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2823 for (i = 0; i < 16; i++) {
2824 memset(&tstate->transinfo[i].curr, 0,
2825 sizeof(tstate->transinfo[i].curr));
2826 memset(&tstate->transinfo[i].goal, 0,
2827 sizeof(tstate->transinfo[i].goal));
2830 memset(tstate, 0, sizeof(*tstate));
2831 ahd->enabled_targets[scsi_id] = tstate;
2835 #ifdef AHD_TARGET_MODE
2837 * Free per target mode instance (ID we respond to as a target)
2838 * transfer negotiation data structures.
2841 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2843 struct ahd_tmode_tstate *tstate;
2846 * Don't clean up our "master" tstate.
2847 * It has our default user settings.
2849 if (scsi_id == ahd->our_id
2853 tstate = ahd->enabled_targets[scsi_id];
2855 free(tstate, M_DEVBUF);
2856 ahd->enabled_targets[scsi_id] = NULL;
2861 * Called when we have an active connection to a target on the bus,
2862 * this function finds the nearest period to the input period limited
2863 * by the capabilities of the bus connectivity of and sync settings for
2867 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2868 struct ahd_initiator_tinfo *tinfo,
2869 u_int *period, u_int *ppr_options, role_t role)
2871 struct ahd_transinfo *transinfo;
2874 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2875 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2876 maxsync = AHD_SYNCRATE_PACED;
2878 maxsync = AHD_SYNCRATE_ULTRA;
2879 /* Can't do DT related options on an SE bus */
2880 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2883 * Never allow a value higher than our current goal
2884 * period otherwise we may allow a target initiated
2885 * negotiation to go above the limit as set by the
2886 * user. In the case of an initiator initiated
2887 * sync negotiation, we limit based on the user
2888 * setting. This allows the system to still accept
2889 * incoming negotiations even if target initiated
2890 * negotiation is not performed.
2892 if (role == ROLE_TARGET)
2893 transinfo = &tinfo->user;
2895 transinfo = &tinfo->goal;
2896 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2897 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2898 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2899 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2901 if (transinfo->period == 0) {
2905 *period = MAX(*period, transinfo->period);
2906 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2911 * Look up the valid period to SCSIRATE conversion in our table.
2912 * Return the period and offset that should be sent to the target
2913 * if this was the beginning of an SDTR.
2916 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2917 u_int *ppr_options, u_int maxsync)
2919 if (*period < maxsync)
2922 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2923 && *period > AHD_SYNCRATE_MIN_DT)
2924 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2926 if (*period > AHD_SYNCRATE_MIN)
2929 /* Honor PPR option conformance rules. */
2930 if (*period > AHD_SYNCRATE_PACED)
2931 *ppr_options &= ~MSG_EXT_PPR_RTI;
2933 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2934 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2936 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2937 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2939 /* Skip all PACED only entries if IU is not available */
2940 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2941 && *period < AHD_SYNCRATE_DT)
2942 *period = AHD_SYNCRATE_DT;
2944 /* Skip all DT only entries if DT is not available */
2945 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2946 && *period < AHD_SYNCRATE_ULTRA2)
2947 *period = AHD_SYNCRATE_ULTRA2;
2951 * Truncate the given synchronous offset to a value the
2952 * current adapter type and syncrate are capable of.
2955 ahd_validate_offset(struct ahd_softc *ahd,
2956 struct ahd_initiator_tinfo *tinfo,
2957 u_int period, u_int *offset, int wide,
2962 /* Limit offset to what we can do */
2965 else if (period <= AHD_SYNCRATE_PACED) {
2966 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2967 maxoffset = MAX_OFFSET_PACED_BUG;
2969 maxoffset = MAX_OFFSET_PACED;
2971 maxoffset = MAX_OFFSET_NON_PACED;
2972 *offset = MIN(*offset, maxoffset);
2973 if (tinfo != NULL) {
2974 if (role == ROLE_TARGET)
2975 *offset = MIN(*offset, tinfo->user.offset);
2977 *offset = MIN(*offset, tinfo->goal.offset);
2982 * Truncate the given transfer width parameter to a value the
2983 * current adapter type is capable of.
2986 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2987 u_int *bus_width, role_t role)
2989 switch (*bus_width) {
2991 if (ahd->features & AHD_WIDE) {
2993 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2997 case MSG_EXT_WDTR_BUS_8_BIT:
2998 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
3001 if (tinfo != NULL) {
3002 if (role == ROLE_TARGET)
3003 *bus_width = MIN(tinfo->user.width, *bus_width);
3005 *bus_width = MIN(tinfo->goal.width, *bus_width);
3010 * Update the bitmask of targets for which the controller should
3011 * negotiate with at the next convenient opportunity. This currently
3012 * means the next time we send the initial identify messages for
3013 * a new transaction.
3016 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3017 struct ahd_tmode_tstate *tstate,
3018 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
3020 u_int auto_negotiate_orig;
3022 auto_negotiate_orig = tstate->auto_negotiate;
3023 if (neg_type == AHD_NEG_ALWAYS) {
3025 * Force our "current" settings to be
3026 * unknown so that unless a bus reset
3027 * occurs the need to renegotiate is
3028 * recorded persistently.
3030 if ((ahd->features & AHD_WIDE) != 0)
3031 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3032 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3033 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3035 if (tinfo->curr.period != tinfo->goal.period
3036 || tinfo->curr.width != tinfo->goal.width
3037 || tinfo->curr.offset != tinfo->goal.offset
3038 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3039 || (neg_type == AHD_NEG_IF_NON_ASYNC
3040 && (tinfo->goal.offset != 0
3041 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3042 || tinfo->goal.ppr_options != 0)))
3043 tstate->auto_negotiate |= devinfo->target_mask;
3045 tstate->auto_negotiate &= ~devinfo->target_mask;
3047 return (auto_negotiate_orig != tstate->auto_negotiate);
3051 * Update the user/goal/curr tables of synchronous negotiation
3052 * parameters as well as, in the case of a current or active update,
3053 * any data structures on the host controller. In the case of an
3054 * active update, the specified target is currently talking to us on
3055 * the bus, so the transfer parameter update must take effect
3059 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3060 u_int period, u_int offset, u_int ppr_options,
3061 u_int type, int paused)
3063 struct ahd_initiator_tinfo *tinfo;
3064 struct ahd_tmode_tstate *tstate;
3071 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3074 if (period == 0 || offset == 0) {
3079 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3080 devinfo->target, &tstate);
3082 if ((type & AHD_TRANS_USER) != 0) {
3083 tinfo->user.period = period;
3084 tinfo->user.offset = offset;
3085 tinfo->user.ppr_options = ppr_options;
3088 if ((type & AHD_TRANS_GOAL) != 0) {
3089 tinfo->goal.period = period;
3090 tinfo->goal.offset = offset;
3091 tinfo->goal.ppr_options = ppr_options;
3094 old_period = tinfo->curr.period;
3095 old_offset = tinfo->curr.offset;
3096 old_ppr = tinfo->curr.ppr_options;
3098 if ((type & AHD_TRANS_CUR) != 0
3099 && (old_period != period
3100 || old_offset != offset
3101 || old_ppr != ppr_options)) {
3104 tinfo->curr.period = period;
3105 tinfo->curr.offset = offset;
3106 tinfo->curr.ppr_options = ppr_options;
3108 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3109 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3114 printf("%s: target %d synchronous with "
3115 "period = 0x%x, offset = 0x%x",
3116 ahd_name(ahd), devinfo->target,
3119 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3123 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3124 printf("%s", options ? "|DT" : "(DT");
3127 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3128 printf("%s", options ? "|IU" : "(IU");
3131 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3132 printf("%s", options ? "|RTI" : "(RTI");
3135 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3136 printf("%s", options ? "|QAS" : "(QAS");
3144 printf("%s: target %d using "
3145 "asynchronous transfers%s\n",
3146 ahd_name(ahd), devinfo->target,
3147 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3153 * Always refresh the neg-table to handle the case of the
3154 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3155 * We will always renegotiate in that case if this is a
3156 * packetized request. Also manage the busfree expected flag
3157 * from this common routine so that we catch changes due to
3158 * WDTR or SDTR messages.
3160 if ((type & AHD_TRANS_CUR) != 0) {
3163 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3166 if (ahd->msg_type != MSG_TYPE_NONE) {
3167 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3168 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3170 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3171 ahd_print_devinfo(ahd, devinfo);
3172 printf("Expecting IU Change busfree\n");
3175 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3176 | MSG_FLAG_IU_REQ_CHANGED;
3178 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3180 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3181 printf("PPR with IU_REQ outstanding\n");
3183 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3188 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3189 tinfo, AHD_NEG_TO_GOAL);
3191 if (update_needed && active)
3192 ahd_update_pending_scbs(ahd);
3196 * Update the user/goal/curr tables of wide negotiation
3197 * parameters as well as, in the case of a current or active update,
3198 * any data structures on the host controller. In the case of an
3199 * active update, the specified target is currently talking to us on
3200 * the bus, so the transfer parameter update must take effect
3204 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3205 u_int width, u_int type, int paused)
3207 struct ahd_initiator_tinfo *tinfo;
3208 struct ahd_tmode_tstate *tstate;
3213 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3215 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3216 devinfo->target, &tstate);
3218 if ((type & AHD_TRANS_USER) != 0)
3219 tinfo->user.width = width;
3221 if ((type & AHD_TRANS_GOAL) != 0)
3222 tinfo->goal.width = width;
3224 oldwidth = tinfo->curr.width;
3225 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3228 tinfo->curr.width = width;
3229 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3230 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3232 printf("%s: target %d using %dbit transfers\n",
3233 ahd_name(ahd), devinfo->target,
3234 8 * (0x01 << width));
3238 if ((type & AHD_TRANS_CUR) != 0) {
3241 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3246 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3247 tinfo, AHD_NEG_TO_GOAL);
3248 if (update_needed && active)
3249 ahd_update_pending_scbs(ahd);
3254 * Update the current state of tagged queuing for a given target.
3257 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3260 ahd_platform_set_tags(ahd, devinfo, alg);
3261 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3262 devinfo->lun, AC_TRANSFER_NEG, &alg);
3266 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3267 struct ahd_transinfo *tinfo)
3269 ahd_mode_state saved_modes;
3274 u_int saved_negoaddr;
3275 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3277 saved_modes = ahd_save_modes(ahd);
3278 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3280 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3281 ahd_outb(ahd, NEGOADDR, devinfo->target);
3282 period = tinfo->period;
3283 offset = tinfo->offset;
3284 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3285 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3286 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3289 period = AHD_SYNCRATE_ASYNC;
3290 if (period == AHD_SYNCRATE_160) {
3291 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3293 * When the SPI4 spec was finalized, PACE transfers
3294 * was not made a configurable option in the PPR
3295 * message. Instead it is assumed to be enabled for
3296 * any syncrate faster than 80MHz. Nevertheless,
3297 * Harpoon2A4 allows this to be configurable.
3299 * Harpoon2A4 also assumes at most 2 data bytes per
3300 * negotiated REQ/ACK offset. Paced transfers take
3301 * 4, so we must adjust our offset.
3303 ppr_opts |= PPROPT_PACE;
3307 * Harpoon2A assumed that there would be a
3308 * fallback rate between 160MHz and 80Mhz,
3309 * so 7 is used as the period factor rather
3310 * than 8 for 160MHz.
3312 period = AHD_SYNCRATE_REVA_160;
3314 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3315 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3319 * Precomp should be disabled for non-paced transfers.
3321 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3323 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3324 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3325 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3327 * Slow down our CRC interval to be
3328 * compatible with non-packetized
3329 * U160 devices that can't handle a
3330 * CRC at full speed.
3332 con_opts |= ENSLOWCRC;
3335 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3337 * On H2A4, revert to a slower slewrate
3338 * on non-paced transfers.
3340 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3345 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3346 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3347 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3348 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3350 ahd_outb(ahd, NEGPERIOD, period);
3351 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3352 ahd_outb(ahd, NEGOFFSET, offset);
3354 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3355 con_opts |= WIDEXFER;
3358 * During packetized transfers, the target will
3359 * give us the opportunity to send command packets
3360 * without us asserting attention.
3362 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3363 con_opts |= ENAUTOATNO;
3364 ahd_outb(ahd, NEGCONOPTS, con_opts);
3365 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3366 ahd_restore_modes(ahd, saved_modes);
3370 * When the transfer settings for a connection change, setup for
3371 * negotiation in pending SCBs to effect the change as quickly as
3372 * possible. We also cancel any negotiations that are scheduled
3373 * for inflight SCBs that have not been started yet.
3376 ahd_update_pending_scbs(struct ahd_softc *ahd)
3378 struct scb *pending_scb;
3379 int pending_scb_count;
3382 ahd_mode_state saved_modes;
3385 * Traverse the pending SCB list and ensure that all of the
3386 * SCBs there have the proper settings. We can only safely
3387 * clear the negotiation required flag (setting requires the
3388 * execution queue to be modified) and this is only possible
3389 * if we are not already attempting to select out for this
3390 * SCB. For this reason, all callers only call this routine
3391 * if we are changing the negotiation settings for the currently
3392 * active transaction on the bus.
3394 pending_scb_count = 0;
3395 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3396 struct ahd_devinfo devinfo;
3397 struct ahd_tmode_tstate *tstate;
3399 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3400 ahd_fetch_transinfo(ahd, devinfo.channel,
3402 devinfo.target, &tstate);
3403 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3404 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3405 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3406 pending_scb->hscb->control &= ~MK_MESSAGE;
3408 ahd_sync_scb(ahd, pending_scb,
3409 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3410 pending_scb_count++;
3413 if (pending_scb_count == 0)
3416 if (ahd_is_paused(ahd)) {
3424 * Force the sequencer to reinitialize the selection for
3425 * the command at the head of the execution queue if it
3426 * has already been setup. The negotiation changes may
3427 * effect whether we select-out with ATN. It is only
3428 * safe to clear ENSELO when the bus is not free and no
3429 * selection is in progres or completed.
3431 saved_modes = ahd_save_modes(ahd);
3432 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3433 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3434 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3435 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3436 saved_scbptr = ahd_get_scbptr(ahd);
3437 /* Ensure that the hscbs down on the card match the new information */
3438 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3442 scb_tag = SCB_GET_TAG(pending_scb);
3443 ahd_set_scbptr(ahd, scb_tag);
3444 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3445 control &= ~MK_MESSAGE;
3446 control |= pending_scb->hscb->control & MK_MESSAGE;
3447 ahd_outb(ahd, SCB_CONTROL, control);
3449 ahd_set_scbptr(ahd, saved_scbptr);
3450 ahd_restore_modes(ahd, saved_modes);
3456 /**************************** Pathing Information *****************************/
3458 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3460 ahd_mode_state saved_modes;
3465 saved_modes = ahd_save_modes(ahd);
3466 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3468 if (ahd_inb(ahd, SSTAT0) & TARGET)
3471 role = ROLE_INITIATOR;
3473 if (role == ROLE_TARGET
3474 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3475 /* We were selected, so pull our id from TARGIDIN */
3476 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3477 } else if (role == ROLE_TARGET)
3478 our_id = ahd_inb(ahd, TOWNID);
3480 our_id = ahd_inb(ahd, IOWNID);
3482 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3483 ahd_compile_devinfo(devinfo,
3485 SCSIID_TARGET(ahd, saved_scsiid),
3486 ahd_inb(ahd, SAVED_LUN),
3487 SCSIID_CHANNEL(ahd, saved_scsiid),
3489 ahd_restore_modes(ahd, saved_modes);
3493 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3495 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3496 devinfo->target, devinfo->lun);
3499 struct ahd_phase_table_entry*
3500 ahd_lookup_phase_entry(int phase)
3502 struct ahd_phase_table_entry *entry;
3503 struct ahd_phase_table_entry *last_entry;
3506 * num_phases doesn't include the default entry which
3507 * will be returned if the phase doesn't match.
3509 last_entry = &ahd_phase_table[num_phases];
3510 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3511 if (phase == entry->phase)
3518 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3519 u_int lun, char channel, role_t role)
3521 devinfo->our_scsiid = our_id;
3522 devinfo->target = target;
3524 devinfo->target_offset = target;
3525 devinfo->channel = channel;
3526 devinfo->role = role;
3528 devinfo->target_offset += 8;
3529 devinfo->target_mask = (0x01 << devinfo->target_offset);
3533 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3539 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3540 role = ROLE_INITIATOR;
3541 if ((scb->hscb->control & TARGET_SCB) != 0)
3543 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3544 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3547 /************************ Message Phase Processing ****************************/
3549 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3550 * or enters the initial message out phase, we are interrupted. Fill our
3551 * outgoing message buffer with the appropriate message and beging handing
3552 * the message phase(s) manually.
3555 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3559 * To facilitate adding multiple messages together,
3560 * each routine should increment the index and len
3561 * variables instead of setting them explicitly.
3563 ahd->msgout_index = 0;
3564 ahd->msgout_len = 0;
3566 if (ahd_currently_packetized(ahd))
3567 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3569 if (ahd->send_msg_perror
3570 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3571 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3573 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3575 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3576 printf("Setting up for Parity Error delivery\n");
3579 } else if (scb == NULL) {
3580 printf("%s: WARNING. No pending message for "
3581 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3582 AHD_CORRECTABLE_ERROR(ahd);
3583 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3585 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3589 if ((scb->flags & SCB_DEVICE_RESET) == 0
3590 && (scb->flags & SCB_PACKETIZED) == 0
3591 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3594 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3595 if ((scb->hscb->control & DISCENB) != 0)
3596 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3597 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3600 if ((scb->hscb->control & TAG_ENB) != 0) {
3601 ahd->msgout_buf[ahd->msgout_index++] =
3602 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3603 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3604 ahd->msgout_len += 2;
3608 if (scb->flags & SCB_DEVICE_RESET) {
3609 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3611 ahd_print_path(ahd, scb);
3612 printf("Bus Device Reset Message Sent\n");
3613 AHD_CORRECTABLE_ERROR(ahd);
3615 * Clear our selection hardware in advance of
3616 * the busfree. We may have an entry in the waiting
3617 * Q for this target, and we don't want to go about
3618 * selecting while we handle the busfree and blow it
3621 ahd_outb(ahd, SCSISEQ0, 0);
3622 } else if ((scb->flags & SCB_ABORT) != 0) {
3623 if ((scb->hscb->control & TAG_ENB) != 0) {
3624 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3626 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3629 ahd_print_path(ahd, scb);
3630 printf("Abort%s Message Sent\n",
3631 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3632 AHD_CORRECTABLE_ERROR(ahd);
3634 * Clear our selection hardware in advance of
3635 * the busfree. We may have an entry in the waiting
3636 * Q for this target, and we don't want to go about
3637 * selecting while we handle the busfree and blow it
3640 ahd_outb(ahd, SCSISEQ0, 0);
3641 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3642 ahd_build_transfer_msg(ahd, devinfo);
3644 * Clear our selection hardware in advance of potential
3645 * PPR IU status change busfree. We may have an entry in
3646 * the waiting Q for this target, and we don't want to go
3647 * about selecting while we handle the busfree and blow
3650 ahd_outb(ahd, SCSISEQ0, 0);
3652 printf("ahd_intr: AWAITING_MSG for an SCB that "
3653 "does not have a waiting message\n");
3654 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3655 devinfo->target_mask);
3656 AHD_FATAL_ERROR(ahd);
3657 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3658 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3659 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3664 * Clear the MK_MESSAGE flag from the SCB so we aren't
3665 * asked to send this message again.
3667 ahd_outb(ahd, SCB_CONTROL,
3668 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3669 scb->hscb->control &= ~MK_MESSAGE;
3670 ahd->msgout_index = 0;
3671 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3675 * Build an appropriate transfer negotiation message for the
3676 * currently active target.
3679 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3682 * We need to initiate transfer negotiations.
3683 * If our current and goal settings are identical,
3684 * we want to renegotiate due to a check condition.
3686 struct ahd_initiator_tinfo *tinfo;
3687 struct ahd_tmode_tstate *tstate;
3695 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3696 devinfo->target, &tstate);
3698 * Filter our period based on the current connection.
3699 * If we can't perform DT transfers on this segment (not in LVD
3700 * mode for instance), then our decision to issue a PPR message
3703 period = tinfo->goal.period;
3704 offset = tinfo->goal.offset;
3705 ppr_options = tinfo->goal.ppr_options;
3706 /* Target initiated PPR is not allowed in the SCSI spec */
3707 if (devinfo->role == ROLE_TARGET)
3709 ahd_devlimited_syncrate(ahd, tinfo, &period,
3710 &ppr_options, devinfo->role);
3711 dowide = tinfo->curr.width != tinfo->goal.width;
3712 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3714 * Only use PPR if we have options that need it, even if the device
3715 * claims to support it. There might be an expander in the way
3718 doppr = ppr_options != 0;
3720 if (!dowide && !dosync && !doppr) {
3721 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3722 dosync = tinfo->goal.offset != 0;
3725 if (!dowide && !dosync && !doppr) {
3727 * Force async with a WDTR message if we have a wide bus,
3728 * or just issue an SDTR with a 0 offset.
3730 if ((ahd->features & AHD_WIDE) != 0)
3736 ahd_print_devinfo(ahd, devinfo);
3737 printf("Ensuring async\n");
3740 /* Target initiated PPR is not allowed in the SCSI spec */
3741 if (devinfo->role == ROLE_TARGET)
3745 * Both the PPR message and SDTR message require the
3746 * goal syncrate to be limited to what the target device
3747 * is capable of handling (based on whether an LVD->SE
3748 * expander is on the bus), so combine these two cases.
3749 * Regardless, guarantee that if we are using WDTR and SDTR
3750 * messages that WDTR comes first.
3752 if (doppr || (dosync && !dowide)) {
3753 offset = tinfo->goal.offset;
3754 ahd_validate_offset(ahd, tinfo, period, &offset,
3755 doppr ? tinfo->goal.width
3756 : tinfo->curr.width,
3759 ahd_construct_ppr(ahd, devinfo, period, offset,
3760 tinfo->goal.width, ppr_options);
3762 ahd_construct_sdtr(ahd, devinfo, period, offset);
3765 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3770 * Build a synchronous negotiation message in our message
3771 * buffer based on the input parameters.
3774 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3775 u_int period, u_int offset)
3778 period = AHD_ASYNC_XFER_PERIOD;
3779 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3780 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3781 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3782 ahd->msgout_buf[ahd->msgout_index++] = period;
3783 ahd->msgout_buf[ahd->msgout_index++] = offset;
3784 ahd->msgout_len += 5;
3786 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3787 ahd_name(ahd), devinfo->channel, devinfo->target,
3788 devinfo->lun, period, offset);
3793 * Build a wide negotiateion message in our message
3794 * buffer based on the input parameters.
3797 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3800 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3801 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3802 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3803 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3804 ahd->msgout_len += 4;
3806 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3807 ahd_name(ahd), devinfo->channel, devinfo->target,
3808 devinfo->lun, bus_width);
3813 * Build a parallel protocol request message in our message
3814 * buffer based on the input parameters.
3817 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3818 u_int period, u_int offset, u_int bus_width,
3822 * Always request precompensation from
3823 * the other target if we are running
3824 * at paced syncrates.
3826 if (period <= AHD_SYNCRATE_PACED)
3827 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3829 period = AHD_ASYNC_XFER_PERIOD;
3830 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3831 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3832 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3833 ahd->msgout_buf[ahd->msgout_index++] = period;
3834 ahd->msgout_buf[ahd->msgout_index++] = 0;
3835 ahd->msgout_buf[ahd->msgout_index++] = offset;
3836 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3837 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3838 ahd->msgout_len += 8;
3840 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3841 "offset %x, ppr_options %x\n", ahd_name(ahd),
3842 devinfo->channel, devinfo->target, devinfo->lun,
3843 bus_width, period, offset, ppr_options);
3848 * Clear any active message state.
3851 ahd_clear_msg_state(struct ahd_softc *ahd)
3853 ahd_mode_state saved_modes;
3855 saved_modes = ahd_save_modes(ahd);
3856 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3857 ahd->send_msg_perror = 0;
3858 ahd->msg_flags = MSG_FLAG_NONE;
3859 ahd->msgout_len = 0;
3860 ahd->msgin_index = 0;
3861 ahd->msg_type = MSG_TYPE_NONE;
3862 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3864 * The target didn't care to respond to our
3865 * message request, so clear ATN.
3867 ahd_outb(ahd, CLRSINT1, CLRATNO);
3869 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3870 ahd_outb(ahd, SEQ_FLAGS2,
3871 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3872 ahd_restore_modes(ahd, saved_modes);
3876 * Manual message loop handler.
3879 ahd_handle_message_phase(struct ahd_softc *ahd)
3881 struct ahd_devinfo devinfo;
3885 ahd_fetch_devinfo(ahd, &devinfo);
3886 end_session = FALSE;
3887 bus_phase = ahd_inb(ahd, LASTPHASE);
3889 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3890 printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3891 ahd_outb(ahd, LQCTL2, LQIRETRY);
3894 switch (ahd->msg_type) {
3895 case MSG_TYPE_INITIATOR_MSGOUT:
3901 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3902 panic("HOST_MSG_LOOP interrupt with no active message");
3905 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3906 ahd_print_devinfo(ahd, &devinfo);
3907 printf("INITIATOR_MSG_OUT");
3910 phasemis = bus_phase != P_MESGOUT;
3913 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3914 printf(" PHASEMIS %s\n",
3915 ahd_lookup_phase_entry(bus_phase)
3919 if (bus_phase == P_MESGIN) {
3921 * Change gears and see if
3922 * this messages is of interest to
3923 * us or should be passed back to
3926 ahd_outb(ahd, CLRSINT1, CLRATNO);
3927 ahd->send_msg_perror = 0;
3928 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3929 ahd->msgin_index = 0;
3936 if (ahd->send_msg_perror) {
3937 ahd_outb(ahd, CLRSINT1, CLRATNO);
3938 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3940 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3941 printf(" byte 0x%x\n", ahd->send_msg_perror);
3944 * If we are notifying the target of a CRC error
3945 * during packetized operations, the target is
3946 * within its rights to acknowledge our message
3949 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3950 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3951 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3953 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3954 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3958 msgdone = ahd->msgout_index == ahd->msgout_len;
3961 * The target has requested a retry.
3962 * Re-assert ATN, reset our message index to
3965 ahd->msgout_index = 0;
3966 ahd_assert_atn(ahd);
3969 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3971 /* Last byte is signified by dropping ATN */
3972 ahd_outb(ahd, CLRSINT1, CLRATNO);
3976 * Clear our interrupt status and present
3977 * the next byte on the bus.
3979 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3981 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3982 printf(" byte 0x%x\n",
3983 ahd->msgout_buf[ahd->msgout_index]);
3985 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3986 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3989 case MSG_TYPE_INITIATOR_MSGIN:
3995 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3996 ahd_print_devinfo(ahd, &devinfo);
3997 printf("INITIATOR_MSG_IN");
4000 phasemis = bus_phase != P_MESGIN;
4003 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4004 printf(" PHASEMIS %s\n",
4005 ahd_lookup_phase_entry(bus_phase)
4009 ahd->msgin_index = 0;
4010 if (bus_phase == P_MESGOUT
4011 && (ahd->send_msg_perror != 0
4012 || (ahd->msgout_len != 0
4013 && ahd->msgout_index == 0))) {
4014 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
4021 /* Pull the byte in without acking it */
4022 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4024 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4025 printf(" byte 0x%x\n",
4026 ahd->msgin_buf[ahd->msgin_index]);
4029 message_done = ahd_parse_msg(ahd, &devinfo);
4033 * Clear our incoming message buffer in case there
4034 * is another message following this one.
4036 ahd->msgin_index = 0;
4039 * If this message illicited a response,
4040 * assert ATN so the target takes us to the
4041 * message out phase.
4043 if (ahd->msgout_len != 0) {
4045 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4046 ahd_print_devinfo(ahd, &devinfo);
4047 printf("Asserting ATN for response\n");
4050 ahd_assert_atn(ahd);
4055 if (message_done == MSGLOOP_TERMINATED) {
4059 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4060 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4064 case MSG_TYPE_TARGET_MSGIN:
4070 * By default, the message loop will continue.
4072 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4074 if (ahd->msgout_len == 0)
4075 panic("Target MSGIN with no active message");
4078 * If we interrupted a mesgout session, the initiator
4079 * will not know this until our first REQ. So, we
4080 * only honor mesgout requests after we've sent our
4083 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4084 && ahd->msgout_index > 0)
4085 msgout_request = TRUE;
4087 msgout_request = FALSE;
4089 if (msgout_request) {
4091 * Change gears and see if
4092 * this messages is of interest to
4093 * us or should be passed back to
4096 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4097 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4098 ahd->msgin_index = 0;
4099 /* Dummy read to REQ for first byte */
4100 ahd_inb(ahd, SCSIDAT);
4101 ahd_outb(ahd, SXFRCTL0,
4102 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4106 msgdone = ahd->msgout_index == ahd->msgout_len;
4108 ahd_outb(ahd, SXFRCTL0,
4109 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4115 * Present the next byte on the bus.
4117 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4118 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4121 case MSG_TYPE_TARGET_MSGOUT:
4127 * By default, the message loop will continue.
4129 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4132 * The initiator signals that this is
4133 * the last byte by dropping ATN.
4135 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4138 * Read the latched byte, but turn off SPIOEN first
4139 * so that we don't inadvertently cause a REQ for the
4142 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4143 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4144 msgdone = ahd_parse_msg(ahd, &devinfo);
4145 if (msgdone == MSGLOOP_TERMINATED) {
4147 * The message is *really* done in that it caused
4148 * us to go to bus free. The sequencer has already
4149 * been reset at this point, so pull the ejection
4158 * XXX Read spec about initiator dropping ATN too soon
4159 * and use msgdone to detect it.
4161 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4162 ahd->msgin_index = 0;
4165 * If this message illicited a response, transition
4166 * to the Message in phase and send it.
4168 if (ahd->msgout_len != 0) {
4169 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4170 ahd_outb(ahd, SXFRCTL0,
4171 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4172 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4173 ahd->msgin_index = 0;
4181 /* Ask for the next byte. */
4182 ahd_outb(ahd, SXFRCTL0,
4183 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4189 panic("Unknown REQINIT message type");
4193 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4194 printf("%s: Returning to Idle Loop\n",
4196 ahd_clear_msg_state(ahd);
4199 * Perform the equivalent of a clear_target_state.
4201 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4202 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4203 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4205 ahd_clear_msg_state(ahd);
4206 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4212 * See if we sent a particular extended message to the target.
4213 * If "full" is true, return true only if the target saw the full
4214 * message. If "full" is false, return true if the target saw at
4215 * least the first byte of the message.
4218 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4226 while (index < ahd->msgout_len) {
4227 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4230 end_index = index + 1 + ahd->msgout_buf[index + 1];
4231 if (ahd->msgout_buf[index+2] == msgval
4232 && type == AHDMSG_EXT) {
4234 if (ahd->msgout_index > end_index)
4236 } else if (ahd->msgout_index > index)
4240 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4241 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4242 /* Skip tag type and tag id or residue param*/
4245 /* Single byte message */
4246 if (type == AHDMSG_1B
4247 && ahd->msgout_index > index
4248 && (ahd->msgout_buf[index] == msgval
4249 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4250 && msgval == MSG_IDENTIFYFLAG)))
4262 * Wait for a complete incoming message, parse it, and respond accordingly.
4265 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4267 struct ahd_initiator_tinfo *tinfo;
4268 struct ahd_tmode_tstate *tstate;
4273 done = MSGLOOP_IN_PROG;
4276 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4277 devinfo->target, &tstate);
4280 * Parse as much of the message as is available,
4281 * rejecting it if we don't support it. When
4282 * the entire message is available and has been
4283 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4284 * that we have parsed an entire message.
4286 * In the case of extended messages, we accept the length
4287 * byte outright and perform more checking once we know the
4288 * extended message type.
4290 switch (ahd->msgin_buf[0]) {
4291 case MSG_DISCONNECT:
4292 case MSG_SAVEDATAPOINTER:
4293 case MSG_CMDCOMPLETE:
4294 case MSG_RESTOREPOINTERS:
4295 case MSG_IGN_WIDE_RESIDUE:
4297 * End our message loop as these are messages
4298 * the sequencer handles on its own.
4300 done = MSGLOOP_TERMINATED;
4302 case MSG_MESSAGE_REJECT:
4303 response = ahd_handle_msg_reject(ahd, devinfo);
4306 done = MSGLOOP_MSGCOMPLETE;
4310 /* Wait for enough of the message to begin validation */
4311 if (ahd->msgin_index < 2)
4313 switch (ahd->msgin_buf[2]) {
4321 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4327 * Wait until we have both args before validating
4328 * and acting on this message.
4330 * Add one to MSG_EXT_SDTR_LEN to account for
4331 * the extended message preamble.
4333 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4336 period = ahd->msgin_buf[3];
4338 saved_offset = offset = ahd->msgin_buf[4];
4339 ahd_devlimited_syncrate(ahd, tinfo, &period,
4340 &ppr_options, devinfo->role);
4341 ahd_validate_offset(ahd, tinfo, period, &offset,
4342 tinfo->curr.width, devinfo->role);
4344 printf("(%s:%c:%d:%d): Received "
4345 "SDTR period %x, offset %x\n\t"
4346 "Filtered to period %x, offset %x\n",
4347 ahd_name(ahd), devinfo->channel,
4348 devinfo->target, devinfo->lun,
4349 ahd->msgin_buf[3], saved_offset,
4352 ahd_set_syncrate(ahd, devinfo, period,
4353 offset, ppr_options,
4354 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4358 * See if we initiated Sync Negotiation
4359 * and didn't have to fall down to async
4362 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4364 if (saved_offset != offset) {
4365 /* Went too low - force async */
4370 * Send our own SDTR in reply
4373 && devinfo->role == ROLE_INITIATOR) {
4374 printf("(%s:%c:%d:%d): Target "
4376 ahd_name(ahd), devinfo->channel,
4377 devinfo->target, devinfo->lun);
4379 ahd->msgout_index = 0;
4380 ahd->msgout_len = 0;
4381 ahd_construct_sdtr(ahd, devinfo,
4383 ahd->msgout_index = 0;
4386 done = MSGLOOP_MSGCOMPLETE;
4393 u_int sending_reply;
4395 sending_reply = FALSE;
4396 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4402 * Wait until we have our arg before validating
4403 * and acting on this message.
4405 * Add one to MSG_EXT_WDTR_LEN to account for
4406 * the extended message preamble.
4408 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4411 bus_width = ahd->msgin_buf[3];
4412 saved_width = bus_width;
4413 ahd_validate_width(ahd, tinfo, &bus_width,
4416 printf("(%s:%c:%d:%d): Received WDTR "
4417 "%x filtered to %x\n",
4418 ahd_name(ahd), devinfo->channel,
4419 devinfo->target, devinfo->lun,
4420 saved_width, bus_width);
4423 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4425 * Don't send a WDTR back to the
4426 * target, since we asked first.
4427 * If the width went higher than our
4428 * request, reject it.
4430 if (saved_width > bus_width) {
4432 printf("(%s:%c:%d:%d): requested %dBit "
4433 "transfers. Rejecting...\n",
4434 ahd_name(ahd), devinfo->channel,
4435 devinfo->target, devinfo->lun,
4436 8 * (0x01 << bus_width));
4441 * Send our own WDTR in reply
4444 && devinfo->role == ROLE_INITIATOR) {
4445 printf("(%s:%c:%d:%d): Target "
4447 ahd_name(ahd), devinfo->channel,
4448 devinfo->target, devinfo->lun);
4450 ahd->msgout_index = 0;
4451 ahd->msgout_len = 0;
4452 ahd_construct_wdtr(ahd, devinfo, bus_width);
4453 ahd->msgout_index = 0;
4455 sending_reply = TRUE;
4458 * After a wide message, we are async, but
4459 * some devices don't seem to honor this portion
4460 * of the spec. Force a renegotiation of the
4461 * sync component of our transfer agreement even
4462 * if our goal is async. By updating our width
4463 * after forcing the negotiation, we avoid
4464 * renegotiating for width.
4466 ahd_update_neg_request(ahd, devinfo, tstate,
4467 tinfo, AHD_NEG_ALWAYS);
4468 ahd_set_width(ahd, devinfo, bus_width,
4469 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4471 if (sending_reply == FALSE && reject == FALSE) {
4473 * We will always have an SDTR to send.
4475 ahd->msgout_index = 0;
4476 ahd->msgout_len = 0;
4477 ahd_build_transfer_msg(ahd, devinfo);
4478 ahd->msgout_index = 0;
4481 done = MSGLOOP_MSGCOMPLETE;
4492 u_int saved_ppr_options;
4494 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4500 * Wait until we have all args before validating
4501 * and acting on this message.
4503 * Add one to MSG_EXT_PPR_LEN to account for
4504 * the extended message preamble.
4506 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4509 period = ahd->msgin_buf[3];
4510 offset = ahd->msgin_buf[5];
4511 bus_width = ahd->msgin_buf[6];
4512 saved_width = bus_width;
4513 ppr_options = ahd->msgin_buf[7];
4515 * According to the spec, a DT only
4516 * period factor with no DT option
4517 * set implies async.
4519 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4522 saved_ppr_options = ppr_options;
4523 saved_offset = offset;
4526 * Transfer options are only available if we
4527 * are negotiating wide.
4530 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4532 ahd_validate_width(ahd, tinfo, &bus_width,
4534 ahd_devlimited_syncrate(ahd, tinfo, &period,
4535 &ppr_options, devinfo->role);
4536 ahd_validate_offset(ahd, tinfo, period, &offset,
4537 bus_width, devinfo->role);
4539 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4541 * If we are unable to do any of the
4542 * requested options (we went too low),
4543 * then we'll have to reject the message.
4545 if (saved_width > bus_width
4546 || saved_offset != offset
4547 || saved_ppr_options != ppr_options) {
4555 if (devinfo->role != ROLE_TARGET)
4556 printf("(%s:%c:%d:%d): Target "
4558 ahd_name(ahd), devinfo->channel,
4559 devinfo->target, devinfo->lun);
4561 printf("(%s:%c:%d:%d): Initiator "
4563 ahd_name(ahd), devinfo->channel,
4564 devinfo->target, devinfo->lun);
4565 ahd->msgout_index = 0;
4566 ahd->msgout_len = 0;
4567 ahd_construct_ppr(ahd, devinfo, period, offset,
4568 bus_width, ppr_options);
4569 ahd->msgout_index = 0;
4573 printf("(%s:%c:%d:%d): Received PPR width %x, "
4574 "period %x, offset %x,options %x\n"
4575 "\tFiltered to width %x, period %x, "
4576 "offset %x, options %x\n",
4577 ahd_name(ahd), devinfo->channel,
4578 devinfo->target, devinfo->lun,
4579 saved_width, ahd->msgin_buf[3],
4580 saved_offset, saved_ppr_options,
4581 bus_width, period, offset, ppr_options);
4583 ahd_set_width(ahd, devinfo, bus_width,
4584 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4586 ahd_set_syncrate(ahd, devinfo, period,
4587 offset, ppr_options,
4588 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4591 done = MSGLOOP_MSGCOMPLETE;
4595 /* Unknown extended message. Reject it. */
4601 #ifdef AHD_TARGET_MODE
4602 case MSG_BUS_DEV_RESET:
4603 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4605 "Bus Device Reset Received",
4606 /*verbose_level*/0);
4608 done = MSGLOOP_TERMINATED;
4612 case MSG_CLEAR_QUEUE:
4616 /* Target mode messages */
4617 if (devinfo->role != ROLE_TARGET) {
4621 tag = SCB_LIST_NULL;
4622 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4623 tag = ahd_inb(ahd, INITIATOR_TAG);
4624 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4625 devinfo->lun, tag, ROLE_TARGET,
4628 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4629 if (tstate != NULL) {
4630 struct ahd_tmode_lstate* lstate;
4632 lstate = tstate->enabled_luns[devinfo->lun];
4633 if (lstate != NULL) {
4634 ahd_queue_lstate_event(ahd, lstate,
4635 devinfo->our_scsiid,
4638 ahd_send_lstate_events(ahd, lstate);
4642 done = MSGLOOP_TERMINATED;
4646 case MSG_QAS_REQUEST:
4648 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4649 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4650 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4652 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4654 case MSG_TERM_IO_PROC:
4662 * Setup to reject the message.
4664 ahd->msgout_index = 0;
4665 ahd->msgout_len = 1;
4666 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4667 done = MSGLOOP_MSGCOMPLETE;
4671 if (done != MSGLOOP_IN_PROG && !response)
4672 /* Clear the outgoing message buffer */
4673 ahd->msgout_len = 0;
4679 * Process a message reject message.
4682 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4685 * What we care about here is if we had an
4686 * outstanding SDTR or WDTR message for this
4687 * target. If we did, this is a signal that
4688 * the target is refusing negotiation.
4691 struct ahd_initiator_tinfo *tinfo;
4692 struct ahd_tmode_tstate *tstate;
4697 scb_index = ahd_get_scbptr(ahd);
4698 scb = ahd_lookup_scb(ahd, scb_index);
4699 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4700 devinfo->our_scsiid,
4701 devinfo->target, &tstate);
4702 /* Might be necessary */
4703 last_msg = ahd_inb(ahd, LAST_MSG);
4705 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4706 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4707 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4709 * Target may not like our SPI-4 PPR Options.
4710 * Attempt to negotiate 80MHz which will turn
4711 * off these options.
4714 printf("(%s:%c:%d:%d): PPR Rejected. "
4715 "Trying simple U160 PPR\n",
4716 ahd_name(ahd), devinfo->channel,
4717 devinfo->target, devinfo->lun);
4719 tinfo->goal.period = AHD_SYNCRATE_DT;
4720 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4721 | MSG_EXT_PPR_QAS_REQ
4722 | MSG_EXT_PPR_DT_REQ;
4725 * Target does not support the PPR message.
4726 * Attempt to negotiate SPI-2 style.
4729 printf("(%s:%c:%d:%d): PPR Rejected. "
4730 "Trying WDTR/SDTR\n",
4731 ahd_name(ahd), devinfo->channel,
4732 devinfo->target, devinfo->lun);
4734 tinfo->goal.ppr_options = 0;
4735 tinfo->curr.transport_version = 2;
4736 tinfo->goal.transport_version = 2;
4738 ahd->msgout_index = 0;
4739 ahd->msgout_len = 0;
4740 ahd_build_transfer_msg(ahd, devinfo);
4741 ahd->msgout_index = 0;
4743 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4744 /* note 8bit xfers */
4745 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4746 "8bit transfers\n", ahd_name(ahd),
4747 devinfo->channel, devinfo->target, devinfo->lun);
4748 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4749 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4752 * No need to clear the sync rate. If the target
4753 * did not accept the command, our syncrate is
4754 * unaffected. If the target started the negotiation,
4755 * but rejected our response, we already cleared the
4756 * sync rate before sending our WDTR.
4758 if (tinfo->goal.offset != tinfo->curr.offset) {
4759 /* Start the sync negotiation */
4760 ahd->msgout_index = 0;
4761 ahd->msgout_len = 0;
4762 ahd_build_transfer_msg(ahd, devinfo);
4763 ahd->msgout_index = 0;
4766 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4767 /* note asynch xfers and clear flag */
4768 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4769 /*offset*/0, /*ppr_options*/0,
4770 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4772 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4773 "Using asynchronous transfers\n",
4774 ahd_name(ahd), devinfo->channel,
4775 devinfo->target, devinfo->lun);
4776 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4780 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4782 if (tag_type == MSG_SIMPLE_TASK) {
4783 printf("(%s:%c:%d:%d): refuses tagged commands. "
4784 "Performing non-tagged I/O\n", ahd_name(ahd),
4785 devinfo->channel, devinfo->target, devinfo->lun);
4786 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4789 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4790 "Performing simple queue tagged I/O only\n",
4791 ahd_name(ahd), devinfo->channel, devinfo->target,
4792 devinfo->lun, tag_type == MSG_ORDERED_TASK
4793 ? "ordered" : "head of queue");
4794 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4799 * Resend the identify for this CCB as the target
4800 * may believe that the selection is invalid otherwise.
4802 ahd_outb(ahd, SCB_CONTROL,
4803 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4804 scb->hscb->control &= mask;
4805 aic_set_transaction_tag(scb, /*enabled*/FALSE,
4806 /*type*/MSG_SIMPLE_TASK);
4807 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4808 ahd_assert_atn(ahd);
4809 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4813 * Requeue all tagged commands for this target
4814 * currently in our possession so they can be
4815 * converted to untagged commands.
4817 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4818 SCB_GET_CHANNEL(ahd, scb),
4819 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4820 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4822 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4824 * Most likely the device believes that we had
4825 * previously negotiated packetized.
4827 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4828 | MSG_FLAG_IU_REQ_CHANGED;
4830 ahd_force_renegotiation(ahd, devinfo);
4831 ahd->msgout_index = 0;
4832 ahd->msgout_len = 0;
4833 ahd_build_transfer_msg(ahd, devinfo);
4834 ahd->msgout_index = 0;
4838 * Otherwise, we ignore it.
4840 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4841 ahd_name(ahd), devinfo->channel, devinfo->target,
4848 * Process an ingnore wide residue message.
4851 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4856 scb_index = ahd_get_scbptr(ahd);
4857 scb = ahd_lookup_scb(ahd, scb_index);
4859 * XXX Actually check data direction in the sequencer?
4860 * Perhaps add datadir to some spare bits in the hscb?
4862 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4863 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
4865 * Ignore the message if we haven't
4866 * seen an appropriate data phase yet.
4870 * If the residual occurred on the last
4871 * transfer and the transfer request was
4872 * expected to end on an odd count, do
4873 * nothing. Otherwise, subtract a byte
4874 * and update the residual count accordingly.
4878 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4879 if ((sgptr & SG_LIST_NULL) != 0
4880 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4881 & SCB_XFERLEN_ODD) != 0) {
4883 * If the residual occurred on the last
4884 * transfer and the transfer request was
4885 * expected to end on an odd count, do
4892 /* Pull in the rest of the sgptr */
4893 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4894 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4895 if ((sgptr & SG_LIST_NULL) != 0) {
4897 * The residual data count is not updated
4898 * for the command run to completion case.
4899 * Explicitly zero the count.
4901 data_cnt &= ~AHD_SG_LEN_MASK;
4904 sgptr &= SG_PTR_MASK;
4905 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4906 struct ahd_dma64_seg *sg;
4908 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4911 * The residual sg ptr points to the next S/G
4912 * to load so we must go back one.
4915 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4916 if (sg != scb->sg_list
4917 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4919 sglen = aic_le32toh(sg->len);
4921 * Preserve High Address and SG_LIST
4922 * bits while setting the count to 1.
4924 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4927 * Increment sg so it points to the
4931 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4935 struct ahd_dma_seg *sg;
4937 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4940 * The residual sg ptr points to the next S/G
4941 * to load so we must go back one.
4944 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4945 if (sg != scb->sg_list
4946 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4948 sglen = aic_le32toh(sg->len);
4950 * Preserve High Address and SG_LIST
4951 * bits while setting the count to 1.
4953 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4956 * Increment sg so it points to the
4960 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4965 * Toggle the "oddness" of the transfer length
4966 * to handle this mid-transfer ignore wide
4967 * residue. This ensures that the oddness is
4968 * correct for subsequent data transfers.
4970 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4971 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4974 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4975 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4977 * The FIFO's pointers will be updated if/when the
4978 * sequencer re-enters a data phase.
4985 * Reinitialize the data pointers for the active transfer
4986 * based on its current residual.
4989 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
4992 ahd_mode_state saved_modes;
4999 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
5000 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
5002 scb_index = ahd_get_scbptr(ahd);
5003 scb = ahd_lookup_scb(ahd, scb_index);
5006 * Release and reacquire the FIFO so we
5007 * have a clean slate.
5009 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5011 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5014 ahd_print_path(ahd, scb);
5015 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5016 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5018 saved_modes = ahd_save_modes(ahd);
5019 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5020 ahd_outb(ahd, DFFSTAT,
5021 ahd_inb(ahd, DFFSTAT)
5022 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5025 * Determine initial values for data_addr and data_cnt
5026 * for resuming the data phase.
5028 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5029 sgptr &= SG_PTR_MASK;
5031 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5032 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5033 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5035 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5036 struct ahd_dma64_seg *sg;
5038 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5040 /* The residual sg_ptr always points to the next sg */
5043 dataptr = aic_le64toh(sg->addr)
5044 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5046 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5048 struct ahd_dma_seg *sg;
5050 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5052 /* The residual sg_ptr always points to the next sg */
5055 dataptr = aic_le32toh(sg->addr)
5056 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5058 ahd_outb(ahd, HADDR + 4,
5059 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5061 ahd_outl(ahd, HADDR, dataptr);
5062 ahd_outb(ahd, HCNT + 2, resid >> 16);
5063 ahd_outb(ahd, HCNT + 1, resid >> 8);
5064 ahd_outb(ahd, HCNT, resid);
5068 * Handle the effects of issuing a bus device reset message.
5071 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5072 u_int lun, cam_status status, char *message,
5075 #ifdef AHD_TARGET_MODE
5076 struct ahd_tmode_tstate* tstate;
5080 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5081 lun, SCB_LIST_NULL, devinfo->role,
5084 #ifdef AHD_TARGET_MODE
5086 * Send an immediate notify ccb to all target mord peripheral
5087 * drivers affected by this action.
5089 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5090 if (tstate != NULL) {
5094 if (lun != CAM_LUN_WILDCARD) {
5096 max_lun = AHD_NUM_LUNS - 1;
5101 for (cur_lun <= max_lun; cur_lun++) {
5102 struct ahd_tmode_lstate* lstate;
5104 lstate = tstate->enabled_luns[cur_lun];
5108 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5109 MSG_BUS_DEV_RESET, /*arg*/0);
5110 ahd_send_lstate_events(ahd, lstate);
5116 * Go back to async/narrow transfers and renegotiate.
5118 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5119 AHD_TRANS_CUR, /*paused*/TRUE);
5120 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5121 /*ppr_options*/0, AHD_TRANS_CUR,
5124 if (status != CAM_SEL_TIMEOUT)
5125 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5126 lun, AC_SENT_BDR, NULL);
5129 && (verbose_level <= bootverbose)) {
5130 AHD_CORRECTABLE_ERROR(ahd);
5131 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5132 message, devinfo->channel, devinfo->target, found);
5136 #ifdef AHD_TARGET_MODE
5138 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5143 * To facilitate adding multiple messages together,
5144 * each routine should increment the index and len
5145 * variables instead of setting them explicitly.
5147 ahd->msgout_index = 0;
5148 ahd->msgout_len = 0;
5150 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5151 ahd_build_transfer_msg(ahd, devinfo);
5153 panic("ahd_intr: AWAITING target message with no message");
5155 ahd->msgout_index = 0;
5156 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5159 /**************************** Initialization **********************************/
5161 ahd_sglist_size(struct ahd_softc *ahd)
5163 bus_size_t list_size;
5165 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5166 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5167 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5172 * Calculate the optimum S/G List allocation size. S/G elements used
5173 * for a given transaction must be physically contiguous. Assume the
5174 * OS will allocate full pages to us, so it doesn't make sense to request
5178 ahd_sglist_allocsize(struct ahd_softc *ahd)
5180 bus_size_t sg_list_increment;
5181 bus_size_t sg_list_size;
5182 bus_size_t max_list_size;
5183 bus_size_t best_list_size;
5185 /* Start out with the minimum required for AHD_NSEG. */
5186 sg_list_increment = ahd_sglist_size(ahd);
5187 sg_list_size = sg_list_increment;
5189 /* Get us as close as possible to a page in size. */
5190 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5191 sg_list_size += sg_list_increment;
5194 * Try to reduce the amount of wastage by allocating
5197 best_list_size = sg_list_size;
5198 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5199 if (max_list_size < 4 * PAGE_SIZE)
5200 max_list_size = 4 * PAGE_SIZE;
5201 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5202 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5203 while ((sg_list_size + sg_list_increment) <= max_list_size
5204 && (sg_list_size % PAGE_SIZE) != 0) {
5206 bus_size_t best_mod;
5208 sg_list_size += sg_list_increment;
5209 new_mod = sg_list_size % PAGE_SIZE;
5210 best_mod = best_list_size % PAGE_SIZE;
5211 if (new_mod > best_mod || new_mod == 0) {
5212 best_list_size = sg_list_size;
5215 return (best_list_size);
5219 * Allocate a controller structure for a new device
5220 * and perform initial initializion.
5223 ahd_alloc(void *platform_arg, char *name)
5225 struct ahd_softc *ahd;
5228 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT);
5230 printf("aic7xxx: cannot malloc softc!\n");
5231 free(name, M_DEVBUF);
5235 ahd = device_get_softc((device_t)platform_arg);
5237 memset(ahd, 0, sizeof(*ahd));
5238 ahd->seep_config = malloc(sizeof(*ahd->seep_config),
5239 M_DEVBUF, M_NOWAIT);
5240 if (ahd->seep_config == NULL) {
5242 free(ahd, M_DEVBUF);
5244 free(name, M_DEVBUF);
5247 LIST_INIT(&ahd->pending_scbs);
5248 LIST_INIT(&ahd->timedout_scbs);
5249 /* We don't know our unit number until the OSM sets it */
5252 ahd->description = NULL;
5253 ahd->bus_description = NULL;
5255 ahd->chip = AHD_NONE;
5256 ahd->features = AHD_FENONE;
5257 ahd->bugs = AHD_BUGNONE;
5258 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5259 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5260 aic_timer_init(&ahd->reset_timer);
5261 aic_timer_init(&ahd->stat_timer);
5262 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5263 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5264 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5265 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5266 ahd->int_coalescing_stop_threshold =
5267 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5269 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5275 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5276 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5277 ahd_name(ahd), (u_int)sizeof(struct scb),
5278 (u_int)sizeof(struct hardware_scb));
5285 ahd_softc_init(struct ahd_softc *ahd)
5294 ahd_softc_insert(struct ahd_softc *ahd)
5296 struct ahd_softc *list_ahd;
5298 #if AIC_PCI_CONFIG > 0
5300 * Second Function PCI devices need to inherit some
5301 * settings from function 0.
5303 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5304 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5305 aic_dev_softc_t list_pci;
5306 aic_dev_softc_t pci;
5308 list_pci = list_ahd->dev_softc;
5309 pci = ahd->dev_softc;
5310 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
5311 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
5312 struct ahd_softc *master;
5313 struct ahd_softc *slave;
5315 if (aic_get_pci_function(list_pci) == 0) {
5322 slave->flags &= ~AHD_BIOS_ENABLED;
5324 master->flags & AHD_BIOS_ENABLED;
5332 * Insertion sort into our list of softcs.
5334 list_ahd = TAILQ_FIRST(&ahd_tailq);
5335 while (list_ahd != NULL
5336 && ahd_softc_comp(ahd, list_ahd) <= 0)
5337 list_ahd = TAILQ_NEXT(list_ahd, links);
5338 if (list_ahd != NULL)
5339 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5341 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5346 ahd_set_unit(struct ahd_softc *ahd, int unit)
5352 ahd_set_name(struct ahd_softc *ahd, char *name)
5354 if (ahd->name != NULL)
5355 free(ahd->name, M_DEVBUF);
5360 ahd_free(struct ahd_softc *ahd)
5364 ahd_terminate_recovery_thread(ahd);
5365 switch (ahd->init_level) {
5371 aic_dmamap_unload(ahd, ahd->shared_data_dmat,
5372 ahd->shared_data_map.dmamap);
5375 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5376 ahd->shared_data_map.dmamap);
5379 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5382 aic_dma_tag_destroy(ahd, ahd->buffer_dmat);
5390 aic_dma_tag_destroy(ahd, ahd->parent_dmat);
5392 ahd_platform_free(ahd);
5393 ahd_fini_scbdata(ahd);
5394 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5395 struct ahd_tmode_tstate *tstate;
5397 tstate = ahd->enabled_targets[i];
5398 if (tstate != NULL) {
5399 #ifdef AHD_TARGET_MODE
5402 for (j = 0; j < AHD_NUM_LUNS; j++) {
5403 struct ahd_tmode_lstate *lstate;
5405 lstate = tstate->enabled_luns[j];
5406 if (lstate != NULL) {
5407 xpt_free_path(lstate->path);
5408 free(lstate, M_DEVBUF);
5412 free(tstate, M_DEVBUF);
5415 #ifdef AHD_TARGET_MODE
5416 if (ahd->black_hole != NULL) {
5417 xpt_free_path(ahd->black_hole->path);
5418 free(ahd->black_hole, M_DEVBUF);
5421 if (ahd->name != NULL)
5422 free(ahd->name, M_DEVBUF);
5423 if (ahd->seep_config != NULL)
5424 free(ahd->seep_config, M_DEVBUF);
5425 if (ahd->saved_stack != NULL)
5426 free(ahd->saved_stack, M_DEVBUF);
5428 free(ahd, M_DEVBUF);
5434 ahd_shutdown(void *arg)
5436 struct ahd_softc *ahd;
5438 ahd = (struct ahd_softc *)arg;
5441 * Stop periodic timer callbacks.
5443 aic_timer_stop(&ahd->reset_timer);
5444 aic_timer_stop(&ahd->stat_timer);
5446 /* This will reset most registers to 0, but not all */
5447 ahd_reset(ahd, /*reinit*/FALSE);
5451 * Reset the controller and record some information about it
5452 * that is only available just after a reset. If "reinit" is
5453 * non-zero, this reset occurred after initial configuration
5454 * and the caller requests that the chip be fully reinitialized
5455 * to a runable state. Chip interrupts are *not* enabled after
5456 * a reinitialization. The caller must enable interrupts via
5457 * ahd_intr_enable().
5460 ahd_reset(struct ahd_softc *ahd, int reinit)
5467 * Preserve the value of the SXFRCTL1 register for all channels.
5468 * It contains settings that affect termination and we don't want
5469 * to disturb the integrity of the bus.
5472 ahd_update_modes(ahd);
5473 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5474 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5476 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5477 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5482 * During the assertion of CHIPRST, the chip
5483 * does not disable its parity logic prior to
5484 * the start of the reset. This may cause a
5485 * parity error to be detected and thus a
5486 * spurious SERR or PERR assertion. Disble
5487 * PERR and SERR responses during the CHIPRST.
5489 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5490 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5491 mod_cmd, /*bytes*/2);
5493 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5496 * Ensure that the reset has finished. We delay 1000us
5497 * prior to reading the register to make sure the chip
5498 * has sufficiently completed its reset to handle register
5504 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5507 printf("%s: WARNING - Failed chip reset! "
5508 "Trying to initialize anyway.\n", ahd_name(ahd));
5509 AHD_FATAL_ERROR(ahd);
5511 ahd_outb(ahd, HCNTRL, ahd->pause);
5513 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5515 * Clear any latched PCI error status and restore
5516 * previous SERR and PERR response enables.
5518 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5520 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5525 * Mode should be SCSI after a chip reset, but lets
5526 * set it just to be safe. We touch the MODE_PTR
5527 * register directly so as to bypass the lazy update
5528 * code in ahd_set_modes().
5530 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5531 ahd_outb(ahd, MODE_PTR,
5532 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5537 * We must always initialize STPWEN to 1 before we
5538 * restore the saved values. STPWEN is initialized
5539 * to a tri-state condition which can only be cleared
5542 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5543 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5545 /* Determine chip configuration */
5546 ahd->features &= ~AHD_WIDE;
5547 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5548 ahd->features |= AHD_WIDE;
5551 * If a recovery action has forced a chip reset,
5552 * re-initialize the chip to our liking.
5561 * Determine the number of SCBs available on the controller
5564 ahd_probe_scbs(struct ahd_softc *ahd) {
5567 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5568 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5569 for (i = 0; i < AHD_SCB_MAX; i++) {
5572 ahd_set_scbptr(ahd, i);
5573 ahd_outw(ahd, SCB_BASE, i);
5574 for (j = 2; j < 64; j++)
5575 ahd_outb(ahd, SCB_BASE+j, 0);
5576 /* Start out life as unallocated (needing an abort) */
5577 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5578 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5580 ahd_set_scbptr(ahd, 0);
5581 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5588 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5592 baddr = (bus_addr_t *)arg;
5593 *baddr = segs->ds_addr;
5597 ahd_initialize_hscbs(struct ahd_softc *ahd)
5601 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5602 ahd_set_scbptr(ahd, i);
5604 /* Clear the control byte. */
5605 ahd_outb(ahd, SCB_CONTROL, 0);
5607 /* Set the next pointer */
5608 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5613 ahd_init_scbdata(struct ahd_softc *ahd)
5615 struct scb_data *scb_data;
5618 scb_data = &ahd->scb_data;
5619 TAILQ_INIT(&scb_data->free_scbs);
5620 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5621 LIST_INIT(&scb_data->free_scb_lists[i]);
5622 LIST_INIT(&scb_data->any_dev_free_scb_list);
5623 SLIST_INIT(&scb_data->hscb_maps);
5624 SLIST_INIT(&scb_data->sg_maps);
5625 SLIST_INIT(&scb_data->sense_maps);
5627 /* Determine the number of hardware SCBs and initialize them */
5628 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5629 if (scb_data->maxhscbs == 0) {
5630 printf("%s: No SCB space found\n", ahd_name(ahd));
5631 AHD_FATAL_ERROR(ahd);
5635 ahd_initialize_hscbs(ahd);
5638 * Create our DMA tags. These tags define the kinds of device
5639 * accessible memory allocations and memory mappings we will
5640 * need to perform during normal operation.
5642 * Unless we need to further restrict the allocation, we rely
5643 * on the restrictions of the parent dmat, hence the common
5644 * use of MAXADDR and MAXSIZE.
5647 /* DMA tag for our hardware scb structures */
5648 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5649 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5650 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5651 /*highaddr*/BUS_SPACE_MAXADDR,
5652 /*filter*/NULL, /*filterarg*/NULL,
5653 PAGE_SIZE, /*nsegments*/1,
5654 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5655 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5659 scb_data->init_level++;
5661 /* DMA tag for our S/G structures. */
5662 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5663 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5664 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5665 /*highaddr*/BUS_SPACE_MAXADDR,
5666 /*filter*/NULL, /*filterarg*/NULL,
5667 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5668 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5669 /*flags*/0, &scb_data->sg_dmat) != 0) {
5673 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5674 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5675 ahd_sglist_allocsize(ahd));
5678 scb_data->init_level++;
5680 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5681 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5682 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5683 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5684 /*highaddr*/BUS_SPACE_MAXADDR,
5685 /*filter*/NULL, /*filterarg*/NULL,
5686 PAGE_SIZE, /*nsegments*/1,
5687 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5688 /*flags*/0, &scb_data->sense_dmat) != 0) {
5692 scb_data->init_level++;
5694 /* Perform initial CCB allocation */
5695 while (ahd_alloc_scbs(ahd) != 0)
5698 if (scb_data->numscbs == 0) {
5699 printf("%s: ahd_init_scbdata - "
5700 "Unable to allocate initial scbs\n",
5706 * Note that we were successful
5716 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5721 * Look on the pending list.
5723 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5724 if (SCB_GET_TAG(scb) == tag)
5729 * Then on all of the collision free lists.
5731 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5732 struct scb *list_scb;
5736 if (SCB_GET_TAG(list_scb) == tag)
5738 list_scb = LIST_NEXT(list_scb, collision_links);
5743 * And finally on the generic free list.
5745 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5746 if (SCB_GET_TAG(scb) == tag)
5754 ahd_fini_scbdata(struct ahd_softc *ahd)
5756 struct scb_data *scb_data;
5758 scb_data = &ahd->scb_data;
5759 if (scb_data == NULL)
5762 switch (scb_data->init_level) {
5766 struct map_node *sns_map;
5768 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5769 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5770 aic_dmamap_unload(ahd, scb_data->sense_dmat,
5772 aic_dmamem_free(ahd, scb_data->sense_dmat,
5773 sns_map->vaddr, sns_map->dmamap);
5774 free(sns_map, M_DEVBUF);
5776 aic_dma_tag_destroy(ahd, scb_data->sense_dmat);
5781 struct map_node *sg_map;
5783 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5784 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5785 aic_dmamap_unload(ahd, scb_data->sg_dmat,
5787 aic_dmamem_free(ahd, scb_data->sg_dmat,
5788 sg_map->vaddr, sg_map->dmamap);
5789 free(sg_map, M_DEVBUF);
5791 aic_dma_tag_destroy(ahd, scb_data->sg_dmat);
5796 struct map_node *hscb_map;
5798 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5799 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5800 aic_dmamap_unload(ahd, scb_data->hscb_dmat,
5802 aic_dmamem_free(ahd, scb_data->hscb_dmat,
5803 hscb_map->vaddr, hscb_map->dmamap);
5804 free(hscb_map, M_DEVBUF);
5806 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5819 * DSP filter Bypass must be enabled until the first selection
5820 * after a change in bus mode (Razor #491 and #493).
5823 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5825 ahd_mode_state saved_modes;
5827 saved_modes = ahd_save_modes(ahd);
5828 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5829 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5830 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5831 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5833 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5834 printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5836 ahd_restore_modes(ahd, saved_modes);
5837 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5841 ahd_iocell_first_selection(struct ahd_softc *ahd)
5843 ahd_mode_state saved_modes;
5846 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5848 saved_modes = ahd_save_modes(ahd);
5849 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5850 sblkctl = ahd_inb(ahd, SBLKCTL);
5851 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5853 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5854 printf("%s: iocell first selection\n", ahd_name(ahd));
5856 if ((sblkctl & ENAB40) != 0) {
5857 ahd_outb(ahd, DSPDATACTL,
5858 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5860 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5861 printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5864 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5865 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5866 ahd_restore_modes(ahd, saved_modes);
5867 ahd->flags |= AHD_HAD_FIRST_SEL;
5870 /*************************** SCB Management ***********************************/
5872 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5874 struct scb_list *free_list;
5875 struct scb_tailq *free_tailq;
5876 struct scb *first_scb;
5878 scb->flags |= SCB_ON_COL_LIST;
5879 AHD_SET_SCB_COL_IDX(scb, col_idx);
5880 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5881 free_tailq = &ahd->scb_data.free_scbs;
5882 first_scb = LIST_FIRST(free_list);
5883 if (first_scb != NULL) {
5884 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5886 LIST_INSERT_HEAD(free_list, scb, collision_links);
5887 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5892 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5894 struct scb_list *free_list;
5895 struct scb_tailq *free_tailq;
5896 struct scb *first_scb;
5899 scb->flags &= ~SCB_ON_COL_LIST;
5900 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5901 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5902 free_tailq = &ahd->scb_data.free_scbs;
5903 first_scb = LIST_FIRST(free_list);
5904 if (first_scb == scb) {
5905 struct scb *next_scb;
5908 * Maintain order in the collision free
5909 * lists for fairness if this device has
5910 * other colliding tags active.
5912 next_scb = LIST_NEXT(scb, collision_links);
5913 if (next_scb != NULL) {
5914 TAILQ_INSERT_AFTER(free_tailq, scb,
5915 next_scb, links.tqe);
5917 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5919 LIST_REMOVE(scb, collision_links);
5923 * Get a free scb. If there are none, see if we can allocate a new SCB.
5926 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5933 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5934 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5935 ahd_rem_col_list(ahd, scb);
5939 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5942 if (ahd_alloc_scbs(ahd) == 0)
5946 LIST_REMOVE(scb, links.le);
5947 if (col_idx != AHD_NEVER_COL_IDX
5948 && (scb->col_scb != NULL)
5949 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5950 LIST_REMOVE(scb->col_scb, links.le);
5951 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5954 scb->flags |= SCB_ACTIVE;
5959 * Return an SCB resource to the free list.
5962 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5965 /* Clean up for the next user */
5966 scb->flags = SCB_FLAG_NONE;
5967 scb->hscb->control = 0;
5968 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5970 if (scb->col_scb == NULL) {
5972 * No collision possible. Just free normally.
5974 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5976 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
5978 * The SCB we might have collided with is on
5979 * a free collision list. Put both SCBs on
5982 ahd_rem_col_list(ahd, scb->col_scb);
5983 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5985 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5986 scb->col_scb, links.le);
5987 } else if ((scb->col_scb->flags
5988 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
5989 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
5991 * The SCB we might collide with on the next allocation
5992 * is still active in a non-packetized, tagged, context.
5993 * Put us on the SCB collision list.
5995 ahd_add_col_list(ahd, scb,
5996 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
5999 * The SCB we might collide with on the next allocation
6000 * is either active in a packetized context, or free.
6001 * Since we can't collide, put this SCB on the generic
6004 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6008 aic_platform_scb_free(ahd, scb);
6012 ahd_alloc_scbs(struct ahd_softc *ahd)
6014 struct scb_data *scb_data;
6015 struct scb *next_scb;
6016 struct hardware_scb *hscb;
6017 struct map_node *hscb_map;
6018 struct map_node *sg_map;
6019 struct map_node *sense_map;
6021 uint8_t *sense_data;
6022 bus_addr_t hscb_busaddr;
6023 bus_addr_t sg_busaddr;
6024 bus_addr_t sense_busaddr;
6028 scb_data = &ahd->scb_data;
6029 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
6030 /* Can't allocate any more */
6033 if (scb_data->scbs_left != 0) {
6036 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
6037 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
6038 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
6039 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
6041 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
6043 if (hscb_map == NULL)
6046 /* Allocate the next batch of hardware SCBs */
6047 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat,
6048 (void **)&hscb_map->vaddr,
6049 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
6050 &hscb_map->dmamap) != 0) {
6051 free(hscb_map, M_DEVBUF);
6055 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
6057 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
6058 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6059 &hscb_map->busaddr, /*flags*/0);
6061 hscb = (struct hardware_scb *)hscb_map->vaddr;
6062 hscb_busaddr = hscb_map->busaddr;
6063 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6066 if (scb_data->sgs_left != 0) {
6069 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6070 - scb_data->sgs_left) * ahd_sglist_size(ahd);
6071 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6072 segs = sg_map->vaddr + offset;
6073 sg_busaddr = sg_map->busaddr + offset;
6075 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
6080 /* Allocate the next batch of S/G lists */
6081 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat,
6082 (void **)&sg_map->vaddr,
6083 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
6084 &sg_map->dmamap) != 0) {
6085 free(sg_map, M_DEVBUF);
6089 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6091 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6092 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6093 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0);
6095 segs = sg_map->vaddr;
6096 sg_busaddr = sg_map->busaddr;
6097 scb_data->sgs_left =
6098 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6100 if (ahd_debug & AHD_SHOW_MEMORY)
6101 printf("Mapped SG data\n");
6105 if (scb_data->sense_left != 0) {
6108 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6109 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6110 sense_data = sense_map->vaddr + offset;
6111 sense_busaddr = sense_map->busaddr + offset;
6113 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
6115 if (sense_map == NULL)
6118 /* Allocate the next batch of sense buffers */
6119 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat,
6120 (void **)&sense_map->vaddr,
6121 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6122 free(sense_map, M_DEVBUF);
6126 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6128 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6129 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6130 &sense_map->busaddr, /*flags*/0);
6132 sense_data = sense_map->vaddr;
6133 sense_busaddr = sense_map->busaddr;
6134 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6136 if (ahd_debug & AHD_SHOW_MEMORY)
6137 printf("Mapped sense data\n");
6141 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6142 newcount = MIN(newcount, scb_data->sgs_left);
6143 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6144 scb_data->sense_left -= newcount;
6145 scb_data->scbs_left -= newcount;
6146 scb_data->sgs_left -= newcount;
6147 for (i = 0; i < newcount; i++) {
6148 struct scb_platform_data *pdata;
6154 next_scb = (struct scb *)malloc(sizeof(*next_scb),
6155 M_DEVBUF, M_NOWAIT);
6156 if (next_scb == NULL)
6159 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
6160 M_DEVBUF, M_NOWAIT);
6161 if (pdata == NULL) {
6162 free(next_scb, M_DEVBUF);
6165 next_scb->platform_data = pdata;
6166 next_scb->hscb_map = hscb_map;
6167 next_scb->sg_map = sg_map;
6168 next_scb->sense_map = sense_map;
6169 next_scb->sg_list = segs;
6170 next_scb->sense_data = sense_data;
6171 next_scb->sense_busaddr = sense_busaddr;
6172 memset(hscb, 0, sizeof(*hscb));
6173 next_scb->hscb = hscb;
6174 hscb->hscb_busaddr = aic_htole32(hscb_busaddr);
6177 * The sequencer always starts with the second entry.
6178 * The first entry is embedded in the scb.
6180 next_scb->sg_list_busaddr = sg_busaddr;
6181 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6182 next_scb->sg_list_busaddr
6183 += sizeof(struct ahd_dma64_seg);
6185 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6186 next_scb->ahd_softc = ahd;
6187 next_scb->flags = SCB_FLAG_NONE;
6189 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6192 free(next_scb, M_DEVBUF);
6193 free(pdata, M_DEVBUF);
6197 next_scb->hscb->tag = aic_htole16(scb_data->numscbs);
6198 col_tag = scb_data->numscbs ^ 0x100;
6199 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6200 if (next_scb->col_scb != NULL)
6201 next_scb->col_scb->col_scb = next_scb;
6202 aic_timer_init(&next_scb->io_timer);
6203 ahd_free_scb(ahd, next_scb);
6205 hscb_busaddr += sizeof(*hscb);
6206 segs += ahd_sglist_size(ahd);
6207 sg_busaddr += ahd_sglist_size(ahd);
6208 sense_data += AHD_SENSE_BUFSIZE;
6209 sense_busaddr += AHD_SENSE_BUFSIZE;
6210 scb_data->numscbs++;
6216 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6222 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6225 speed = "Ultra320 ";
6226 if ((ahd->features & AHD_WIDE) != 0) {
6231 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6232 speed, type, ahd->channel, ahd->our_id);
6235 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
6236 ahd->scb_data.maxhscbs);
6239 static const char *channel_strings[] = {
6246 static const char *termstat_strings[] = {
6247 "Terminated Correctly",
6254 * Start the board, ready for normal operation
6257 ahd_init(struct ahd_softc *ahd)
6259 uint8_t *next_vaddr;
6260 bus_addr_t next_baddr;
6261 size_t driver_data_size;
6265 uint8_t current_sensing;
6268 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6270 ahd->stack_size = ahd_probe_stack_size(ahd);
6271 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t),
6272 M_DEVBUF, M_NOWAIT);
6273 if (ahd->saved_stack == NULL)
6277 * Verify that the compiler hasn't over-agressively
6278 * padded important structures.
6280 if (sizeof(struct hardware_scb) != 64)
6281 panic("Hardware SCB size is incorrect");
6284 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6285 ahd->flags |= AHD_SEQUENCER_DEBUG;
6289 * Default to allowing initiator operations.
6291 ahd->flags |= AHD_INITIATORROLE;
6294 * Only allow target mode features if this unit has them enabled.
6296 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6297 ahd->features &= ~AHD_TARGETMODE;
6300 /* DMA tag for mapping buffers into device visible space. */
6301 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6302 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6303 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6304 ? (bus_addr_t)0x7FFFFFFFFFULL
6305 : BUS_SPACE_MAXADDR_32BIT,
6306 /*highaddr*/BUS_SPACE_MAXADDR,
6307 /*filter*/NULL, /*filterarg*/NULL,
6308 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6309 /*nsegments*/AHD_NSEG,
6310 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6311 /*flags*/BUS_DMA_ALLOCNOW,
6312 &ahd->buffer_dmat) != 0) {
6320 * DMA tag for our command fifos and other data in system memory
6321 * the card's sequencer must be able to access. For initiator
6322 * roles, we need to allocate space for the qoutfifo. When providing
6323 * for the target mode role, we must additionally provide space for
6324 * the incoming target command fifo.
6326 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6327 + sizeof(struct hardware_scb);
6328 if ((ahd->features & AHD_TARGETMODE) != 0)
6329 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6330 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6331 driver_data_size += PKT_OVERRUN_BUFSIZE;
6332 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6333 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6334 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6335 /*highaddr*/BUS_SPACE_MAXADDR,
6336 /*filter*/NULL, /*filterarg*/NULL,
6339 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6340 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6346 /* Allocation of driver data */
6347 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat,
6348 (void **)&ahd->shared_data_map.vaddr,
6349 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
6350 &ahd->shared_data_map.dmamap) != 0) {
6356 /* And permanently map it in */
6357 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6358 ahd->shared_data_map.vaddr, driver_data_size,
6359 ahd_dmamap_cb, &ahd->shared_data_map.busaddr,
6361 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6362 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6363 next_baddr = ahd->shared_data_map.busaddr
6364 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6365 if ((ahd->features & AHD_TARGETMODE) != 0) {
6366 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6367 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6368 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6371 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6372 ahd->overrun_buf = next_vaddr;
6373 next_vaddr += PKT_OVERRUN_BUFSIZE;
6374 next_baddr += PKT_OVERRUN_BUFSIZE;
6378 * We need one SCB to serve as the "next SCB". Since the
6379 * tag identifier in this SCB will never be used, there is
6380 * no point in using a valid HSCB tag from an SCB pulled from
6381 * the standard free pool. So, we allocate this "sentinel"
6382 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6384 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6385 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6386 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr);
6390 /* Allocate SCB data now that buffer_dmat is initialized */
6391 if (ahd_init_scbdata(ahd) != 0)
6394 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6395 ahd->flags &= ~AHD_RESET_BUS_A;
6398 * Before committing these settings to the chip, give
6399 * the OSM one last chance to modify our configuration.
6401 ahd_platform_init(ahd);
6403 /* Bring up the chip. */
6406 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6408 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6412 * Verify termination based on current draw and
6413 * warn user if the bus is over/under terminated.
6415 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6418 printf("%s: current sensing timeout 1\n", ahd_name(ahd));
6421 for (i = 20, fstat = FLX_FSTAT_BUSY;
6422 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6423 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6425 printf("%s: current sensing timeout 2\n",
6431 printf("%s: Timedout during current-sensing test\n",
6436 /* Latch Current Sensing status. */
6437 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing);
6439 printf("%s: current sensing timeout 3\n", ahd_name(ahd));
6443 /* Diable current sensing. */
6444 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6447 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6448 printf("%s: current_sensing == 0x%x\n",
6449 ahd_name(ahd), current_sensing);
6453 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6456 term_stat = (current_sensing & FLX_CSTAT_MASK);
6457 switch (term_stat) {
6458 case FLX_CSTAT_OVER:
6459 case FLX_CSTAT_UNDER:
6461 case FLX_CSTAT_INVALID:
6462 case FLX_CSTAT_OKAY:
6463 if (warn_user == 0 && bootverbose == 0)
6465 printf("%s: %s Channel %s\n", ahd_name(ahd),
6466 channel_strings[i], termstat_strings[term_stat]);
6471 printf("%s: WARNING. Termination is not configured correctly.\n"
6472 "%s: WARNING. SCSI bus operations may FAIL.\n",
6473 ahd_name(ahd), ahd_name(ahd));
6474 AHD_CORRECTABLE_ERROR(ahd);
6478 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
6479 ahd_stat_timer, ahd);
6484 * (Re)initialize chip state after a chip reset.
6487 ahd_chip_init(struct ahd_softc *ahd)
6491 u_int scsiseq_template;
6496 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6498 * Take the LED out of diagnostic mode
6500 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6503 * Return HS_MAILBOX to its default value.
6505 ahd->hs_mailbox = 0;
6506 ahd_outb(ahd, HS_MAILBOX, 0);
6508 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6509 ahd_outb(ahd, IOWNID, ahd->our_id);
6510 ahd_outb(ahd, TOWNID, ahd->our_id);
6511 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6512 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6513 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6514 && (ahd->seltime != STIMESEL_MIN)) {
6516 * The selection timer duration is twice as long
6517 * as it should be. Halve it by adding "1" to
6518 * the user specified setting.
6520 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6522 sxfrctl1 |= ahd->seltime;
6525 ahd_outb(ahd, SXFRCTL0, DFON);
6526 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6527 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6530 * Now that termination is set, wait for up
6531 * to 500ms for our transceivers to settle. If
6532 * the adapter does not have a cable attached,
6533 * the transceivers may never settle, so don't
6534 * complain if we fail here.
6537 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6541 /* Clear any false bus resets due to the transceivers settling */
6542 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6543 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6545 /* Initialize mode specific S/G state. */
6546 for (i = 0; i < 2; i++) {
6547 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6548 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6549 ahd_outb(ahd, SG_STATE, 0);
6550 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6551 ahd_outb(ahd, SEQIMODE,
6552 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6553 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6556 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6557 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6558 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6559 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6560 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6561 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6562 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6564 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6566 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6567 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6569 * Do not issue a target abort when a split completion
6570 * error occurs. Let our PCIX interrupt handler deal
6571 * with it instead. H2A4 Razor #625
6573 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6575 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6576 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6579 * Tweak IOCELL settings.
6581 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6582 for (i = 0; i < NUMDSPS; i++) {
6583 ahd_outb(ahd, DSPSELECT, i);
6584 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6587 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6588 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6589 WRTBIASCTL_HP_DEFAULT);
6592 ahd_setup_iocell_workaround(ahd);
6595 * Enable LQI Manager interrupts.
6597 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6598 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6599 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6600 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6602 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6603 * manually for the command phase at the start of a packetized
6604 * selection case. ENLQOBUSFREE should be made redundant by
6605 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6606 * events fail to assert the BUSFREE interrupt so we must
6607 * also enable LQOBUSFREE interrupts.
6609 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6612 * Setup sequencer interrupt handlers.
6614 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6615 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6618 * Setup SCB Offset registers.
6620 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6621 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6624 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6626 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6627 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6628 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6629 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6630 shared_data.idata.cdb));
6631 ahd_outb(ahd, QNEXTPTR,
6632 offsetof(struct hardware_scb, next_hscb_busaddr));
6633 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6634 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6635 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6636 ahd_outb(ahd, LUNLEN,
6637 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6639 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6641 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6642 ahd_outb(ahd, MAXCMD, 0xFF);
6643 ahd_outb(ahd, SCBAUTOPTR,
6644 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6646 /* We haven't been enabled for target mode yet. */
6647 ahd_outb(ahd, MULTARGID, 0);
6648 ahd_outb(ahd, MULTARGID + 1, 0);
6650 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6651 /* Initialize the negotiation table. */
6652 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6654 * Clear the spare bytes in the neg table to avoid
6655 * spurious parity errors.
6657 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6658 ahd_outb(ahd, NEGOADDR, target);
6659 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6660 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6661 ahd_outb(ahd, ANNEXDAT, 0);
6664 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6665 struct ahd_devinfo devinfo;
6666 struct ahd_initiator_tinfo *tinfo;
6667 struct ahd_tmode_tstate *tstate;
6669 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6671 ahd_compile_devinfo(&devinfo, ahd->our_id,
6672 target, CAM_LUN_WILDCARD,
6673 'A', ROLE_INITIATOR);
6674 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6677 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6678 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6680 #ifdef NEEDS_MORE_TESTING
6682 * Always enable abort on incoming L_Qs if this feature is
6683 * supported. We use this to catch invalid SCB references.
6685 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6686 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6689 ahd_outb(ahd, LQCTL1, 0);
6691 /* All of our queues are empty */
6692 ahd->qoutfifonext = 0;
6693 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6694 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6695 for (i = 0; i < AHD_QOUT_SIZE; i++)
6696 ahd->qoutfifo[i].valid_tag = 0;
6697 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6699 ahd->qinfifonext = 0;
6700 for (i = 0; i < AHD_QIN_SIZE; i++)
6701 ahd->qinfifo[i] = SCB_LIST_NULL;
6703 if ((ahd->features & AHD_TARGETMODE) != 0) {
6704 /* All target command blocks start out invalid. */
6705 for (i = 0; i < AHD_TMODE_CMDS; i++)
6706 ahd->targetcmds[i].cmd_valid = 0;
6707 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6708 ahd->tqinfifonext = 1;
6709 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6710 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6713 /* Initialize Scratch Ram. */
6714 ahd_outb(ahd, SEQ_FLAGS, 0);
6715 ahd_outb(ahd, SEQ_FLAGS2, 0);
6717 /* We don't have any waiting selections */
6718 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6719 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6720 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6721 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6722 for (i = 0; i < AHD_NUM_TARGETS; i++)
6723 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6726 * Nobody is waiting to be DMAed into the QOUTFIFO.
6728 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6729 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6730 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6731 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6732 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6735 * The Freeze Count is 0.
6737 ahd->qfreeze_cnt = 0;
6738 ahd_outw(ahd, QFREEZE_COUNT, 0);
6739 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6742 * Tell the sequencer where it can find our arrays in memory.
6744 busaddr = ahd->shared_data_map.busaddr;
6745 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6746 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6749 * Setup the allowed SCSI Sequences based on operational mode.
6750 * If we are a target, we'll enable select in operations once
6751 * we've had a lun enabled.
6753 scsiseq_template = ENAUTOATNP;
6754 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6755 scsiseq_template |= ENRSELI;
6756 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6758 /* There are no busy SCBs yet. */
6759 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6762 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6763 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6767 * Initialize the group code to command length table.
6768 * Vendor Unique codes are set to 0 so we only capture
6769 * the first byte of the cdb. These can be overridden
6770 * when target mode is enabled.
6772 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6773 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6774 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6775 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6776 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6777 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6778 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6779 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6781 /* Tell the sequencer of our initial queue positions */
6782 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6783 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6784 ahd->qinfifonext = 0;
6785 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6786 ahd_set_hescb_qoff(ahd, 0);
6787 ahd_set_snscb_qoff(ahd, 0);
6788 ahd_set_sescb_qoff(ahd, 0);
6789 ahd_set_sdscb_qoff(ahd, 0);
6792 * Tell the sequencer which SCB will be the next one it receives.
6794 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6795 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6798 * Default to coalescing disabled.
6800 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6801 ahd_outw(ahd, CMDS_PENDING, 0);
6802 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6803 ahd->int_coalescing_maxcmds,
6804 ahd->int_coalescing_mincmds);
6805 ahd_enable_coalescing(ahd, FALSE);
6808 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6812 * Setup default device and controller settings.
6813 * This should only be called if our probe has
6814 * determined that no configuration data is available.
6817 ahd_default_config(struct ahd_softc *ahd)
6824 * Allocate a tstate to house information for our
6825 * initiator presence on the bus as well as the user
6826 * data for any target mode initiator.
6828 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6829 printf("%s: unable to allocate ahd_tmode_tstate. "
6830 "Failing attach\n", ahd_name(ahd));
6831 AHD_FATAL_ERROR(ahd);
6835 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6836 struct ahd_devinfo devinfo;
6837 struct ahd_initiator_tinfo *tinfo;
6838 struct ahd_tmode_tstate *tstate;
6839 uint16_t target_mask;
6841 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6844 * We support SPC2 and SPI4.
6846 tinfo->user.protocol_version = 4;
6847 tinfo->user.transport_version = 4;
6849 target_mask = 0x01 << targ;
6850 ahd->user_discenable |= target_mask;
6851 tstate->discenable |= target_mask;
6852 ahd->user_tagenable |= target_mask;
6853 #ifdef AHD_FORCE_160
6854 tinfo->user.period = AHD_SYNCRATE_DT;
6856 tinfo->user.period = AHD_SYNCRATE_160;
6858 tinfo->user.offset = MAX_OFFSET;
6859 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6860 | MSG_EXT_PPR_WR_FLOW
6861 | MSG_EXT_PPR_HOLD_MCS
6862 | MSG_EXT_PPR_IU_REQ
6863 | MSG_EXT_PPR_QAS_REQ
6864 | MSG_EXT_PPR_DT_REQ;
6865 if ((ahd->features & AHD_RTI) != 0)
6866 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6868 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6871 * Start out Async/Narrow/Untagged and with
6872 * conservative protocol support.
6874 tinfo->goal.protocol_version = 2;
6875 tinfo->goal.transport_version = 2;
6876 tinfo->curr.protocol_version = 2;
6877 tinfo->curr.transport_version = 2;
6878 ahd_compile_devinfo(&devinfo, ahd->our_id,
6879 targ, CAM_LUN_WILDCARD,
6880 'A', ROLE_INITIATOR);
6881 tstate->tagenable &= ~target_mask;
6882 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6883 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6884 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6885 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6892 * Parse device configuration information.
6895 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6900 max_targ = sc->max_targets & CFMAXTARG;
6901 ahd->our_id = sc->brtime_id & CFSCSIID;
6904 * Allocate a tstate to house information for our
6905 * initiator presence on the bus as well as the user
6906 * data for any target mode initiator.
6908 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6909 printf("%s: unable to allocate ahd_tmode_tstate. "
6910 "Failing attach\n", ahd_name(ahd));
6911 AHD_FATAL_ERROR(ahd);
6915 for (targ = 0; targ < max_targ; targ++) {
6916 struct ahd_devinfo devinfo;
6917 struct ahd_initiator_tinfo *tinfo;
6918 struct ahd_transinfo *user_tinfo;
6919 struct ahd_tmode_tstate *tstate;
6920 uint16_t target_mask;
6922 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6924 user_tinfo = &tinfo->user;
6927 * We support SPC2 and SPI4.
6929 tinfo->user.protocol_version = 4;
6930 tinfo->user.transport_version = 4;
6932 target_mask = 0x01 << targ;
6933 ahd->user_discenable &= ~target_mask;
6934 tstate->discenable &= ~target_mask;
6935 ahd->user_tagenable &= ~target_mask;
6936 if (sc->device_flags[targ] & CFDISC) {
6937 tstate->discenable |= target_mask;
6938 ahd->user_discenable |= target_mask;
6939 ahd->user_tagenable |= target_mask;
6942 * Cannot be packetized without disconnection.
6944 sc->device_flags[targ] &= ~CFPACKETIZED;
6947 user_tinfo->ppr_options = 0;
6948 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6949 if (user_tinfo->period < CFXFER_ASYNC) {
6950 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6951 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6952 user_tinfo->offset = MAX_OFFSET;
6954 user_tinfo->offset = 0;
6955 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6957 #ifdef AHD_FORCE_160
6958 if (user_tinfo->period <= AHD_SYNCRATE_160)
6959 user_tinfo->period = AHD_SYNCRATE_DT;
6962 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6963 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6964 | MSG_EXT_PPR_WR_FLOW
6965 | MSG_EXT_PPR_HOLD_MCS
6966 | MSG_EXT_PPR_IU_REQ;
6967 if ((ahd->features & AHD_RTI) != 0)
6968 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6971 if ((sc->device_flags[targ] & CFQAS) != 0)
6972 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6974 if ((sc->device_flags[targ] & CFWIDEB) != 0)
6975 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6977 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6979 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6980 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6981 user_tinfo->period, user_tinfo->offset,
6982 user_tinfo->ppr_options);
6985 * Start out Async/Narrow/Untagged and with
6986 * conservative protocol support.
6988 tstate->tagenable &= ~target_mask;
6989 tinfo->goal.protocol_version = 2;
6990 tinfo->goal.transport_version = 2;
6991 tinfo->curr.protocol_version = 2;
6992 tinfo->curr.transport_version = 2;
6993 ahd_compile_devinfo(&devinfo, ahd->our_id,
6994 targ, CAM_LUN_WILDCARD,
6995 'A', ROLE_INITIATOR);
6996 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6997 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6998 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6999 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
7003 ahd->flags &= ~AHD_SPCHK_ENB_A;
7004 if (sc->bios_control & CFSPARITY)
7005 ahd->flags |= AHD_SPCHK_ENB_A;
7007 ahd->flags &= ~AHD_RESET_BUS_A;
7008 if (sc->bios_control & CFRESETB)
7009 ahd->flags |= AHD_RESET_BUS_A;
7011 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
7012 if (sc->bios_control & CFEXTEND)
7013 ahd->flags |= AHD_EXTENDED_TRANS_A;
7015 ahd->flags &= ~AHD_BIOS_ENABLED;
7016 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
7017 ahd->flags |= AHD_BIOS_ENABLED;
7019 ahd->flags &= ~AHD_STPWLEVEL_A;
7020 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
7021 ahd->flags |= AHD_STPWLEVEL_A;
7027 * Parse device configuration information.
7030 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
7034 error = ahd_verify_vpd_cksum(vpd);
7037 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
7038 ahd->flags |= AHD_BOOT_CHANNEL;
7043 ahd_intr_enable(struct ahd_softc *ahd, int enable)
7047 hcntrl = ahd_inb(ahd, HCNTRL);
7049 ahd->pause &= ~INTEN;
7050 ahd->unpause &= ~INTEN;
7053 ahd->pause |= INTEN;
7054 ahd->unpause |= INTEN;
7056 ahd_outb(ahd, HCNTRL, hcntrl);
7060 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
7063 if (timer > AHD_TIMER_MAX_US)
7064 timer = AHD_TIMER_MAX_US;
7065 ahd->int_coalescing_timer = timer;
7067 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7068 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7069 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7070 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7071 ahd->int_coalescing_maxcmds = maxcmds;
7072 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7073 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7074 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7078 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7081 ahd->hs_mailbox &= ~ENINT_COALESCE;
7083 ahd->hs_mailbox |= ENINT_COALESCE;
7084 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7085 ahd_flush_device_writes(ahd);
7086 ahd_run_qoutfifo(ahd);
7090 * Ensure that the card is paused in a location
7091 * outside of all critical sections and that all
7092 * pending work is completed prior to returning.
7093 * This routine should only be called from outside
7094 * an interrupt context.
7097 ahd_pause_and_flushwork(struct ahd_softc *ahd)
7103 ahd->flags |= AHD_ALL_INTERRUPTS;
7106 * Freeze the outgoing selections. We do this only
7107 * until we are safely paused without further selections
7111 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7112 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
7116 * Give the sequencer some time to service
7117 * any active selections.
7123 intstat = ahd_inb(ahd, INTSTAT);
7124 if ((intstat & INT_PEND) == 0) {
7125 ahd_clear_critical_section(ahd);
7126 intstat = ahd_inb(ahd, INTSTAT);
7129 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7130 && ((intstat & INT_PEND) != 0
7131 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7132 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7134 if (maxloops == 0) {
7135 printf("Infinite interrupt loop, INTSTAT = %x",
7136 ahd_inb(ahd, INTSTAT));
7137 AHD_FATAL_ERROR(ahd);
7140 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7142 ahd_flush_qoutfifo(ahd);
7144 ahd_platform_flushwork(ahd);
7145 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7149 ahd_suspend(struct ahd_softc *ahd)
7152 ahd_pause_and_flushwork(ahd);
7154 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7163 ahd_resume(struct ahd_softc *ahd)
7166 ahd_reset(ahd, /*reinit*/TRUE);
7167 ahd_intr_enable(ahd, TRUE);
7172 /************************** Busy Target Table *********************************/
7174 * Set SCBPTR to the SCB that contains the busy
7175 * table entry for TCL. Return the offset into
7176 * the SCB that contains the entry for TCL.
7177 * saved_scbid is dereferenced and set to the
7178 * scbid that should be restored once manipualtion
7179 * of the TCL entry is complete.
7181 static __inline u_int
7182 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7185 * Index to the SCB that contains the busy entry.
7187 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7188 *saved_scbid = ahd_get_scbptr(ahd);
7189 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7190 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7193 * And now calculate the SCB offset to the entry.
7194 * Each entry is 2 bytes wide, hence the
7195 * multiplication by 2.
7197 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7201 * Return the untagged transaction id for a given target/channel lun.
7204 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7210 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7211 scbid = ahd_inw_scbram(ahd, scb_offset);
7212 ahd_set_scbptr(ahd, saved_scbptr);
7217 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7222 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7223 ahd_outw(ahd, scb_offset, scbid);
7224 ahd_set_scbptr(ahd, saved_scbptr);
7227 /************************** SCB and SCB queue management **********************/
7229 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7230 char channel, int lun, u_int tag, role_t role)
7232 int targ = SCB_GET_TARGET(ahd, scb);
7233 char chan = SCB_GET_CHANNEL(ahd, scb);
7234 int slun = SCB_GET_LUN(scb);
7237 match = ((chan == channel) || (channel == ALL_CHANNELS));
7239 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7241 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7243 #ifdef AHD_TARGET_MODE
7246 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7247 if (role == ROLE_INITIATOR) {
7248 match = (group != XPT_FC_GROUP_TMODE)
7249 && ((tag == SCB_GET_TAG(scb))
7250 || (tag == SCB_LIST_NULL));
7251 } else if (role == ROLE_TARGET) {
7252 match = (group == XPT_FC_GROUP_TMODE)
7253 && ((tag == scb->io_ctx->csio.tag_id)
7254 || (tag == SCB_LIST_NULL));
7256 #else /* !AHD_TARGET_MODE */
7257 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7258 #endif /* AHD_TARGET_MODE */
7265 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7271 target = SCB_GET_TARGET(ahd, scb);
7272 lun = SCB_GET_LUN(scb);
7273 channel = SCB_GET_CHANNEL(ahd, scb);
7275 ahd_search_qinfifo(ahd, target, channel, lun,
7276 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7277 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7279 ahd_platform_freeze_devq(ahd, scb);
7283 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7285 struct scb *prev_scb;
7286 ahd_mode_state saved_modes;
7288 saved_modes = ahd_save_modes(ahd);
7289 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7291 if (ahd_qinfifo_count(ahd) != 0) {
7295 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7296 prev_tag = ahd->qinfifo[prev_pos];
7297 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7299 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7300 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7301 ahd_restore_modes(ahd, saved_modes);
7305 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7308 if (prev_scb == NULL) {
7311 busaddr = aic_le32toh(scb->hscb->hscb_busaddr);
7312 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7314 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7315 ahd_sync_scb(ahd, prev_scb,
7316 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7318 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7320 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7321 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7325 ahd_qinfifo_count(struct ahd_softc *ahd)
7329 u_int wrap_qinfifonext;
7331 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7332 qinpos = ahd_get_snscb_qoff(ahd);
7333 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7334 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7335 if (wrap_qinfifonext >= wrap_qinpos)
7336 return (wrap_qinfifonext - wrap_qinpos);
7338 return (wrap_qinfifonext
7339 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7343 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7346 ahd_mode_state saved_modes;
7349 saved_modes = ahd_save_modes(ahd);
7350 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7353 * Don't count any commands as outstanding that the
7354 * sequencer has already marked for completion.
7356 ahd_flush_qoutfifo(ahd);
7359 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7362 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7363 ahd_restore_modes(ahd, saved_modes);
7364 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7368 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7373 ostat = aic_get_transaction_status(scb);
7374 if (ostat == CAM_REQ_INPROG)
7375 aic_set_transaction_status(scb, status);
7376 cstat = aic_get_transaction_status(scb);
7377 if (cstat != CAM_REQ_CMP)
7378 aic_freeze_scb(scb);
7383 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7384 int lun, u_int tag, role_t role, uint32_t status,
7385 ahd_search_action action)
7388 struct scb *mk_msg_scb;
7389 struct scb *prev_scb;
7390 ahd_mode_state saved_modes;
7403 /* Must be in CCHAN mode */
7404 saved_modes = ahd_save_modes(ahd);
7405 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7408 * Halt any pending SCB DMA. The sequencer will reinitiate
7409 * this dma if the qinfifo is not empty once we unpause.
7411 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7412 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7413 ahd_outb(ahd, CCSCBCTL,
7414 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7415 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7418 /* Determine sequencer's position in the qinfifo. */
7419 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7420 qinstart = ahd_get_snscb_qoff(ahd);
7421 qinpos = AHD_QIN_WRAP(qinstart);
7425 if (action == SEARCH_PRINT) {
7426 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7427 qinstart, ahd->qinfifonext);
7431 * Start with an empty queue. Entries that are not chosen
7432 * for removal will be re-added to the queue as we go.
7434 ahd->qinfifonext = qinstart;
7435 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7436 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7438 while (qinpos != qintail) {
7439 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7441 printf("qinpos = %d, SCB index = %d\n",
7442 qinpos, ahd->qinfifo[qinpos]);
7443 AHD_FATAL_ERROR(ahd);
7447 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7449 * We found an scb that needs to be acted on.
7453 case SEARCH_COMPLETE:
7454 if ((scb->flags & SCB_ACTIVE) == 0)
7455 printf("Inactive SCB in qinfifo\n");
7456 ahd_done_with_status(ahd, scb, status);
7461 printf(" 0x%x", ahd->qinfifo[qinpos]);
7464 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7469 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7472 qinpos = AHD_QIN_WRAP(qinpos+1);
7475 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7477 if (action == SEARCH_PRINT)
7478 printf("\nWAITING_TID_QUEUES:\n");
7481 * Search waiting for selection lists. We traverse the
7482 * list of "their ids" waiting for selection and, if
7483 * appropriate, traverse the SCBs of each "their id"
7484 * looking for matches.
7486 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7487 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7488 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7489 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7490 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7493 savedscbptr = ahd_get_scbptr(ahd);
7494 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7495 tid_prev = SCB_LIST_NULL;
7497 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7502 if (targets > AHD_NUM_TARGETS)
7503 panic("TID LIST LOOP");
7505 if (scbid >= ahd->scb_data.numscbs) {
7506 printf("%s: Waiting TID List inconsistency. "
7507 "SCB index == 0x%x, yet numscbs == 0x%x.",
7508 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7509 ahd_dump_card_state(ahd);
7510 panic("for safety");
7512 scb = ahd_lookup_scb(ahd, scbid);
7514 printf("%s: SCB = 0x%x Not Active!\n",
7515 ahd_name(ahd), scbid);
7516 panic("Waiting TID List traversal\n");
7518 ahd_set_scbptr(ahd, scbid);
7519 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7520 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7521 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7527 * We found a list of scbs that needs to be searched.
7529 if (action == SEARCH_PRINT)
7530 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7532 found += ahd_search_scb_list(ahd, target, channel,
7533 lun, tag, role, status,
7534 action, &tid_head, &tid_tail,
7535 SCB_GET_TARGET(ahd, scb));
7537 * Check any MK_MESSAGE SCB that is still waiting to
7538 * enter this target's waiting for selection queue.
7540 if (mk_msg_scb != NULL
7541 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7544 * We found an scb that needs to be acted on.
7548 case SEARCH_COMPLETE:
7549 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7550 printf("Inactive SCB pending MK_MSG\n");
7551 ahd_done_with_status(ahd, mk_msg_scb, status);
7557 printf("Removing MK_MSG scb\n");
7560 * Reset our tail to the tail of the
7561 * main per-target list.
7563 tail_offset = WAITING_SCB_TAILS
7564 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7565 ahd_outw(ahd, tail_offset, tid_tail);
7567 seq_flags2 &= ~PENDING_MK_MESSAGE;
7568 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7569 ahd_outw(ahd, CMDS_PENDING,
7570 ahd_inw(ahd, CMDS_PENDING)-1);
7575 printf(" 0x%x", SCB_GET_TAG(scb));
7582 if (mk_msg_scb != NULL
7583 && SCBID_IS_NULL(tid_head)
7584 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7585 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7587 * When removing the last SCB for a target
7588 * queue with a pending MK_MESSAGE scb, we
7589 * must queue the MK_MESSAGE scb.
7591 printf("Queueing mk_msg_scb\n");
7592 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7593 seq_flags2 &= ~PENDING_MK_MESSAGE;
7594 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7597 if (tid_head != scbid)
7598 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7599 if (!SCBID_IS_NULL(tid_head))
7600 tid_prev = tid_head;
7601 if (action == SEARCH_PRINT)
7605 /* Restore saved state. */
7606 ahd_set_scbptr(ahd, savedscbptr);
7607 ahd_restore_modes(ahd, saved_modes);
7612 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7613 int lun, u_int tag, role_t role, uint32_t status,
7614 ahd_search_action action, u_int *list_head,
7615 u_int *list_tail, u_int tid)
7623 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7625 prev = SCB_LIST_NULL;
7627 *list_tail = SCB_LIST_NULL;
7628 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7629 if (scbid >= ahd->scb_data.numscbs) {
7630 printf("%s:SCB List inconsistency. "
7631 "SCB == 0x%x, yet numscbs == 0x%x.",
7632 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7633 ahd_dump_card_state(ahd);
7634 panic("for safety");
7636 scb = ahd_lookup_scb(ahd, scbid);
7638 printf("%s: SCB = %d Not Active!\n",
7639 ahd_name(ahd), scbid);
7640 panic("Waiting List traversal\n");
7642 ahd_set_scbptr(ahd, scbid);
7644 next = ahd_inw_scbram(ahd, SCB_NEXT);
7645 if (ahd_match_scb(ahd, scb, target, channel,
7646 lun, SCB_LIST_NULL, role) == 0) {
7652 case SEARCH_COMPLETE:
7653 if ((scb->flags & SCB_ACTIVE) == 0)
7654 printf("Inactive SCB in Waiting List\n");
7655 ahd_done_with_status(ahd, scb, status);
7658 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7660 if (SCBID_IS_NULL(prev))
7664 printf("0x%x ", scbid);
7669 if (found > AHD_SCB_MAX)
7670 panic("SCB LIST LOOP");
7672 if (action == SEARCH_COMPLETE
7673 || action == SEARCH_REMOVE)
7674 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7679 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7680 u_int tid_cur, u_int tid_next)
7682 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7684 if (SCBID_IS_NULL(tid_cur)) {
7685 /* Bypass current TID list */
7686 if (SCBID_IS_NULL(tid_prev)) {
7687 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7689 ahd_set_scbptr(ahd, tid_prev);
7690 ahd_outw(ahd, SCB_NEXT2, tid_next);
7692 if (SCBID_IS_NULL(tid_next))
7693 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7695 /* Stitch through tid_cur */
7696 if (SCBID_IS_NULL(tid_prev)) {
7697 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7699 ahd_set_scbptr(ahd, tid_prev);
7700 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7702 ahd_set_scbptr(ahd, tid_cur);
7703 ahd_outw(ahd, SCB_NEXT2, tid_next);
7705 if (SCBID_IS_NULL(tid_next))
7706 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7711 * Manipulate the waiting for selection list and return the
7712 * scb that follows the one that we remove.
7715 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7716 u_int prev, u_int next, u_int tid)
7720 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7721 if (!SCBID_IS_NULL(prev)) {
7722 ahd_set_scbptr(ahd, prev);
7723 ahd_outw(ahd, SCB_NEXT, next);
7727 * SCBs that have MK_MESSAGE set in them may
7728 * cause the tail pointer to be updated without
7729 * setting the next pointer of the previous tail.
7730 * Only clear the tail if the removed SCB was
7733 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7734 if (SCBID_IS_NULL(next)
7735 && ahd_inw(ahd, tail_offset) == scbid)
7736 ahd_outw(ahd, tail_offset, prev);
7738 ahd_add_scb_to_free_list(ahd, scbid);
7743 * Add the SCB as selected by SCBPTR onto the on chip list of
7744 * free hardware SCBs. This list is empty/unused if we are not
7745 * performing SCB paging.
7748 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7750 /* XXX Need some other mechanism to designate "free". */
7752 * Invalidate the tag so that our abort
7753 * routines don't think it's active.
7754 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7758 /******************************** Error Handling ******************************/
7760 * Abort all SCBs that match the given description (target/channel/lun/tag),
7761 * setting their status to the passed in status if the status has not already
7762 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7763 * is paused before it is called.
7766 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7767 int lun, u_int tag, role_t role, uint32_t status)
7770 struct scb *scbp_next;
7776 ahd_mode_state saved_modes;
7778 /* restore this when we're done */
7779 saved_modes = ahd_save_modes(ahd);
7780 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7782 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7783 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7786 * Clean out the busy target table for any untagged commands.
7790 if (target != CAM_TARGET_WILDCARD) {
7797 if (lun == CAM_LUN_WILDCARD) {
7799 maxlun = AHD_NUM_LUNS_NONPKT;
7800 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7801 minlun = maxlun = 0;
7807 if (role != ROLE_TARGET) {
7808 for (;i < maxtarget; i++) {
7809 for (j = minlun;j < maxlun; j++) {
7813 tcl = BUILD_TCL_RAW(i, 'A', j);
7814 scbid = ahd_find_busy_tcl(ahd, tcl);
7815 scbp = ahd_lookup_scb(ahd, scbid);
7817 || ahd_match_scb(ahd, scbp, target, channel,
7818 lun, tag, role) == 0)
7820 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7826 * Don't abort commands that have already completed,
7827 * but haven't quite made it up to the host yet.
7829 ahd_flush_qoutfifo(ahd);
7832 * Go through the pending CCB list and look for
7833 * commands for this target that are still active.
7834 * These are other tagged commands that were
7835 * disconnected when the reset occurred.
7837 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7838 while (scbp_next != NULL) {
7840 scbp_next = LIST_NEXT(scbp, pending_links);
7841 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7844 ostat = aic_get_transaction_status(scbp);
7845 if (ostat == CAM_REQ_INPROG)
7846 aic_set_transaction_status(scbp, status);
7847 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
7848 aic_freeze_scb(scbp);
7849 if ((scbp->flags & SCB_ACTIVE) == 0)
7850 printf("Inactive SCB on pending list\n");
7851 ahd_done(ahd, scbp);
7855 ahd_restore_modes(ahd, saved_modes);
7856 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7857 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7862 ahd_reset_current_bus(struct ahd_softc *ahd)
7866 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7867 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7868 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7869 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7870 ahd_flush_device_writes(ahd);
7871 aic_delay(AHD_BUSRESET_DELAY);
7872 /* Turn off the bus reset */
7873 ahd_outb(ahd, SCSISEQ0, scsiseq);
7874 ahd_flush_device_writes(ahd);
7875 aic_delay(AHD_BUSRESET_DELAY);
7876 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7879 * Certain chip state is not cleared for
7880 * SCSI bus resets that we initiate, so
7881 * we must reset the chip.
7883 ahd_reset(ahd, /*reinit*/TRUE);
7884 ahd_intr_enable(ahd, /*enable*/TRUE);
7885 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7888 ahd_clear_intstat(ahd);
7892 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7894 struct ahd_devinfo devinfo;
7902 ahd->pending_device = NULL;
7904 ahd_compile_devinfo(&devinfo,
7905 CAM_TARGET_WILDCARD,
7906 CAM_TARGET_WILDCARD,
7908 channel, ROLE_UNKNOWN);
7911 /* Make sure the sequencer is in a safe location. */
7912 ahd_clear_critical_section(ahd);
7914 #ifdef AHD_TARGET_MODE
7915 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7916 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7919 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7922 * Disable selections so no automatic hardware
7923 * functions will modify chip state.
7925 ahd_outb(ahd, SCSISEQ0, 0);
7926 ahd_outb(ahd, SCSISEQ1, 0);
7929 * Safely shut down our DMA engines. Always start with
7930 * the FIFO that is not currently active (if any are
7931 * actively connected).
7933 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7934 if (next_fifo > CURRFIFO_1)
7935 /* If disconneced, arbitrarily start with FIFO1. */
7936 next_fifo = fifo = 0;
7938 next_fifo ^= CURRFIFO_1;
7939 ahd_set_modes(ahd, next_fifo, next_fifo);
7940 ahd_outb(ahd, DFCNTRL,
7941 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7942 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7945 * Set CURRFIFO to the now inactive channel.
7947 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7948 ahd_outb(ahd, DFFSTAT, next_fifo);
7949 } while (next_fifo != fifo);
7952 * Reset the bus if we are initiating this reset
7954 ahd_clear_msg_state(ahd);
7955 ahd_outb(ahd, SIMODE1,
7956 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
7959 ahd_reset_current_bus(ahd);
7961 ahd_clear_intstat(ahd);
7964 * Clean up all the state information for the
7965 * pending transactions on this bus.
7967 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7968 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7969 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7972 * Cleanup anything left in the FIFOs.
7974 ahd_clear_fifo(ahd, 0);
7975 ahd_clear_fifo(ahd, 1);
7978 * Revert to async/narrow transfers until we renegotiate.
7980 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7981 for (target = 0; target <= max_scsiid; target++) {
7982 if (ahd->enabled_targets[target] == NULL)
7984 for (initiator = 0; initiator <= max_scsiid; initiator++) {
7985 struct ahd_devinfo devinfo;
7987 ahd_compile_devinfo(&devinfo, target, initiator,
7990 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7991 AHD_TRANS_CUR, /*paused*/TRUE);
7992 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
7993 /*offset*/0, /*ppr_options*/0,
7994 AHD_TRANS_CUR, /*paused*/TRUE);
7998 #ifdef AHD_TARGET_MODE
7999 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
8002 * Send an immediate notify ccb to all target more peripheral
8003 * drivers affected by this action.
8005 for (target = 0; target <= max_scsiid; target++) {
8006 struct ahd_tmode_tstate* tstate;
8009 tstate = ahd->enabled_targets[target];
8012 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
8013 struct ahd_tmode_lstate* lstate;
8015 lstate = tstate->enabled_luns[lun];
8019 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
8020 EVENT_TYPE_BUS_RESET, /*arg*/0);
8021 ahd_send_lstate_events(ahd, lstate);
8025 /* Notify the XPT that a bus reset occurred */
8026 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
8027 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
8030 * Freeze the SIMQ until our poller can determine that
8031 * the bus reset has really gone away. We set the initial
8032 * timer to 0 to have the check performed as soon as possible
8033 * from the timer context.
8035 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
8036 ahd->flags |= AHD_RESET_POLL_ACTIVE;
8037 aic_freeze_simq(ahd);
8038 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
8043 #define AHD_RESET_POLL_MS 1
8045 ahd_reset_poll(void *arg)
8047 struct ahd_softc *ahd = (struct ahd_softc *)arg;
8052 ahd_update_modes(ahd);
8053 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8054 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
8055 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
8056 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_MS,
8057 ahd_reset_poll, ahd);
8063 /* Reset is now low. Complete chip reinitialization. */
8064 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8065 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8066 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8068 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8069 aic_release_simq(ahd);
8073 /**************************** Statistics Processing ***************************/
8075 ahd_stat_timer(void *arg)
8077 struct ahd_softc *ahd = (struct ahd_softc *)arg;
8081 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8082 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8083 enint_coal |= ENINT_COALESCE;
8084 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8085 enint_coal &= ~ENINT_COALESCE;
8087 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8088 ahd_enable_coalescing(ahd, enint_coal);
8090 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8091 printf("%s: Interrupt coalescing "
8092 "now %sabled. Cmds %d\n",
8094 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8095 ahd->cmdcmplt_total);
8099 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8100 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8101 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8102 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
8103 ahd_stat_timer, ahd);
8107 /****************************** Status Processing *****************************/
8109 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8111 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8112 ahd_handle_scsi_status(ahd, scb);
8114 ahd_calc_residual(ahd, scb);
8120 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8122 struct hardware_scb *hscb;
8126 * The sequencer freezes its select-out queue
8127 * anytime a SCSI status error occurs. We must
8128 * handle the error and increment our qfreeze count
8129 * to allow the sequencer to continue. We don't
8130 * bother clearing critical sections here since all
8131 * operations are on data structures that the sequencer
8132 * is not touching once the queue is frozen.
8136 if (ahd_is_paused(ahd)) {
8143 /* Freeze the queue until the client sees the error. */
8144 ahd_freeze_devq(ahd, scb);
8145 aic_freeze_scb(scb);
8147 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8152 /* Don't want to clobber the original sense code */
8153 if ((scb->flags & SCB_SENSE) != 0) {
8155 * Clear the SCB_SENSE Flag and perform
8156 * a normal command completion.
8158 scb->flags &= ~SCB_SENSE;
8159 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8163 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8164 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8165 switch (hscb->shared_data.istatus.scsi_status) {
8166 case STATUS_PKT_SENSE:
8168 struct scsi_status_iu_header *siu;
8170 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8171 siu = (struct scsi_status_iu_header *)scb->sense_data;
8172 aic_set_scsi_status(scb, siu->status);
8174 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8175 ahd_print_path(ahd, scb);
8176 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8177 SCB_GET_TAG(scb), siu->status);
8178 printf("\tflags = 0x%x, sense len = 0x%x, "
8180 siu->flags, scsi_4btoul(siu->sense_length),
8181 scsi_4btoul(siu->pkt_failures_length));
8184 if ((siu->flags & SIU_RSPVALID) != 0) {
8185 ahd_print_path(ahd, scb);
8186 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8187 printf("Unable to parse pkt_failures\n");
8189 switch (SIU_PKTFAIL_CODE(siu)) {
8191 printf("No packet failure found\n");
8192 AHD_UNCORRECTABLE_ERROR(ahd);
8194 case SIU_PFC_CIU_FIELDS_INVALID:
8195 printf("Invalid Command IU Field\n");
8196 AHD_UNCORRECTABLE_ERROR(ahd);
8198 case SIU_PFC_TMF_NOT_SUPPORTED:
8199 printf("TMF not supportd\n");
8200 AHD_UNCORRECTABLE_ERROR(ahd);
8202 case SIU_PFC_TMF_FAILED:
8203 printf("TMF failed\n");
8204 AHD_UNCORRECTABLE_ERROR(ahd);
8206 case SIU_PFC_INVALID_TYPE_CODE:
8207 printf("Invalid L_Q Type code\n");
8208 AHD_UNCORRECTABLE_ERROR(ahd);
8210 case SIU_PFC_ILLEGAL_REQUEST:
8211 AHD_UNCORRECTABLE_ERROR(ahd);
8212 printf("Illegal request\n");
8217 if (siu->status == SCSI_STATUS_OK)
8218 aic_set_transaction_status(scb,
8221 if ((siu->flags & SIU_SNSVALID) != 0) {
8222 scb->flags |= SCB_PKT_SENSE;
8224 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8225 printf("Sense data available\n");
8231 case SCSI_STATUS_CMD_TERMINATED:
8232 case SCSI_STATUS_CHECK_COND:
8234 struct ahd_devinfo devinfo;
8235 struct ahd_dma_seg *sg;
8236 struct scsi_sense *sc;
8237 struct ahd_initiator_tinfo *targ_info;
8238 struct ahd_tmode_tstate *tstate;
8239 struct ahd_transinfo *tinfo;
8241 if (ahd_debug & AHD_SHOW_SENSE) {
8242 ahd_print_path(ahd, scb);
8243 printf("SCB %d: requests Check Status\n",
8248 if (aic_perform_autosense(scb) == 0)
8251 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8252 SCB_GET_TARGET(ahd, scb),
8254 SCB_GET_CHANNEL(ahd, scb),
8256 targ_info = ahd_fetch_transinfo(ahd,
8261 tinfo = &targ_info->curr;
8263 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8265 * Save off the residual if there is one.
8267 ahd_update_residual(ahd, scb);
8269 if (ahd_debug & AHD_SHOW_SENSE) {
8270 ahd_print_path(ahd, scb);
8271 printf("Sending Sense\n");
8275 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8276 aic_get_sense_bufsize(ahd, scb),
8278 sc->opcode = REQUEST_SENSE;
8280 if (tinfo->protocol_version <= SCSI_REV_2
8281 && SCB_GET_LUN(scb) < 8)
8282 sc->byte2 = SCB_GET_LUN(scb) << 5;
8285 sc->length = aic_get_sense_bufsize(ahd, scb);
8289 * We can't allow the target to disconnect.
8290 * This will be an untagged transaction and
8291 * having the target disconnect will make this
8292 * transaction indestinguishable from outstanding
8293 * tagged transactions.
8298 * This request sense could be because the
8299 * the device lost power or in some other
8300 * way has lost our transfer negotiations.
8301 * Renegotiate if appropriate. Unit attention
8302 * errors will be reported before any data
8305 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) {
8306 ahd_update_neg_request(ahd, &devinfo,
8308 AHD_NEG_IF_NON_ASYNC);
8310 if (tstate->auto_negotiate & devinfo.target_mask) {
8311 hscb->control |= MK_MESSAGE;
8313 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8314 scb->flags |= SCB_AUTO_NEGOTIATE;
8316 hscb->cdb_len = sizeof(*sc);
8317 ahd_setup_data_scb(ahd, scb);
8318 scb->flags |= SCB_SENSE;
8319 ahd_queue_scb(ahd, scb);
8321 * Ensure we have enough time to actually
8322 * retrieve the sense, but only schedule
8323 * the timer if we are not in recovery or
8324 * this is a recovery SCB that is allowed
8325 * to have an active timer.
8327 if (ahd->scb_data.recovery_scbs == 0
8328 || (scb->flags & SCB_RECOVERY_SCB) != 0)
8329 aic_scb_timer_reset(scb, 5 * 1000);
8332 case SCSI_STATUS_OK:
8333 printf("%s: Interrupted for staus of 0???\n",
8343 * Calculate the residual for a just completed SCB.
8346 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8348 struct hardware_scb *hscb;
8349 struct initiator_status *spkt;
8351 uint32_t resid_sgptr;
8357 * SG_STATUS_VALID clear in sgptr.
8358 * 2) Transferless command
8359 * 3) Never performed any transfers.
8360 * sgptr has SG_FULL_RESID set.
8361 * 4) No residual but target did not
8362 * save data pointers after the
8363 * last transfer, so sgptr was
8365 * 5) We have a partial residual.
8366 * Use residual_sgptr to determine
8371 sgptr = aic_le32toh(hscb->sgptr);
8372 if ((sgptr & SG_STATUS_VALID) == 0)
8375 sgptr &= ~SG_STATUS_VALID;
8377 if ((sgptr & SG_LIST_NULL) != 0)
8382 * Residual fields are the same in both
8383 * target and initiator status packets,
8384 * so we can always use the initiator fields
8385 * regardless of the role for this SCB.
8387 spkt = &hscb->shared_data.istatus;
8388 resid_sgptr = aic_le32toh(spkt->residual_sgptr);
8389 if ((sgptr & SG_FULL_RESID) != 0) {
8391 resid = aic_get_transfer_length(scb);
8392 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8395 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8396 ahd_print_path(ahd, scb);
8397 printf("data overrun detected Tag == 0x%x.\n",
8399 ahd_freeze_devq(ahd, scb);
8400 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8401 aic_freeze_scb(scb);
8403 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8404 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8407 struct ahd_dma_seg *sg;
8410 * Remainder of the SG where the transfer
8413 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8414 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8416 /* The residual sg_ptr always points to the next sg */
8420 * Add up the contents of all residual
8421 * SG segments that are after the SG where
8422 * the transfer stopped.
8424 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8426 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
8429 if ((scb->flags & SCB_SENSE) == 0)
8430 aic_set_residual(scb, resid);
8432 aic_set_sense_residual(scb, resid);
8435 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8436 ahd_print_path(ahd, scb);
8437 printf("Handled %sResidual of %d bytes\n",
8438 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8443 /******************************* Target Mode **********************************/
8444 #ifdef AHD_TARGET_MODE
8446 * Add a target mode event to this lun's queue
8449 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8450 u_int initiator_id, u_int event_type, u_int event_arg)
8452 struct ahd_tmode_event *event;
8455 xpt_freeze_devq(lstate->path, /*count*/1);
8456 if (lstate->event_w_idx >= lstate->event_r_idx)
8457 pending = lstate->event_w_idx - lstate->event_r_idx;
8459 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8460 - (lstate->event_r_idx - lstate->event_w_idx);
8462 if (event_type == EVENT_TYPE_BUS_RESET
8463 || event_type == MSG_BUS_DEV_RESET) {
8465 * Any earlier events are irrelevant, so reset our buffer.
8466 * This has the effect of allowing us to deal with reset
8467 * floods (an external device holding down the reset line)
8468 * without losing the event that is really interesting.
8470 lstate->event_r_idx = 0;
8471 lstate->event_w_idx = 0;
8472 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8475 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8476 xpt_print_path(lstate->path);
8477 printf("immediate event %x:%x lost\n",
8478 lstate->event_buffer[lstate->event_r_idx].event_type,
8479 lstate->event_buffer[lstate->event_r_idx].event_arg);
8480 lstate->event_r_idx++;
8481 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8482 lstate->event_r_idx = 0;
8483 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8486 event = &lstate->event_buffer[lstate->event_w_idx];
8487 event->initiator_id = initiator_id;
8488 event->event_type = event_type;
8489 event->event_arg = event_arg;
8490 lstate->event_w_idx++;
8491 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8492 lstate->event_w_idx = 0;
8496 * Send any target mode events queued up waiting
8497 * for immediate notify resources.
8500 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8502 struct ccb_hdr *ccbh;
8503 struct ccb_immediate_notify *inot;
8505 while (lstate->event_r_idx != lstate->event_w_idx
8506 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8507 struct ahd_tmode_event *event;
8509 event = &lstate->event_buffer[lstate->event_r_idx];
8510 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8511 inot = (struct ccb_immediate_notify *)ccbh;
8512 switch (event->event_type) {
8513 case EVENT_TYPE_BUS_RESET:
8514 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8517 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8518 inot->arg = event->event_type;
8519 inot->seq_id = event->event_arg;
8522 inot->initiator_id = event->initiator_id;
8523 xpt_done((union ccb *)inot);
8524 lstate->event_r_idx++;
8525 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8526 lstate->event_r_idx = 0;
8531 /******************** Sequencer Program Patching/Download *********************/
8535 ahd_dumpseq(struct ahd_softc* ahd)
8542 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8543 ahd_outw(ahd, PRGMCNT, 0);
8544 for (i = 0; i < max_prog; i++) {
8545 uint8_t ins_bytes[4];
8547 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8548 printf("0x%08x\n", ins_bytes[0] << 24
8549 | ins_bytes[1] << 16
8557 ahd_loadseq(struct ahd_softc *ahd)
8559 struct cs cs_table[num_critical_sections];
8560 u_int begin_set[num_critical_sections];
8561 u_int end_set[num_critical_sections];
8562 struct patch *cur_patch;
8568 u_int sg_prefetch_cnt;
8569 u_int sg_prefetch_cnt_limit;
8570 u_int sg_prefetch_align;
8572 u_int cacheline_mask;
8573 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8576 printf("%s: Downloading Sequencer Program...",
8579 #if DOWNLOAD_CONST_COUNT != 8
8580 #error "Download Const Mismatch"
8583 * Start out with 0 critical sections
8584 * that apply to this firmware load.
8588 memset(begin_set, 0, sizeof(begin_set));
8589 memset(end_set, 0, sizeof(end_set));
8592 * Setup downloadable constant table.
8594 * The computation for the S/G prefetch variables is
8595 * a bit complicated. We would like to always fetch
8596 * in terms of cachelined sized increments. However,
8597 * if the cacheline is not an even multiple of the
8598 * SG element size or is larger than our SG RAM, using
8599 * just the cache size might leave us with only a portion
8600 * of an SG element at the tail of a prefetch. If the
8601 * cacheline is larger than our S/G prefetch buffer less
8602 * the size of an SG element, we may round down to a cacheline
8603 * that doesn't contain any or all of the S/G of interest
8604 * within the bounds of our S/G ram. Provide variables to
8605 * the sequencer that will allow it to handle these edge
8608 /* Start by aligning to the nearest cacheline. */
8609 sg_prefetch_align = ahd->pci_cachesize;
8610 if (sg_prefetch_align == 0)
8611 sg_prefetch_align = 8;
8612 /* Round down to the nearest power of 2. */
8613 while (powerof2(sg_prefetch_align) == 0)
8614 sg_prefetch_align--;
8616 cacheline_mask = sg_prefetch_align - 1;
8619 * If the cacheline boundary is greater than half our prefetch RAM
8620 * we risk not being able to fetch even a single complete S/G
8621 * segment if we align to that boundary.
8623 if (sg_prefetch_align > CCSGADDR_MAX/2)
8624 sg_prefetch_align = CCSGADDR_MAX/2;
8625 /* Start by fetching a single cacheline. */
8626 sg_prefetch_cnt = sg_prefetch_align;
8628 * Increment the prefetch count by cachelines until
8629 * at least one S/G element will fit.
8631 sg_size = sizeof(struct ahd_dma_seg);
8632 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8633 sg_size = sizeof(struct ahd_dma64_seg);
8634 while (sg_prefetch_cnt < sg_size)
8635 sg_prefetch_cnt += sg_prefetch_align;
8637 * If the cacheline is not an even multiple of
8638 * the S/G size, we may only get a partial S/G when
8639 * we align. Add a cacheline if this is the case.
8641 if ((sg_prefetch_align % sg_size) != 0
8642 && (sg_prefetch_cnt < CCSGADDR_MAX))
8643 sg_prefetch_cnt += sg_prefetch_align;
8645 * Lastly, compute a value that the sequencer can use
8646 * to determine if the remainder of the CCSGRAM buffer
8647 * has a full S/G element in it.
8649 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8650 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8651 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8652 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8653 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8654 download_consts[SG_SIZEOF] = sg_size;
8655 download_consts[PKT_OVERRUN_BUFOFFSET] =
8656 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8657 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8658 download_consts[CACHELINE_MASK] = cacheline_mask;
8659 cur_patch = patches;
8662 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8663 ahd_outw(ahd, PRGMCNT, 0);
8665 for (i = 0; i < sizeof(seqprog)/4; i++) {
8666 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8668 * Don't download this instruction as it
8669 * is in a patch that was removed.
8674 * Move through the CS table until we find a CS
8675 * that might apply to this instruction.
8677 for (; cur_cs < num_critical_sections; cur_cs++) {
8678 if (critical_sections[cur_cs].end <= i) {
8679 if (begin_set[cs_count] == TRUE
8680 && end_set[cs_count] == FALSE) {
8681 cs_table[cs_count].end = downloaded;
8682 end_set[cs_count] = TRUE;
8687 if (critical_sections[cur_cs].begin <= i
8688 && begin_set[cs_count] == FALSE) {
8689 cs_table[cs_count].begin = downloaded;
8690 begin_set[cs_count] = TRUE;
8694 ahd_download_instr(ahd, i, download_consts);
8698 ahd->num_critical_sections = cs_count;
8699 if (cs_count != 0) {
8700 cs_count *= sizeof(struct cs);
8701 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
8702 if (ahd->critical_sections == NULL)
8703 panic("ahd_loadseq: Could not malloc");
8704 memcpy(ahd->critical_sections, cs_table, cs_count);
8706 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8709 printf(" %d instructions downloaded\n", downloaded);
8710 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8711 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8716 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8717 u_int start_instr, u_int *skip_addr)
8719 struct patch *cur_patch;
8720 struct patch *last_patch;
8723 num_patches = sizeof(patches)/sizeof(struct patch);
8724 last_patch = &patches[num_patches];
8725 cur_patch = *start_patch;
8727 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8728 if (cur_patch->patch_func(ahd) == 0) {
8729 /* Start rejecting code */
8730 *skip_addr = start_instr + cur_patch->skip_instr;
8731 cur_patch += cur_patch->skip_patch;
8733 /* Accepted this patch. Advance to the next
8734 * one and wait for our instruction pointer to
8741 *start_patch = cur_patch;
8742 if (start_instr < *skip_addr)
8743 /* Still skipping */
8750 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8752 struct patch *cur_patch;
8758 cur_patch = patches;
8761 for (i = 0; i < address;) {
8762 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8764 if (skip_addr > i) {
8767 end_addr = MIN(address, skip_addr);
8768 address_offset += end_addr - i;
8774 return (address - address_offset);
8778 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8780 union ins_formats instr;
8781 struct ins_format1 *fmt1_ins;
8782 struct ins_format3 *fmt3_ins;
8786 * The firmware is always compiled into a little endian format.
8788 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8790 fmt1_ins = &instr.format1;
8793 /* Pull the opcode */
8794 opcode = instr.format1.opcode;
8805 fmt3_ins = &instr.format3;
8806 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8815 if (fmt1_ins->parity != 0) {
8816 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8818 fmt1_ins->parity = 0;
8824 /* Calculate odd parity for the instruction */
8825 for (i = 0, count = 0; i < 31; i++) {
8829 if ((instr.integer & mask) != 0)
8832 if ((count & 0x01) == 0)
8833 instr.format1.parity = 1;
8835 /* The sequencer is a little endian cpu */
8836 instr.integer = aic_htole32(instr.integer);
8837 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8841 panic("Unknown opcode encountered in seq program");
8847 ahd_probe_stack_size(struct ahd_softc *ahd)
8856 * We avoid using 0 as a pattern to avoid
8857 * confusion if the stack implementation
8858 * "back-fills" with zeros when "poping'
8861 for (i = 1; i <= last_probe+1; i++) {
8862 ahd_outb(ahd, STACK, i & 0xFF);
8863 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8867 for (i = last_probe+1; i > 0; i--) {
8870 stack_entry = ahd_inb(ahd, STACK)
8871 |(ahd_inb(ahd, STACK) << 8);
8872 if (stack_entry != i)
8878 return (last_probe);
8882 ahd_dump_all_cards_state(void)
8884 struct ahd_softc *list_ahd;
8886 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8887 ahd_dump_card_state(list_ahd);
8892 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8893 const char *name, u_int address, u_int value,
8894 u_int *cur_column, u_int wrap_point)
8900 if (cur_column == NULL) {
8902 cur_column = &dummy_column;
8905 if (cur_column != NULL && *cur_column >= wrap_point) {
8909 printed = printf("%s[0x%x]", name, value);
8910 if (table == NULL) {
8911 printed += printf(" ");
8912 *cur_column += printed;
8916 while (printed_mask != 0xFF) {
8919 for (entry = 0; entry < num_entries; entry++) {
8920 if (((value & table[entry].mask)
8921 != table[entry].value)
8922 || ((printed_mask & table[entry].mask)
8923 == table[entry].mask))
8926 printed += printf("%s%s",
8927 printed_mask == 0 ? ":(" : "|",
8929 printed_mask |= table[entry].mask;
8933 if (entry >= num_entries)
8936 if (printed_mask != 0)
8937 printed += printf(") ");
8939 printed += printf(" ");
8940 *cur_column += printed;
8945 ahd_dump_card_state(struct ahd_softc *ahd)
8948 ahd_mode_state saved_modes;
8952 u_int saved_scb_index;
8956 if (ahd_is_paused(ahd)) {
8962 saved_modes = ahd_save_modes(ahd);
8963 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8964 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8965 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8967 ahd_inw(ahd, CURADDR),
8968 ahd_build_mode_state(ahd, ahd->saved_src_mode,
8969 ahd->saved_dst_mode));
8971 printf("Card was paused\n");
8973 if (ahd_check_cmdcmpltqueues(ahd))
8974 printf("Completions are pending\n");
8977 * Mode independent registers.
8980 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
8981 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
8982 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
8983 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
8984 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
8985 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
8986 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
8987 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
8988 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
8989 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
8990 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
8991 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
8992 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
8993 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
8994 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
8995 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
8996 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
8997 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
8998 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
8999 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
9001 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
9002 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
9004 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
9005 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
9006 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
9007 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
9008 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
9009 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
9010 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
9011 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
9012 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
9013 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
9014 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
9015 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
9017 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
9018 "CURRSCB 0x%x NEXTSCB 0x%x\n",
9019 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
9020 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
9021 ahd_inw(ahd, NEXTSCB));
9024 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
9025 CAM_LUN_WILDCARD, SCB_LIST_NULL,
9026 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
9027 saved_scb_index = ahd_get_scbptr(ahd);
9028 printf("Pending list:");
9030 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9031 if (i++ > AHD_SCB_MAX)
9033 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
9034 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
9035 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9036 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
9038 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
9041 printf("\nTotal %d\n", i);
9043 printf("Kernel Free SCB lists: ");
9045 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
9046 struct scb *list_scb;
9048 printf("\n COLIDX[%d]: ", AHD_GET_SCB_COL_IDX(ahd, scb));
9051 printf("%d ", SCB_GET_TAG(list_scb));
9052 list_scb = LIST_NEXT(list_scb, collision_links);
9053 } while (list_scb && i++ < AHD_SCB_MAX);
9056 printf("\n Any Device: ");
9057 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
9058 if (i++ > AHD_SCB_MAX)
9060 printf("%d ", SCB_GET_TAG(scb));
9064 printf("Sequencer Complete DMA-inprog list: ");
9065 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
9067 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9068 ahd_set_scbptr(ahd, scb_index);
9069 printf("%d ", scb_index);
9070 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9074 printf("Sequencer Complete list: ");
9075 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
9077 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9078 ahd_set_scbptr(ahd, scb_index);
9079 printf("%d ", scb_index);
9080 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9084 printf("Sequencer DMA-Up and Complete list: ");
9085 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9087 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9088 ahd_set_scbptr(ahd, scb_index);
9089 printf("%d ", scb_index);
9090 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9093 printf("Sequencer On QFreeze and Complete list: ");
9094 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9096 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9097 ahd_set_scbptr(ahd, scb_index);
9098 printf("%d ", scb_index);
9099 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9102 ahd_set_scbptr(ahd, saved_scb_index);
9103 dffstat = ahd_inb(ahd, DFFSTAT);
9104 for (i = 0; i < 2; i++) {
9106 struct scb *fifo_scb;
9110 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9111 fifo_scbptr = ahd_get_scbptr(ahd);
9112 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9114 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9115 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9117 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9118 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9119 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9120 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9121 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9123 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9124 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9125 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9126 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9131 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9132 ahd_inl(ahd, SHADDR+4),
9133 ahd_inl(ahd, SHADDR),
9134 (ahd_inb(ahd, SHCNT)
9135 | (ahd_inb(ahd, SHCNT + 1) << 8)
9136 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9141 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9142 ahd_inl(ahd, HADDR+4),
9143 ahd_inl(ahd, HADDR),
9145 | (ahd_inb(ahd, HCNT + 1) << 8)
9146 | (ahd_inb(ahd, HCNT + 2) << 16)));
9147 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9149 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9150 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9151 if (fifo_scb != NULL)
9152 ahd_dump_sglist(fifo_scb);
9157 for (i = 0; i < 20; i++)
9158 printf("0x%x ", ahd_inb(ahd, LQIN + i));
9160 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9161 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9162 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9163 ahd_inb(ahd, OPTIONMODE));
9164 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9165 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9166 ahd_inb(ahd, MAXCMDCNT));
9167 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9168 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9169 ahd_inb(ahd, SAVED_LUN));
9170 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9172 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9174 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9176 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9177 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9178 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9179 ahd_inw(ahd, DINDEX));
9180 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9181 ahd_name(ahd), ahd_get_scbptr(ahd),
9182 ahd_inw_scbram(ahd, SCB_NEXT),
9183 ahd_inw_scbram(ahd, SCB_NEXT2));
9184 printf("CDB %x %x %x %x %x %x\n",
9185 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9186 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9187 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9188 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9189 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9190 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
9192 for (i = 0; i < ahd->stack_size; i++) {
9193 ahd->saved_stack[i] =
9194 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9195 printf(" 0x%x", ahd->saved_stack[i]);
9197 for (i = ahd->stack_size-1; i >= 0; i--) {
9198 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9199 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9201 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9202 ahd_platform_dump_card_state(ahd);
9203 ahd_restore_modes(ahd, saved_modes);
9209 ahd_dump_scbs(struct ahd_softc *ahd)
9211 ahd_mode_state saved_modes;
9212 u_int saved_scb_index;
9215 saved_modes = ahd_save_modes(ahd);
9216 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9217 saved_scb_index = ahd_get_scbptr(ahd);
9218 for (i = 0; i < AHD_SCB_MAX; i++) {
9219 ahd_set_scbptr(ahd, i);
9221 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9222 ahd_inb_scbram(ahd, SCB_CONTROL),
9223 ahd_inb_scbram(ahd, SCB_SCSIID),
9224 ahd_inw_scbram(ahd, SCB_NEXT),
9225 ahd_inw_scbram(ahd, SCB_NEXT2),
9226 ahd_inl_scbram(ahd, SCB_SGPTR),
9227 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9230 ahd_set_scbptr(ahd, saved_scb_index);
9231 ahd_restore_modes(ahd, saved_modes);
9234 /*************************** Timeout Handling *********************************/
9236 ahd_timeout(struct scb *scb)
9238 struct ahd_softc *ahd;
9240 ahd = scb->ahd_softc;
9241 if ((scb->flags & SCB_ACTIVE) != 0) {
9242 if ((scb->flags & SCB_TIMEDOUT) == 0) {
9243 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb,
9245 scb->flags |= SCB_TIMEDOUT;
9247 ahd_wakeup_recovery_thread(ahd);
9252 * ahd_recover_commands determines if any of the commands that have currently
9253 * timedout are the root cause for this timeout. Innocent commands are given
9254 * a new timeout while we wait for the command executing on the bus to timeout.
9255 * This routine is invoked from a thread context so we are allowed to sleep.
9256 * Our lock is not held on entry.
9259 ahd_recover_commands(struct ahd_softc *ahd)
9262 struct scb *active_scb;
9265 u_int active_scbptr;
9269 * Pause the controller and manually flush any
9270 * commands that have just completed but that our
9271 * interrupt handler has yet to see.
9273 was_paused = ahd_is_paused(ahd);
9275 printf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd),
9276 was_paused ? "" : "not ");
9277 AHD_CORRECTABLE_ERROR(ahd);
9278 ahd_dump_card_state(ahd);
9280 ahd_pause_and_flushwork(ahd);
9282 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) {
9284 * The timedout commands have already
9285 * completed. This typically means
9286 * that either the timeout value was on
9287 * the hairy edge of what the device
9288 * requires or - more likely - interrupts
9289 * are not happening.
9291 printf("%s: Timedout SCBs already complete. "
9292 "Interrupts may not be functioning.\n", ahd_name(ahd));
9298 * Determine identity of SCB acting on the bus.
9299 * This test only catches non-packetized transactions.
9300 * Due to the fleeting nature of packetized operations,
9301 * we can't easily determine that a packetized operation
9304 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9305 last_phase = ahd_inb(ahd, LASTPHASE);
9306 active_scbptr = ahd_get_scbptr(ahd);
9308 if (last_phase != P_BUSFREE
9309 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)
9310 active_scb = ahd_lookup_scb(ahd, active_scbptr);
9312 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9317 target = SCB_GET_TARGET(ahd, scb);
9318 channel = SCB_GET_CHANNEL(ahd, scb);
9319 lun = SCB_GET_LUN(scb);
9321 ahd_print_path(ahd, scb);
9322 printf("SCB %d - timed out\n", SCB_GET_TAG(scb));
9324 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
9326 * Been down this road before.
9327 * Do a full bus reset.
9329 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
9331 found = ahd_reset_channel(ahd, channel,
9332 /*Initiate Reset*/TRUE);
9333 printf("%s: Issued Channel %c Bus Reset. "
9334 "%d SCBs aborted\n", ahd_name(ahd), channel,
9340 * Remove the command from the timedout list in
9341 * preparation for requeing it.
9343 LIST_REMOVE(scb, timedout_links);
9344 scb->flags &= ~SCB_TIMEDOUT;
9346 if (active_scb != NULL) {
9347 if (active_scb != scb) {
9349 * If the active SCB is not us, assume that
9350 * the active SCB has a longer timeout than
9351 * the timedout SCB, and wait for the active
9352 * SCB to timeout. As a safeguard, only
9353 * allow this deferral to continue if some
9354 * untimed-out command is outstanding.
9356 if (ahd_other_scb_timeout(ahd, scb,
9363 * We're active on the bus, so assert ATN
9364 * and hope that the target responds.
9366 ahd_set_recoveryscb(ahd, active_scb);
9367 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
9368 ahd_outb(ahd, MSG_OUT, HOST_MSG);
9369 ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
9370 ahd_print_path(ahd, active_scb);
9371 printf("BDR message in message buffer\n");
9372 aic_scb_timer_reset(scb, 2 * 1000);
9374 } else if (last_phase != P_BUSFREE
9375 && ahd_inb(ahd, SCSIPHASE) == 0) {
9377 * SCB is not identified, there
9378 * is no pending REQ, and the sequencer
9379 * has not seen a busfree. Looks like
9380 * a stuck connection waiting to
9381 * go busfree. Reset the bus.
9383 printf("%s: Connection stuck awaiting busfree or "
9384 "Identify Msg.\n", ahd_name(ahd));
9386 } else if (ahd_search_qinfifo(ahd, target, channel, lun,
9388 ROLE_INITIATOR, /*status*/0,
9389 SEARCH_COUNT) > 0) {
9391 * We haven't even gone out on the bus
9392 * yet, so the timeout must be due to
9393 * some other command. Reset the timer
9396 if (ahd_other_scb_timeout(ahd, scb, NULL) == 0)
9400 * This SCB is for a disconnected transaction
9401 * and we haven't found a better candidate on
9402 * the bus to explain this timeout.
9404 ahd_set_recoveryscb(ahd, scb);
9407 * Actually re-queue this SCB in an attempt
9408 * to select the device before it reconnects.
9409 * In either case (selection or reselection),
9410 * we will now issue a target reset to the
9413 scb->flags |= SCB_DEVICE_RESET;
9414 scb->hscb->cdb_len = 0;
9415 scb->hscb->task_attribute = 0;
9416 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK;
9418 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9419 if ((scb->flags & SCB_PACKETIZED) != 0) {
9421 * Mark the SCB has having an outstanding
9422 * task management function. Should the command
9423 * complete normally before the task management
9424 * function can be sent, the host will be
9425 * notified to abort our requeued SCB.
9427 ahd_outb(ahd, SCB_TASK_MANAGEMENT,
9428 scb->hscb->task_management);
9431 * If non-packetized, set the MK_MESSAGE control
9432 * bit indicating that we desire to send a
9433 * message. We also set the disconnected flag
9434 * since there is no guarantee that our SCB
9435 * control byte matches the version on the
9436 * card. We don't want the sequencer to abort
9437 * the command thinking an unsolicited
9438 * reselection occurred.
9440 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
9443 * The sequencer will never re-reference the
9444 * in-core SCB. To make sure we are notified
9445 * during reslection, set the MK_MESSAGE flag in
9446 * the card's copy of the SCB.
9448 ahd_outb(ahd, SCB_CONTROL,
9449 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE);
9453 * Clear out any entries in the QINFIFO first
9454 * so we are the next SCB for this target
9457 ahd_search_qinfifo(ahd, target, channel, lun,
9458 SCB_LIST_NULL, ROLE_INITIATOR,
9459 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
9460 ahd_qinfifo_requeue_tail(ahd, scb);
9461 ahd_set_scbptr(ahd, active_scbptr);
9462 ahd_print_path(ahd, scb);
9463 printf("Queuing a BDR SCB\n");
9464 aic_scb_timer_reset(scb, 2 * 1000);
9470 * Any remaining SCBs were not the "culprit", so remove
9471 * them from the timeout list. The timer for these commands
9472 * will be reset once the recovery SCB completes.
9474 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9475 LIST_REMOVE(scb, timedout_links);
9476 scb->flags &= ~SCB_TIMEDOUT;
9483 * Re-schedule a timeout for the passed in SCB if we determine that some
9484 * other SCB is in the process of recovery or an SCB with a longer
9485 * timeout is still pending. Limit our search to just "other_scb"
9486 * if it is non-NULL.
9489 ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb,
9490 struct scb *other_scb)
9495 ahd_print_path(ahd, scb);
9496 printf("Other SCB Timeout%s",
9497 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
9498 ? " again\n" : "\n");
9500 AHD_UNCORRECTABLE_ERROR(ahd);
9501 newtimeout = aic_get_timeout(scb);
9502 scb->flags |= SCB_OTHERTCL_TIMEOUT;
9504 if (other_scb != NULL) {
9505 if ((other_scb->flags
9506 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9507 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9509 newtimeout = MAX(aic_get_timeout(other_scb),
9513 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) {
9514 if ((other_scb->flags
9515 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9516 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9518 newtimeout = MAX(aic_get_timeout(other_scb),
9525 aic_scb_timer_reset(scb, newtimeout);
9527 ahd_print_path(ahd, scb);
9528 printf("No other SCB worth waiting for...\n");
9531 return (found != 0);
9534 /**************************** Flexport Logic **********************************/
9536 * Read count 16bit words from 16bit word address start_addr from the
9537 * SEEPROM attached to the controller, into buf, using the controller's
9538 * SEEPROM reading state machine. Optionally treat the data as a byte
9539 * stream in terms of byte order.
9542 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9543 u_int start_addr, u_int count, int bytestream)
9550 * If we never make it through the loop even once,
9551 * we were passed invalid arguments.
9554 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9555 end_addr = start_addr + count;
9556 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9557 ahd_outb(ahd, SEEADR, cur_addr);
9558 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9560 error = ahd_wait_seeprom(ahd);
9563 if (bytestream != 0) {
9564 uint8_t *bytestream_ptr;
9566 bytestream_ptr = (uint8_t *)buf;
9567 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9568 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9571 * ahd_inw() already handles machine byte order.
9573 *buf = ahd_inw(ahd, SEEDAT);
9581 * Write count 16bit words from buf, into SEEPROM attache to the
9582 * controller starting at 16bit word address start_addr, using the
9583 * controller's SEEPROM writing state machine.
9586 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9587 u_int start_addr, u_int count)
9594 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9597 /* Place the chip into write-enable mode */
9598 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9599 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9600 error = ahd_wait_seeprom(ahd);
9605 * Write the data. If we don't get through the loop at
9606 * least once, the arguments were invalid.
9609 end_addr = start_addr + count;
9610 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9611 ahd_outw(ahd, SEEDAT, *buf++);
9612 ahd_outb(ahd, SEEADR, cur_addr);
9613 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9615 retval = ahd_wait_seeprom(ahd);
9623 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9624 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9625 error = ahd_wait_seeprom(ahd);
9632 * Wait ~100us for the serial eeprom to satisfy our request.
9635 ahd_wait_seeprom(struct ahd_softc *ahd)
9640 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9649 * Validate the two checksums in the per_channel
9650 * vital product data struct.
9653 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9660 vpdarray = (uint8_t *)vpd;
9661 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9663 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9664 checksum = checksum + vpdarray[i];
9666 || (-checksum & 0xFF) != vpd->vpd_checksum)
9670 maxaddr = offsetof(struct vpd_config, checksum);
9671 for (i = offsetof(struct vpd_config, default_target_flags);
9673 checksum = checksum + vpdarray[i];
9675 || (-checksum & 0xFF) != vpd->checksum)
9681 ahd_verify_cksum(struct seeprom_config *sc)
9688 maxaddr = (sizeof(*sc)/2) - 1;
9690 scarray = (uint16_t *)sc;
9692 for (i = 0; i < maxaddr; i++)
9693 checksum = checksum + scarray[i];
9695 || (checksum & 0xFFFF) != sc->checksum) {
9703 ahd_acquire_seeprom(struct ahd_softc *ahd)
9706 * We should be able to determine the SEEPROM type
9707 * from the flexport logic, but unfortunately not
9708 * all implementations have this logic and there is
9709 * no programatic method for determining if the logic
9717 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9719 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9726 ahd_release_seeprom(struct ahd_softc *ahd)
9728 /* Currently a no-op */
9732 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9736 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9738 panic("ahd_write_flexport: address out of range");
9739 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9740 error = ahd_wait_flexport(ahd);
9743 ahd_outb(ahd, BRDDAT, value);
9744 ahd_flush_device_writes(ahd);
9745 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9746 ahd_flush_device_writes(ahd);
9747 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9748 ahd_flush_device_writes(ahd);
9749 ahd_outb(ahd, BRDCTL, 0);
9750 ahd_flush_device_writes(ahd);
9755 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9759 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9761 panic("ahd_read_flexport: address out of range");
9762 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9763 error = ahd_wait_flexport(ahd);
9766 *value = ahd_inb(ahd, BRDDAT);
9767 ahd_outb(ahd, BRDCTL, 0);
9768 ahd_flush_device_writes(ahd);
9773 * Wait at most 2 seconds for flexport arbitration to succeed.
9776 ahd_wait_flexport(struct ahd_softc *ahd)
9780 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9781 cnt = 1000000 * 2 / 5;
9782 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9790 /************************* Target Mode ****************************************/
9791 #ifdef AHD_TARGET_MODE
9793 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9794 struct ahd_tmode_tstate **tstate,
9795 struct ahd_tmode_lstate **lstate,
9796 int notfound_failure)
9799 if ((ahd->features & AHD_TARGETMODE) == 0)
9800 return (CAM_REQ_INVALID);
9803 * Handle the 'black hole' device that sucks up
9804 * requests to unattached luns on enabled targets.
9806 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9807 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9809 *lstate = ahd->black_hole;
9813 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9814 if (ccb->ccb_h.target_id > max_id)
9815 return (CAM_TID_INVALID);
9817 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9818 return (CAM_LUN_INVALID);
9820 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9822 if (*tstate != NULL)
9824 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9827 if (notfound_failure != 0 && *lstate == NULL)
9828 return (CAM_PATH_INVALID);
9830 return (CAM_REQ_CMP);
9834 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9837 struct ahd_tmode_tstate *tstate;
9838 struct ahd_tmode_lstate *lstate;
9839 struct ccb_en_lun *cel;
9847 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9848 /*notfound_failure*/FALSE);
9850 if (status != CAM_REQ_CMP) {
9851 ccb->ccb_h.status = status;
9855 if ((ahd->features & AHD_MULTIROLE) != 0) {
9858 our_id = ahd->our_id;
9859 if (ccb->ccb_h.target_id != our_id
9860 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9861 if ((ahd->features & AHD_MULTI_TID) != 0
9862 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9864 * Only allow additional targets if
9865 * the initiator role is disabled.
9866 * The hardware cannot handle a re-select-in
9867 * on the initiator id during a re-select-out
9868 * on a different target id.
9870 status = CAM_TID_INVALID;
9871 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9872 || ahd->enabled_luns > 0) {
9874 * Only allow our target id to change
9875 * if the initiator role is not configured
9876 * and there are no enabled luns which
9877 * are attached to the currently registered
9880 status = CAM_TID_INVALID;
9885 if (status != CAM_REQ_CMP) {
9886 ccb->ccb_h.status = status;
9891 * We now have an id that is valid.
9892 * If we aren't in target mode, switch modes.
9894 if ((ahd->flags & AHD_TARGETROLE) == 0
9895 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9896 printf("Configuring Target Mode\n");
9897 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9898 ccb->ccb_h.status = CAM_BUSY;
9901 ahd->flags |= AHD_TARGETROLE;
9902 if ((ahd->features & AHD_MULTIROLE) == 0)
9903 ahd->flags &= ~AHD_INITIATORROLE;
9909 target = ccb->ccb_h.target_id;
9910 lun = ccb->ccb_h.target_lun;
9911 channel = SIM_CHANNEL(ahd, sim);
9912 target_mask = 0x01 << target;
9916 if (cel->enable != 0) {
9919 /* Are we already enabled?? */
9920 if (lstate != NULL) {
9921 xpt_print_path(ccb->ccb_h.path);
9922 printf("Lun already enabled\n");
9923 AHD_CORRECTABLE_ERROR(ahd);
9924 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9928 if (cel->grp6_len != 0
9929 || cel->grp7_len != 0) {
9931 * Don't (yet?) support vendor
9932 * specific commands.
9934 ccb->ccb_h.status = CAM_REQ_INVALID;
9935 printf("Non-zero Group Codes\n");
9941 * Setup our data structures.
9943 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9944 tstate = ahd_alloc_tstate(ahd, target, channel);
9945 if (tstate == NULL) {
9946 xpt_print_path(ccb->ccb_h.path);
9947 printf("Couldn't allocate tstate\n");
9948 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9952 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
9953 if (lstate == NULL) {
9954 xpt_print_path(ccb->ccb_h.path);
9955 printf("Couldn't allocate lstate\n");
9956 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9959 memset(lstate, 0, sizeof(*lstate));
9960 status = xpt_create_path(&lstate->path, /*periph*/NULL,
9961 xpt_path_path_id(ccb->ccb_h.path),
9962 xpt_path_target_id(ccb->ccb_h.path),
9963 xpt_path_lun_id(ccb->ccb_h.path));
9964 if (status != CAM_REQ_CMP) {
9965 free(lstate, M_DEVBUF);
9966 xpt_print_path(ccb->ccb_h.path);
9967 printf("Couldn't allocate path\n");
9968 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9971 SLIST_INIT(&lstate->accept_tios);
9972 SLIST_INIT(&lstate->immed_notifies);
9974 if (target != CAM_TARGET_WILDCARD) {
9975 tstate->enabled_luns[lun] = lstate;
9976 ahd->enabled_luns++;
9978 if ((ahd->features & AHD_MULTI_TID) != 0) {
9981 targid_mask = ahd_inw(ahd, TARGID);
9982 targid_mask |= target_mask;
9983 ahd_outw(ahd, TARGID, targid_mask);
9984 ahd_update_scsiid(ahd, targid_mask);
9989 channel = SIM_CHANNEL(ahd, sim);
9990 our_id = SIM_SCSI_ID(ahd, sim);
9993 * This can only happen if selections
9996 if (target != our_id) {
10001 sblkctl = ahd_inb(ahd, SBLKCTL);
10002 cur_channel = (sblkctl & SELBUSB)
10004 if ((ahd->features & AHD_TWIN) == 0)
10006 swap = cur_channel != channel;
10007 ahd->our_id = target;
10010 ahd_outb(ahd, SBLKCTL,
10011 sblkctl ^ SELBUSB);
10013 ahd_outb(ahd, SCSIID, target);
10016 ahd_outb(ahd, SBLKCTL, sblkctl);
10020 ahd->black_hole = lstate;
10021 /* Allow select-in operations */
10022 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
10023 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10024 scsiseq1 |= ENSELI;
10025 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10026 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10027 scsiseq1 |= ENSELI;
10028 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10031 ccb->ccb_h.status = CAM_REQ_CMP;
10032 xpt_print_path(ccb->ccb_h.path);
10033 printf("Lun now enabled for target mode\n");
10038 if (lstate == NULL) {
10039 ccb->ccb_h.status = CAM_LUN_INVALID;
10043 ccb->ccb_h.status = CAM_REQ_CMP;
10044 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
10045 struct ccb_hdr *ccbh;
10047 ccbh = &scb->io_ctx->ccb_h;
10048 if (ccbh->func_code == XPT_CONT_TARGET_IO
10049 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
10050 printf("CTIO pending\n");
10051 ccb->ccb_h.status = CAM_REQ_INVALID;
10056 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
10057 printf("ATIOs pending\n");
10058 ccb->ccb_h.status = CAM_REQ_INVALID;
10061 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
10062 printf("INOTs pending\n");
10063 ccb->ccb_h.status = CAM_REQ_INVALID;
10066 if (ccb->ccb_h.status != CAM_REQ_CMP) {
10070 xpt_print_path(ccb->ccb_h.path);
10071 printf("Target mode disabled\n");
10072 xpt_free_path(lstate->path);
10073 free(lstate, M_DEVBUF);
10076 /* Can we clean up the target too? */
10077 if (target != CAM_TARGET_WILDCARD) {
10078 tstate->enabled_luns[lun] = NULL;
10079 ahd->enabled_luns--;
10080 for (empty = 1, i = 0; i < 8; i++)
10081 if (tstate->enabled_luns[i] != NULL) {
10087 ahd_free_tstate(ahd, target, channel,
10089 if (ahd->features & AHD_MULTI_TID) {
10092 targid_mask = ahd_inw(ahd, TARGID);
10093 targid_mask &= ~target_mask;
10094 ahd_outw(ahd, TARGID, targid_mask);
10095 ahd_update_scsiid(ahd, targid_mask);
10099 ahd->black_hole = NULL;
10102 * We can't allow selections without
10103 * our black hole device.
10107 if (ahd->enabled_luns == 0) {
10108 /* Disallow select-in */
10111 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10112 scsiseq1 &= ~ENSELI;
10113 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10114 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10115 scsiseq1 &= ~ENSELI;
10116 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10118 if ((ahd->features & AHD_MULTIROLE) == 0) {
10119 printf("Configuring Initiator Mode\n");
10120 ahd->flags &= ~AHD_TARGETROLE;
10121 ahd->flags |= AHD_INITIATORROLE;
10126 * Unpaused. The extra unpause
10127 * that follows is harmless.
10137 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
10143 if ((ahd->features & AHD_MULTI_TID) == 0)
10144 panic("ahd_update_scsiid called on non-multitid unit\n");
10147 * Since we will rely on the TARGID mask
10148 * for selection enables, ensure that OID
10149 * in SCSIID is not set to some other ID
10150 * that we don't want to allow selections on.
10152 if ((ahd->features & AHD_ULTRA2) != 0)
10153 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
10155 scsiid = ahd_inb(ahd, SCSIID);
10156 scsiid_mask = 0x1 << (scsiid & OID);
10157 if ((targid_mask & scsiid_mask) == 0) {
10160 /* ffs counts from 1 */
10161 our_id = ffs(targid_mask);
10163 our_id = ahd->our_id;
10169 if ((ahd->features & AHD_ULTRA2) != 0)
10170 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
10172 ahd_outb(ahd, SCSIID, scsiid);
10177 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
10179 struct target_cmd *cmd;
10181 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
10182 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
10184 * Only advance through the queue if we
10185 * have the resources to process the command.
10187 if (ahd_handle_target_cmd(ahd, cmd) != 0)
10190 cmd->cmd_valid = 0;
10191 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
10192 ahd->shared_data_dmamap,
10193 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
10194 sizeof(struct target_cmd),
10195 BUS_DMASYNC_PREREAD);
10196 ahd->tqinfifonext++;
10199 * Lazily update our position in the target mode incoming
10200 * command queue as seen by the sequencer.
10202 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
10205 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
10206 hs_mailbox &= ~HOST_TQINPOS;
10207 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
10208 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
10214 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
10216 struct ahd_tmode_tstate *tstate;
10217 struct ahd_tmode_lstate *lstate;
10218 struct ccb_accept_tio *atio;
10224 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
10225 target = SCSIID_OUR_ID(cmd->scsiid);
10226 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
10229 tstate = ahd->enabled_targets[target];
10231 if (tstate != NULL)
10232 lstate = tstate->enabled_luns[lun];
10235 * Commands for disabled luns go to the black hole driver.
10237 if (lstate == NULL)
10238 lstate = ahd->black_hole;
10240 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
10241 if (atio == NULL) {
10242 ahd->flags |= AHD_TQINFIFO_BLOCKED;
10244 * Wait for more ATIOs from the peripheral driver for this lun.
10248 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
10250 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10251 printf("Incoming command from %d for %d:%d%s\n",
10252 initiator, target, lun,
10253 lstate == ahd->black_hole ? "(Black Holed)" : "");
10255 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
10257 if (lstate == ahd->black_hole) {
10258 /* Fill in the wildcards */
10259 atio->ccb_h.target_id = target;
10260 atio->ccb_h.target_lun = lun;
10264 * Package it up and send it off to
10265 * whomever has this lun enabled.
10267 atio->sense_len = 0;
10268 atio->init_id = initiator;
10269 if (byte[0] != 0xFF) {
10270 /* Tag was included */
10271 atio->tag_action = *byte++;
10272 atio->tag_id = *byte++;
10273 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
10275 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
10279 /* Okay. Now determine the cdb size based on the command code */
10280 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
10286 atio->cdb_len = 10;
10289 atio->cdb_len = 16;
10292 atio->cdb_len = 12;
10296 /* Only copy the opcode. */
10298 printf("Reserved or VU command code type encountered\n");
10302 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
10304 atio->ccb_h.status |= CAM_CDB_RECVD;
10306 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
10308 * We weren't allowed to disconnect.
10309 * We're hanging on the bus until a
10310 * continue target I/O comes in response
10311 * to this accept tio.
10314 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10315 printf("Received Immediate Command %d:%d:%d - %p\n",
10316 initiator, target, lun, ahd->pending_device);
10318 ahd->pending_device = lstate;
10319 ahd_freeze_ccb((union ccb *)atio);
10320 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
10322 xpt_done((union ccb*)atio);