2 * Core routines and tables shareable across OS platforms.
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1994-2002, 2004 Justin T. Gibbs.
7 * Copyright (c) 2000-2003 Adaptec Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
42 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#246 $
46 #include "aic79xx_osm.h"
47 #include "aic79xx_inline.h"
48 #include "aicasm/aicasm_insformat.h"
50 #include <sys/cdefs.h>
51 __FBSDID("$FreeBSD$");
52 #include <dev/aic7xxx/aic79xx_osm.h>
53 #include <dev/aic7xxx/aic79xx_inline.h>
54 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
57 /******************************** Globals *************************************/
58 struct ahd_softc_tailq ahd_tailq = TAILQ_HEAD_INITIALIZER(ahd_tailq);
59 uint32_t ahd_attach_to_HostRAID_controllers = 1;
61 /***************************** Lookup Tables **********************************/
62 char *ahd_chip_names[] =
71 * Hardware error codes.
73 struct ahd_hard_error_entry {
78 static struct ahd_hard_error_entry ahd_hard_errors[] = {
79 { DSCTMOUT, "Discard Timer has timed out" },
80 { ILLOPCODE, "Illegal Opcode in sequencer program" },
81 { SQPARERR, "Sequencer Parity Error" },
82 { DPARERR, "Data-path Parity Error" },
83 { MPARERR, "Scratch or SCB Memory Parity Error" },
84 { CIOPARERR, "CIOBUS Parity Error" },
86 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
88 static struct ahd_phase_table_entry ahd_phase_table[] =
90 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
91 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
92 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
93 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
94 { P_COMMAND, MSG_NOOP, "in Command phase" },
95 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
96 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
97 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
98 { P_BUSFREE, MSG_NOOP, "while idle" },
99 { 0, MSG_NOOP, "in unknown phase" }
103 * In most cases we only wish to itterate over real phases, so
104 * exclude the last element from the count.
106 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
108 /* Our Sequencer Program */
109 #include "aic79xx_seq.h"
111 /**************************** Function Declarations ***************************/
112 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
113 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
115 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
117 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
118 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
119 static void ahd_force_renegotiation(struct ahd_softc *ahd,
120 struct ahd_devinfo *devinfo);
122 static struct ahd_tmode_tstate*
123 ahd_alloc_tstate(struct ahd_softc *ahd,
124 u_int scsi_id, char channel);
125 #ifdef AHD_TARGET_MODE
126 static void ahd_free_tstate(struct ahd_softc *ahd,
127 u_int scsi_id, char channel, int force);
129 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
130 struct ahd_initiator_tinfo *,
134 static void ahd_update_neg_table(struct ahd_softc *ahd,
135 struct ahd_devinfo *devinfo,
136 struct ahd_transinfo *tinfo);
137 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
138 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
139 struct ahd_devinfo *devinfo);
140 static void ahd_scb_devinfo(struct ahd_softc *ahd,
141 struct ahd_devinfo *devinfo,
143 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
144 struct ahd_devinfo *devinfo,
146 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
147 struct ahd_devinfo *devinfo);
148 static void ahd_construct_sdtr(struct ahd_softc *ahd,
149 struct ahd_devinfo *devinfo,
150 u_int period, u_int offset);
151 static void ahd_construct_wdtr(struct ahd_softc *ahd,
152 struct ahd_devinfo *devinfo,
154 static void ahd_construct_ppr(struct ahd_softc *ahd,
155 struct ahd_devinfo *devinfo,
156 u_int period, u_int offset,
157 u_int bus_width, u_int ppr_options);
158 static void ahd_clear_msg_state(struct ahd_softc *ahd);
159 static void ahd_handle_message_phase(struct ahd_softc *ahd);
165 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
166 u_int msgval, int full);
167 static int ahd_parse_msg(struct ahd_softc *ahd,
168 struct ahd_devinfo *devinfo);
169 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
170 struct ahd_devinfo *devinfo);
171 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
172 struct ahd_devinfo *devinfo);
173 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
174 static void ahd_handle_devreset(struct ahd_softc *ahd,
175 struct ahd_devinfo *devinfo,
176 u_int lun, cam_status status,
177 char *message, int verbose_level);
178 #ifdef AHD_TARGET_MODE
179 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
180 struct ahd_devinfo *devinfo,
184 static u_int ahd_sglist_size(struct ahd_softc *ahd);
185 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
186 static bus_dmamap_callback_t
188 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
189 static int ahd_init_scbdata(struct ahd_softc *ahd);
190 static void ahd_fini_scbdata(struct ahd_softc *ahd);
191 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
192 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
193 static void ahd_add_col_list(struct ahd_softc *ahd,
194 struct scb *scb, u_int col_idx);
195 static void ahd_rem_col_list(struct ahd_softc *ahd,
197 static void ahd_chip_init(struct ahd_softc *ahd);
198 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
199 struct scb *prev_scb,
201 static int ahd_qinfifo_count(struct ahd_softc *ahd);
202 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
203 char channel, int lun, u_int tag,
204 role_t role, uint32_t status,
205 ahd_search_action action,
206 u_int *list_head, u_int *list_tail,
208 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
209 u_int tid_prev, u_int tid_cur,
211 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
213 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
214 u_int prev, u_int next, u_int tid);
215 static void ahd_reset_current_bus(struct ahd_softc *ahd);
216 static ahd_callback_t ahd_reset_poll;
217 static ahd_callback_t ahd_stat_timer;
219 static void ahd_dumpseq(struct ahd_softc *ahd);
221 static void ahd_loadseq(struct ahd_softc *ahd);
222 static int ahd_check_patch(struct ahd_softc *ahd,
223 struct patch **start_patch,
224 u_int start_instr, u_int *skip_addr);
225 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
227 static void ahd_download_instr(struct ahd_softc *ahd,
228 u_int instrptr, uint8_t *dconsts);
229 static int ahd_probe_stack_size(struct ahd_softc *ahd);
230 static int ahd_other_scb_timeout(struct ahd_softc *ahd,
232 struct scb *other_scb);
233 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
235 static void ahd_run_data_fifo(struct ahd_softc *ahd,
238 #ifdef AHD_TARGET_MODE
239 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
240 struct ahd_tmode_lstate *lstate,
244 static void ahd_update_scsiid(struct ahd_softc *ahd,
246 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
247 struct target_cmd *cmd);
250 /******************************** Private Inlines *****************************/
251 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
252 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
253 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
256 ahd_assert_atn(struct ahd_softc *ahd)
258 ahd_outb(ahd, SCSISIGO, ATNO);
262 * Determine if the current connection has a packetized
263 * agreement. This does not necessarily mean that we
264 * are currently in a packetized transfer. We could
265 * just as easily be sending or receiving a message.
268 ahd_currently_packetized(struct ahd_softc *ahd)
270 ahd_mode_state saved_modes;
273 saved_modes = ahd_save_modes(ahd);
274 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
276 * The packetized bit refers to the last
277 * connection, not the current one. Check
278 * for non-zero LQISTATE instead.
280 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
281 packetized = ahd_inb(ahd, LQISTATE) != 0;
283 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
284 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
286 ahd_restore_modes(ahd, saved_modes);
291 ahd_set_active_fifo(struct ahd_softc *ahd)
295 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
296 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
297 switch (active_fifo) {
300 ahd_set_modes(ahd, active_fifo, active_fifo);
307 /************************* Sequencer Execution Control ************************/
309 * Restart the sequencer program from address zero
312 ahd_restart(struct ahd_softc *ahd)
317 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
319 /* No more pending messages */
320 ahd_clear_msg_state(ahd);
321 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
322 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
323 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
324 ahd_outb(ahd, SEQINTCTL, 0);
325 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
326 ahd_outb(ahd, SEQ_FLAGS, 0);
327 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
328 ahd_outb(ahd, SAVED_LUN, 0xFF);
331 * Ensure that the sequencer's idea of TQINPOS
332 * matches our own. The sequencer increments TQINPOS
333 * only after it sees a DMA complete and a reset could
334 * occur before the increment leaving the kernel to believe
335 * the command arrived but the sequencer to not.
337 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
339 /* Always allow reselection */
340 ahd_outb(ahd, SCSISEQ1,
341 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
342 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
345 * Clear any pending sequencer interrupt. It is no
346 * longer relevant since we're resetting the Program
349 ahd_outb(ahd, CLRINT, CLRSEQINT);
351 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
356 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
358 ahd_mode_state saved_modes;
361 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
362 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
364 saved_modes = ahd_save_modes(ahd);
365 ahd_set_modes(ahd, fifo, fifo);
366 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
367 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
368 ahd_outb(ahd, CCSGCTL, CCSGRESET);
369 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
370 ahd_outb(ahd, SG_STATE, 0);
371 ahd_restore_modes(ahd, saved_modes);
374 /************************* Input/Output Queues ********************************/
376 * Flush and completed commands that are sitting in the command
377 * complete queues down on the chip but have yet to be dma'ed back up.
380 ahd_flush_qoutfifo(struct ahd_softc *ahd)
383 ahd_mode_state saved_modes;
389 saved_modes = ahd_save_modes(ahd);
392 * Flush the good status FIFO for completed packetized commands.
394 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
395 saved_scbptr = ahd_get_scbptr(ahd);
396 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
400 scbid = ahd_inw(ahd, GSFIFO);
401 scb = ahd_lookup_scb(ahd, scbid);
403 printf("%s: Warning - GSFIFO SCB %d invalid\n",
404 ahd_name(ahd), scbid);
405 AHD_CORRECTABLE_ERROR(ahd);
409 * Determine if this transaction is still active in
410 * any FIFO. If it is, we must flush that FIFO to
411 * the host before completing the command.
415 for (i = 0; i < 2; i++) {
416 /* Toggle to the other mode. */
418 ahd_set_modes(ahd, fifo_mode, fifo_mode);
420 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
423 ahd_run_data_fifo(ahd, scb);
426 * Running this FIFO may cause a CFG4DATA for
427 * this same transaction to assert in the other
428 * FIFO or a new snapshot SAVEPTRS interrupt
429 * in this FIFO. Even running a FIFO may not
430 * clear the transaction if we are still waiting
431 * for data to drain to the host. We must loop
432 * until the transaction is not active in either
433 * FIFO just to be sure. Reset our loop counter
434 * so we will visit both FIFOs again before
435 * declaring this transaction finished. We
436 * also delay a bit so that status has a chance
437 * to change before we look at this FIFO again.
442 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
443 ahd_set_scbptr(ahd, scbid);
444 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
445 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
446 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
447 & SG_LIST_NULL) != 0)) {
451 * The transfer completed with a residual.
452 * Place this SCB on the complete DMA list
453 * so that we update our in-core copy of the
454 * SCB before completing the command.
456 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
457 ahd_outb(ahd, SCB_SGPTR,
458 ahd_inb_scbram(ahd, SCB_SGPTR)
460 ahd_outw(ahd, SCB_TAG, scbid);
461 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
462 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
463 if (SCBID_IS_NULL(comp_head)) {
464 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
465 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
469 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
470 ahd_set_scbptr(ahd, tail);
471 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
472 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
473 ahd_set_scbptr(ahd, scbid);
476 ahd_complete_scb(ahd, scb);
478 ahd_set_scbptr(ahd, saved_scbptr);
481 * Setup for command channel portion of flush.
483 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
486 * Wait for any inprogress DMA to complete and clear DMA state
487 * if this if for an SCB in the qinfifo.
489 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
491 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
492 if ((ccscbctl & ARRDONE) != 0)
494 } else if ((ccscbctl & CCSCBDONE) != 0)
499 * We leave the sequencer to cleanup in the case of DMA's to
500 * update the qoutfifo. In all other cases (DMA's to the
501 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
502 * we disable the DMA engine so that the sequencer will not
503 * attempt to handle the DMA completion.
505 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
506 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
509 * Complete any SCBs that just finished
510 * being DMA'ed into the qoutfifo.
512 ahd_run_qoutfifo(ahd);
514 saved_scbptr = ahd_get_scbptr(ahd);
516 * Manually update/complete any completed SCBs that are waiting to be
517 * DMA'ed back up to the host.
519 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
520 while (!SCBID_IS_NULL(scbid)) {
524 ahd_set_scbptr(ahd, scbid);
525 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
526 scb = ahd_lookup_scb(ahd, scbid);
528 printf("%s: Warning - DMA-up and complete "
529 "SCB %d invalid\n", ahd_name(ahd), scbid);
530 AHD_CORRECTABLE_ERROR(ahd);
533 hscb_ptr = (uint8_t *)scb->hscb;
534 for (i = 0; i < sizeof(struct hardware_scb); i++)
535 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
537 ahd_complete_scb(ahd, scb);
540 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
541 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
543 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
544 while (!SCBID_IS_NULL(scbid)) {
546 ahd_set_scbptr(ahd, scbid);
547 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
548 scb = ahd_lookup_scb(ahd, scbid);
550 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
551 ahd_name(ahd), scbid);
552 AHD_CORRECTABLE_ERROR(ahd);
556 ahd_complete_scb(ahd, scb);
559 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
561 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
562 while (!SCBID_IS_NULL(scbid)) {
564 ahd_set_scbptr(ahd, scbid);
565 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
566 scb = ahd_lookup_scb(ahd, scbid);
568 printf("%s: Warning - Complete SCB %d invalid\n",
569 ahd_name(ahd), scbid);
570 AHD_CORRECTABLE_ERROR(ahd);
574 ahd_complete_scb(ahd, scb);
577 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
582 ahd_set_scbptr(ahd, saved_scbptr);
583 ahd_restore_modes(ahd, saved_modes);
584 ahd->flags |= AHD_UPDATE_PEND_CMDS;
588 * Determine if an SCB for a packetized transaction
589 * is active in a FIFO.
592 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
596 * The FIFO is only active for our transaction if
597 * the SCBPTR matches the SCB's ID and the firmware
598 * has installed a handler for the FIFO or we have
599 * a pending SAVEPTRS or CFG4DATA interrupt.
601 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
602 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
603 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
610 * Run a data fifo to completion for a transaction we know
611 * has completed across the SCSI bus (good status has been
612 * received). We are already set to the correct FIFO mode
613 * on entry to this routine.
615 * This function attempts to operate exactly as the firmware
616 * would when running this FIFO. Care must be taken to update
617 * this routine any time the firmware's FIFO algorithm is
621 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
625 seqintsrc = ahd_inb(ahd, SEQINTSRC);
626 if ((seqintsrc & CFG4DATA) != 0) {
631 * Clear full residual flag.
633 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
634 ahd_outb(ahd, SCB_SGPTR, sgptr);
637 * Load datacnt and address.
639 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
640 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
642 ahd_outb(ahd, SG_STATE, 0);
644 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
645 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
646 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
647 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
648 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
651 * Initialize Residual Fields.
653 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
654 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
657 * Mark the SCB as having a FIFO in use.
659 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
660 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
663 * Install a "fake" handler for this FIFO.
665 ahd_outw(ahd, LONGJMP_ADDR, 0);
668 * Notify the hardware that we have satisfied
669 * this sequencer interrupt.
671 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
672 } else if ((seqintsrc & SAVEPTRS) != 0) {
676 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
678 * Snapshot Save Pointers. All that
679 * is necessary to clear the snapshot
686 * Disable S/G fetch so the DMA engine
687 * is available to future users.
689 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
690 ahd_outb(ahd, CCSGCTL, 0);
691 ahd_outb(ahd, SG_STATE, 0);
694 * Flush the data FIFO. Strickly only
695 * necessary for Rev A parts.
697 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
700 * Calculate residual.
702 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
703 resid = ahd_inl(ahd, SHCNT);
704 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
705 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
706 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
708 * Must back up to the correct S/G element.
709 * Typically this just means resetting our
710 * low byte to the offset in the SG_CACHE,
711 * but if we wrapped, we have to correct
712 * the other bytes of the sgptr too.
714 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
715 && (sgptr & 0x80) == 0)
718 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
720 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
721 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
722 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
723 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
724 sgptr | SG_LIST_NULL);
729 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
730 ahd_outl(ahd, SCB_DATACNT, resid);
731 ahd_outl(ahd, SCB_SGPTR, sgptr);
732 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
733 ahd_outb(ahd, SEQIMODE,
734 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
736 * If the data is to the SCSI bus, we are
737 * done, otherwise wait for FIFOEMP.
739 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
741 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
748 * Disable S/G fetch so the DMA engine
749 * is available to future users. We won't
750 * be using the DMA engine to load segments.
752 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
753 ahd_outb(ahd, CCSGCTL, 0);
754 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
758 * Wait for the DMA engine to notice that the
759 * host transfer is enabled and that there is
760 * space in the S/G FIFO for new segments before
761 * loading more segments.
763 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
764 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
767 * Determine the offset of the next S/G
770 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
771 sgptr &= SG_PTR_MASK;
772 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
773 struct ahd_dma64_seg *sg;
775 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
776 data_addr = sg->addr;
778 sgptr += sizeof(*sg);
780 struct ahd_dma_seg *sg;
782 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
783 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
785 data_addr |= sg->addr;
787 sgptr += sizeof(*sg);
791 * Update residual information.
793 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
794 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
799 if (data_len & AHD_DMA_LAST_SEG) {
801 ahd_outb(ahd, SG_STATE, 0);
803 ahd_outq(ahd, HADDR, data_addr);
804 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
805 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
808 * Advertise the segment to the hardware.
810 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
811 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
813 * Use SCSIENWRDIS so that SCSIEN
814 * is never modified by this
817 dfcntrl |= SCSIENWRDIS;
819 ahd_outb(ahd, DFCNTRL, dfcntrl);
821 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
824 * Transfer completed to the end of SG list
825 * and has flushed to the host.
827 ahd_outb(ahd, SCB_SGPTR,
828 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
830 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
833 * Clear any handler for this FIFO, decrement
834 * the FIFO use count for the SCB, and release
837 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
838 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
839 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
840 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
845 * Look for entries in the QoutFIFO that have completed.
846 * The valid_tag completion field indicates the validity
847 * of the entry - the valid value toggles each time through
848 * the queue. We use the sg_status field in the completion
849 * entry to avoid referencing the hscb if the completion
850 * occurred with no errors and no residual. sg_status is
851 * a copy of the first byte (little endian) of the sgptr
855 ahd_run_qoutfifo(struct ahd_softc *ahd)
857 struct ahd_completion *completion;
861 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
862 panic("ahd_run_qoutfifo recursion");
863 ahd->flags |= AHD_RUNNING_QOUTFIFO;
864 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
866 completion = &ahd->qoutfifo[ahd->qoutfifonext];
868 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
871 scb_index = aic_le16toh(completion->tag);
872 scb = ahd_lookup_scb(ahd, scb_index);
874 printf("%s: WARNING no command for scb %d "
875 "(cmdcmplt)\nQOUTPOS = %d\n",
876 ahd_name(ahd), scb_index,
878 AHD_CORRECTABLE_ERROR(ahd);
879 ahd_dump_card_state(ahd);
880 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
881 ahd_handle_scb_status(ahd, scb);
886 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
887 if (ahd->qoutfifonext == 0)
888 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
890 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
893 /************************* Interrupt Handling *********************************/
895 ahd_handle_hwerrint(struct ahd_softc *ahd)
898 * Some catastrophic hardware error has occurred.
899 * Print it for the user and disable the controller.
904 error = ahd_inb(ahd, ERROR);
905 for (i = 0; i < num_errors; i++) {
906 if ((error & ahd_hard_errors[i].errno) != 0) {
907 printf("%s: hwerrint, %s\n",
908 ahd_name(ahd), ahd_hard_errors[i].errmesg);
909 AHD_UNCORRECTABLE_ERROR(ahd);
913 ahd_dump_card_state(ahd);
916 /* Tell everyone that this HBA is no longer available */
917 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
918 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
921 /* Tell the system that this controller has gone away. */
926 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
931 * Save the sequencer interrupt code and clear the SEQINT
932 * bit. We will unpause the sequencer, if appropriate,
933 * after servicing the request.
935 seqintcode = ahd_inb(ahd, SEQINTCODE);
936 ahd_outb(ahd, CLRINT, CLRSEQINT);
937 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
939 * Unpause the sequencer and let it clear
940 * SEQINT by writing NO_SEQINT to it. This
941 * will cause the sequencer to be paused again,
942 * which is the expected state of this routine.
945 while (!ahd_is_paused(ahd))
947 ahd_outb(ahd, CLRINT, CLRSEQINT);
949 ahd_update_modes(ahd);
951 if ((ahd_debug & AHD_SHOW_MISC) != 0)
952 printf("%s: Handle Seqint Called for code %d\n",
953 ahd_name(ahd), seqintcode);
955 switch (seqintcode) {
956 case ENTERING_NONPACK:
961 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
962 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
963 scbid = ahd_get_scbptr(ahd);
964 scb = ahd_lookup_scb(ahd, scbid);
967 * Somehow need to know if this
968 * is from a selection or reselection.
969 * From that, we can determine target
970 * ID so we at least have an I_T nexus.
973 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
974 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
975 ahd_outb(ahd, SEQ_FLAGS, 0x0);
977 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
978 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
980 * Phase change after read stream with
981 * CRC error with P0 asserted on last
985 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
986 printf("%s: Assuming LQIPHASE_NLQ with "
987 "P0 assertion\n", ahd_name(ahd));
991 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
992 printf("%s: Entering NONPACK\n", ahd_name(ahd));
997 printf("%s: Invalid Sequencer interrupt occurred.\n",
999 ahd_dump_card_state(ahd);
1000 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1001 AHD_UNCORRECTABLE_ERROR(ahd);
1003 case STATUS_OVERRUN:
1008 scbid = ahd_get_scbptr(ahd);
1009 scb = ahd_lookup_scb(ahd, scbid);
1011 ahd_print_path(ahd, scb);
1013 printf("%s: ", ahd_name(ahd));
1014 printf("SCB %d Packetized Status Overrun", scbid);
1015 ahd_dump_card_state(ahd);
1016 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1017 AHD_UNCORRECTABLE_ERROR(ahd);
1020 case CFG4ISTAT_INTR:
1025 scbid = ahd_get_scbptr(ahd);
1026 scb = ahd_lookup_scb(ahd, scbid);
1028 ahd_dump_card_state(ahd);
1029 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1030 AHD_FATAL_ERROR(ahd);
1031 panic("For safety");
1033 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1034 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1035 ahd_outb(ahd, HCNT + 2, 0);
1036 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1037 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1044 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1045 printf("%s: ILLEGAL_PHASE 0x%x\n",
1046 ahd_name(ahd), bus_phase);
1048 switch (bus_phase) {
1056 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1057 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1058 AHD_UNCORRECTABLE_ERROR(ahd);
1062 struct ahd_devinfo devinfo;
1064 struct ahd_tmode_tstate *tstate;
1068 * If a target takes us into the command phase
1069 * assume that it has been externally reset and
1070 * has thus lost our previous packetized negotiation
1071 * agreement. Since we have not sent an identify
1072 * message and may not have fully qualified the
1073 * connection, we change our command to TUR, assert
1074 * ATN and ABORT the task when we go to message in
1075 * phase. The OSM will see the REQUEUE_REQUEST
1076 * status and retry the command.
1078 scbid = ahd_get_scbptr(ahd);
1079 scb = ahd_lookup_scb(ahd, scbid);
1081 AHD_CORRECTABLE_ERROR(ahd);
1082 printf("Invalid phase with no valid SCB. "
1083 "Resetting bus.\n");
1084 ahd_reset_channel(ahd, 'A',
1085 /*Initiate Reset*/TRUE);
1088 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1089 SCB_GET_TARGET(ahd, scb),
1091 SCB_GET_CHANNEL(ahd, scb),
1093 ahd_fetch_transinfo(ahd,
1098 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1099 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1100 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1101 /*offset*/0, /*ppr_options*/0,
1102 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1103 ahd_outb(ahd, SCB_CDB_STORE, 0);
1104 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1105 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1106 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1107 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1108 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1109 ahd_outb(ahd, SCB_CDB_LEN, 6);
1110 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1111 scb->hscb->control |= MK_MESSAGE;
1112 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1113 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1114 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1116 * The lun is 0, regardless of the SCB's lun
1117 * as we have not sent an identify message.
1119 ahd_outb(ahd, SAVED_LUN, 0);
1120 ahd_outb(ahd, SEQ_FLAGS, 0);
1121 ahd_assert_atn(ahd);
1122 scb->flags &= ~SCB_PACKETIZED;
1123 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1124 ahd_freeze_devq(ahd, scb);
1125 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
1126 aic_freeze_scb(scb);
1129 * Allow the sequencer to continue with
1130 * non-pack processing.
1132 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1133 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1134 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1135 ahd_outb(ahd, CLRLQOINT1, 0);
1138 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1139 ahd_print_path(ahd, scb);
1140 AHD_CORRECTABLE_ERROR(ahd);
1141 printf("Unexpected command phase from "
1142 "packetized target\n");
1156 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1157 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1158 ahd_inb(ahd, MODE_PTR));
1161 scb_index = ahd_get_scbptr(ahd);
1162 scb = ahd_lookup_scb(ahd, scb_index);
1165 * Attempt to transfer to an SCB that is
1168 ahd_assert_atn(ahd);
1169 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1170 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1171 ahd->msgout_len = 1;
1172 ahd->msgout_index = 0;
1173 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1175 * Clear status received flag to prevent any
1176 * attempt to complete this bogus SCB.
1178 ahd_outb(ahd, SCB_CONTROL,
1179 ahd_inb_scbram(ahd, SCB_CONTROL)
1184 case DUMP_CARD_STATE:
1186 ahd_dump_card_state(ahd);
1192 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1193 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1194 "SG_CACHE_SHADOW = 0x%x\n",
1195 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1196 ahd_inb(ahd, SG_CACHE_SHADOW));
1199 ahd_reinitialize_dataptrs(ahd);
1204 struct ahd_devinfo devinfo;
1207 * The sequencer has encountered a message phase
1208 * that requires host assistance for completion.
1209 * While handling the message phase(s), we will be
1210 * notified by the sequencer after each byte is
1211 * transferred so we can track bus phase changes.
1213 * If this is the first time we've seen a HOST_MSG_LOOP
1214 * interrupt, initialize the state of the host message
1217 ahd_fetch_devinfo(ahd, &devinfo);
1218 if (ahd->msg_type == MSG_TYPE_NONE) {
1223 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1224 if (bus_phase != P_MESGIN
1225 && bus_phase != P_MESGOUT) {
1226 printf("ahd_intr: HOST_MSG_LOOP bad "
1227 "phase 0x%x\n", bus_phase);
1228 AHD_CORRECTABLE_ERROR(ahd);
1230 * Probably transitioned to bus free before
1231 * we got here. Just punt the message.
1233 ahd_dump_card_state(ahd);
1234 ahd_clear_intstat(ahd);
1239 scb_index = ahd_get_scbptr(ahd);
1240 scb = ahd_lookup_scb(ahd, scb_index);
1241 if (devinfo.role == ROLE_INITIATOR) {
1242 if (bus_phase == P_MESGOUT)
1243 ahd_setup_initiator_msgout(ahd,
1248 MSG_TYPE_INITIATOR_MSGIN;
1249 ahd->msgin_index = 0;
1252 #ifdef AHD_TARGET_MODE
1254 if (bus_phase == P_MESGOUT) {
1256 MSG_TYPE_TARGET_MSGOUT;
1257 ahd->msgin_index = 0;
1260 ahd_setup_target_msgin(ahd,
1267 ahd_handle_message_phase(ahd);
1272 /* Ensure we don't leave the selection hardware on */
1273 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1274 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1276 printf("%s:%c:%d: no active SCB for reconnecting "
1277 "target - issuing BUS DEVICE RESET\n",
1278 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1279 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1280 "REG0 == 0x%x ACCUM = 0x%x\n",
1281 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1282 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1283 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1285 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1286 ahd_find_busy_tcl(ahd,
1287 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1288 ahd_inb(ahd, SAVED_LUN))),
1289 ahd_inw(ahd, SINDEX));
1290 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1291 "SCB_CONTROL == 0x%x\n",
1292 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1293 ahd_inb_scbram(ahd, SCB_LUN),
1294 ahd_inb_scbram(ahd, SCB_CONTROL));
1295 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1296 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1297 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1298 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1299 ahd_dump_card_state(ahd);
1300 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1301 ahd->msgout_len = 1;
1302 ahd->msgout_index = 0;
1303 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1304 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1305 ahd_assert_atn(ahd);
1308 case PROTO_VIOLATION:
1310 ahd_handle_proto_violation(ahd);
1315 struct ahd_devinfo devinfo;
1317 ahd_fetch_devinfo(ahd, &devinfo);
1318 ahd_handle_ign_wide_residue(ahd, &devinfo);
1325 lastphase = ahd_inb(ahd, LASTPHASE);
1326 printf("%s:%c:%d: unknown scsi bus phase %x, "
1327 "lastphase = 0x%x. Attempting to continue\n",
1329 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1330 lastphase, ahd_inb(ahd, SCSISIGI));
1331 AHD_CORRECTABLE_ERROR(ahd);
1334 case MISSED_BUSFREE:
1338 lastphase = ahd_inb(ahd, LASTPHASE);
1339 printf("%s:%c:%d: Missed busfree. "
1340 "Lastphase = 0x%x, Curphase = 0x%x\n",
1342 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1343 lastphase, ahd_inb(ahd, SCSISIGI));
1344 AHD_CORRECTABLE_ERROR(ahd);
1351 * When the sequencer detects an overrun, it
1352 * places the controller in "BITBUCKET" mode
1353 * and allows the target to complete its transfer.
1354 * Unfortunately, none of the counters get updated
1355 * when the controller is in this mode, so we have
1356 * no way of knowing how large the overrun was.
1364 scbindex = ahd_get_scbptr(ahd);
1365 scb = ahd_lookup_scb(ahd, scbindex);
1367 lastphase = ahd_inb(ahd, LASTPHASE);
1368 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1369 ahd_print_path(ahd, scb);
1370 printf("data overrun detected %s. Tag == 0x%x.\n",
1371 ahd_lookup_phase_entry(lastphase)->phasemsg,
1373 ahd_print_path(ahd, scb);
1374 printf("%s seen Data Phase. Length = %ld. "
1376 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1377 ? "Have" : "Haven't",
1378 aic_get_transfer_length(scb), scb->sg_count);
1379 ahd_dump_sglist(scb);
1384 * Set this and it will take effect when the
1385 * target does a command complete.
1387 ahd_freeze_devq(ahd, scb);
1388 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1389 aic_freeze_scb(scb);
1394 struct ahd_devinfo devinfo;
1398 ahd_fetch_devinfo(ahd, &devinfo);
1399 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1400 ahd_name(ahd), devinfo.channel, devinfo.target,
1402 scbid = ahd_get_scbptr(ahd);
1403 scb = ahd_lookup_scb(ahd, scbid);
1404 AHD_CORRECTABLE_ERROR(ahd);
1406 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1408 * Ensure that we didn't put a second instance of this
1409 * SCB into the QINFIFO.
1411 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1412 SCB_GET_CHANNEL(ahd, scb),
1413 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1414 ROLE_INITIATOR, /*status*/0,
1416 ahd_outb(ahd, SCB_CONTROL,
1417 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1420 case TASKMGMT_FUNC_COMPLETE:
1425 scbid = ahd_get_scbptr(ahd);
1426 scb = ahd_lookup_scb(ahd, scbid);
1432 ahd_print_path(ahd, scb);
1433 printf("Task Management Func 0x%x Complete\n",
1434 scb->hscb->task_management);
1435 lun = CAM_LUN_WILDCARD;
1436 tag = SCB_LIST_NULL;
1438 switch (scb->hscb->task_management) {
1439 case SIU_TASKMGMT_ABORT_TASK:
1440 tag = SCB_GET_TAG(scb);
1441 case SIU_TASKMGMT_ABORT_TASK_SET:
1442 case SIU_TASKMGMT_CLEAR_TASK_SET:
1443 lun = scb->hscb->lun;
1444 error = CAM_REQ_ABORTED;
1445 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1446 'A', lun, tag, ROLE_INITIATOR,
1449 case SIU_TASKMGMT_LUN_RESET:
1450 lun = scb->hscb->lun;
1451 case SIU_TASKMGMT_TARGET_RESET:
1453 struct ahd_devinfo devinfo;
1455 ahd_scb_devinfo(ahd, &devinfo, scb);
1456 error = CAM_BDR_SENT;
1457 ahd_handle_devreset(ahd, &devinfo, lun,
1459 lun != CAM_LUN_WILDCARD
1462 /*verbose_level*/0);
1466 panic("Unexpected TaskMgmt Func\n");
1472 case TASKMGMT_CMD_CMPLT_OKAY:
1478 * An ABORT TASK TMF failed to be delivered before
1479 * the targeted command completed normally.
1481 scbid = ahd_get_scbptr(ahd);
1482 scb = ahd_lookup_scb(ahd, scbid);
1485 * Remove the second instance of this SCB from
1486 * the QINFIFO if it is still there.
1488 ahd_print_path(ahd, scb);
1489 printf("SCB completes before TMF\n");
1491 * Handle losing the race. Wait until any
1492 * current selection completes. We will then
1493 * set the TMF back to zero in this SCB so that
1494 * the sequencer doesn't bother to issue another
1495 * sequencer interrupt for its completion.
1497 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1498 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1499 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1501 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1502 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1503 SCB_GET_CHANNEL(ahd, scb),
1504 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1505 ROLE_INITIATOR, /*status*/0,
1514 printf("%s: Tracepoint %d\n", ahd_name(ahd),
1515 seqintcode - TRACEPOINT0);
1520 ahd_handle_hwerrint(ahd);
1523 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1528 * The sequencer is paused immediately on
1529 * a SEQINT, so we should restart it when
1536 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1547 ahd_update_modes(ahd);
1548 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1550 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1551 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1552 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1553 lqistat1 = ahd_inb(ahd, LQISTAT1);
1554 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1555 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1556 if ((status0 & (SELDI|SELDO)) != 0) {
1559 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1560 simode0 = ahd_inb(ahd, SIMODE0);
1561 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1562 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1564 scbid = ahd_get_scbptr(ahd);
1565 scb = ahd_lookup_scb(ahd, scbid);
1567 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1570 if ((status0 & IOERR) != 0) {
1573 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1574 printf("%s: Transceiver State Has Changed to %s mode\n",
1575 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1576 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1578 * A change in I/O mode is equivalent to a bus reset.
1580 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1582 ahd_setup_iocell_workaround(ahd);
1584 } else if ((status0 & OVERRUN) != 0) {
1586 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1588 AHD_CORRECTABLE_ERROR(ahd);
1589 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1590 } else if ((status & SCSIRSTI) != 0) {
1592 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1593 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1594 AHD_UNCORRECTABLE_ERROR(ahd);
1595 } else if ((status & SCSIPERR) != 0) {
1597 /* Make sure the sequencer is in a safe location. */
1598 ahd_clear_critical_section(ahd);
1600 ahd_handle_transmission_error(ahd);
1601 } else if (lqostat0 != 0) {
1603 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1604 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1605 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1606 ahd_outb(ahd, CLRLQOINT1, 0);
1607 } else if ((status & SELTO) != 0) {
1610 /* Stop the selection */
1611 ahd_outb(ahd, SCSISEQ0, 0);
1613 /* Make sure the sequencer is in a safe location. */
1614 ahd_clear_critical_section(ahd);
1616 /* No more pending messages */
1617 ahd_clear_msg_state(ahd);
1619 /* Clear interrupt state */
1620 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1623 * Although the driver does not care about the
1624 * 'Selection in Progress' status bit, the busy
1625 * LED does. SELINGO is only cleared by a successful
1626 * selection, so we must manually clear it to insure
1627 * the LED turns off just incase no future successful
1628 * selections occur (e.g. no devices on the bus).
1630 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1632 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1633 scb = ahd_lookup_scb(ahd, scbid);
1635 printf("%s: ahd_intr - referenced scb not "
1636 "valid during SELTO scb(0x%x)\n",
1637 ahd_name(ahd), scbid);
1638 ahd_dump_card_state(ahd);
1639 AHD_UNCORRECTABLE_ERROR(ahd);
1641 struct ahd_devinfo devinfo;
1643 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1644 ahd_print_path(ahd, scb);
1645 printf("Saw Selection Timeout for SCB 0x%x\n",
1649 ahd_scb_devinfo(ahd, &devinfo, scb);
1650 aic_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1651 ahd_freeze_devq(ahd, scb);
1654 * Cancel any pending transactions on the device
1655 * now that it seems to be missing. This will
1656 * also revert us to async/narrow transfers until
1657 * we can renegotiate with the device.
1659 ahd_handle_devreset(ahd, &devinfo,
1662 "Selection Timeout",
1663 /*verbose_level*/1);
1665 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1666 ahd_iocell_first_selection(ahd);
1668 } else if ((status0 & (SELDI|SELDO)) != 0) {
1670 ahd_iocell_first_selection(ahd);
1672 } else if (status3 != 0) {
1673 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1674 ahd_name(ahd), status3);
1675 AHD_CORRECTABLE_ERROR(ahd);
1676 ahd_outb(ahd, CLRSINT3, status3);
1677 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1679 /* Make sure the sequencer is in a safe location. */
1680 ahd_clear_critical_section(ahd);
1682 ahd_handle_lqiphase_error(ahd, lqistat1);
1683 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1685 * This status can be delayed during some
1686 * streaming operations. The SCSIPHASE
1687 * handler has already dealt with this case
1688 * so just clear the error.
1690 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1691 } else if ((status & BUSFREE) != 0
1692 || (lqistat1 & LQOBUSFREE) != 0) {
1700 * Clear our selection hardware as soon as possible.
1701 * We may have an entry in the waiting Q for this target,
1702 * that is affected by this busfree and we don't want to
1703 * go about selecting the target while we handle the event.
1705 ahd_outb(ahd, SCSISEQ0, 0);
1707 /* Make sure the sequencer is in a safe location. */
1708 ahd_clear_critical_section(ahd);
1711 * Determine what we were up to at the time of
1714 mode = AHD_MODE_SCSI;
1715 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1716 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1717 switch (busfreetime) {
1724 mode = busfreetime == BUSFREE_DFF0
1725 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1726 ahd_set_modes(ahd, mode, mode);
1727 scbid = ahd_get_scbptr(ahd);
1728 scb = ahd_lookup_scb(ahd, scbid);
1730 printf("%s: Invalid SCB %d in DFF%d "
1731 "during unexpected busfree\n",
1732 ahd_name(ahd), scbid, mode);
1734 AHD_CORRECTABLE_ERROR(ahd);
1736 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1746 packetized = (lqostat1 & LQOBUSFREE) != 0;
1748 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1749 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1750 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1751 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1753 * Assume packetized if we are not
1754 * on the bus in a non-packetized
1755 * capacity and any pending selection
1756 * was a packetized selection.
1763 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1764 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1768 * Busfrees that occur in non-packetized phases are
1769 * handled by the nonpkt_busfree handler.
1771 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1772 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1775 restart = ahd_handle_nonpkt_busfree(ahd);
1778 * Clear the busfree interrupt status. The setting of
1779 * the interrupt is a pulse, so in a perfect world, we
1780 * would not need to muck with the ENBUSFREE logic. This
1781 * would ensure that if the bus moves on to another
1782 * connection, busfree protection is still in force. If
1783 * BUSFREEREV is broken, however, we must manually clear
1784 * the ENBUSFREE if the busfree occurred during a non-pack
1785 * connection so that we don't get false positives during
1786 * future, packetized, connections.
1788 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1790 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1791 ahd_outb(ahd, SIMODE1,
1792 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1795 ahd_clear_fifo(ahd, mode);
1797 ahd_clear_msg_state(ahd);
1798 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1805 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1806 ahd_name(ahd), status);
1807 ahd_dump_card_state(ahd);
1808 ahd_clear_intstat(ahd);
1814 ahd_handle_transmission_error(struct ahd_softc *ahd)
1827 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1828 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1829 ahd_inb(ahd, LQISTAT2);
1830 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1831 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1834 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1835 lqistate = ahd_inb(ahd, LQISTATE);
1836 if ((lqistate >= 0x1E && lqistate <= 0x24)
1837 || (lqistate == 0x29)) {
1839 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1840 printf("%s: NLQCRC found via LQISTATE\n",
1844 lqistat1 |= LQICRCI_NLQ;
1846 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1849 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1850 lastphase = ahd_inb(ahd, LASTPHASE);
1851 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1852 perrdiag = ahd_inb(ahd, PERRDIAG);
1853 msg_out = MSG_INITIATOR_DET_ERR;
1854 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1857 * Try to find the SCB associated with this error.
1861 || (lqistat1 & LQICRCI_NLQ) != 0) {
1862 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1863 ahd_set_active_fifo(ahd);
1864 scbid = ahd_get_scbptr(ahd);
1865 scb = ahd_lookup_scb(ahd, scbid);
1866 if (scb != NULL && SCB_IS_SILENT(scb))
1871 if (silent == FALSE) {
1872 printf("%s: Transmission error detected\n", ahd_name(ahd));
1873 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1874 ahd_lastphase_print(lastphase, &cur_col, 50);
1875 ahd_scsisigi_print(curphase, &cur_col, 50);
1876 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1878 AHD_CORRECTABLE_ERROR(ahd);
1879 ahd_dump_card_state(ahd);
1882 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1883 if (silent == FALSE) {
1884 printf("%s: Gross protocol error during incoming "
1885 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1886 ahd_name(ahd), lqistat1);
1887 AHD_UNCORRECTABLE_ERROR(ahd);
1889 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1891 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1893 * A CRC error has been detected on an incoming LQ.
1894 * The bus is currently hung on the last ACK.
1895 * Hit LQIRETRY to release the last ack, and
1896 * wait for the sequencer to determine that ATNO
1897 * is asserted while in message out to take us
1898 * to our host message loop. No NONPACKREQ or
1899 * LQIPHASE type errors will occur in this
1900 * scenario. After this first LQIRETRY, the LQI
1901 * manager will be in ISELO where it will
1902 * happily sit until another packet phase begins.
1903 * Unexpected bus free detection is enabled
1904 * through any phases that occur after we release
1905 * this last ack until the LQI manager sees a
1906 * packet phase. This implies we may have to
1907 * ignore a perfectly valid "unexected busfree"
1908 * after our "initiator detected error" message is
1909 * sent. A busfree is the expected response after
1910 * we tell the target that it's L_Q was corrupted.
1911 * (SPI4R09 10.7.3.3.3)
1913 ahd_outb(ahd, LQCTL2, LQIRETRY);
1914 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1915 AHD_CORRECTABLE_ERROR(ahd);
1916 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1918 * We detected a CRC error in a NON-LQ packet.
1919 * The hardware has varying behavior in this situation
1920 * depending on whether this packet was part of a
1924 * The hardware has already acked the complete packet.
1925 * If the target honors our outstanding ATN condition,
1926 * we should be (or soon will be) in MSGOUT phase.
1927 * This will trigger the LQIPHASE_LQ status bit as the
1928 * hardware was expecting another LQ. Unexpected
1929 * busfree detection is enabled. Once LQIPHASE_LQ is
1930 * true (first entry into host message loop is much
1931 * the same), we must clear LQIPHASE_LQ and hit
1932 * LQIRETRY so the hardware is ready to handle
1933 * a future LQ. NONPACKREQ will not be asserted again
1934 * once we hit LQIRETRY until another packet is
1935 * processed. The target may either go busfree
1936 * or start another packet in response to our message.
1938 * Read Streaming P0 asserted:
1939 * If we raise ATN and the target completes the entire
1940 * stream (P0 asserted during the last packet), the
1941 * hardware will ack all data and return to the ISTART
1942 * state. When the target reponds to our ATN condition,
1943 * LQIPHASE_LQ will be asserted. We should respond to
1944 * this with an LQIRETRY to prepare for any future
1945 * packets. NONPACKREQ will not be asserted again
1946 * once we hit LQIRETRY until another packet is
1947 * processed. The target may either go busfree or
1948 * start another packet in response to our message.
1949 * Busfree detection is enabled.
1951 * Read Streaming P0 not asserted:
1952 * If we raise ATN and the target transitions to
1953 * MSGOUT in or after a packet where P0 is not
1954 * asserted, the hardware will assert LQIPHASE_NLQ.
1955 * We should respond to the LQIPHASE_NLQ with an
1956 * LQIRETRY. Should the target stay in a non-pkt
1957 * phase after we send our message, the hardware
1958 * will assert LQIPHASE_LQ. Recovery is then just as
1959 * listed above for the read streaming with P0 asserted.
1960 * Busfree detection is enabled.
1962 if (silent == FALSE)
1963 printf("LQICRC_NLQ\n");
1965 printf("%s: No SCB valid for LQICRC_NLQ. "
1966 "Resetting bus\n", ahd_name(ahd));
1967 AHD_UNCORRECTABLE_ERROR(ahd);
1968 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1971 } else if ((lqistat1 & LQIBADLQI) != 0) {
1972 printf("Need to handle BADLQI!\n");
1973 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1975 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1976 if ((curphase & ~P_DATAIN_DT) != 0) {
1977 /* Ack the byte. So we can continue. */
1978 if (silent == FALSE)
1979 printf("Acking %s to clear perror\n",
1980 ahd_lookup_phase_entry(curphase)->phasemsg);
1981 ahd_inb(ahd, SCSIDAT);
1984 if (curphase == P_MESGIN)
1985 msg_out = MSG_PARITY_ERROR;
1989 * We've set the hardware to assert ATN if we
1990 * get a parity error on "in" phases, so all we
1991 * need to do is stuff the message buffer with
1992 * the appropriate message. "In" phases have set
1993 * mesg_out to something other than MSG_NOP.
1995 ahd->send_msg_perror = msg_out;
1996 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1997 scb->flags |= SCB_TRANSMISSION_ERROR;
1998 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1999 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2004 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
2007 * Clear the sources of the interrupts.
2009 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2010 ahd_outb(ahd, CLRLQIINT1, lqistat1);
2013 * If the "illegal" phase changes were in response
2014 * to our ATN to flag a CRC error, AND we ended up
2015 * on packet boundaries, clear the error, restart the
2016 * LQI manager as appropriate, and go on our merry
2017 * way toward sending the message. Otherwise, reset
2018 * the bus to clear the error.
2020 ahd_set_active_fifo(ahd);
2021 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
2022 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
2023 if ((lqistat1 & LQIPHASE_LQ) != 0) {
2024 printf("LQIRETRY for LQIPHASE_LQ\n");
2025 AHD_CORRECTABLE_ERROR(ahd);
2026 ahd_outb(ahd, LQCTL2, LQIRETRY);
2027 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
2028 printf("LQIRETRY for LQIPHASE_NLQ\n");
2029 AHD_CORRECTABLE_ERROR(ahd);
2030 ahd_outb(ahd, LQCTL2, LQIRETRY);
2032 panic("ahd_handle_lqiphase_error: No phase errors\n");
2033 ahd_dump_card_state(ahd);
2034 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2037 printf("Reseting Channel for LQI Phase error\n");
2038 AHD_CORRECTABLE_ERROR(ahd);
2039 ahd_dump_card_state(ahd);
2040 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2045 * Packetized unexpected or expected busfree.
2046 * Entered in mode based on busfreetime.
2049 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2053 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2054 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2055 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2056 if ((lqostat1 & LQOBUSFREE) != 0) {
2065 * The LQO manager detected an unexpected busfree
2068 * 1) During an outgoing LQ.
2069 * 2) After an outgoing LQ but before the first
2070 * REQ of the command packet.
2071 * 3) During an outgoing command packet.
2073 * In all cases, CURRSCB is pointing to the
2074 * SCB that encountered the failure. Clean
2075 * up the queue, clear SELDO and LQOBUSFREE,
2076 * and allow the sequencer to restart the select
2077 * out at its lesure.
2079 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2080 scbid = ahd_inw(ahd, CURRSCB);
2081 scb = ahd_lookup_scb(ahd, scbid);
2083 panic("SCB not valid during LQOBUSFREE");
2087 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2088 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2089 ahd_outb(ahd, CLRLQOINT1, 0);
2090 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2091 ahd_flush_device_writes(ahd);
2092 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2095 * Return the LQO manager to its idle loop. It will
2096 * not do this automatically if the busfree occurs
2097 * after the first REQ of either the LQ or command
2098 * packet or between the LQ and command packet.
2100 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2103 * Update the waiting for selection queue so
2104 * we restart on the correct SCB.
2106 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2107 saved_scbptr = ahd_get_scbptr(ahd);
2108 if (waiting_h != scbid) {
2110 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2111 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2112 if (waiting_t == waiting_h) {
2113 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2114 next = SCB_LIST_NULL;
2116 ahd_set_scbptr(ahd, waiting_h);
2117 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2119 ahd_set_scbptr(ahd, scbid);
2120 ahd_outw(ahd, SCB_NEXT2, next);
2122 ahd_set_scbptr(ahd, saved_scbptr);
2123 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2124 if (SCB_IS_SILENT(scb) == FALSE) {
2125 ahd_print_path(ahd, scb);
2126 printf("Probable outgoing LQ CRC error. "
2127 "Retrying command\n");
2128 AHD_CORRECTABLE_ERROR(ahd);
2130 scb->crc_retry_count++;
2132 aic_set_transaction_status(scb, CAM_UNCOR_PARITY);
2133 aic_freeze_scb(scb);
2134 ahd_freeze_devq(ahd, scb);
2136 /* Return unpausing the sequencer. */
2138 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2140 * Ignore what are really parity errors that
2141 * occur on the last REQ of a free running
2142 * clock prior to going busfree. Some drives
2143 * do not properly active negate just before
2144 * going busfree resulting in a parity glitch.
2146 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2148 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2149 printf("%s: Parity on last REQ detected "
2150 "during busfree phase.\n",
2153 /* Return unpausing the sequencer. */
2156 if (ahd->src_mode != AHD_MODE_SCSI) {
2160 scbid = ahd_get_scbptr(ahd);
2161 scb = ahd_lookup_scb(ahd, scbid);
2162 ahd_print_path(ahd, scb);
2163 printf("Unexpected PKT busfree condition\n");
2164 AHD_UNCORRECTABLE_ERROR(ahd);
2165 ahd_dump_card_state(ahd);
2166 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2167 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2168 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2170 /* Return restarting the sequencer. */
2173 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2174 AHD_UNCORRECTABLE_ERROR(ahd);
2175 ahd_dump_card_state(ahd);
2176 /* Restart the sequencer. */
2181 * Non-packetized unexpected or expected busfree.
2184 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2186 struct ahd_devinfo devinfo;
2192 u_int initiator_role_id;
2198 * Look at what phase we were last in. If its message out,
2199 * chances are pretty good that the busfree was in response
2200 * to one of our abort requests.
2202 lastphase = ahd_inb(ahd, LASTPHASE);
2203 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2204 saved_lun = ahd_inb(ahd, SAVED_LUN);
2205 target = SCSIID_TARGET(ahd, saved_scsiid);
2206 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2207 ahd_compile_devinfo(&devinfo, initiator_role_id,
2208 target, saved_lun, 'A', ROLE_INITIATOR);
2211 scbid = ahd_get_scbptr(ahd);
2212 scb = ahd_lookup_scb(ahd, scbid);
2214 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2217 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2218 if (lastphase == P_MESGOUT) {
2221 tag = SCB_LIST_NULL;
2222 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2223 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2228 ahd_print_devinfo(ahd, &devinfo);
2229 printf("Abort for unidentified "
2230 "connection completed.\n");
2231 /* restart the sequencer. */
2234 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2235 ahd_print_path(ahd, scb);
2236 printf("SCB %d - Abort%s Completed.\n",
2238 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2240 if (sent_msg == MSG_ABORT_TAG)
2241 tag = SCB_GET_TAG(scb);
2243 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2245 * This abort is in response to an
2246 * unexpected switch to command phase
2247 * for a packetized connection. Since
2248 * the identify message was never sent,
2249 * "saved lun" is 0. We really want to
2250 * abort only the SCB that encountered
2251 * this error, which could have a different
2252 * lun. The SCB will be retried so the OS
2253 * will see the UA after renegotiating to
2256 tag = SCB_GET_TAG(scb);
2257 saved_lun = scb->hscb->lun;
2259 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2260 tag, ROLE_INITIATOR,
2262 printf("found == 0x%x\n", found);
2264 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2265 MSG_BUS_DEV_RESET, TRUE)) {
2268 * Don't mark the user's request for this BDR
2269 * as completing with CAM_BDR_SENT. CAM3
2270 * specifies CAM_REQ_CMP.
2273 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2274 && ahd_match_scb(ahd, scb, target, 'A',
2275 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2277 aic_set_transaction_status(scb, CAM_REQ_CMP);
2279 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2280 CAM_BDR_SENT, "Bus Device Reset",
2281 /*verbose_level*/0);
2283 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2284 && ppr_busfree == 0) {
2285 struct ahd_initiator_tinfo *tinfo;
2286 struct ahd_tmode_tstate *tstate;
2291 * If the previous negotiation was packetized,
2292 * this could be because the device has been
2293 * reset without our knowledge. Force our
2294 * current negotiation to async and retry the
2295 * negotiation. Otherwise retry the command
2296 * with non-ppr negotiation.
2299 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2300 printf("PPR negotiation rejected busfree.\n");
2302 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2304 devinfo.target, &tstate);
2305 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2306 ahd_set_width(ahd, &devinfo,
2307 MSG_EXT_WDTR_BUS_8_BIT,
2310 ahd_set_syncrate(ahd, &devinfo,
2311 /*period*/0, /*offset*/0,
2316 * The expect PPR busfree handler below
2317 * will effect the retry and necessary
2321 tinfo->curr.transport_version = 2;
2322 tinfo->goal.transport_version = 2;
2323 tinfo->goal.ppr_options = 0;
2325 * Remove any SCBs in the waiting for selection
2326 * queue that may also be for this target so
2327 * that command ordering is preserved.
2329 ahd_freeze_devq(ahd, scb);
2330 ahd_qinfifo_requeue_tail(ahd, scb);
2333 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2334 && ppr_busfree == 0) {
2336 * Negotiation Rejected. Go-narrow and
2340 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2341 printf("WDTR negotiation rejected busfree.\n");
2343 ahd_set_width(ahd, &devinfo,
2344 MSG_EXT_WDTR_BUS_8_BIT,
2345 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2348 * Remove any SCBs in the waiting for selection
2349 * queue that may also be for this target so that
2350 * command ordering is preserved.
2352 ahd_freeze_devq(ahd, scb);
2353 ahd_qinfifo_requeue_tail(ahd, scb);
2355 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2356 && ppr_busfree == 0) {
2358 * Negotiation Rejected. Go-async and
2362 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2363 printf("SDTR negotiation rejected busfree.\n");
2365 ahd_set_syncrate(ahd, &devinfo,
2366 /*period*/0, /*offset*/0,
2368 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2371 * Remove any SCBs in the waiting for selection
2372 * queue that may also be for this target so that
2373 * command ordering is preserved.
2375 ahd_freeze_devq(ahd, scb);
2376 ahd_qinfifo_requeue_tail(ahd, scb);
2378 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2379 && ahd_sent_msg(ahd, AHDMSG_1B,
2380 MSG_INITIATOR_DET_ERR, TRUE)) {
2383 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2384 printf("Expected IDE Busfree\n");
2387 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2388 && ahd_sent_msg(ahd, AHDMSG_1B,
2389 MSG_MESSAGE_REJECT, TRUE)) {
2392 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2393 printf("Expected QAS Reject Busfree\n");
2400 * The busfree required flag is honored at the end of
2401 * the message phases. We check it last in case we
2402 * had to send some other message that caused a busfree.
2405 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2406 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2408 ahd_freeze_devq(ahd, scb);
2409 aic_set_transaction_status(scb, CAM_REQUEUE_REQ);
2410 aic_freeze_scb(scb);
2411 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2412 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2413 SCB_GET_CHANNEL(ahd, scb),
2414 SCB_GET_LUN(scb), SCB_LIST_NULL,
2415 ROLE_INITIATOR, CAM_REQ_ABORTED);
2418 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2419 printf("PPR Negotiation Busfree.\n");
2425 if (printerror != 0) {
2432 if ((scb->hscb->control & TAG_ENB) != 0)
2433 tag = SCB_GET_TAG(scb);
2435 tag = SCB_LIST_NULL;
2436 ahd_print_path(ahd, scb);
2437 aborted = ahd_abort_scbs(ahd, target, 'A',
2438 SCB_GET_LUN(scb), tag,
2443 * We had not fully identified this connection,
2444 * so we cannot abort anything.
2446 printf("%s: ", ahd_name(ahd));
2448 printf("Unexpected busfree %s, %d SCBs aborted, "
2449 "PRGMCNT == 0x%x\n",
2450 ahd_lookup_phase_entry(lastphase)->phasemsg,
2452 ahd_inw(ahd, PRGMCNT));
2453 AHD_UNCORRECTABLE_ERROR(ahd);
2454 ahd_dump_card_state(ahd);
2455 if (lastphase != P_BUSFREE)
2456 ahd_force_renegotiation(ahd, &devinfo);
2458 /* Always restart the sequencer. */
2463 ahd_handle_proto_violation(struct ahd_softc *ahd)
2465 struct ahd_devinfo devinfo;
2473 ahd_fetch_devinfo(ahd, &devinfo);
2474 scbid = ahd_get_scbptr(ahd);
2475 scb = ahd_lookup_scb(ahd, scbid);
2476 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2477 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2478 lastphase = ahd_inb(ahd, LASTPHASE);
2479 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2482 * The reconnecting target either did not send an
2483 * identify message, or did, but we didn't find an SCB
2486 ahd_print_devinfo(ahd, &devinfo);
2487 printf("Target did not send an IDENTIFY message. "
2488 "LASTPHASE = 0x%x.\n", lastphase);
2489 AHD_UNCORRECTABLE_ERROR(ahd);
2491 } else if (scb == NULL) {
2493 * We don't seem to have an SCB active for this
2494 * transaction. Print an error and reset the bus.
2496 ahd_print_devinfo(ahd, &devinfo);
2497 printf("No SCB found during protocol violation\n");
2498 AHD_UNCORRECTABLE_ERROR(ahd);
2499 goto proto_violation_reset;
2501 aic_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2502 if ((seq_flags & NO_CDB_SENT) != 0) {
2503 ahd_print_path(ahd, scb);
2504 printf("No or incomplete CDB sent to device.\n");
2505 AHD_UNCORRECTABLE_ERROR(ahd);
2506 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2507 & STATUS_RCVD) == 0) {
2509 * The target never bothered to provide status to
2510 * us prior to completing the command. Since we don't
2511 * know the disposition of this command, we must attempt
2512 * to abort it. Assert ATN and prepare to send an abort
2515 ahd_print_path(ahd, scb);
2516 printf("Completed command without status.\n");
2518 ahd_print_path(ahd, scb);
2519 printf("Unknown protocol violation.\n");
2520 AHD_UNCORRECTABLE_ERROR(ahd);
2521 ahd_dump_card_state(ahd);
2524 if ((lastphase & ~P_DATAIN_DT) == 0
2525 || lastphase == P_COMMAND) {
2526 proto_violation_reset:
2528 * Target either went directly to data
2529 * phase or didn't respond to our ATN.
2530 * The only safe thing to do is to blow
2531 * it away with a bus reset.
2533 found = ahd_reset_channel(ahd, 'A', TRUE);
2534 printf("%s: Issued Channel %c Bus Reset. "
2535 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2536 AHD_UNCORRECTABLE_ERROR(ahd);
2539 * Leave the selection hardware off in case
2540 * this abort attempt will affect yet to
2543 ahd_outb(ahd, SCSISEQ0,
2544 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2545 ahd_assert_atn(ahd);
2546 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2548 ahd_print_devinfo(ahd, &devinfo);
2549 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2550 ahd->msgout_len = 1;
2551 ahd->msgout_index = 0;
2552 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2554 ahd_print_path(ahd, scb);
2555 scb->flags |= SCB_ABORT;
2557 printf("Protocol violation %s. Attempting to abort.\n",
2558 ahd_lookup_phase_entry(curphase)->phasemsg);
2559 AHD_UNCORRECTABLE_ERROR(ahd);
2564 * Force renegotiation to occur the next time we initiate
2565 * a command to the current device.
2568 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2570 struct ahd_initiator_tinfo *targ_info;
2571 struct ahd_tmode_tstate *tstate;
2574 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2575 ahd_print_devinfo(ahd, devinfo);
2576 printf("Forcing renegotiation\n");
2579 targ_info = ahd_fetch_transinfo(ahd,
2581 devinfo->our_scsiid,
2584 ahd_update_neg_request(ahd, devinfo, tstate,
2585 targ_info, AHD_NEG_IF_NON_ASYNC);
2588 #define AHD_MAX_STEPS 2000
2590 ahd_clear_critical_section(struct ahd_softc *ahd)
2592 ahd_mode_state saved_modes;
2604 if (ahd->num_critical_sections == 0)
2617 saved_modes = ahd_save_modes(ahd);
2623 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2624 seqaddr = ahd_inw(ahd, CURADDR);
2626 cs = ahd->critical_sections;
2627 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2629 if (cs->begin < seqaddr && cs->end >= seqaddr)
2633 if (i == ahd->num_critical_sections)
2636 if (steps > AHD_MAX_STEPS) {
2637 printf("%s: Infinite loop in critical section\n"
2638 "%s: First Instruction 0x%x now 0x%x\n",
2639 ahd_name(ahd), ahd_name(ahd), first_instr,
2641 AHD_FATAL_ERROR(ahd);
2642 ahd_dump_card_state(ahd);
2643 panic("critical section loop");
2648 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2649 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2652 if (stepping == FALSE) {
2654 first_instr = seqaddr;
2655 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2656 simode0 = ahd_inb(ahd, SIMODE0);
2657 simode3 = ahd_inb(ahd, SIMODE3);
2658 lqimode0 = ahd_inb(ahd, LQIMODE0);
2659 lqimode1 = ahd_inb(ahd, LQIMODE1);
2660 lqomode0 = ahd_inb(ahd, LQOMODE0);
2661 lqomode1 = ahd_inb(ahd, LQOMODE1);
2662 ahd_outb(ahd, SIMODE0, 0);
2663 ahd_outb(ahd, SIMODE3, 0);
2664 ahd_outb(ahd, LQIMODE0, 0);
2665 ahd_outb(ahd, LQIMODE1, 0);
2666 ahd_outb(ahd, LQOMODE0, 0);
2667 ahd_outb(ahd, LQOMODE1, 0);
2668 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2669 simode1 = ahd_inb(ahd, SIMODE1);
2671 * We don't clear ENBUSFREE. Unfortunately
2672 * we cannot re-enable busfree detection within
2673 * the current connection, so we must leave it
2674 * on while single stepping.
2676 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2677 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2680 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2681 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2682 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2683 ahd_outb(ahd, HCNTRL, ahd->unpause);
2684 while (!ahd_is_paused(ahd))
2686 ahd_update_modes(ahd);
2689 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2690 ahd_outb(ahd, SIMODE0, simode0);
2691 ahd_outb(ahd, SIMODE3, simode3);
2692 ahd_outb(ahd, LQIMODE0, lqimode0);
2693 ahd_outb(ahd, LQIMODE1, lqimode1);
2694 ahd_outb(ahd, LQOMODE0, lqomode0);
2695 ahd_outb(ahd, LQOMODE1, lqomode1);
2696 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2697 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2698 ahd_outb(ahd, SIMODE1, simode1);
2700 * SCSIINT seems to glitch occasionally when
2701 * the interrupt masks are restored. Clear SCSIINT
2702 * one more time so that only persistent errors
2703 * are seen as a real interrupt.
2705 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2707 ahd_restore_modes(ahd, saved_modes);
2711 * Clear any pending interrupt status.
2714 ahd_clear_intstat(struct ahd_softc *ahd)
2716 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2717 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2718 /* Clear any interrupt conditions this may have caused */
2719 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2720 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2721 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2722 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2723 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2724 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2725 |CLRLQOATNPKT|CLRLQOTCRC);
2726 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2727 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2728 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2729 ahd_outb(ahd, CLRLQOINT0, 0);
2730 ahd_outb(ahd, CLRLQOINT1, 0);
2732 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2733 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2734 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2735 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2736 |CLRIOERR|CLROVERRUN);
2737 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2740 /**************************** Debugging Routines ******************************/
2742 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2745 ahd_print_scb(struct scb *scb)
2747 struct hardware_scb *hscb;
2751 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2757 printf("Shared Data: ");
2758 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2759 printf("%#02x", hscb->shared_data.idata.cdb[i]);
2760 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2761 (uint32_t)((aic_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2762 (uint32_t)(aic_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2763 aic_le32toh(hscb->datacnt),
2764 aic_le32toh(hscb->sgptr),
2766 ahd_dump_sglist(scb);
2770 ahd_dump_sglist(struct scb *scb)
2774 if (scb->sg_count > 0) {
2775 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2776 struct ahd_dma64_seg *sg_list;
2778 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2779 for (i = 0; i < scb->sg_count; i++) {
2782 addr = aic_le64toh(sg_list[i].addr);
2783 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2785 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2786 (uint32_t)(addr & 0xFFFFFFFF),
2787 sg_list[i].len & AHD_SG_LEN_MASK,
2788 (sg_list[i].len & AHD_DMA_LAST_SEG)
2792 struct ahd_dma_seg *sg_list;
2794 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2795 for (i = 0; i < scb->sg_count; i++) {
2798 len = aic_le32toh(sg_list[i].len);
2799 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2801 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2802 aic_le32toh(sg_list[i].addr),
2803 len & AHD_SG_LEN_MASK,
2804 len & AHD_DMA_LAST_SEG ? " Last" : "");
2810 /************************* Transfer Negotiation *******************************/
2812 * Allocate per target mode instance (ID we respond to as a target)
2813 * transfer negotiation data structures.
2815 static struct ahd_tmode_tstate *
2816 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2818 struct ahd_tmode_tstate *master_tstate;
2819 struct ahd_tmode_tstate *tstate;
2822 master_tstate = ahd->enabled_targets[ahd->our_id];
2823 if (ahd->enabled_targets[scsi_id] != NULL
2824 && ahd->enabled_targets[scsi_id] != master_tstate)
2825 panic("%s: ahd_alloc_tstate - Target already allocated",
2827 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
2832 * If we have allocated a master tstate, copy user settings from
2833 * the master tstate (taken from SRAM or the EEPROM) for this
2834 * channel, but reset our current and goal settings to async/narrow
2835 * until an initiator talks to us.
2837 if (master_tstate != NULL) {
2838 memcpy(tstate, master_tstate, sizeof(*tstate));
2839 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2840 for (i = 0; i < 16; i++) {
2841 memset(&tstate->transinfo[i].curr, 0,
2842 sizeof(tstate->transinfo[i].curr));
2843 memset(&tstate->transinfo[i].goal, 0,
2844 sizeof(tstate->transinfo[i].goal));
2847 memset(tstate, 0, sizeof(*tstate));
2848 ahd->enabled_targets[scsi_id] = tstate;
2852 #ifdef AHD_TARGET_MODE
2854 * Free per target mode instance (ID we respond to as a target)
2855 * transfer negotiation data structures.
2858 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2860 struct ahd_tmode_tstate *tstate;
2863 * Don't clean up our "master" tstate.
2864 * It has our default user settings.
2866 if (scsi_id == ahd->our_id
2870 tstate = ahd->enabled_targets[scsi_id];
2872 free(tstate, M_DEVBUF);
2873 ahd->enabled_targets[scsi_id] = NULL;
2878 * Called when we have an active connection to a target on the bus,
2879 * this function finds the nearest period to the input period limited
2880 * by the capabilities of the bus connectivity of and sync settings for
2884 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2885 struct ahd_initiator_tinfo *tinfo,
2886 u_int *period, u_int *ppr_options, role_t role)
2888 struct ahd_transinfo *transinfo;
2891 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2892 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2893 maxsync = AHD_SYNCRATE_PACED;
2895 maxsync = AHD_SYNCRATE_ULTRA;
2896 /* Can't do DT related options on an SE bus */
2897 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2900 * Never allow a value higher than our current goal
2901 * period otherwise we may allow a target initiated
2902 * negotiation to go above the limit as set by the
2903 * user. In the case of an initiator initiated
2904 * sync negotiation, we limit based on the user
2905 * setting. This allows the system to still accept
2906 * incoming negotiations even if target initiated
2907 * negotiation is not performed.
2909 if (role == ROLE_TARGET)
2910 transinfo = &tinfo->user;
2912 transinfo = &tinfo->goal;
2913 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2914 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2915 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2916 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2918 if (transinfo->period == 0) {
2922 *period = MAX(*period, transinfo->period);
2923 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2928 * Look up the valid period to SCSIRATE conversion in our table.
2929 * Return the period and offset that should be sent to the target
2930 * if this was the beginning of an SDTR.
2933 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2934 u_int *ppr_options, u_int maxsync)
2936 if (*period < maxsync)
2939 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2940 && *period > AHD_SYNCRATE_MIN_DT)
2941 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2943 if (*period > AHD_SYNCRATE_MIN)
2946 /* Honor PPR option conformance rules. */
2947 if (*period > AHD_SYNCRATE_PACED)
2948 *ppr_options &= ~MSG_EXT_PPR_RTI;
2950 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2951 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2953 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2954 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2956 /* Skip all PACED only entries if IU is not available */
2957 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2958 && *period < AHD_SYNCRATE_DT)
2959 *period = AHD_SYNCRATE_DT;
2961 /* Skip all DT only entries if DT is not available */
2962 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2963 && *period < AHD_SYNCRATE_ULTRA2)
2964 *period = AHD_SYNCRATE_ULTRA2;
2968 * Truncate the given synchronous offset to a value the
2969 * current adapter type and syncrate are capable of.
2972 ahd_validate_offset(struct ahd_softc *ahd,
2973 struct ahd_initiator_tinfo *tinfo,
2974 u_int period, u_int *offset, int wide,
2979 /* Limit offset to what we can do */
2982 else if (period <= AHD_SYNCRATE_PACED) {
2983 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2984 maxoffset = MAX_OFFSET_PACED_BUG;
2986 maxoffset = MAX_OFFSET_PACED;
2988 maxoffset = MAX_OFFSET_NON_PACED;
2989 *offset = MIN(*offset, maxoffset);
2990 if (tinfo != NULL) {
2991 if (role == ROLE_TARGET)
2992 *offset = MIN(*offset, tinfo->user.offset);
2994 *offset = MIN(*offset, tinfo->goal.offset);
2999 * Truncate the given transfer width parameter to a value the
3000 * current adapter type is capable of.
3003 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
3004 u_int *bus_width, role_t role)
3006 switch (*bus_width) {
3008 if (ahd->features & AHD_WIDE) {
3010 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3014 case MSG_EXT_WDTR_BUS_8_BIT:
3015 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
3018 if (tinfo != NULL) {
3019 if (role == ROLE_TARGET)
3020 *bus_width = MIN(tinfo->user.width, *bus_width);
3022 *bus_width = MIN(tinfo->goal.width, *bus_width);
3027 * Update the bitmask of targets for which the controller should
3028 * negotiate with at the next convenient opportunity. This currently
3029 * means the next time we send the initial identify messages for
3030 * a new transaction.
3033 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3034 struct ahd_tmode_tstate *tstate,
3035 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
3037 u_int auto_negotiate_orig;
3039 auto_negotiate_orig = tstate->auto_negotiate;
3040 if (neg_type == AHD_NEG_ALWAYS) {
3042 * Force our "current" settings to be
3043 * unknown so that unless a bus reset
3044 * occurs the need to renegotiate is
3045 * recorded persistently.
3047 if ((ahd->features & AHD_WIDE) != 0)
3048 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3049 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3050 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3052 if (tinfo->curr.period != tinfo->goal.period
3053 || tinfo->curr.width != tinfo->goal.width
3054 || tinfo->curr.offset != tinfo->goal.offset
3055 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3056 || (neg_type == AHD_NEG_IF_NON_ASYNC
3057 && (tinfo->goal.offset != 0
3058 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3059 || tinfo->goal.ppr_options != 0)))
3060 tstate->auto_negotiate |= devinfo->target_mask;
3062 tstate->auto_negotiate &= ~devinfo->target_mask;
3064 return (auto_negotiate_orig != tstate->auto_negotiate);
3068 * Update the user/goal/curr tables of synchronous negotiation
3069 * parameters as well as, in the case of a current or active update,
3070 * any data structures on the host controller. In the case of an
3071 * active update, the specified target is currently talking to us on
3072 * the bus, so the transfer parameter update must take effect
3076 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3077 u_int period, u_int offset, u_int ppr_options,
3078 u_int type, int paused)
3080 struct ahd_initiator_tinfo *tinfo;
3081 struct ahd_tmode_tstate *tstate;
3088 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3091 if (period == 0 || offset == 0) {
3096 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3097 devinfo->target, &tstate);
3099 if ((type & AHD_TRANS_USER) != 0) {
3100 tinfo->user.period = period;
3101 tinfo->user.offset = offset;
3102 tinfo->user.ppr_options = ppr_options;
3105 if ((type & AHD_TRANS_GOAL) != 0) {
3106 tinfo->goal.period = period;
3107 tinfo->goal.offset = offset;
3108 tinfo->goal.ppr_options = ppr_options;
3111 old_period = tinfo->curr.period;
3112 old_offset = tinfo->curr.offset;
3113 old_ppr = tinfo->curr.ppr_options;
3115 if ((type & AHD_TRANS_CUR) != 0
3116 && (old_period != period
3117 || old_offset != offset
3118 || old_ppr != ppr_options)) {
3122 tinfo->curr.period = period;
3123 tinfo->curr.offset = offset;
3124 tinfo->curr.ppr_options = ppr_options;
3126 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3127 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3132 printf("%s: target %d synchronous with "
3133 "period = 0x%x, offset = 0x%x",
3134 ahd_name(ahd), devinfo->target,
3137 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3141 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3142 printf("%s", options ? "|DT" : "(DT");
3145 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3146 printf("%s", options ? "|IU" : "(IU");
3149 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3150 printf("%s", options ? "|RTI" : "(RTI");
3153 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3154 printf("%s", options ? "|QAS" : "(QAS");
3162 printf("%s: target %d using "
3163 "asynchronous transfers%s\n",
3164 ahd_name(ahd), devinfo->target,
3165 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3171 * Always refresh the neg-table to handle the case of the
3172 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3173 * We will always renegotiate in that case if this is a
3174 * packetized request. Also manage the busfree expected flag
3175 * from this common routine so that we catch changes due to
3176 * WDTR or SDTR messages.
3178 if ((type & AHD_TRANS_CUR) != 0) {
3181 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3184 if (ahd->msg_type != MSG_TYPE_NONE) {
3185 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3186 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3188 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3189 ahd_print_devinfo(ahd, devinfo);
3190 printf("Expecting IU Change busfree\n");
3193 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3194 | MSG_FLAG_IU_REQ_CHANGED;
3196 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3198 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3199 printf("PPR with IU_REQ outstanding\n");
3201 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3206 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3207 tinfo, AHD_NEG_TO_GOAL);
3209 if (update_needed && active)
3210 ahd_update_pending_scbs(ahd);
3214 * Update the user/goal/curr tables of wide negotiation
3215 * parameters as well as, in the case of a current or active update,
3216 * any data structures on the host controller. In the case of an
3217 * active update, the specified target is currently talking to us on
3218 * the bus, so the transfer parameter update must take effect
3222 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3223 u_int width, u_int type, int paused)
3225 struct ahd_initiator_tinfo *tinfo;
3226 struct ahd_tmode_tstate *tstate;
3231 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3233 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3234 devinfo->target, &tstate);
3236 if ((type & AHD_TRANS_USER) != 0)
3237 tinfo->user.width = width;
3239 if ((type & AHD_TRANS_GOAL) != 0)
3240 tinfo->goal.width = width;
3242 oldwidth = tinfo->curr.width;
3243 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3247 tinfo->curr.width = width;
3248 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3249 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3251 printf("%s: target %d using %dbit transfers\n",
3252 ahd_name(ahd), devinfo->target,
3253 8 * (0x01 << width));
3257 if ((type & AHD_TRANS_CUR) != 0) {
3260 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3265 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3266 tinfo, AHD_NEG_TO_GOAL);
3267 if (update_needed && active)
3268 ahd_update_pending_scbs(ahd);
3273 * Update the current state of tagged queuing for a given target.
3276 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3279 ahd_platform_set_tags(ahd, devinfo, alg);
3280 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3281 devinfo->lun, AC_TRANSFER_NEG, &alg);
3285 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3286 struct ahd_transinfo *tinfo)
3288 ahd_mode_state saved_modes;
3293 u_int saved_negoaddr;
3294 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3296 saved_modes = ahd_save_modes(ahd);
3297 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3299 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3300 ahd_outb(ahd, NEGOADDR, devinfo->target);
3301 period = tinfo->period;
3302 offset = tinfo->offset;
3303 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3304 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3305 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3308 period = AHD_SYNCRATE_ASYNC;
3309 if (period == AHD_SYNCRATE_160) {
3311 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3313 * When the SPI4 spec was finalized, PACE transfers
3314 * was not made a configurable option in the PPR
3315 * message. Instead it is assumed to be enabled for
3316 * any syncrate faster than 80MHz. Nevertheless,
3317 * Harpoon2A4 allows this to be configurable.
3319 * Harpoon2A4 also assumes at most 2 data bytes per
3320 * negotiated REQ/ACK offset. Paced transfers take
3321 * 4, so we must adjust our offset.
3323 ppr_opts |= PPROPT_PACE;
3327 * Harpoon2A assumed that there would be a
3328 * fallback rate between 160MHz and 80Mhz,
3329 * so 7 is used as the period factor rather
3330 * than 8 for 160MHz.
3332 period = AHD_SYNCRATE_REVA_160;
3334 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3335 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3339 * Precomp should be disabled for non-paced transfers.
3341 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3343 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3344 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3345 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3347 * Slow down our CRC interval to be
3348 * compatible with non-packetized
3349 * U160 devices that can't handle a
3350 * CRC at full speed.
3352 con_opts |= ENSLOWCRC;
3355 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3357 * On H2A4, revert to a slower slewrate
3358 * on non-paced transfers.
3360 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3365 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3366 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3367 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3368 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3370 ahd_outb(ahd, NEGPERIOD, period);
3371 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3372 ahd_outb(ahd, NEGOFFSET, offset);
3374 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3375 con_opts |= WIDEXFER;
3378 * During packetized transfers, the target will
3379 * give us the opportunity to send command packets
3380 * without us asserting attention.
3382 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3383 con_opts |= ENAUTOATNO;
3384 ahd_outb(ahd, NEGCONOPTS, con_opts);
3385 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3386 ahd_restore_modes(ahd, saved_modes);
3390 * When the transfer settings for a connection change, setup for
3391 * negotiation in pending SCBs to effect the change as quickly as
3392 * possible. We also cancel any negotiations that are scheduled
3393 * for inflight SCBs that have not been started yet.
3396 ahd_update_pending_scbs(struct ahd_softc *ahd)
3398 struct scb *pending_scb;
3399 int pending_scb_count;
3402 ahd_mode_state saved_modes;
3405 * Traverse the pending SCB list and ensure that all of the
3406 * SCBs there have the proper settings. We can only safely
3407 * clear the negotiation required flag (setting requires the
3408 * execution queue to be modified) and this is only possible
3409 * if we are not already attempting to select out for this
3410 * SCB. For this reason, all callers only call this routine
3411 * if we are changing the negotiation settings for the currently
3412 * active transaction on the bus.
3414 pending_scb_count = 0;
3415 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3416 struct ahd_devinfo devinfo;
3417 struct ahd_tmode_tstate *tstate;
3419 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3420 ahd_fetch_transinfo(ahd, devinfo.channel,
3422 devinfo.target, &tstate);
3423 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3424 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3425 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3426 pending_scb->hscb->control &= ~MK_MESSAGE;
3428 ahd_sync_scb(ahd, pending_scb,
3429 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3430 pending_scb_count++;
3433 if (pending_scb_count == 0)
3436 if (ahd_is_paused(ahd)) {
3444 * Force the sequencer to reinitialize the selection for
3445 * the command at the head of the execution queue if it
3446 * has already been setup. The negotiation changes may
3447 * effect whether we select-out with ATN. It is only
3448 * safe to clear ENSELO when the bus is not free and no
3449 * selection is in progres or completed.
3451 saved_modes = ahd_save_modes(ahd);
3452 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3453 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3454 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3455 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3456 saved_scbptr = ahd_get_scbptr(ahd);
3457 /* Ensure that the hscbs down on the card match the new information */
3458 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3462 scb_tag = SCB_GET_TAG(pending_scb);
3463 ahd_set_scbptr(ahd, scb_tag);
3464 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3465 control &= ~MK_MESSAGE;
3466 control |= pending_scb->hscb->control & MK_MESSAGE;
3467 ahd_outb(ahd, SCB_CONTROL, control);
3469 ahd_set_scbptr(ahd, saved_scbptr);
3470 ahd_restore_modes(ahd, saved_modes);
3476 /**************************** Pathing Information *****************************/
3478 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3480 ahd_mode_state saved_modes;
3485 saved_modes = ahd_save_modes(ahd);
3486 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3488 if (ahd_inb(ahd, SSTAT0) & TARGET)
3491 role = ROLE_INITIATOR;
3493 if (role == ROLE_TARGET
3494 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3495 /* We were selected, so pull our id from TARGIDIN */
3496 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3497 } else if (role == ROLE_TARGET)
3498 our_id = ahd_inb(ahd, TOWNID);
3500 our_id = ahd_inb(ahd, IOWNID);
3502 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3503 ahd_compile_devinfo(devinfo,
3505 SCSIID_TARGET(ahd, saved_scsiid),
3506 ahd_inb(ahd, SAVED_LUN),
3507 SCSIID_CHANNEL(ahd, saved_scsiid),
3509 ahd_restore_modes(ahd, saved_modes);
3513 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3515 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3516 devinfo->target, devinfo->lun);
3519 struct ahd_phase_table_entry*
3520 ahd_lookup_phase_entry(int phase)
3522 struct ahd_phase_table_entry *entry;
3523 struct ahd_phase_table_entry *last_entry;
3526 * num_phases doesn't include the default entry which
3527 * will be returned if the phase doesn't match.
3529 last_entry = &ahd_phase_table[num_phases];
3530 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3531 if (phase == entry->phase)
3538 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3539 u_int lun, char channel, role_t role)
3541 devinfo->our_scsiid = our_id;
3542 devinfo->target = target;
3544 devinfo->target_offset = target;
3545 devinfo->channel = channel;
3546 devinfo->role = role;
3548 devinfo->target_offset += 8;
3549 devinfo->target_mask = (0x01 << devinfo->target_offset);
3553 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3559 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3560 role = ROLE_INITIATOR;
3561 if ((scb->hscb->control & TARGET_SCB) != 0)
3563 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3564 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3568 /************************ Message Phase Processing ****************************/
3570 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3571 * or enters the initial message out phase, we are interrupted. Fill our
3572 * outgoing message buffer with the appropriate message and beging handing
3573 * the message phase(s) manually.
3576 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3580 * To facilitate adding multiple messages together,
3581 * each routine should increment the index and len
3582 * variables instead of setting them explicitly.
3584 ahd->msgout_index = 0;
3585 ahd->msgout_len = 0;
3587 if (ahd_currently_packetized(ahd))
3588 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3590 if (ahd->send_msg_perror
3591 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3592 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3594 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3596 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3597 printf("Setting up for Parity Error delivery\n");
3600 } else if (scb == NULL) {
3601 printf("%s: WARNING. No pending message for "
3602 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3603 AHD_CORRECTABLE_ERROR(ahd);
3604 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3606 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3610 if ((scb->flags & SCB_DEVICE_RESET) == 0
3611 && (scb->flags & SCB_PACKETIZED) == 0
3612 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3615 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3616 if ((scb->hscb->control & DISCENB) != 0)
3617 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3618 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3621 if ((scb->hscb->control & TAG_ENB) != 0) {
3622 ahd->msgout_buf[ahd->msgout_index++] =
3623 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3624 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3625 ahd->msgout_len += 2;
3629 if (scb->flags & SCB_DEVICE_RESET) {
3630 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3632 ahd_print_path(ahd, scb);
3633 printf("Bus Device Reset Message Sent\n");
3634 AHD_CORRECTABLE_ERROR(ahd);
3636 * Clear our selection hardware in advance of
3637 * the busfree. We may have an entry in the waiting
3638 * Q for this target, and we don't want to go about
3639 * selecting while we handle the busfree and blow it
3642 ahd_outb(ahd, SCSISEQ0, 0);
3643 } else if ((scb->flags & SCB_ABORT) != 0) {
3645 if ((scb->hscb->control & TAG_ENB) != 0) {
3646 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3648 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3651 ahd_print_path(ahd, scb);
3652 printf("Abort%s Message Sent\n",
3653 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3654 AHD_CORRECTABLE_ERROR(ahd);
3656 * Clear our selection hardware in advance of
3657 * the busfree. We may have an entry in the waiting
3658 * Q for this target, and we don't want to go about
3659 * selecting while we handle the busfree and blow it
3662 ahd_outb(ahd, SCSISEQ0, 0);
3663 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3664 ahd_build_transfer_msg(ahd, devinfo);
3666 * Clear our selection hardware in advance of potential
3667 * PPR IU status change busfree. We may have an entry in
3668 * the waiting Q for this target, and we don't want to go
3669 * about selecting while we handle the busfree and blow
3672 ahd_outb(ahd, SCSISEQ0, 0);
3674 printf("ahd_intr: AWAITING_MSG for an SCB that "
3675 "does not have a waiting message\n");
3676 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3677 devinfo->target_mask);
3678 AHD_FATAL_ERROR(ahd);
3679 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3680 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3681 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3686 * Clear the MK_MESSAGE flag from the SCB so we aren't
3687 * asked to send this message again.
3689 ahd_outb(ahd, SCB_CONTROL,
3690 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3691 scb->hscb->control &= ~MK_MESSAGE;
3692 ahd->msgout_index = 0;
3693 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3697 * Build an appropriate transfer negotiation message for the
3698 * currently active target.
3701 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3704 * We need to initiate transfer negotiations.
3705 * If our current and goal settings are identical,
3706 * we want to renegotiate due to a check condition.
3708 struct ahd_initiator_tinfo *tinfo;
3709 struct ahd_tmode_tstate *tstate;
3717 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3718 devinfo->target, &tstate);
3720 * Filter our period based on the current connection.
3721 * If we can't perform DT transfers on this segment (not in LVD
3722 * mode for instance), then our decision to issue a PPR message
3725 period = tinfo->goal.period;
3726 offset = tinfo->goal.offset;
3727 ppr_options = tinfo->goal.ppr_options;
3728 /* Target initiated PPR is not allowed in the SCSI spec */
3729 if (devinfo->role == ROLE_TARGET)
3731 ahd_devlimited_syncrate(ahd, tinfo, &period,
3732 &ppr_options, devinfo->role);
3733 dowide = tinfo->curr.width != tinfo->goal.width;
3734 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3736 * Only use PPR if we have options that need it, even if the device
3737 * claims to support it. There might be an expander in the way
3740 doppr = ppr_options != 0;
3742 if (!dowide && !dosync && !doppr) {
3743 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3744 dosync = tinfo->goal.offset != 0;
3747 if (!dowide && !dosync && !doppr) {
3749 * Force async with a WDTR message if we have a wide bus,
3750 * or just issue an SDTR with a 0 offset.
3752 if ((ahd->features & AHD_WIDE) != 0)
3758 ahd_print_devinfo(ahd, devinfo);
3759 printf("Ensuring async\n");
3762 /* Target initiated PPR is not allowed in the SCSI spec */
3763 if (devinfo->role == ROLE_TARGET)
3767 * Both the PPR message and SDTR message require the
3768 * goal syncrate to be limited to what the target device
3769 * is capable of handling (based on whether an LVD->SE
3770 * expander is on the bus), so combine these two cases.
3771 * Regardless, guarantee that if we are using WDTR and SDTR
3772 * messages that WDTR comes first.
3774 if (doppr || (dosync && !dowide)) {
3776 offset = tinfo->goal.offset;
3777 ahd_validate_offset(ahd, tinfo, period, &offset,
3778 doppr ? tinfo->goal.width
3779 : tinfo->curr.width,
3782 ahd_construct_ppr(ahd, devinfo, period, offset,
3783 tinfo->goal.width, ppr_options);
3785 ahd_construct_sdtr(ahd, devinfo, period, offset);
3788 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3793 * Build a synchronous negotiation message in our message
3794 * buffer based on the input parameters.
3797 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3798 u_int period, u_int offset)
3801 period = AHD_ASYNC_XFER_PERIOD;
3802 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3803 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR_LEN;
3804 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_SDTR;
3805 ahd->msgout_buf[ahd->msgout_index++] = period;
3806 ahd->msgout_buf[ahd->msgout_index++] = offset;
3807 ahd->msgout_len += 5;
3809 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3810 ahd_name(ahd), devinfo->channel, devinfo->target,
3811 devinfo->lun, period, offset);
3816 * Build a wide negotiateion message in our message
3817 * buffer based on the input parameters.
3820 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3823 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3824 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR_LEN;
3825 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_WDTR;
3826 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3827 ahd->msgout_len += 4;
3829 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3830 ahd_name(ahd), devinfo->channel, devinfo->target,
3831 devinfo->lun, bus_width);
3836 * Build a parallel protocol request message in our message
3837 * buffer based on the input parameters.
3840 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3841 u_int period, u_int offset, u_int bus_width,
3845 * Always request precompensation from
3846 * the other target if we are running
3847 * at paced syncrates.
3849 if (period <= AHD_SYNCRATE_PACED)
3850 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3852 period = AHD_ASYNC_XFER_PERIOD;
3853 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXTENDED;
3854 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR_LEN;
3855 ahd->msgout_buf[ahd->msgout_index++] = MSG_EXT_PPR;
3856 ahd->msgout_buf[ahd->msgout_index++] = period;
3857 ahd->msgout_buf[ahd->msgout_index++] = 0;
3858 ahd->msgout_buf[ahd->msgout_index++] = offset;
3859 ahd->msgout_buf[ahd->msgout_index++] = bus_width;
3860 ahd->msgout_buf[ahd->msgout_index++] = ppr_options;
3861 ahd->msgout_len += 8;
3863 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3864 "offset %x, ppr_options %x\n", ahd_name(ahd),
3865 devinfo->channel, devinfo->target, devinfo->lun,
3866 bus_width, period, offset, ppr_options);
3871 * Clear any active message state.
3874 ahd_clear_msg_state(struct ahd_softc *ahd)
3876 ahd_mode_state saved_modes;
3878 saved_modes = ahd_save_modes(ahd);
3879 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3880 ahd->send_msg_perror = 0;
3881 ahd->msg_flags = MSG_FLAG_NONE;
3882 ahd->msgout_len = 0;
3883 ahd->msgin_index = 0;
3884 ahd->msg_type = MSG_TYPE_NONE;
3885 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3887 * The target didn't care to respond to our
3888 * message request, so clear ATN.
3890 ahd_outb(ahd, CLRSINT1, CLRATNO);
3892 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3893 ahd_outb(ahd, SEQ_FLAGS2,
3894 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3895 ahd_restore_modes(ahd, saved_modes);
3899 * Manual message loop handler.
3902 ahd_handle_message_phase(struct ahd_softc *ahd)
3904 struct ahd_devinfo devinfo;
3908 ahd_fetch_devinfo(ahd, &devinfo);
3909 end_session = FALSE;
3910 bus_phase = ahd_inb(ahd, LASTPHASE);
3912 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3913 printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3914 ahd_outb(ahd, LQCTL2, LQIRETRY);
3917 switch (ahd->msg_type) {
3918 case MSG_TYPE_INITIATOR_MSGOUT:
3924 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3925 panic("HOST_MSG_LOOP interrupt with no active message");
3928 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3929 ahd_print_devinfo(ahd, &devinfo);
3930 printf("INITIATOR_MSG_OUT");
3933 phasemis = bus_phase != P_MESGOUT;
3936 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3937 printf(" PHASEMIS %s\n",
3938 ahd_lookup_phase_entry(bus_phase)
3942 if (bus_phase == P_MESGIN) {
3944 * Change gears and see if
3945 * this messages is of interest to
3946 * us or should be passed back to
3949 ahd_outb(ahd, CLRSINT1, CLRATNO);
3950 ahd->send_msg_perror = 0;
3951 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3952 ahd->msgin_index = 0;
3959 if (ahd->send_msg_perror) {
3960 ahd_outb(ahd, CLRSINT1, CLRATNO);
3961 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3963 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3964 printf(" byte 0x%x\n", ahd->send_msg_perror);
3967 * If we are notifying the target of a CRC error
3968 * during packetized operations, the target is
3969 * within its rights to acknowledge our message
3972 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3973 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3974 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3976 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3977 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3981 msgdone = ahd->msgout_index == ahd->msgout_len;
3984 * The target has requested a retry.
3985 * Re-assert ATN, reset our message index to
3988 ahd->msgout_index = 0;
3989 ahd_assert_atn(ahd);
3992 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3994 /* Last byte is signified by dropping ATN */
3995 ahd_outb(ahd, CLRSINT1, CLRATNO);
3999 * Clear our interrupt status and present
4000 * the next byte on the bus.
4002 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4004 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4005 printf(" byte 0x%x\n",
4006 ahd->msgout_buf[ahd->msgout_index]);
4008 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
4009 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
4012 case MSG_TYPE_INITIATOR_MSGIN:
4018 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4019 ahd_print_devinfo(ahd, &devinfo);
4020 printf("INITIATOR_MSG_IN");
4023 phasemis = bus_phase != P_MESGIN;
4026 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4027 printf(" PHASEMIS %s\n",
4028 ahd_lookup_phase_entry(bus_phase)
4032 ahd->msgin_index = 0;
4033 if (bus_phase == P_MESGOUT
4034 && (ahd->send_msg_perror != 0
4035 || (ahd->msgout_len != 0
4036 && ahd->msgout_index == 0))) {
4037 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
4044 /* Pull the byte in without acking it */
4045 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4047 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4048 printf(" byte 0x%x\n",
4049 ahd->msgin_buf[ahd->msgin_index]);
4052 message_done = ahd_parse_msg(ahd, &devinfo);
4056 * Clear our incoming message buffer in case there
4057 * is another message following this one.
4059 ahd->msgin_index = 0;
4062 * If this message illicited a response,
4063 * assert ATN so the target takes us to the
4064 * message out phase.
4066 if (ahd->msgout_len != 0) {
4068 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4069 ahd_print_devinfo(ahd, &devinfo);
4070 printf("Asserting ATN for response\n");
4073 ahd_assert_atn(ahd);
4078 if (message_done == MSGLOOP_TERMINATED) {
4082 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4083 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4087 case MSG_TYPE_TARGET_MSGIN:
4093 * By default, the message loop will continue.
4095 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4097 if (ahd->msgout_len == 0)
4098 panic("Target MSGIN with no active message");
4101 * If we interrupted a mesgout session, the initiator
4102 * will not know this until our first REQ. So, we
4103 * only honor mesgout requests after we've sent our
4106 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4107 && ahd->msgout_index > 0)
4108 msgout_request = TRUE;
4110 msgout_request = FALSE;
4112 if (msgout_request) {
4115 * Change gears and see if
4116 * this messages is of interest to
4117 * us or should be passed back to
4120 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4121 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4122 ahd->msgin_index = 0;
4123 /* Dummy read to REQ for first byte */
4124 ahd_inb(ahd, SCSIDAT);
4125 ahd_outb(ahd, SXFRCTL0,
4126 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4130 msgdone = ahd->msgout_index == ahd->msgout_len;
4132 ahd_outb(ahd, SXFRCTL0,
4133 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4139 * Present the next byte on the bus.
4141 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4142 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4145 case MSG_TYPE_TARGET_MSGOUT:
4151 * By default, the message loop will continue.
4153 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4156 * The initiator signals that this is
4157 * the last byte by dropping ATN.
4159 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4162 * Read the latched byte, but turn off SPIOEN first
4163 * so that we don't inadvertently cause a REQ for the
4166 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4167 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4168 msgdone = ahd_parse_msg(ahd, &devinfo);
4169 if (msgdone == MSGLOOP_TERMINATED) {
4171 * The message is *really* done in that it caused
4172 * us to go to bus free. The sequencer has already
4173 * been reset at this point, so pull the ejection
4182 * XXX Read spec about initiator dropping ATN too soon
4183 * and use msgdone to detect it.
4185 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4186 ahd->msgin_index = 0;
4189 * If this message illicited a response, transition
4190 * to the Message in phase and send it.
4192 if (ahd->msgout_len != 0) {
4193 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4194 ahd_outb(ahd, SXFRCTL0,
4195 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4196 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4197 ahd->msgin_index = 0;
4205 /* Ask for the next byte. */
4206 ahd_outb(ahd, SXFRCTL0,
4207 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4213 panic("Unknown REQINIT message type");
4217 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4218 printf("%s: Returning to Idle Loop\n",
4220 ahd_clear_msg_state(ahd);
4223 * Perform the equivalent of a clear_target_state.
4225 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4226 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4227 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4229 ahd_clear_msg_state(ahd);
4230 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4236 * See if we sent a particular extended message to the target.
4237 * If "full" is true, return true only if the target saw the full
4238 * message. If "full" is false, return true if the target saw at
4239 * least the first byte of the message.
4242 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4250 while (index < ahd->msgout_len) {
4251 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4254 end_index = index + 1 + ahd->msgout_buf[index + 1];
4255 if (ahd->msgout_buf[index+2] == msgval
4256 && type == AHDMSG_EXT) {
4259 if (ahd->msgout_index > end_index)
4261 } else if (ahd->msgout_index > index)
4265 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4266 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4268 /* Skip tag type and tag id or residue param*/
4271 /* Single byte message */
4272 if (type == AHDMSG_1B
4273 && ahd->msgout_index > index
4274 && (ahd->msgout_buf[index] == msgval
4275 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4276 && msgval == MSG_IDENTIFYFLAG)))
4288 * Wait for a complete incoming message, parse it, and respond accordingly.
4291 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4293 struct ahd_initiator_tinfo *tinfo;
4294 struct ahd_tmode_tstate *tstate;
4299 done = MSGLOOP_IN_PROG;
4302 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4303 devinfo->target, &tstate);
4306 * Parse as much of the message as is available,
4307 * rejecting it if we don't support it. When
4308 * the entire message is available and has been
4309 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4310 * that we have parsed an entire message.
4312 * In the case of extended messages, we accept the length
4313 * byte outright and perform more checking once we know the
4314 * extended message type.
4316 switch (ahd->msgin_buf[0]) {
4317 case MSG_DISCONNECT:
4318 case MSG_SAVEDATAPOINTER:
4319 case MSG_CMDCOMPLETE:
4320 case MSG_RESTOREPOINTERS:
4321 case MSG_IGN_WIDE_RESIDUE:
4323 * End our message loop as these are messages
4324 * the sequencer handles on its own.
4326 done = MSGLOOP_TERMINATED;
4328 case MSG_MESSAGE_REJECT:
4329 response = ahd_handle_msg_reject(ahd, devinfo);
4332 done = MSGLOOP_MSGCOMPLETE;
4336 /* Wait for enough of the message to begin validation */
4337 if (ahd->msgin_index < 2)
4339 switch (ahd->msgin_buf[2]) {
4347 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4353 * Wait until we have both args before validating
4354 * and acting on this message.
4356 * Add one to MSG_EXT_SDTR_LEN to account for
4357 * the extended message preamble.
4359 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4362 period = ahd->msgin_buf[3];
4364 saved_offset = offset = ahd->msgin_buf[4];
4365 ahd_devlimited_syncrate(ahd, tinfo, &period,
4366 &ppr_options, devinfo->role);
4367 ahd_validate_offset(ahd, tinfo, period, &offset,
4368 tinfo->curr.width, devinfo->role);
4370 printf("(%s:%c:%d:%d): Received "
4371 "SDTR period %x, offset %x\n\t"
4372 "Filtered to period %x, offset %x\n",
4373 ahd_name(ahd), devinfo->channel,
4374 devinfo->target, devinfo->lun,
4375 ahd->msgin_buf[3], saved_offset,
4378 ahd_set_syncrate(ahd, devinfo, period,
4379 offset, ppr_options,
4380 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4384 * See if we initiated Sync Negotiation
4385 * and didn't have to fall down to async
4388 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4390 if (saved_offset != offset) {
4391 /* Went too low - force async */
4396 * Send our own SDTR in reply
4399 && devinfo->role == ROLE_INITIATOR) {
4400 printf("(%s:%c:%d:%d): Target "
4402 ahd_name(ahd), devinfo->channel,
4403 devinfo->target, devinfo->lun);
4405 ahd->msgout_index = 0;
4406 ahd->msgout_len = 0;
4407 ahd_construct_sdtr(ahd, devinfo,
4409 ahd->msgout_index = 0;
4412 done = MSGLOOP_MSGCOMPLETE;
4419 u_int sending_reply;
4421 sending_reply = FALSE;
4422 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4428 * Wait until we have our arg before validating
4429 * and acting on this message.
4431 * Add one to MSG_EXT_WDTR_LEN to account for
4432 * the extended message preamble.
4434 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4437 bus_width = ahd->msgin_buf[3];
4438 saved_width = bus_width;
4439 ahd_validate_width(ahd, tinfo, &bus_width,
4442 printf("(%s:%c:%d:%d): Received WDTR "
4443 "%x filtered to %x\n",
4444 ahd_name(ahd), devinfo->channel,
4445 devinfo->target, devinfo->lun,
4446 saved_width, bus_width);
4449 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4451 * Don't send a WDTR back to the
4452 * target, since we asked first.
4453 * If the width went higher than our
4454 * request, reject it.
4456 if (saved_width > bus_width) {
4458 printf("(%s:%c:%d:%d): requested %dBit "
4459 "transfers. Rejecting...\n",
4460 ahd_name(ahd), devinfo->channel,
4461 devinfo->target, devinfo->lun,
4462 8 * (0x01 << bus_width));
4467 * Send our own WDTR in reply
4470 && devinfo->role == ROLE_INITIATOR) {
4471 printf("(%s:%c:%d:%d): Target "
4473 ahd_name(ahd), devinfo->channel,
4474 devinfo->target, devinfo->lun);
4476 ahd->msgout_index = 0;
4477 ahd->msgout_len = 0;
4478 ahd_construct_wdtr(ahd, devinfo, bus_width);
4479 ahd->msgout_index = 0;
4481 sending_reply = TRUE;
4484 * After a wide message, we are async, but
4485 * some devices don't seem to honor this portion
4486 * of the spec. Force a renegotiation of the
4487 * sync component of our transfer agreement even
4488 * if our goal is async. By updating our width
4489 * after forcing the negotiation, we avoid
4490 * renegotiating for width.
4492 ahd_update_neg_request(ahd, devinfo, tstate,
4493 tinfo, AHD_NEG_ALWAYS);
4494 ahd_set_width(ahd, devinfo, bus_width,
4495 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4497 if (sending_reply == FALSE && reject == FALSE) {
4500 * We will always have an SDTR to send.
4502 ahd->msgout_index = 0;
4503 ahd->msgout_len = 0;
4504 ahd_build_transfer_msg(ahd, devinfo);
4505 ahd->msgout_index = 0;
4508 done = MSGLOOP_MSGCOMPLETE;
4519 u_int saved_ppr_options;
4521 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4527 * Wait until we have all args before validating
4528 * and acting on this message.
4530 * Add one to MSG_EXT_PPR_LEN to account for
4531 * the extended message preamble.
4533 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4536 period = ahd->msgin_buf[3];
4537 offset = ahd->msgin_buf[5];
4538 bus_width = ahd->msgin_buf[6];
4539 saved_width = bus_width;
4540 ppr_options = ahd->msgin_buf[7];
4542 * According to the spec, a DT only
4543 * period factor with no DT option
4544 * set implies async.
4546 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4549 saved_ppr_options = ppr_options;
4550 saved_offset = offset;
4553 * Transfer options are only available if we
4554 * are negotiating wide.
4557 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4559 ahd_validate_width(ahd, tinfo, &bus_width,
4561 ahd_devlimited_syncrate(ahd, tinfo, &period,
4562 &ppr_options, devinfo->role);
4563 ahd_validate_offset(ahd, tinfo, period, &offset,
4564 bus_width, devinfo->role);
4566 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4568 * If we are unable to do any of the
4569 * requested options (we went too low),
4570 * then we'll have to reject the message.
4572 if (saved_width > bus_width
4573 || saved_offset != offset
4574 || saved_ppr_options != ppr_options) {
4582 if (devinfo->role != ROLE_TARGET)
4583 printf("(%s:%c:%d:%d): Target "
4585 ahd_name(ahd), devinfo->channel,
4586 devinfo->target, devinfo->lun);
4588 printf("(%s:%c:%d:%d): Initiator "
4590 ahd_name(ahd), devinfo->channel,
4591 devinfo->target, devinfo->lun);
4592 ahd->msgout_index = 0;
4593 ahd->msgout_len = 0;
4594 ahd_construct_ppr(ahd, devinfo, period, offset,
4595 bus_width, ppr_options);
4596 ahd->msgout_index = 0;
4600 printf("(%s:%c:%d:%d): Received PPR width %x, "
4601 "period %x, offset %x,options %x\n"
4602 "\tFiltered to width %x, period %x, "
4603 "offset %x, options %x\n",
4604 ahd_name(ahd), devinfo->channel,
4605 devinfo->target, devinfo->lun,
4606 saved_width, ahd->msgin_buf[3],
4607 saved_offset, saved_ppr_options,
4608 bus_width, period, offset, ppr_options);
4610 ahd_set_width(ahd, devinfo, bus_width,
4611 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4613 ahd_set_syncrate(ahd, devinfo, period,
4614 offset, ppr_options,
4615 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4618 done = MSGLOOP_MSGCOMPLETE;
4622 /* Unknown extended message. Reject it. */
4628 #ifdef AHD_TARGET_MODE
4629 case MSG_BUS_DEV_RESET:
4630 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4632 "Bus Device Reset Received",
4633 /*verbose_level*/0);
4635 done = MSGLOOP_TERMINATED;
4639 case MSG_CLEAR_QUEUE:
4643 /* Target mode messages */
4644 if (devinfo->role != ROLE_TARGET) {
4648 tag = SCB_LIST_NULL;
4649 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4650 tag = ahd_inb(ahd, INITIATOR_TAG);
4651 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4652 devinfo->lun, tag, ROLE_TARGET,
4655 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4656 if (tstate != NULL) {
4657 struct ahd_tmode_lstate* lstate;
4659 lstate = tstate->enabled_luns[devinfo->lun];
4660 if (lstate != NULL) {
4661 ahd_queue_lstate_event(ahd, lstate,
4662 devinfo->our_scsiid,
4665 ahd_send_lstate_events(ahd, lstate);
4669 done = MSGLOOP_TERMINATED;
4673 case MSG_QAS_REQUEST:
4675 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4676 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4677 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4679 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4681 case MSG_TERM_IO_PROC:
4689 * Setup to reject the message.
4691 ahd->msgout_index = 0;
4692 ahd->msgout_len = 1;
4693 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4694 done = MSGLOOP_MSGCOMPLETE;
4698 if (done != MSGLOOP_IN_PROG && !response)
4699 /* Clear the outgoing message buffer */
4700 ahd->msgout_len = 0;
4706 * Process a message reject message.
4709 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4712 * What we care about here is if we had an
4713 * outstanding SDTR or WDTR message for this
4714 * target. If we did, this is a signal that
4715 * the target is refusing negotiation.
4718 struct ahd_initiator_tinfo *tinfo;
4719 struct ahd_tmode_tstate *tstate;
4724 scb_index = ahd_get_scbptr(ahd);
4725 scb = ahd_lookup_scb(ahd, scb_index);
4726 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4727 devinfo->our_scsiid,
4728 devinfo->target, &tstate);
4729 /* Might be necessary */
4730 last_msg = ahd_inb(ahd, LAST_MSG);
4732 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4733 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4734 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4736 * Target may not like our SPI-4 PPR Options.
4737 * Attempt to negotiate 80MHz which will turn
4738 * off these options.
4741 printf("(%s:%c:%d:%d): PPR Rejected. "
4742 "Trying simple U160 PPR\n",
4743 ahd_name(ahd), devinfo->channel,
4744 devinfo->target, devinfo->lun);
4746 tinfo->goal.period = AHD_SYNCRATE_DT;
4747 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4748 | MSG_EXT_PPR_QAS_REQ
4749 | MSG_EXT_PPR_DT_REQ;
4752 * Target does not support the PPR message.
4753 * Attempt to negotiate SPI-2 style.
4756 printf("(%s:%c:%d:%d): PPR Rejected. "
4757 "Trying WDTR/SDTR\n",
4758 ahd_name(ahd), devinfo->channel,
4759 devinfo->target, devinfo->lun);
4761 tinfo->goal.ppr_options = 0;
4762 tinfo->curr.transport_version = 2;
4763 tinfo->goal.transport_version = 2;
4765 ahd->msgout_index = 0;
4766 ahd->msgout_len = 0;
4767 ahd_build_transfer_msg(ahd, devinfo);
4768 ahd->msgout_index = 0;
4770 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4772 /* note 8bit xfers */
4773 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4774 "8bit transfers\n", ahd_name(ahd),
4775 devinfo->channel, devinfo->target, devinfo->lun);
4776 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4777 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4780 * No need to clear the sync rate. If the target
4781 * did not accept the command, our syncrate is
4782 * unaffected. If the target started the negotiation,
4783 * but rejected our response, we already cleared the
4784 * sync rate before sending our WDTR.
4786 if (tinfo->goal.offset != tinfo->curr.offset) {
4788 /* Start the sync negotiation */
4789 ahd->msgout_index = 0;
4790 ahd->msgout_len = 0;
4791 ahd_build_transfer_msg(ahd, devinfo);
4792 ahd->msgout_index = 0;
4795 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4796 /* note asynch xfers and clear flag */
4797 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4798 /*offset*/0, /*ppr_options*/0,
4799 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4801 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4802 "Using asynchronous transfers\n",
4803 ahd_name(ahd), devinfo->channel,
4804 devinfo->target, devinfo->lun);
4805 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4809 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4811 if (tag_type == MSG_SIMPLE_TASK) {
4812 printf("(%s:%c:%d:%d): refuses tagged commands. "
4813 "Performing non-tagged I/O\n", ahd_name(ahd),
4814 devinfo->channel, devinfo->target, devinfo->lun);
4815 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4818 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4819 "Performing simple queue tagged I/O only\n",
4820 ahd_name(ahd), devinfo->channel, devinfo->target,
4821 devinfo->lun, tag_type == MSG_ORDERED_TASK
4822 ? "ordered" : "head of queue");
4823 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4828 * Resend the identify for this CCB as the target
4829 * may believe that the selection is invalid otherwise.
4831 ahd_outb(ahd, SCB_CONTROL,
4832 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4833 scb->hscb->control &= mask;
4834 aic_set_transaction_tag(scb, /*enabled*/FALSE,
4835 /*type*/MSG_SIMPLE_TASK);
4836 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4837 ahd_assert_atn(ahd);
4838 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4842 * Requeue all tagged commands for this target
4843 * currently in our possession so they can be
4844 * converted to untagged commands.
4846 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4847 SCB_GET_CHANNEL(ahd, scb),
4848 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4849 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4851 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4853 * Most likely the device believes that we had
4854 * previously negotiated packetized.
4856 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4857 | MSG_FLAG_IU_REQ_CHANGED;
4859 ahd_force_renegotiation(ahd, devinfo);
4860 ahd->msgout_index = 0;
4861 ahd->msgout_len = 0;
4862 ahd_build_transfer_msg(ahd, devinfo);
4863 ahd->msgout_index = 0;
4867 * Otherwise, we ignore it.
4869 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4870 ahd_name(ahd), devinfo->channel, devinfo->target,
4877 * Process an ingnore wide residue message.
4880 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4885 scb_index = ahd_get_scbptr(ahd);
4886 scb = ahd_lookup_scb(ahd, scb_index);
4888 * XXX Actually check data direction in the sequencer?
4889 * Perhaps add datadir to some spare bits in the hscb?
4891 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4892 || aic_get_transfer_dir(scb) != CAM_DIR_IN) {
4894 * Ignore the message if we haven't
4895 * seen an appropriate data phase yet.
4899 * If the residual occurred on the last
4900 * transfer and the transfer request was
4901 * expected to end on an odd count, do
4902 * nothing. Otherwise, subtract a byte
4903 * and update the residual count accordingly.
4907 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4908 if ((sgptr & SG_LIST_NULL) != 0
4909 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4910 & SCB_XFERLEN_ODD) != 0) {
4912 * If the residual occurred on the last
4913 * transfer and the transfer request was
4914 * expected to end on an odd count, do
4922 /* Pull in the rest of the sgptr */
4923 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4924 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4925 if ((sgptr & SG_LIST_NULL) != 0) {
4927 * The residual data count is not updated
4928 * for the command run to completion case.
4929 * Explicitly zero the count.
4931 data_cnt &= ~AHD_SG_LEN_MASK;
4933 data_addr = ahd_inq(ahd, SHADDR);
4936 sgptr &= SG_PTR_MASK;
4937 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4938 struct ahd_dma64_seg *sg;
4940 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4943 * The residual sg ptr points to the next S/G
4944 * to load so we must go back one.
4947 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4948 if (sg != scb->sg_list
4949 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4952 sglen = aic_le32toh(sg->len);
4954 * Preserve High Address and SG_LIST
4955 * bits while setting the count to 1.
4957 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4958 data_addr = aic_le64toh(sg->addr)
4959 + (sglen & AHD_SG_LEN_MASK)
4963 * Increment sg so it points to the
4967 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4971 struct ahd_dma_seg *sg;
4973 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4976 * The residual sg ptr points to the next S/G
4977 * to load so we must go back one.
4980 sglen = aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
4981 if (sg != scb->sg_list
4982 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4985 sglen = aic_le32toh(sg->len);
4987 * Preserve High Address and SG_LIST
4988 * bits while setting the count to 1.
4990 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4991 data_addr = aic_le32toh(sg->addr)
4992 + (sglen & AHD_SG_LEN_MASK)
4996 * Increment sg so it points to the
5000 sgptr = ahd_sg_virt_to_bus(ahd, scb,
5005 * Toggle the "oddness" of the transfer length
5006 * to handle this mid-transfer ignore wide
5007 * residue. This ensures that the oddness is
5008 * correct for subsequent data transfers.
5010 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
5011 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
5014 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
5015 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
5017 * The FIFO's pointers will be updated if/when the
5018 * sequencer re-enters a data phase.
5026 * Reinitialize the data pointers for the active transfer
5027 * based on its current residual.
5030 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
5033 ahd_mode_state saved_modes;
5040 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
5041 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
5043 scb_index = ahd_get_scbptr(ahd);
5044 scb = ahd_lookup_scb(ahd, scb_index);
5047 * Release and reacquire the FIFO so we
5048 * have a clean slate.
5050 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5052 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5055 ahd_print_path(ahd, scb);
5056 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5057 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5059 saved_modes = ahd_save_modes(ahd);
5060 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5061 ahd_outb(ahd, DFFSTAT,
5062 ahd_inb(ahd, DFFSTAT)
5063 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5066 * Determine initial values for data_addr and data_cnt
5067 * for resuming the data phase.
5069 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5070 sgptr &= SG_PTR_MASK;
5072 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5073 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5074 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5076 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5077 struct ahd_dma64_seg *sg;
5079 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5081 /* The residual sg_ptr always points to the next sg */
5084 dataptr = aic_le64toh(sg->addr)
5085 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5087 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5089 struct ahd_dma_seg *sg;
5091 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5093 /* The residual sg_ptr always points to the next sg */
5096 dataptr = aic_le32toh(sg->addr)
5097 + (aic_le32toh(sg->len) & AHD_SG_LEN_MASK)
5099 ahd_outb(ahd, HADDR + 4,
5100 (aic_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5102 ahd_outl(ahd, HADDR, dataptr);
5103 ahd_outb(ahd, HCNT + 2, resid >> 16);
5104 ahd_outb(ahd, HCNT + 1, resid >> 8);
5105 ahd_outb(ahd, HCNT, resid);
5109 * Handle the effects of issuing a bus device reset message.
5112 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5113 u_int lun, cam_status status, char *message,
5116 #ifdef AHD_TARGET_MODE
5117 struct ahd_tmode_tstate* tstate;
5121 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5122 lun, SCB_LIST_NULL, devinfo->role,
5125 #ifdef AHD_TARGET_MODE
5127 * Send an immediate notify ccb to all target mord peripheral
5128 * drivers affected by this action.
5130 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5131 if (tstate != NULL) {
5135 if (lun != CAM_LUN_WILDCARD) {
5137 max_lun = AHD_NUM_LUNS - 1;
5142 for (cur_lun <= max_lun; cur_lun++) {
5143 struct ahd_tmode_lstate* lstate;
5145 lstate = tstate->enabled_luns[cur_lun];
5149 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5150 MSG_BUS_DEV_RESET, /*arg*/0);
5151 ahd_send_lstate_events(ahd, lstate);
5157 * Go back to async/narrow transfers and renegotiate.
5159 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5160 AHD_TRANS_CUR, /*paused*/TRUE);
5161 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5162 /*ppr_options*/0, AHD_TRANS_CUR,
5165 if (status != CAM_SEL_TIMEOUT)
5166 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5167 lun, AC_SENT_BDR, NULL);
5170 && (verbose_level <= bootverbose)) {
5171 AHD_CORRECTABLE_ERROR(ahd);
5172 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5173 message, devinfo->channel, devinfo->target, found);
5177 #ifdef AHD_TARGET_MODE
5179 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5184 * To facilitate adding multiple messages together,
5185 * each routine should increment the index and len
5186 * variables instead of setting them explicitly.
5188 ahd->msgout_index = 0;
5189 ahd->msgout_len = 0;
5191 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5192 ahd_build_transfer_msg(ahd, devinfo);
5194 panic("ahd_intr: AWAITING target message with no message");
5196 ahd->msgout_index = 0;
5197 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5200 /**************************** Initialization **********************************/
5202 ahd_sglist_size(struct ahd_softc *ahd)
5204 bus_size_t list_size;
5206 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5207 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5208 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5213 * Calculate the optimum S/G List allocation size. S/G elements used
5214 * for a given transaction must be physically contiguous. Assume the
5215 * OS will allocate full pages to us, so it doesn't make sense to request
5219 ahd_sglist_allocsize(struct ahd_softc *ahd)
5221 bus_size_t sg_list_increment;
5222 bus_size_t sg_list_size;
5223 bus_size_t max_list_size;
5224 bus_size_t best_list_size;
5226 /* Start out with the minimum required for AHD_NSEG. */
5227 sg_list_increment = ahd_sglist_size(ahd);
5228 sg_list_size = sg_list_increment;
5230 /* Get us as close as possible to a page in size. */
5231 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5232 sg_list_size += sg_list_increment;
5235 * Try to reduce the amount of wastage by allocating
5238 best_list_size = sg_list_size;
5239 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5240 if (max_list_size < 4 * PAGE_SIZE)
5241 max_list_size = 4 * PAGE_SIZE;
5242 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5243 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5244 while ((sg_list_size + sg_list_increment) <= max_list_size
5245 && (sg_list_size % PAGE_SIZE) != 0) {
5247 bus_size_t best_mod;
5249 sg_list_size += sg_list_increment;
5250 new_mod = sg_list_size % PAGE_SIZE;
5251 best_mod = best_list_size % PAGE_SIZE;
5252 if (new_mod > best_mod || new_mod == 0) {
5253 best_list_size = sg_list_size;
5256 return (best_list_size);
5260 * Allocate a controller structure for a new device
5261 * and perform initial initializion.
5264 ahd_alloc(void *platform_arg, char *name)
5266 struct ahd_softc *ahd;
5269 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT);
5271 printf("aic7xxx: cannot malloc softc!\n");
5272 free(name, M_DEVBUF);
5276 ahd = device_get_softc((device_t)platform_arg);
5278 memset(ahd, 0, sizeof(*ahd));
5279 ahd->seep_config = malloc(sizeof(*ahd->seep_config),
5280 M_DEVBUF, M_NOWAIT);
5281 if (ahd->seep_config == NULL) {
5283 free(ahd, M_DEVBUF);
5285 free(name, M_DEVBUF);
5288 LIST_INIT(&ahd->pending_scbs);
5289 LIST_INIT(&ahd->timedout_scbs);
5290 /* We don't know our unit number until the OSM sets it */
5293 ahd->description = NULL;
5294 ahd->bus_description = NULL;
5296 ahd->chip = AHD_NONE;
5297 ahd->features = AHD_FENONE;
5298 ahd->bugs = AHD_BUGNONE;
5299 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5300 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5301 aic_timer_init(&ahd->reset_timer);
5302 aic_timer_init(&ahd->stat_timer);
5303 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5304 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5305 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5306 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5307 ahd->int_coalescing_stop_threshold =
5308 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5310 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5316 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5317 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5318 ahd_name(ahd), (u_int)sizeof(struct scb),
5319 (u_int)sizeof(struct hardware_scb));
5326 ahd_softc_init(struct ahd_softc *ahd)
5335 ahd_softc_insert(struct ahd_softc *ahd)
5337 struct ahd_softc *list_ahd;
5339 #if AIC_PCI_CONFIG > 0
5341 * Second Function PCI devices need to inherit some
5342 * settings from function 0.
5344 if ((ahd->features & AHD_MULTI_FUNC) != 0) {
5345 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
5346 aic_dev_softc_t list_pci;
5347 aic_dev_softc_t pci;
5349 list_pci = list_ahd->dev_softc;
5350 pci = ahd->dev_softc;
5351 if (aic_get_pci_slot(list_pci) == aic_get_pci_slot(pci)
5352 && aic_get_pci_bus(list_pci) == aic_get_pci_bus(pci)) {
5353 struct ahd_softc *master;
5354 struct ahd_softc *slave;
5356 if (aic_get_pci_function(list_pci) == 0) {
5363 slave->flags &= ~AHD_BIOS_ENABLED;
5365 master->flags & AHD_BIOS_ENABLED;
5373 * Insertion sort into our list of softcs.
5375 list_ahd = TAILQ_FIRST(&ahd_tailq);
5376 while (list_ahd != NULL
5377 && ahd_softc_comp(ahd, list_ahd) <= 0)
5378 list_ahd = TAILQ_NEXT(list_ahd, links);
5379 if (list_ahd != NULL)
5380 TAILQ_INSERT_BEFORE(list_ahd, ahd, links);
5382 TAILQ_INSERT_TAIL(&ahd_tailq, ahd, links);
5387 ahd_set_unit(struct ahd_softc *ahd, int unit)
5393 ahd_set_name(struct ahd_softc *ahd, char *name)
5395 if (ahd->name != NULL)
5396 free(ahd->name, M_DEVBUF);
5401 ahd_free(struct ahd_softc *ahd)
5405 ahd_terminate_recovery_thread(ahd);
5406 switch (ahd->init_level) {
5412 aic_dmamap_unload(ahd, ahd->shared_data_dmat,
5413 ahd->shared_data_map.dmamap);
5416 aic_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5417 ahd->shared_data_map.dmamap);
5420 aic_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5423 aic_dma_tag_destroy(ahd, ahd->buffer_dmat);
5431 aic_dma_tag_destroy(ahd, ahd->parent_dmat);
5433 ahd_platform_free(ahd);
5434 ahd_fini_scbdata(ahd);
5435 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5436 struct ahd_tmode_tstate *tstate;
5438 tstate = ahd->enabled_targets[i];
5439 if (tstate != NULL) {
5440 #ifdef AHD_TARGET_MODE
5443 for (j = 0; j < AHD_NUM_LUNS; j++) {
5444 struct ahd_tmode_lstate *lstate;
5446 lstate = tstate->enabled_luns[j];
5447 if (lstate != NULL) {
5448 xpt_free_path(lstate->path);
5449 free(lstate, M_DEVBUF);
5453 free(tstate, M_DEVBUF);
5456 #ifdef AHD_TARGET_MODE
5457 if (ahd->black_hole != NULL) {
5458 xpt_free_path(ahd->black_hole->path);
5459 free(ahd->black_hole, M_DEVBUF);
5462 if (ahd->name != NULL)
5463 free(ahd->name, M_DEVBUF);
5464 if (ahd->seep_config != NULL)
5465 free(ahd->seep_config, M_DEVBUF);
5466 if (ahd->saved_stack != NULL)
5467 free(ahd->saved_stack, M_DEVBUF);
5469 free(ahd, M_DEVBUF);
5475 ahd_shutdown(void *arg)
5477 struct ahd_softc *ahd;
5479 ahd = (struct ahd_softc *)arg;
5482 * Stop periodic timer callbacks.
5484 aic_timer_stop(&ahd->reset_timer);
5485 aic_timer_stop(&ahd->stat_timer);
5487 /* This will reset most registers to 0, but not all */
5488 ahd_reset(ahd, /*reinit*/FALSE);
5492 * Reset the controller and record some information about it
5493 * that is only available just after a reset. If "reinit" is
5494 * non-zero, this reset occurred after initial configuration
5495 * and the caller requests that the chip be fully reinitialized
5496 * to a runable state. Chip interrupts are *not* enabled after
5497 * a reinitialization. The caller must enable interrupts via
5498 * ahd_intr_enable().
5501 ahd_reset(struct ahd_softc *ahd, int reinit)
5508 * Preserve the value of the SXFRCTL1 register for all channels.
5509 * It contains settings that affect termination and we don't want
5510 * to disturb the integrity of the bus.
5513 ahd_update_modes(ahd);
5514 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5515 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5517 cmd = aic_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5518 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5523 * During the assertion of CHIPRST, the chip
5524 * does not disable its parity logic prior to
5525 * the start of the reset. This may cause a
5526 * parity error to be detected and thus a
5527 * spurious SERR or PERR assertion. Disble
5528 * PERR and SERR responses during the CHIPRST.
5530 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5531 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5532 mod_cmd, /*bytes*/2);
5534 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5537 * Ensure that the reset has finished. We delay 1000us
5538 * prior to reading the register to make sure the chip
5539 * has sufficiently completed its reset to handle register
5545 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5548 printf("%s: WARNING - Failed chip reset! "
5549 "Trying to initialize anyway.\n", ahd_name(ahd));
5550 AHD_FATAL_ERROR(ahd);
5552 ahd_outb(ahd, HCNTRL, ahd->pause);
5554 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5556 * Clear any latched PCI error status and restore
5557 * previous SERR and PERR response enables.
5559 aic_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5561 aic_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5566 * Mode should be SCSI after a chip reset, but lets
5567 * set it just to be safe. We touch the MODE_PTR
5568 * register directly so as to bypass the lazy update
5569 * code in ahd_set_modes().
5571 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5572 ahd_outb(ahd, MODE_PTR,
5573 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5578 * We must always initialize STPWEN to 1 before we
5579 * restore the saved values. STPWEN is initialized
5580 * to a tri-state condition which can only be cleared
5583 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5584 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5586 /* Determine chip configuration */
5587 ahd->features &= ~AHD_WIDE;
5588 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5589 ahd->features |= AHD_WIDE;
5592 * If a recovery action has forced a chip reset,
5593 * re-initialize the chip to our liking.
5602 * Determine the number of SCBs available on the controller
5605 ahd_probe_scbs(struct ahd_softc *ahd) {
5608 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5609 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5610 for (i = 0; i < AHD_SCB_MAX; i++) {
5613 ahd_set_scbptr(ahd, i);
5614 ahd_outw(ahd, SCB_BASE, i);
5615 for (j = 2; j < 64; j++)
5616 ahd_outb(ahd, SCB_BASE+j, 0);
5617 /* Start out life as unallocated (needing an abort) */
5618 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5619 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5621 ahd_set_scbptr(ahd, 0);
5622 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5629 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5633 baddr = (bus_addr_t *)arg;
5634 *baddr = segs->ds_addr;
5638 ahd_initialize_hscbs(struct ahd_softc *ahd)
5642 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5643 ahd_set_scbptr(ahd, i);
5645 /* Clear the control byte. */
5646 ahd_outb(ahd, SCB_CONTROL, 0);
5648 /* Set the next pointer */
5649 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5654 ahd_init_scbdata(struct ahd_softc *ahd)
5656 struct scb_data *scb_data;
5659 scb_data = &ahd->scb_data;
5660 TAILQ_INIT(&scb_data->free_scbs);
5661 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5662 LIST_INIT(&scb_data->free_scb_lists[i]);
5663 LIST_INIT(&scb_data->any_dev_free_scb_list);
5664 SLIST_INIT(&scb_data->hscb_maps);
5665 SLIST_INIT(&scb_data->sg_maps);
5666 SLIST_INIT(&scb_data->sense_maps);
5668 /* Determine the number of hardware SCBs and initialize them */
5669 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5670 if (scb_data->maxhscbs == 0) {
5671 printf("%s: No SCB space found\n", ahd_name(ahd));
5672 AHD_FATAL_ERROR(ahd);
5676 ahd_initialize_hscbs(ahd);
5679 * Create our DMA tags. These tags define the kinds of device
5680 * accessible memory allocations and memory mappings we will
5681 * need to perform during normal operation.
5683 * Unless we need to further restrict the allocation, we rely
5684 * on the restrictions of the parent dmat, hence the common
5685 * use of MAXADDR and MAXSIZE.
5688 /* DMA tag for our hardware scb structures */
5689 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5690 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5691 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5692 /*highaddr*/BUS_SPACE_MAXADDR,
5693 /*filter*/NULL, /*filterarg*/NULL,
5694 PAGE_SIZE, /*nsegments*/1,
5695 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5696 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5700 scb_data->init_level++;
5702 /* DMA tag for our S/G structures. */
5703 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5704 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5705 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5706 /*highaddr*/BUS_SPACE_MAXADDR,
5707 /*filter*/NULL, /*filterarg*/NULL,
5708 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5709 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5710 /*flags*/0, &scb_data->sg_dmat) != 0) {
5714 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5715 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5716 ahd_sglist_allocsize(ahd));
5719 scb_data->init_level++;
5721 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5722 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5723 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5724 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5725 /*highaddr*/BUS_SPACE_MAXADDR,
5726 /*filter*/NULL, /*filterarg*/NULL,
5727 PAGE_SIZE, /*nsegments*/1,
5728 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5729 /*flags*/0, &scb_data->sense_dmat) != 0) {
5733 scb_data->init_level++;
5735 /* Perform initial CCB allocation */
5736 while (ahd_alloc_scbs(ahd) != 0)
5739 if (scb_data->numscbs == 0) {
5740 printf("%s: ahd_init_scbdata - "
5741 "Unable to allocate initial scbs\n",
5747 * Note that we were successful
5757 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5762 * Look on the pending list.
5764 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5765 if (SCB_GET_TAG(scb) == tag)
5770 * Then on all of the collision free lists.
5772 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5773 struct scb *list_scb;
5777 if (SCB_GET_TAG(list_scb) == tag)
5779 list_scb = LIST_NEXT(list_scb, collision_links);
5784 * And finally on the generic free list.
5786 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5787 if (SCB_GET_TAG(scb) == tag)
5795 ahd_fini_scbdata(struct ahd_softc *ahd)
5797 struct scb_data *scb_data;
5799 scb_data = &ahd->scb_data;
5800 if (scb_data == NULL)
5803 switch (scb_data->init_level) {
5807 struct map_node *sns_map;
5809 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5810 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5811 aic_dmamap_unload(ahd, scb_data->sense_dmat,
5813 aic_dmamem_free(ahd, scb_data->sense_dmat,
5814 sns_map->vaddr, sns_map->dmamap);
5815 free(sns_map, M_DEVBUF);
5817 aic_dma_tag_destroy(ahd, scb_data->sense_dmat);
5822 struct map_node *sg_map;
5824 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5825 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5826 aic_dmamap_unload(ahd, scb_data->sg_dmat,
5828 aic_dmamem_free(ahd, scb_data->sg_dmat,
5829 sg_map->vaddr, sg_map->dmamap);
5830 free(sg_map, M_DEVBUF);
5832 aic_dma_tag_destroy(ahd, scb_data->sg_dmat);
5837 struct map_node *hscb_map;
5839 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5840 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5841 aic_dmamap_unload(ahd, scb_data->hscb_dmat,
5843 aic_dmamem_free(ahd, scb_data->hscb_dmat,
5844 hscb_map->vaddr, hscb_map->dmamap);
5845 free(hscb_map, M_DEVBUF);
5847 aic_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5860 * DSP filter Bypass must be enabled until the first selection
5861 * after a change in bus mode (Razor #491 and #493).
5864 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5866 ahd_mode_state saved_modes;
5868 saved_modes = ahd_save_modes(ahd);
5869 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5870 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5871 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5872 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5874 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5875 printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5877 ahd_restore_modes(ahd, saved_modes);
5878 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5882 ahd_iocell_first_selection(struct ahd_softc *ahd)
5884 ahd_mode_state saved_modes;
5887 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5889 saved_modes = ahd_save_modes(ahd);
5890 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5891 sblkctl = ahd_inb(ahd, SBLKCTL);
5892 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5894 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5895 printf("%s: iocell first selection\n", ahd_name(ahd));
5897 if ((sblkctl & ENAB40) != 0) {
5898 ahd_outb(ahd, DSPDATACTL,
5899 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5901 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5902 printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5905 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5906 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5907 ahd_restore_modes(ahd, saved_modes);
5908 ahd->flags |= AHD_HAD_FIRST_SEL;
5911 /*************************** SCB Management ***********************************/
5913 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5915 struct scb_list *free_list;
5916 struct scb_tailq *free_tailq;
5917 struct scb *first_scb;
5919 scb->flags |= SCB_ON_COL_LIST;
5920 AHD_SET_SCB_COL_IDX(scb, col_idx);
5921 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5922 free_tailq = &ahd->scb_data.free_scbs;
5923 first_scb = LIST_FIRST(free_list);
5924 if (first_scb != NULL) {
5925 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5927 LIST_INSERT_HEAD(free_list, scb, collision_links);
5928 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5933 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5935 struct scb_list *free_list;
5936 struct scb_tailq *free_tailq;
5937 struct scb *first_scb;
5940 scb->flags &= ~SCB_ON_COL_LIST;
5941 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5942 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5943 free_tailq = &ahd->scb_data.free_scbs;
5944 first_scb = LIST_FIRST(free_list);
5945 if (first_scb == scb) {
5946 struct scb *next_scb;
5949 * Maintain order in the collision free
5950 * lists for fairness if this device has
5951 * other colliding tags active.
5953 next_scb = LIST_NEXT(scb, collision_links);
5954 if (next_scb != NULL) {
5955 TAILQ_INSERT_AFTER(free_tailq, scb,
5956 next_scb, links.tqe);
5958 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5960 LIST_REMOVE(scb, collision_links);
5964 * Get a free scb. If there are none, see if we can allocate a new SCB.
5967 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5974 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5975 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5976 ahd_rem_col_list(ahd, scb);
5980 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5984 if (ahd_alloc_scbs(ahd) == 0)
5988 LIST_REMOVE(scb, links.le);
5989 if (col_idx != AHD_NEVER_COL_IDX
5990 && (scb->col_scb != NULL)
5991 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5992 LIST_REMOVE(scb->col_scb, links.le);
5993 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5996 scb->flags |= SCB_ACTIVE;
6001 * Return an SCB resource to the free list.
6004 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
6007 /* Clean up for the next user */
6008 scb->flags = SCB_FLAG_NONE;
6009 scb->hscb->control = 0;
6010 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
6012 if (scb->col_scb == NULL) {
6015 * No collision possible. Just free normally.
6017 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6019 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
6022 * The SCB we might have collided with is on
6023 * a free collision list. Put both SCBs on
6026 ahd_rem_col_list(ahd, scb->col_scb);
6027 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6029 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6030 scb->col_scb, links.le);
6031 } else if ((scb->col_scb->flags
6032 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
6033 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
6036 * The SCB we might collide with on the next allocation
6037 * is still active in a non-packetized, tagged, context.
6038 * Put us on the SCB collision list.
6040 ahd_add_col_list(ahd, scb,
6041 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
6044 * The SCB we might collide with on the next allocation
6045 * is either active in a packetized context, or free.
6046 * Since we can't collide, put this SCB on the generic
6049 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
6053 aic_platform_scb_free(ahd, scb);
6057 ahd_alloc_scbs(struct ahd_softc *ahd)
6059 struct scb_data *scb_data;
6060 struct scb *next_scb;
6061 struct hardware_scb *hscb;
6062 struct map_node *hscb_map;
6063 struct map_node *sg_map;
6064 struct map_node *sense_map;
6066 uint8_t *sense_data;
6067 bus_addr_t hscb_busaddr;
6068 bus_addr_t sg_busaddr;
6069 bus_addr_t sense_busaddr;
6073 scb_data = &ahd->scb_data;
6074 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
6075 /* Can't allocate any more */
6078 if (scb_data->scbs_left != 0) {
6081 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
6082 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
6083 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
6084 hscb_busaddr = hscb_map->busaddr + (offset * sizeof(*hscb));
6086 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
6088 if (hscb_map == NULL)
6091 /* Allocate the next batch of hardware SCBs */
6092 if (aic_dmamem_alloc(ahd, scb_data->hscb_dmat,
6093 (void **)&hscb_map->vaddr,
6094 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
6095 &hscb_map->dmamap) != 0) {
6096 free(hscb_map, M_DEVBUF);
6100 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
6102 aic_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
6103 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6104 &hscb_map->busaddr, /*flags*/0);
6106 hscb = (struct hardware_scb *)hscb_map->vaddr;
6107 hscb_busaddr = hscb_map->busaddr;
6108 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6111 if (scb_data->sgs_left != 0) {
6114 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6115 - scb_data->sgs_left) * ahd_sglist_size(ahd);
6116 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6117 segs = sg_map->vaddr + offset;
6118 sg_busaddr = sg_map->busaddr + offset;
6120 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
6125 /* Allocate the next batch of S/G lists */
6126 if (aic_dmamem_alloc(ahd, scb_data->sg_dmat,
6127 (void **)&sg_map->vaddr,
6128 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
6129 &sg_map->dmamap) != 0) {
6130 free(sg_map, M_DEVBUF);
6134 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6136 aic_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6137 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6138 ahd_dmamap_cb, &sg_map->busaddr, /*flags*/0);
6140 segs = sg_map->vaddr;
6141 sg_busaddr = sg_map->busaddr;
6142 scb_data->sgs_left =
6143 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6145 if (ahd_debug & AHD_SHOW_MEMORY)
6146 printf("Mapped SG data\n");
6150 if (scb_data->sense_left != 0) {
6153 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6154 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6155 sense_data = sense_map->vaddr + offset;
6156 sense_busaddr = sense_map->busaddr + offset;
6158 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
6160 if (sense_map == NULL)
6163 /* Allocate the next batch of sense buffers */
6164 if (aic_dmamem_alloc(ahd, scb_data->sense_dmat,
6165 (void **)&sense_map->vaddr,
6166 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6167 free(sense_map, M_DEVBUF);
6171 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6173 aic_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6174 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6175 &sense_map->busaddr, /*flags*/0);
6177 sense_data = sense_map->vaddr;
6178 sense_busaddr = sense_map->busaddr;
6179 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6181 if (ahd_debug & AHD_SHOW_MEMORY)
6182 printf("Mapped sense data\n");
6186 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6187 newcount = MIN(newcount, scb_data->sgs_left);
6188 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6189 scb_data->sense_left -= newcount;
6190 scb_data->scbs_left -= newcount;
6191 scb_data->sgs_left -= newcount;
6192 for (i = 0; i < newcount; i++) {
6193 struct scb_platform_data *pdata;
6199 next_scb = (struct scb *)malloc(sizeof(*next_scb),
6200 M_DEVBUF, M_NOWAIT);
6201 if (next_scb == NULL)
6204 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
6205 M_DEVBUF, M_NOWAIT);
6206 if (pdata == NULL) {
6207 free(next_scb, M_DEVBUF);
6210 next_scb->platform_data = pdata;
6211 next_scb->hscb_map = hscb_map;
6212 next_scb->sg_map = sg_map;
6213 next_scb->sense_map = sense_map;
6214 next_scb->sg_list = segs;
6215 next_scb->sense_data = sense_data;
6216 next_scb->sense_busaddr = sense_busaddr;
6217 memset(hscb, 0, sizeof(*hscb));
6218 next_scb->hscb = hscb;
6219 hscb->hscb_busaddr = aic_htole32(hscb_busaddr);
6222 * The sequencer always starts with the second entry.
6223 * The first entry is embedded in the scb.
6225 next_scb->sg_list_busaddr = sg_busaddr;
6226 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6227 next_scb->sg_list_busaddr
6228 += sizeof(struct ahd_dma64_seg);
6230 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6231 next_scb->ahd_softc = ahd;
6232 next_scb->flags = SCB_FLAG_NONE;
6234 error = aic_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6237 free(next_scb, M_DEVBUF);
6238 free(pdata, M_DEVBUF);
6242 next_scb->hscb->tag = aic_htole16(scb_data->numscbs);
6243 col_tag = scb_data->numscbs ^ 0x100;
6244 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6245 if (next_scb->col_scb != NULL)
6246 next_scb->col_scb->col_scb = next_scb;
6247 aic_timer_init(&next_scb->io_timer);
6248 ahd_free_scb(ahd, next_scb);
6250 hscb_busaddr += sizeof(*hscb);
6251 segs += ahd_sglist_size(ahd);
6252 sg_busaddr += ahd_sglist_size(ahd);
6253 sense_data += AHD_SENSE_BUFSIZE;
6254 sense_busaddr += AHD_SENSE_BUFSIZE;
6255 scb_data->numscbs++;
6261 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6267 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6270 speed = "Ultra320 ";
6271 if ((ahd->features & AHD_WIDE) != 0) {
6276 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6277 speed, type, ahd->channel, ahd->our_id);
6280 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
6281 ahd->scb_data.maxhscbs);
6284 static const char *channel_strings[] = {
6291 static const char *termstat_strings[] = {
6292 "Terminated Correctly",
6299 * Start the board, ready for normal operation
6302 ahd_init(struct ahd_softc *ahd)
6304 uint8_t *next_vaddr;
6305 bus_addr_t next_baddr;
6306 size_t driver_data_size;
6310 uint8_t current_sensing;
6313 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6315 ahd->stack_size = ahd_probe_stack_size(ahd);
6316 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t),
6317 M_DEVBUF, M_NOWAIT);
6318 if (ahd->saved_stack == NULL)
6322 * Verify that the compiler hasn't over-agressively
6323 * padded important structures.
6325 if (sizeof(struct hardware_scb) != 64)
6326 panic("Hardware SCB size is incorrect");
6329 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6330 ahd->flags |= AHD_SEQUENCER_DEBUG;
6334 * Default to allowing initiator operations.
6336 ahd->flags |= AHD_INITIATORROLE;
6339 * Only allow target mode features if this unit has them enabled.
6341 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6342 ahd->features &= ~AHD_TARGETMODE;
6345 /* DMA tag for mapping buffers into device visible space. */
6346 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6347 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6348 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6349 ? (bus_addr_t)0x7FFFFFFFFFULL
6350 : BUS_SPACE_MAXADDR_32BIT,
6351 /*highaddr*/BUS_SPACE_MAXADDR,
6352 /*filter*/NULL, /*filterarg*/NULL,
6353 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6354 /*nsegments*/AHD_NSEG,
6355 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6356 /*flags*/BUS_DMA_ALLOCNOW,
6357 &ahd->buffer_dmat) != 0) {
6365 * DMA tag for our command fifos and other data in system memory
6366 * the card's sequencer must be able to access. For initiator
6367 * roles, we need to allocate space for the qoutfifo. When providing
6368 * for the target mode role, we must additionally provide space for
6369 * the incoming target command fifo.
6371 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6372 + sizeof(struct hardware_scb);
6373 if ((ahd->features & AHD_TARGETMODE) != 0)
6374 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6375 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6376 driver_data_size += PKT_OVERRUN_BUFSIZE;
6377 if (aic_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6378 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6379 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6380 /*highaddr*/BUS_SPACE_MAXADDR,
6381 /*filter*/NULL, /*filterarg*/NULL,
6384 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6385 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6391 /* Allocation of driver data */
6392 if (aic_dmamem_alloc(ahd, ahd->shared_data_dmat,
6393 (void **)&ahd->shared_data_map.vaddr,
6394 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
6395 &ahd->shared_data_map.dmamap) != 0) {
6401 /* And permanently map it in */
6402 aic_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6403 ahd->shared_data_map.vaddr, driver_data_size,
6404 ahd_dmamap_cb, &ahd->shared_data_map.busaddr,
6406 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6407 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6408 next_baddr = ahd->shared_data_map.busaddr
6409 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6410 if ((ahd->features & AHD_TARGETMODE) != 0) {
6411 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6412 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6413 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6416 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6417 ahd->overrun_buf = next_vaddr;
6418 next_vaddr += PKT_OVERRUN_BUFSIZE;
6419 next_baddr += PKT_OVERRUN_BUFSIZE;
6423 * We need one SCB to serve as the "next SCB". Since the
6424 * tag identifier in this SCB will never be used, there is
6425 * no point in using a valid HSCB tag from an SCB pulled from
6426 * the standard free pool. So, we allocate this "sentinel"
6427 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6429 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6430 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6431 ahd->next_queued_hscb->hscb_busaddr = aic_htole32(next_baddr);
6435 /* Allocate SCB data now that buffer_dmat is initialized */
6436 if (ahd_init_scbdata(ahd) != 0)
6439 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6440 ahd->flags &= ~AHD_RESET_BUS_A;
6443 * Before committing these settings to the chip, give
6444 * the OSM one last chance to modify our configuration.
6446 ahd_platform_init(ahd);
6448 /* Bring up the chip. */
6451 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6453 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6457 * Verify termination based on current draw and
6458 * warn user if the bus is over/under terminated.
6460 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6463 printf("%s: current sensing timeout 1\n", ahd_name(ahd));
6466 for (i = 20, fstat = FLX_FSTAT_BUSY;
6467 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6468 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6470 printf("%s: current sensing timeout 2\n",
6476 printf("%s: Timedout during current-sensing test\n",
6481 /* Latch Current Sensing status. */
6482 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing);
6484 printf("%s: current sensing timeout 3\n", ahd_name(ahd));
6488 /* Diable current sensing. */
6489 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6492 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6493 printf("%s: current_sensing == 0x%x\n",
6494 ahd_name(ahd), current_sensing);
6498 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6501 term_stat = (current_sensing & FLX_CSTAT_MASK);
6502 switch (term_stat) {
6503 case FLX_CSTAT_OVER:
6504 case FLX_CSTAT_UNDER:
6506 case FLX_CSTAT_INVALID:
6507 case FLX_CSTAT_OKAY:
6508 if (warn_user == 0 && bootverbose == 0)
6510 printf("%s: %s Channel %s\n", ahd_name(ahd),
6511 channel_strings[i], termstat_strings[term_stat]);
6516 printf("%s: WARNING. Termination is not configured correctly.\n"
6517 "%s: WARNING. SCSI bus operations may FAIL.\n",
6518 ahd_name(ahd), ahd_name(ahd));
6519 AHD_CORRECTABLE_ERROR(ahd);
6523 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
6524 ahd_stat_timer, ahd);
6529 * (Re)initialize chip state after a chip reset.
6532 ahd_chip_init(struct ahd_softc *ahd)
6536 u_int scsiseq_template;
6541 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6543 * Take the LED out of diagnostic mode
6545 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6548 * Return HS_MAILBOX to its default value.
6550 ahd->hs_mailbox = 0;
6551 ahd_outb(ahd, HS_MAILBOX, 0);
6553 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6554 ahd_outb(ahd, IOWNID, ahd->our_id);
6555 ahd_outb(ahd, TOWNID, ahd->our_id);
6556 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6557 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6558 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6559 && (ahd->seltime != STIMESEL_MIN)) {
6561 * The selection timer duration is twice as long
6562 * as it should be. Halve it by adding "1" to
6563 * the user specified setting.
6565 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6567 sxfrctl1 |= ahd->seltime;
6570 ahd_outb(ahd, SXFRCTL0, DFON);
6571 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6572 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6575 * Now that termination is set, wait for up
6576 * to 500ms for our transceivers to settle. If
6577 * the adapter does not have a cable attached,
6578 * the transceivers may never settle, so don't
6579 * complain if we fail here.
6582 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6586 /* Clear any false bus resets due to the transceivers settling */
6587 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6588 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6590 /* Initialize mode specific S/G state. */
6591 for (i = 0; i < 2; i++) {
6592 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6593 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6594 ahd_outb(ahd, SG_STATE, 0);
6595 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6596 ahd_outb(ahd, SEQIMODE,
6597 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6598 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6601 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6602 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6603 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6604 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6605 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6606 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6607 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6609 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6611 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6612 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6614 * Do not issue a target abort when a split completion
6615 * error occurs. Let our PCIX interrupt handler deal
6616 * with it instead. H2A4 Razor #625
6618 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6620 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6621 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6624 * Tweak IOCELL settings.
6626 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6627 for (i = 0; i < NUMDSPS; i++) {
6628 ahd_outb(ahd, DSPSELECT, i);
6629 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6632 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6633 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6634 WRTBIASCTL_HP_DEFAULT);
6637 ahd_setup_iocell_workaround(ahd);
6640 * Enable LQI Manager interrupts.
6642 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6643 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6644 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6645 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6647 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6648 * manually for the command phase at the start of a packetized
6649 * selection case. ENLQOBUSFREE should be made redundant by
6650 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6651 * events fail to assert the BUSFREE interrupt so we must
6652 * also enable LQOBUSFREE interrupts.
6654 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6657 * Setup sequencer interrupt handlers.
6659 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6660 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6663 * Setup SCB Offset registers.
6665 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6666 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6669 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6671 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6672 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6673 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6674 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6675 shared_data.idata.cdb));
6676 ahd_outb(ahd, QNEXTPTR,
6677 offsetof(struct hardware_scb, next_hscb_busaddr));
6678 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6679 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6680 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6681 ahd_outb(ahd, LUNLEN,
6682 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6684 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6686 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6687 ahd_outb(ahd, MAXCMD, 0xFF);
6688 ahd_outb(ahd, SCBAUTOPTR,
6689 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6691 /* We haven't been enabled for target mode yet. */
6692 ahd_outb(ahd, MULTARGID, 0);
6693 ahd_outb(ahd, MULTARGID + 1, 0);
6695 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6696 /* Initialize the negotiation table. */
6697 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6699 * Clear the spare bytes in the neg table to avoid
6700 * spurious parity errors.
6702 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6703 ahd_outb(ahd, NEGOADDR, target);
6704 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6705 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6706 ahd_outb(ahd, ANNEXDAT, 0);
6709 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6710 struct ahd_devinfo devinfo;
6711 struct ahd_initiator_tinfo *tinfo;
6712 struct ahd_tmode_tstate *tstate;
6714 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6716 ahd_compile_devinfo(&devinfo, ahd->our_id,
6717 target, CAM_LUN_WILDCARD,
6718 'A', ROLE_INITIATOR);
6719 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6722 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6723 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6725 #ifdef NEEDS_MORE_TESTING
6727 * Always enable abort on incoming L_Qs if this feature is
6728 * supported. We use this to catch invalid SCB references.
6730 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6731 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6734 ahd_outb(ahd, LQCTL1, 0);
6736 /* All of our queues are empty */
6737 ahd->qoutfifonext = 0;
6738 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6739 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6740 for (i = 0; i < AHD_QOUT_SIZE; i++)
6741 ahd->qoutfifo[i].valid_tag = 0;
6742 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6744 ahd->qinfifonext = 0;
6745 for (i = 0; i < AHD_QIN_SIZE; i++)
6746 ahd->qinfifo[i] = SCB_LIST_NULL;
6748 if ((ahd->features & AHD_TARGETMODE) != 0) {
6749 /* All target command blocks start out invalid. */
6750 for (i = 0; i < AHD_TMODE_CMDS; i++)
6751 ahd->targetcmds[i].cmd_valid = 0;
6752 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6753 ahd->tqinfifonext = 1;
6754 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6755 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6758 /* Initialize Scratch Ram. */
6759 ahd_outb(ahd, SEQ_FLAGS, 0);
6760 ahd_outb(ahd, SEQ_FLAGS2, 0);
6762 /* We don't have any waiting selections */
6763 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6764 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6765 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6766 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6767 for (i = 0; i < AHD_NUM_TARGETS; i++)
6768 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6771 * Nobody is waiting to be DMAed into the QOUTFIFO.
6773 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6774 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6775 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6776 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6777 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6780 * The Freeze Count is 0.
6782 ahd->qfreeze_cnt = 0;
6783 ahd_outw(ahd, QFREEZE_COUNT, 0);
6784 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6787 * Tell the sequencer where it can find our arrays in memory.
6789 busaddr = ahd->shared_data_map.busaddr;
6790 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6791 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6794 * Setup the allowed SCSI Sequences based on operational mode.
6795 * If we are a target, we'll enable select in operations once
6796 * we've had a lun enabled.
6798 scsiseq_template = ENAUTOATNP;
6799 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6800 scsiseq_template |= ENRSELI;
6801 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6803 /* There are no busy SCBs yet. */
6804 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6807 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6808 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6812 * Initialize the group code to command length table.
6813 * Vendor Unique codes are set to 0 so we only capture
6814 * the first byte of the cdb. These can be overridden
6815 * when target mode is enabled.
6817 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6818 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6819 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6820 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6821 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6822 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6823 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6824 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6826 /* Tell the sequencer of our initial queue positions */
6827 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6828 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6829 ahd->qinfifonext = 0;
6830 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6831 ahd_set_hescb_qoff(ahd, 0);
6832 ahd_set_snscb_qoff(ahd, 0);
6833 ahd_set_sescb_qoff(ahd, 0);
6834 ahd_set_sdscb_qoff(ahd, 0);
6837 * Tell the sequencer which SCB will be the next one it receives.
6839 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6840 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6843 * Default to coalescing disabled.
6845 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6846 ahd_outw(ahd, CMDS_PENDING, 0);
6847 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6848 ahd->int_coalescing_maxcmds,
6849 ahd->int_coalescing_mincmds);
6850 ahd_enable_coalescing(ahd, FALSE);
6853 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6857 * Setup default device and controller settings.
6858 * This should only be called if our probe has
6859 * determined that no configuration data is available.
6862 ahd_default_config(struct ahd_softc *ahd)
6869 * Allocate a tstate to house information for our
6870 * initiator presence on the bus as well as the user
6871 * data for any target mode initiator.
6873 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6874 printf("%s: unable to allocate ahd_tmode_tstate. "
6875 "Failing attach\n", ahd_name(ahd));
6876 AHD_FATAL_ERROR(ahd);
6880 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6881 struct ahd_devinfo devinfo;
6882 struct ahd_initiator_tinfo *tinfo;
6883 struct ahd_tmode_tstate *tstate;
6884 uint16_t target_mask;
6886 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6889 * We support SPC2 and SPI4.
6891 tinfo->user.protocol_version = 4;
6892 tinfo->user.transport_version = 4;
6894 target_mask = 0x01 << targ;
6895 ahd->user_discenable |= target_mask;
6896 tstate->discenable |= target_mask;
6897 ahd->user_tagenable |= target_mask;
6898 #ifdef AHD_FORCE_160
6899 tinfo->user.period = AHD_SYNCRATE_DT;
6901 tinfo->user.period = AHD_SYNCRATE_160;
6903 tinfo->user.offset = MAX_OFFSET;
6904 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6905 | MSG_EXT_PPR_WR_FLOW
6906 | MSG_EXT_PPR_HOLD_MCS
6907 | MSG_EXT_PPR_IU_REQ
6908 | MSG_EXT_PPR_QAS_REQ
6909 | MSG_EXT_PPR_DT_REQ;
6910 if ((ahd->features & AHD_RTI) != 0)
6911 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6913 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6916 * Start out Async/Narrow/Untagged and with
6917 * conservative protocol support.
6919 tinfo->goal.protocol_version = 2;
6920 tinfo->goal.transport_version = 2;
6921 tinfo->curr.protocol_version = 2;
6922 tinfo->curr.transport_version = 2;
6923 ahd_compile_devinfo(&devinfo, ahd->our_id,
6924 targ, CAM_LUN_WILDCARD,
6925 'A', ROLE_INITIATOR);
6926 tstate->tagenable &= ~target_mask;
6927 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6928 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6929 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6930 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6937 * Parse device configuration information.
6940 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6945 max_targ = sc->max_targets & CFMAXTARG;
6946 ahd->our_id = sc->brtime_id & CFSCSIID;
6949 * Allocate a tstate to house information for our
6950 * initiator presence on the bus as well as the user
6951 * data for any target mode initiator.
6953 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6954 printf("%s: unable to allocate ahd_tmode_tstate. "
6955 "Failing attach\n", ahd_name(ahd));
6956 AHD_FATAL_ERROR(ahd);
6960 for (targ = 0; targ < max_targ; targ++) {
6961 struct ahd_devinfo devinfo;
6962 struct ahd_initiator_tinfo *tinfo;
6963 struct ahd_transinfo *user_tinfo;
6964 struct ahd_tmode_tstate *tstate;
6965 uint16_t target_mask;
6967 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6969 user_tinfo = &tinfo->user;
6972 * We support SPC2 and SPI4.
6974 tinfo->user.protocol_version = 4;
6975 tinfo->user.transport_version = 4;
6977 target_mask = 0x01 << targ;
6978 ahd->user_discenable &= ~target_mask;
6979 tstate->discenable &= ~target_mask;
6980 ahd->user_tagenable &= ~target_mask;
6981 if (sc->device_flags[targ] & CFDISC) {
6982 tstate->discenable |= target_mask;
6983 ahd->user_discenable |= target_mask;
6984 ahd->user_tagenable |= target_mask;
6987 * Cannot be packetized without disconnection.
6989 sc->device_flags[targ] &= ~CFPACKETIZED;
6992 user_tinfo->ppr_options = 0;
6993 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6994 if (user_tinfo->period < CFXFER_ASYNC) {
6995 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6996 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6997 user_tinfo->offset = MAX_OFFSET;
6999 user_tinfo->offset = 0;
7000 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
7002 #ifdef AHD_FORCE_160
7003 if (user_tinfo->period <= AHD_SYNCRATE_160)
7004 user_tinfo->period = AHD_SYNCRATE_DT;
7007 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
7008 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
7009 | MSG_EXT_PPR_WR_FLOW
7010 | MSG_EXT_PPR_HOLD_MCS
7011 | MSG_EXT_PPR_IU_REQ;
7012 if ((ahd->features & AHD_RTI) != 0)
7013 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
7016 if ((sc->device_flags[targ] & CFQAS) != 0)
7017 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
7019 if ((sc->device_flags[targ] & CFWIDEB) != 0)
7020 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
7022 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
7024 if ((ahd_debug & AHD_SHOW_MISC) != 0)
7025 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
7026 user_tinfo->period, user_tinfo->offset,
7027 user_tinfo->ppr_options);
7030 * Start out Async/Narrow/Untagged and with
7031 * conservative protocol support.
7033 tstate->tagenable &= ~target_mask;
7034 tinfo->goal.protocol_version = 2;
7035 tinfo->goal.transport_version = 2;
7036 tinfo->curr.protocol_version = 2;
7037 tinfo->curr.transport_version = 2;
7038 ahd_compile_devinfo(&devinfo, ahd->our_id,
7039 targ, CAM_LUN_WILDCARD,
7040 'A', ROLE_INITIATOR);
7041 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7042 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
7043 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
7044 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
7048 ahd->flags &= ~AHD_SPCHK_ENB_A;
7049 if (sc->bios_control & CFSPARITY)
7050 ahd->flags |= AHD_SPCHK_ENB_A;
7052 ahd->flags &= ~AHD_RESET_BUS_A;
7053 if (sc->bios_control & CFRESETB)
7054 ahd->flags |= AHD_RESET_BUS_A;
7056 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
7057 if (sc->bios_control & CFEXTEND)
7058 ahd->flags |= AHD_EXTENDED_TRANS_A;
7060 ahd->flags &= ~AHD_BIOS_ENABLED;
7061 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
7062 ahd->flags |= AHD_BIOS_ENABLED;
7064 ahd->flags &= ~AHD_STPWLEVEL_A;
7065 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
7066 ahd->flags |= AHD_STPWLEVEL_A;
7072 * Parse device configuration information.
7075 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
7079 error = ahd_verify_vpd_cksum(vpd);
7082 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
7083 ahd->flags |= AHD_BOOT_CHANNEL;
7088 ahd_intr_enable(struct ahd_softc *ahd, int enable)
7092 hcntrl = ahd_inb(ahd, HCNTRL);
7094 ahd->pause &= ~INTEN;
7095 ahd->unpause &= ~INTEN;
7098 ahd->pause |= INTEN;
7099 ahd->unpause |= INTEN;
7101 ahd_outb(ahd, HCNTRL, hcntrl);
7105 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
7108 if (timer > AHD_TIMER_MAX_US)
7109 timer = AHD_TIMER_MAX_US;
7110 ahd->int_coalescing_timer = timer;
7112 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7113 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7114 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7115 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7116 ahd->int_coalescing_maxcmds = maxcmds;
7117 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7118 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7119 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7123 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7126 ahd->hs_mailbox &= ~ENINT_COALESCE;
7128 ahd->hs_mailbox |= ENINT_COALESCE;
7129 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7130 ahd_flush_device_writes(ahd);
7131 ahd_run_qoutfifo(ahd);
7135 * Ensure that the card is paused in a location
7136 * outside of all critical sections and that all
7137 * pending work is completed prior to returning.
7138 * This routine should only be called from outside
7139 * an interrupt context.
7142 ahd_pause_and_flushwork(struct ahd_softc *ahd)
7148 ahd->flags |= AHD_ALL_INTERRUPTS;
7151 * Freeze the outgoing selections. We do this only
7152 * until we are safely paused without further selections
7156 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7157 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
7162 * Give the sequencer some time to service
7163 * any active selections.
7169 intstat = ahd_inb(ahd, INTSTAT);
7170 if ((intstat & INT_PEND) == 0) {
7171 ahd_clear_critical_section(ahd);
7172 intstat = ahd_inb(ahd, INTSTAT);
7175 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7176 && ((intstat & INT_PEND) != 0
7177 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7178 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7180 if (maxloops == 0) {
7181 printf("Infinite interrupt loop, INTSTAT = %x",
7182 ahd_inb(ahd, INTSTAT));
7183 AHD_FATAL_ERROR(ahd);
7186 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7188 ahd_flush_qoutfifo(ahd);
7190 ahd_platform_flushwork(ahd);
7191 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7195 ahd_suspend(struct ahd_softc *ahd)
7198 ahd_pause_and_flushwork(ahd);
7200 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7209 ahd_resume(struct ahd_softc *ahd)
7212 ahd_reset(ahd, /*reinit*/TRUE);
7213 ahd_intr_enable(ahd, TRUE);
7218 /************************** Busy Target Table *********************************/
7220 * Set SCBPTR to the SCB that contains the busy
7221 * table entry for TCL. Return the offset into
7222 * the SCB that contains the entry for TCL.
7223 * saved_scbid is dereferenced and set to the
7224 * scbid that should be restored once manipualtion
7225 * of the TCL entry is complete.
7227 static __inline u_int
7228 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7231 * Index to the SCB that contains the busy entry.
7233 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7234 *saved_scbid = ahd_get_scbptr(ahd);
7235 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7236 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7239 * And now calculate the SCB offset to the entry.
7240 * Each entry is 2 bytes wide, hence the
7241 * multiplication by 2.
7243 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7247 * Return the untagged transaction id for a given target/channel lun.
7250 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7256 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7257 scbid = ahd_inw_scbram(ahd, scb_offset);
7258 ahd_set_scbptr(ahd, saved_scbptr);
7263 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7268 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7269 ahd_outw(ahd, scb_offset, scbid);
7270 ahd_set_scbptr(ahd, saved_scbptr);
7273 /************************** SCB and SCB queue management **********************/
7275 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7276 char channel, int lun, u_int tag, role_t role)
7278 int targ = SCB_GET_TARGET(ahd, scb);
7279 char chan = SCB_GET_CHANNEL(ahd, scb);
7280 int slun = SCB_GET_LUN(scb);
7283 match = ((chan == channel) || (channel == ALL_CHANNELS));
7285 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7287 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7289 #ifdef AHD_TARGET_MODE
7292 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7293 if (role == ROLE_INITIATOR) {
7294 match = (group != XPT_FC_GROUP_TMODE)
7295 && ((tag == SCB_GET_TAG(scb))
7296 || (tag == SCB_LIST_NULL));
7297 } else if (role == ROLE_TARGET) {
7298 match = (group == XPT_FC_GROUP_TMODE)
7299 && ((tag == scb->io_ctx->csio.tag_id)
7300 || (tag == SCB_LIST_NULL));
7302 #else /* !AHD_TARGET_MODE */
7303 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7304 #endif /* AHD_TARGET_MODE */
7311 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7317 target = SCB_GET_TARGET(ahd, scb);
7318 lun = SCB_GET_LUN(scb);
7319 channel = SCB_GET_CHANNEL(ahd, scb);
7321 ahd_search_qinfifo(ahd, target, channel, lun,
7322 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7323 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7325 ahd_platform_freeze_devq(ahd, scb);
7329 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7331 struct scb *prev_scb;
7332 ahd_mode_state saved_modes;
7334 saved_modes = ahd_save_modes(ahd);
7335 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7337 if (ahd_qinfifo_count(ahd) != 0) {
7341 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7342 prev_tag = ahd->qinfifo[prev_pos];
7343 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7345 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7346 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7347 ahd_restore_modes(ahd, saved_modes);
7351 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7354 if (prev_scb == NULL) {
7357 busaddr = aic_le32toh(scb->hscb->hscb_busaddr);
7358 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7360 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7361 ahd_sync_scb(ahd, prev_scb,
7362 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7364 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7366 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7367 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7371 ahd_qinfifo_count(struct ahd_softc *ahd)
7375 u_int wrap_qinfifonext;
7377 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7378 qinpos = ahd_get_snscb_qoff(ahd);
7379 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7380 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7381 if (wrap_qinfifonext >= wrap_qinpos)
7382 return (wrap_qinfifonext - wrap_qinpos);
7384 return (wrap_qinfifonext
7385 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7389 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7392 ahd_mode_state saved_modes;
7395 saved_modes = ahd_save_modes(ahd);
7396 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7399 * Don't count any commands as outstanding that the
7400 * sequencer has already marked for completion.
7402 ahd_flush_qoutfifo(ahd);
7405 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7408 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7409 ahd_restore_modes(ahd, saved_modes);
7410 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7414 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7419 ostat = aic_get_transaction_status(scb);
7420 if (ostat == CAM_REQ_INPROG)
7421 aic_set_transaction_status(scb, status);
7422 cstat = aic_get_transaction_status(scb);
7423 if (cstat != CAM_REQ_CMP)
7424 aic_freeze_scb(scb);
7429 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7430 int lun, u_int tag, role_t role, uint32_t status,
7431 ahd_search_action action)
7434 struct scb *mk_msg_scb;
7435 struct scb *prev_scb;
7436 ahd_mode_state saved_modes;
7449 /* Must be in CCHAN mode */
7450 saved_modes = ahd_save_modes(ahd);
7451 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7454 * Halt any pending SCB DMA. The sequencer will reinitiate
7455 * this dma if the qinfifo is not empty once we unpause.
7457 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7458 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7459 ahd_outb(ahd, CCSCBCTL,
7460 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7461 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7464 /* Determine sequencer's position in the qinfifo. */
7465 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7466 qinstart = ahd_get_snscb_qoff(ahd);
7467 qinpos = AHD_QIN_WRAP(qinstart);
7471 if (action == SEARCH_PRINT) {
7472 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7473 qinstart, ahd->qinfifonext);
7477 * Start with an empty queue. Entries that are not chosen
7478 * for removal will be re-added to the queue as we go.
7480 ahd->qinfifonext = qinstart;
7481 busaddr = aic_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7482 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7484 while (qinpos != qintail) {
7485 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7487 printf("qinpos = %d, SCB index = %d\n",
7488 qinpos, ahd->qinfifo[qinpos]);
7489 AHD_FATAL_ERROR(ahd);
7493 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7495 * We found an scb that needs to be acted on.
7499 case SEARCH_COMPLETE:
7500 if ((scb->flags & SCB_ACTIVE) == 0)
7501 printf("Inactive SCB in qinfifo\n");
7502 ahd_done_with_status(ahd, scb, status);
7507 printf(" 0x%x", ahd->qinfifo[qinpos]);
7510 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7515 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7518 qinpos = AHD_QIN_WRAP(qinpos+1);
7521 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7523 if (action == SEARCH_PRINT)
7524 printf("\nWAITING_TID_QUEUES:\n");
7527 * Search waiting for selection lists. We traverse the
7528 * list of "their ids" waiting for selection and, if
7529 * appropriate, traverse the SCBs of each "their id"
7530 * looking for matches.
7532 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7533 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7534 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7535 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7536 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7539 savedscbptr = ahd_get_scbptr(ahd);
7540 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7541 tid_prev = SCB_LIST_NULL;
7543 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7548 if (targets > AHD_NUM_TARGETS)
7549 panic("TID LIST LOOP");
7551 if (scbid >= ahd->scb_data.numscbs) {
7552 printf("%s: Waiting TID List inconsistency. "
7553 "SCB index == 0x%x, yet numscbs == 0x%x.",
7554 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7555 ahd_dump_card_state(ahd);
7556 panic("for safety");
7558 scb = ahd_lookup_scb(ahd, scbid);
7560 printf("%s: SCB = 0x%x Not Active!\n",
7561 ahd_name(ahd), scbid);
7562 panic("Waiting TID List traversal\n");
7564 ahd_set_scbptr(ahd, scbid);
7565 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7566 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7567 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7573 * We found a list of scbs that needs to be searched.
7575 if (action == SEARCH_PRINT)
7576 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7578 found += ahd_search_scb_list(ahd, target, channel,
7579 lun, tag, role, status,
7580 action, &tid_head, &tid_tail,
7581 SCB_GET_TARGET(ahd, scb));
7583 * Check any MK_MESSAGE SCB that is still waiting to
7584 * enter this target's waiting for selection queue.
7586 if (mk_msg_scb != NULL
7587 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7591 * We found an scb that needs to be acted on.
7595 case SEARCH_COMPLETE:
7596 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7597 printf("Inactive SCB pending MK_MSG\n");
7598 ahd_done_with_status(ahd, mk_msg_scb, status);
7604 printf("Removing MK_MSG scb\n");
7607 * Reset our tail to the tail of the
7608 * main per-target list.
7610 tail_offset = WAITING_SCB_TAILS
7611 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7612 ahd_outw(ahd, tail_offset, tid_tail);
7614 seq_flags2 &= ~PENDING_MK_MESSAGE;
7615 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7616 ahd_outw(ahd, CMDS_PENDING,
7617 ahd_inw(ahd, CMDS_PENDING)-1);
7622 printf(" 0x%x", SCB_GET_TAG(scb));
7629 if (mk_msg_scb != NULL
7630 && SCBID_IS_NULL(tid_head)
7631 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7632 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7635 * When removing the last SCB for a target
7636 * queue with a pending MK_MESSAGE scb, we
7637 * must queue the MK_MESSAGE scb.
7639 printf("Queueing mk_msg_scb\n");
7640 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7641 seq_flags2 &= ~PENDING_MK_MESSAGE;
7642 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7645 if (tid_head != scbid)
7646 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7647 if (!SCBID_IS_NULL(tid_head))
7648 tid_prev = tid_head;
7649 if (action == SEARCH_PRINT)
7653 /* Restore saved state. */
7654 ahd_set_scbptr(ahd, savedscbptr);
7655 ahd_restore_modes(ahd, saved_modes);
7660 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7661 int lun, u_int tag, role_t role, uint32_t status,
7662 ahd_search_action action, u_int *list_head,
7663 u_int *list_tail, u_int tid)
7671 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7673 prev = SCB_LIST_NULL;
7675 *list_tail = SCB_LIST_NULL;
7676 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7677 if (scbid >= ahd->scb_data.numscbs) {
7678 printf("%s:SCB List inconsistency. "
7679 "SCB == 0x%x, yet numscbs == 0x%x.",
7680 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7681 ahd_dump_card_state(ahd);
7682 panic("for safety");
7684 scb = ahd_lookup_scb(ahd, scbid);
7686 printf("%s: SCB = %d Not Active!\n",
7687 ahd_name(ahd), scbid);
7688 panic("Waiting List traversal\n");
7690 ahd_set_scbptr(ahd, scbid);
7692 next = ahd_inw_scbram(ahd, SCB_NEXT);
7693 if (ahd_match_scb(ahd, scb, target, channel,
7694 lun, SCB_LIST_NULL, role) == 0) {
7700 case SEARCH_COMPLETE:
7701 if ((scb->flags & SCB_ACTIVE) == 0)
7702 printf("Inactive SCB in Waiting List\n");
7703 ahd_done_with_status(ahd, scb, status);
7706 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7708 if (SCBID_IS_NULL(prev))
7712 printf("0x%x ", scbid);
7717 if (found > AHD_SCB_MAX)
7718 panic("SCB LIST LOOP");
7720 if (action == SEARCH_COMPLETE
7721 || action == SEARCH_REMOVE)
7722 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7727 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7728 u_int tid_cur, u_int tid_next)
7730 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7732 if (SCBID_IS_NULL(tid_cur)) {
7734 /* Bypass current TID list */
7735 if (SCBID_IS_NULL(tid_prev)) {
7736 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7738 ahd_set_scbptr(ahd, tid_prev);
7739 ahd_outw(ahd, SCB_NEXT2, tid_next);
7741 if (SCBID_IS_NULL(tid_next))
7742 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7745 /* Stitch through tid_cur */
7746 if (SCBID_IS_NULL(tid_prev)) {
7747 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7749 ahd_set_scbptr(ahd, tid_prev);
7750 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7752 ahd_set_scbptr(ahd, tid_cur);
7753 ahd_outw(ahd, SCB_NEXT2, tid_next);
7755 if (SCBID_IS_NULL(tid_next))
7756 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7761 * Manipulate the waiting for selection list and return the
7762 * scb that follows the one that we remove.
7765 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7766 u_int prev, u_int next, u_int tid)
7770 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7771 if (!SCBID_IS_NULL(prev)) {
7772 ahd_set_scbptr(ahd, prev);
7773 ahd_outw(ahd, SCB_NEXT, next);
7777 * SCBs that have MK_MESSAGE set in them may
7778 * cause the tail pointer to be updated without
7779 * setting the next pointer of the previous tail.
7780 * Only clear the tail if the removed SCB was
7783 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7784 if (SCBID_IS_NULL(next)
7785 && ahd_inw(ahd, tail_offset) == scbid)
7786 ahd_outw(ahd, tail_offset, prev);
7788 ahd_add_scb_to_free_list(ahd, scbid);
7793 * Add the SCB as selected by SCBPTR onto the on chip list of
7794 * free hardware SCBs. This list is empty/unused if we are not
7795 * performing SCB paging.
7798 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7800 /* XXX Need some other mechanism to designate "free". */
7802 * Invalidate the tag so that our abort
7803 * routines don't think it's active.
7804 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7808 /******************************** Error Handling ******************************/
7810 * Abort all SCBs that match the given description (target/channel/lun/tag),
7811 * setting their status to the passed in status if the status has not already
7812 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7813 * is paused before it is called.
7816 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7817 int lun, u_int tag, role_t role, uint32_t status)
7820 struct scb *scbp_next;
7826 ahd_mode_state saved_modes;
7828 /* restore this when we're done */
7829 saved_modes = ahd_save_modes(ahd);
7830 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7832 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7833 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7836 * Clean out the busy target table for any untagged commands.
7840 if (target != CAM_TARGET_WILDCARD) {
7847 if (lun == CAM_LUN_WILDCARD) {
7849 maxlun = AHD_NUM_LUNS_NONPKT;
7850 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7851 minlun = maxlun = 0;
7857 if (role != ROLE_TARGET) {
7858 for (;i < maxtarget; i++) {
7859 for (j = minlun;j < maxlun; j++) {
7863 tcl = BUILD_TCL_RAW(i, 'A', j);
7864 scbid = ahd_find_busy_tcl(ahd, tcl);
7865 scbp = ahd_lookup_scb(ahd, scbid);
7867 || ahd_match_scb(ahd, scbp, target, channel,
7868 lun, tag, role) == 0)
7870 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7876 * Don't abort commands that have already completed,
7877 * but haven't quite made it up to the host yet.
7879 ahd_flush_qoutfifo(ahd);
7882 * Go through the pending CCB list and look for
7883 * commands for this target that are still active.
7884 * These are other tagged commands that were
7885 * disconnected when the reset occurred.
7887 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7888 while (scbp_next != NULL) {
7890 scbp_next = LIST_NEXT(scbp, pending_links);
7891 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7894 ostat = aic_get_transaction_status(scbp);
7895 if (ostat == CAM_REQ_INPROG)
7896 aic_set_transaction_status(scbp, status);
7897 if (aic_get_transaction_status(scbp) != CAM_REQ_CMP)
7898 aic_freeze_scb(scbp);
7899 if ((scbp->flags & SCB_ACTIVE) == 0)
7900 printf("Inactive SCB on pending list\n");
7901 ahd_done(ahd, scbp);
7905 ahd_restore_modes(ahd, saved_modes);
7906 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7907 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7912 ahd_reset_current_bus(struct ahd_softc *ahd)
7916 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7917 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7918 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7919 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7920 ahd_flush_device_writes(ahd);
7921 aic_delay(AHD_BUSRESET_DELAY);
7922 /* Turn off the bus reset */
7923 ahd_outb(ahd, SCSISEQ0, scsiseq);
7924 ahd_flush_device_writes(ahd);
7925 aic_delay(AHD_BUSRESET_DELAY);
7926 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7929 * Certain chip state is not cleared for
7930 * SCSI bus resets that we initiate, so
7931 * we must reset the chip.
7933 ahd_reset(ahd, /*reinit*/TRUE);
7934 ahd_intr_enable(ahd, /*enable*/TRUE);
7935 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7938 ahd_clear_intstat(ahd);
7942 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7944 struct ahd_devinfo devinfo;
7952 ahd->pending_device = NULL;
7954 ahd_compile_devinfo(&devinfo,
7955 CAM_TARGET_WILDCARD,
7956 CAM_TARGET_WILDCARD,
7958 channel, ROLE_UNKNOWN);
7961 /* Make sure the sequencer is in a safe location. */
7962 ahd_clear_critical_section(ahd);
7964 #ifdef AHD_TARGET_MODE
7965 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7966 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7969 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7972 * Disable selections so no automatic hardware
7973 * functions will modify chip state.
7975 ahd_outb(ahd, SCSISEQ0, 0);
7976 ahd_outb(ahd, SCSISEQ1, 0);
7979 * Safely shut down our DMA engines. Always start with
7980 * the FIFO that is not currently active (if any are
7981 * actively connected).
7983 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7984 if (next_fifo > CURRFIFO_1)
7985 /* If disconneced, arbitrarily start with FIFO1. */
7986 next_fifo = fifo = 0;
7988 next_fifo ^= CURRFIFO_1;
7989 ahd_set_modes(ahd, next_fifo, next_fifo);
7990 ahd_outb(ahd, DFCNTRL,
7991 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7992 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7995 * Set CURRFIFO to the now inactive channel.
7997 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7998 ahd_outb(ahd, DFFSTAT, next_fifo);
7999 } while (next_fifo != fifo);
8002 * Reset the bus if we are initiating this reset
8004 ahd_clear_msg_state(ahd);
8005 ahd_outb(ahd, SIMODE1,
8006 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
8009 ahd_reset_current_bus(ahd);
8011 ahd_clear_intstat(ahd);
8014 * Clean up all the state information for the
8015 * pending transactions on this bus.
8017 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
8018 CAM_LUN_WILDCARD, SCB_LIST_NULL,
8019 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
8022 * Cleanup anything left in the FIFOs.
8024 ahd_clear_fifo(ahd, 0);
8025 ahd_clear_fifo(ahd, 1);
8028 * Revert to async/narrow transfers until we renegotiate.
8030 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
8031 for (target = 0; target <= max_scsiid; target++) {
8033 if (ahd->enabled_targets[target] == NULL)
8035 for (initiator = 0; initiator <= max_scsiid; initiator++) {
8036 struct ahd_devinfo devinfo;
8038 ahd_compile_devinfo(&devinfo, target, initiator,
8041 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
8042 AHD_TRANS_CUR, /*paused*/TRUE);
8043 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
8044 /*offset*/0, /*ppr_options*/0,
8045 AHD_TRANS_CUR, /*paused*/TRUE);
8049 #ifdef AHD_TARGET_MODE
8050 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
8053 * Send an immediate notify ccb to all target more peripheral
8054 * drivers affected by this action.
8056 for (target = 0; target <= max_scsiid; target++) {
8057 struct ahd_tmode_tstate* tstate;
8060 tstate = ahd->enabled_targets[target];
8063 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
8064 struct ahd_tmode_lstate* lstate;
8066 lstate = tstate->enabled_luns[lun];
8070 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
8071 EVENT_TYPE_BUS_RESET, /*arg*/0);
8072 ahd_send_lstate_events(ahd, lstate);
8076 /* Notify the XPT that a bus reset occurred */
8077 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
8078 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
8081 * Freeze the SIMQ until our poller can determine that
8082 * the bus reset has really gone away. We set the initial
8083 * timer to 0 to have the check performed as soon as possible
8084 * from the timer context.
8086 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
8087 ahd->flags |= AHD_RESET_POLL_ACTIVE;
8088 aic_freeze_simq(ahd);
8089 aic_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
8095 #define AHD_RESET_POLL_MS 1
8097 ahd_reset_poll(void *arg)
8099 struct ahd_softc *ahd = (struct ahd_softc *)arg;
8104 ahd_update_modes(ahd);
8105 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8106 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
8107 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
8108 aic_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_MS,
8109 ahd_reset_poll, ahd);
8115 /* Reset is now low. Complete chip reinitialization. */
8116 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8117 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8118 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8120 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8121 aic_release_simq(ahd);
8125 /**************************** Statistics Processing ***************************/
8127 ahd_stat_timer(void *arg)
8129 struct ahd_softc *ahd = (struct ahd_softc *)arg;
8133 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8134 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8135 enint_coal |= ENINT_COALESCE;
8136 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8137 enint_coal &= ~ENINT_COALESCE;
8139 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8140 ahd_enable_coalescing(ahd, enint_coal);
8142 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8143 printf("%s: Interrupt coalescing "
8144 "now %sabled. Cmds %d\n",
8146 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8147 ahd->cmdcmplt_total);
8151 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8152 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8153 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8154 aic_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_MS,
8155 ahd_stat_timer, ahd);
8159 /****************************** Status Processing *****************************/
8161 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8163 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8164 ahd_handle_scsi_status(ahd, scb);
8166 ahd_calc_residual(ahd, scb);
8172 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8174 struct hardware_scb *hscb;
8178 * The sequencer freezes its select-out queue
8179 * anytime a SCSI status error occurs. We must
8180 * handle the error and increment our qfreeze count
8181 * to allow the sequencer to continue. We don't
8182 * bother clearing critical sections here since all
8183 * operations are on data structures that the sequencer
8184 * is not touching once the queue is frozen.
8188 if (ahd_is_paused(ahd)) {
8195 /* Freeze the queue until the client sees the error. */
8196 ahd_freeze_devq(ahd, scb);
8197 aic_freeze_scb(scb);
8199 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8204 /* Don't want to clobber the original sense code */
8205 if ((scb->flags & SCB_SENSE) != 0) {
8207 * Clear the SCB_SENSE Flag and perform
8208 * a normal command completion.
8210 scb->flags &= ~SCB_SENSE;
8211 aic_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8215 aic_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8216 aic_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8217 switch (hscb->shared_data.istatus.scsi_status) {
8218 case STATUS_PKT_SENSE:
8220 struct scsi_status_iu_header *siu;
8222 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8223 siu = (struct scsi_status_iu_header *)scb->sense_data;
8224 aic_set_scsi_status(scb, siu->status);
8226 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8227 ahd_print_path(ahd, scb);
8228 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8229 SCB_GET_TAG(scb), siu->status);
8230 printf("\tflags = 0x%x, sense len = 0x%x, "
8232 siu->flags, scsi_4btoul(siu->sense_length),
8233 scsi_4btoul(siu->pkt_failures_length));
8236 if ((siu->flags & SIU_RSPVALID) != 0) {
8237 ahd_print_path(ahd, scb);
8238 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8239 printf("Unable to parse pkt_failures\n");
8242 switch (SIU_PKTFAIL_CODE(siu)) {
8244 printf("No packet failure found\n");
8245 AHD_UNCORRECTABLE_ERROR(ahd);
8247 case SIU_PFC_CIU_FIELDS_INVALID:
8248 printf("Invalid Command IU Field\n");
8249 AHD_UNCORRECTABLE_ERROR(ahd);
8251 case SIU_PFC_TMF_NOT_SUPPORTED:
8252 printf("TMF not supportd\n");
8253 AHD_UNCORRECTABLE_ERROR(ahd);
8255 case SIU_PFC_TMF_FAILED:
8256 printf("TMF failed\n");
8257 AHD_UNCORRECTABLE_ERROR(ahd);
8259 case SIU_PFC_INVALID_TYPE_CODE:
8260 printf("Invalid L_Q Type code\n");
8261 AHD_UNCORRECTABLE_ERROR(ahd);
8263 case SIU_PFC_ILLEGAL_REQUEST:
8264 AHD_UNCORRECTABLE_ERROR(ahd);
8265 printf("Illegal request\n");
8270 if (siu->status == SCSI_STATUS_OK)
8271 aic_set_transaction_status(scb,
8274 if ((siu->flags & SIU_SNSVALID) != 0) {
8275 scb->flags |= SCB_PKT_SENSE;
8277 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8278 printf("Sense data available\n");
8284 case SCSI_STATUS_CMD_TERMINATED:
8285 case SCSI_STATUS_CHECK_COND:
8287 struct ahd_devinfo devinfo;
8288 struct ahd_dma_seg *sg;
8289 struct scsi_sense *sc;
8290 struct ahd_initiator_tinfo *targ_info;
8291 struct ahd_tmode_tstate *tstate;
8292 struct ahd_transinfo *tinfo;
8294 if (ahd_debug & AHD_SHOW_SENSE) {
8295 ahd_print_path(ahd, scb);
8296 printf("SCB %d: requests Check Status\n",
8301 if (aic_perform_autosense(scb) == 0)
8304 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8305 SCB_GET_TARGET(ahd, scb),
8307 SCB_GET_CHANNEL(ahd, scb),
8309 targ_info = ahd_fetch_transinfo(ahd,
8314 tinfo = &targ_info->curr;
8316 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8318 * Save off the residual if there is one.
8320 ahd_update_residual(ahd, scb);
8322 if (ahd_debug & AHD_SHOW_SENSE) {
8323 ahd_print_path(ahd, scb);
8324 printf("Sending Sense\n");
8328 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8329 aic_get_sense_bufsize(ahd, scb),
8331 sc->opcode = REQUEST_SENSE;
8333 if (tinfo->protocol_version <= SCSI_REV_2
8334 && SCB_GET_LUN(scb) < 8)
8335 sc->byte2 = SCB_GET_LUN(scb) << 5;
8338 sc->length = aic_get_sense_bufsize(ahd, scb);
8342 * We can't allow the target to disconnect.
8343 * This will be an untagged transaction and
8344 * having the target disconnect will make this
8345 * transaction indestinguishable from outstanding
8346 * tagged transactions.
8351 * This request sense could be because the
8352 * the device lost power or in some other
8353 * way has lost our transfer negotiations.
8354 * Renegotiate if appropriate. Unit attention
8355 * errors will be reported before any data
8358 if (aic_get_residual(scb) == aic_get_transfer_length(scb)) {
8359 ahd_update_neg_request(ahd, &devinfo,
8361 AHD_NEG_IF_NON_ASYNC);
8363 if (tstate->auto_negotiate & devinfo.target_mask) {
8364 hscb->control |= MK_MESSAGE;
8366 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8367 scb->flags |= SCB_AUTO_NEGOTIATE;
8369 hscb->cdb_len = sizeof(*sc);
8370 ahd_setup_data_scb(ahd, scb);
8371 scb->flags |= SCB_SENSE;
8372 ahd_queue_scb(ahd, scb);
8374 * Ensure we have enough time to actually
8375 * retrieve the sense, but only schedule
8376 * the timer if we are not in recovery or
8377 * this is a recovery SCB that is allowed
8378 * to have an active timer.
8380 if (ahd->scb_data.recovery_scbs == 0
8381 || (scb->flags & SCB_RECOVERY_SCB) != 0)
8382 aic_scb_timer_reset(scb, 5 * 1000);
8385 case SCSI_STATUS_OK:
8386 printf("%s: Interrupted for staus of 0???\n",
8396 * Calculate the residual for a just completed SCB.
8399 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8401 struct hardware_scb *hscb;
8402 struct initiator_status *spkt;
8404 uint32_t resid_sgptr;
8410 * SG_STATUS_VALID clear in sgptr.
8411 * 2) Transferless command
8412 * 3) Never performed any transfers.
8413 * sgptr has SG_FULL_RESID set.
8414 * 4) No residual but target did not
8415 * save data pointers after the
8416 * last transfer, so sgptr was
8418 * 5) We have a partial residual.
8419 * Use residual_sgptr to determine
8424 sgptr = aic_le32toh(hscb->sgptr);
8425 if ((sgptr & SG_STATUS_VALID) == 0)
8428 sgptr &= ~SG_STATUS_VALID;
8430 if ((sgptr & SG_LIST_NULL) != 0)
8435 * Residual fields are the same in both
8436 * target and initiator status packets,
8437 * so we can always use the initiator fields
8438 * regardless of the role for this SCB.
8440 spkt = &hscb->shared_data.istatus;
8441 resid_sgptr = aic_le32toh(spkt->residual_sgptr);
8442 if ((sgptr & SG_FULL_RESID) != 0) {
8444 resid = aic_get_transfer_length(scb);
8445 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8448 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8449 ahd_print_path(ahd, scb);
8450 printf("data overrun detected Tag == 0x%x.\n",
8452 ahd_freeze_devq(ahd, scb);
8453 aic_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8454 aic_freeze_scb(scb);
8456 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8457 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8460 struct ahd_dma_seg *sg;
8463 * Remainder of the SG where the transfer
8466 resid = aic_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8467 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8469 /* The residual sg_ptr always points to the next sg */
8473 * Add up the contents of all residual
8474 * SG segments that are after the SG where
8475 * the transfer stopped.
8477 while ((aic_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8479 resid += aic_le32toh(sg->len) & AHD_SG_LEN_MASK;
8482 if ((scb->flags & SCB_SENSE) == 0)
8483 aic_set_residual(scb, resid);
8485 aic_set_sense_residual(scb, resid);
8488 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8489 ahd_print_path(ahd, scb);
8490 printf("Handled %sResidual of %d bytes\n",
8491 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8496 /******************************* Target Mode **********************************/
8497 #ifdef AHD_TARGET_MODE
8499 * Add a target mode event to this lun's queue
8502 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8503 u_int initiator_id, u_int event_type, u_int event_arg)
8505 struct ahd_tmode_event *event;
8508 xpt_freeze_devq(lstate->path, /*count*/1);
8509 if (lstate->event_w_idx >= lstate->event_r_idx)
8510 pending = lstate->event_w_idx - lstate->event_r_idx;
8512 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8513 - (lstate->event_r_idx - lstate->event_w_idx);
8515 if (event_type == EVENT_TYPE_BUS_RESET
8516 || event_type == MSG_BUS_DEV_RESET) {
8518 * Any earlier events are irrelevant, so reset our buffer.
8519 * This has the effect of allowing us to deal with reset
8520 * floods (an external device holding down the reset line)
8521 * without losing the event that is really interesting.
8523 lstate->event_r_idx = 0;
8524 lstate->event_w_idx = 0;
8525 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8528 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8529 xpt_print_path(lstate->path);
8530 printf("immediate event %x:%x lost\n",
8531 lstate->event_buffer[lstate->event_r_idx].event_type,
8532 lstate->event_buffer[lstate->event_r_idx].event_arg);
8533 lstate->event_r_idx++;
8534 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8535 lstate->event_r_idx = 0;
8536 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8539 event = &lstate->event_buffer[lstate->event_w_idx];
8540 event->initiator_id = initiator_id;
8541 event->event_type = event_type;
8542 event->event_arg = event_arg;
8543 lstate->event_w_idx++;
8544 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8545 lstate->event_w_idx = 0;
8549 * Send any target mode events queued up waiting
8550 * for immediate notify resources.
8553 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8555 struct ccb_hdr *ccbh;
8556 struct ccb_immediate_notify *inot;
8558 while (lstate->event_r_idx != lstate->event_w_idx
8559 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8560 struct ahd_tmode_event *event;
8562 event = &lstate->event_buffer[lstate->event_r_idx];
8563 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8564 inot = (struct ccb_immediate_notify *)ccbh;
8565 switch (event->event_type) {
8566 case EVENT_TYPE_BUS_RESET:
8567 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8570 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8571 inot->arg = event->event_type;
8572 inot->seq_id = event->event_arg;
8575 inot->initiator_id = event->initiator_id;
8576 xpt_done((union ccb *)inot);
8577 lstate->event_r_idx++;
8578 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8579 lstate->event_r_idx = 0;
8584 /******************** Sequencer Program Patching/Download *********************/
8588 ahd_dumpseq(struct ahd_softc* ahd)
8595 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8596 ahd_outw(ahd, PRGMCNT, 0);
8597 for (i = 0; i < max_prog; i++) {
8598 uint8_t ins_bytes[4];
8600 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8601 printf("0x%08x\n", ins_bytes[0] << 24
8602 | ins_bytes[1] << 16
8610 ahd_loadseq(struct ahd_softc *ahd)
8612 struct cs cs_table[num_critical_sections];
8613 u_int begin_set[num_critical_sections];
8614 u_int end_set[num_critical_sections];
8615 struct patch *cur_patch;
8621 u_int sg_prefetch_cnt;
8622 u_int sg_prefetch_cnt_limit;
8623 u_int sg_prefetch_align;
8625 u_int cacheline_mask;
8626 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8629 printf("%s: Downloading Sequencer Program...",
8632 #if DOWNLOAD_CONST_COUNT != 8
8633 #error "Download Const Mismatch"
8636 * Start out with 0 critical sections
8637 * that apply to this firmware load.
8641 memset(begin_set, 0, sizeof(begin_set));
8642 memset(end_set, 0, sizeof(end_set));
8645 * Setup downloadable constant table.
8647 * The computation for the S/G prefetch variables is
8648 * a bit complicated. We would like to always fetch
8649 * in terms of cachelined sized increments. However,
8650 * if the cacheline is not an even multiple of the
8651 * SG element size or is larger than our SG RAM, using
8652 * just the cache size might leave us with only a portion
8653 * of an SG element at the tail of a prefetch. If the
8654 * cacheline is larger than our S/G prefetch buffer less
8655 * the size of an SG element, we may round down to a cacheline
8656 * that doesn't contain any or all of the S/G of interest
8657 * within the bounds of our S/G ram. Provide variables to
8658 * the sequencer that will allow it to handle these edge
8661 /* Start by aligning to the nearest cacheline. */
8662 sg_prefetch_align = ahd->pci_cachesize;
8663 if (sg_prefetch_align == 0)
8664 sg_prefetch_align = 8;
8665 /* Round down to the nearest power of 2. */
8666 while (powerof2(sg_prefetch_align) == 0)
8667 sg_prefetch_align--;
8669 cacheline_mask = sg_prefetch_align - 1;
8672 * If the cacheline boundary is greater than half our prefetch RAM
8673 * we risk not being able to fetch even a single complete S/G
8674 * segment if we align to that boundary.
8676 if (sg_prefetch_align > CCSGADDR_MAX/2)
8677 sg_prefetch_align = CCSGADDR_MAX/2;
8678 /* Start by fetching a single cacheline. */
8679 sg_prefetch_cnt = sg_prefetch_align;
8681 * Increment the prefetch count by cachelines until
8682 * at least one S/G element will fit.
8684 sg_size = sizeof(struct ahd_dma_seg);
8685 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8686 sg_size = sizeof(struct ahd_dma64_seg);
8687 while (sg_prefetch_cnt < sg_size)
8688 sg_prefetch_cnt += sg_prefetch_align;
8690 * If the cacheline is not an even multiple of
8691 * the S/G size, we may only get a partial S/G when
8692 * we align. Add a cacheline if this is the case.
8694 if ((sg_prefetch_align % sg_size) != 0
8695 && (sg_prefetch_cnt < CCSGADDR_MAX))
8696 sg_prefetch_cnt += sg_prefetch_align;
8698 * Lastly, compute a value that the sequencer can use
8699 * to determine if the remainder of the CCSGRAM buffer
8700 * has a full S/G element in it.
8702 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8703 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8704 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8705 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8706 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8707 download_consts[SG_SIZEOF] = sg_size;
8708 download_consts[PKT_OVERRUN_BUFOFFSET] =
8709 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8710 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8711 download_consts[CACHELINE_MASK] = cacheline_mask;
8712 cur_patch = patches;
8715 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8716 ahd_outw(ahd, PRGMCNT, 0);
8718 for (i = 0; i < sizeof(seqprog)/4; i++) {
8719 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8721 * Don't download this instruction as it
8722 * is in a patch that was removed.
8727 * Move through the CS table until we find a CS
8728 * that might apply to this instruction.
8730 for (; cur_cs < num_critical_sections; cur_cs++) {
8731 if (critical_sections[cur_cs].end <= i) {
8732 if (begin_set[cs_count] == TRUE
8733 && end_set[cs_count] == FALSE) {
8734 cs_table[cs_count].end = downloaded;
8735 end_set[cs_count] = TRUE;
8740 if (critical_sections[cur_cs].begin <= i
8741 && begin_set[cs_count] == FALSE) {
8742 cs_table[cs_count].begin = downloaded;
8743 begin_set[cs_count] = TRUE;
8747 ahd_download_instr(ahd, i, download_consts);
8751 ahd->num_critical_sections = cs_count;
8752 if (cs_count != 0) {
8754 cs_count *= sizeof(struct cs);
8755 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
8756 if (ahd->critical_sections == NULL)
8757 panic("ahd_loadseq: Could not malloc");
8758 memcpy(ahd->critical_sections, cs_table, cs_count);
8760 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8763 printf(" %d instructions downloaded\n", downloaded);
8764 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8765 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8770 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8771 u_int start_instr, u_int *skip_addr)
8773 struct patch *cur_patch;
8774 struct patch *last_patch;
8777 num_patches = sizeof(patches)/sizeof(struct patch);
8778 last_patch = &patches[num_patches];
8779 cur_patch = *start_patch;
8781 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8783 if (cur_patch->patch_func(ahd) == 0) {
8785 /* Start rejecting code */
8786 *skip_addr = start_instr + cur_patch->skip_instr;
8787 cur_patch += cur_patch->skip_patch;
8789 /* Accepted this patch. Advance to the next
8790 * one and wait for our instruction pointer to
8797 *start_patch = cur_patch;
8798 if (start_instr < *skip_addr)
8799 /* Still skipping */
8806 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8808 struct patch *cur_patch;
8814 cur_patch = patches;
8817 for (i = 0; i < address;) {
8819 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8821 if (skip_addr > i) {
8824 end_addr = MIN(address, skip_addr);
8825 address_offset += end_addr - i;
8831 return (address - address_offset);
8835 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8837 union ins_formats instr;
8838 struct ins_format1 *fmt1_ins;
8839 struct ins_format3 *fmt3_ins;
8843 * The firmware is always compiled into a little endian format.
8845 instr.integer = aic_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8847 fmt1_ins = &instr.format1;
8850 /* Pull the opcode */
8851 opcode = instr.format1.opcode;
8862 fmt3_ins = &instr.format3;
8863 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8872 if (fmt1_ins->parity != 0) {
8873 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8875 fmt1_ins->parity = 0;
8881 /* Calculate odd parity for the instruction */
8882 for (i = 0, count = 0; i < 31; i++) {
8886 if ((instr.integer & mask) != 0)
8889 if ((count & 0x01) == 0)
8890 instr.format1.parity = 1;
8892 /* The sequencer is a little endian cpu */
8893 instr.integer = aic_htole32(instr.integer);
8894 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8898 panic("Unknown opcode encountered in seq program");
8904 ahd_probe_stack_size(struct ahd_softc *ahd)
8913 * We avoid using 0 as a pattern to avoid
8914 * confusion if the stack implementation
8915 * "back-fills" with zeros when "poping'
8918 for (i = 1; i <= last_probe+1; i++) {
8919 ahd_outb(ahd, STACK, i & 0xFF);
8920 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8924 for (i = last_probe+1; i > 0; i--) {
8927 stack_entry = ahd_inb(ahd, STACK)
8928 |(ahd_inb(ahd, STACK) << 8);
8929 if (stack_entry != i)
8935 return (last_probe);
8939 ahd_dump_all_cards_state(void)
8941 struct ahd_softc *list_ahd;
8943 TAILQ_FOREACH(list_ahd, &ahd_tailq, links) {
8944 ahd_dump_card_state(list_ahd);
8949 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8950 const char *name, u_int address, u_int value,
8951 u_int *cur_column, u_int wrap_point)
8957 if (cur_column == NULL) {
8959 cur_column = &dummy_column;
8962 if (cur_column != NULL && *cur_column >= wrap_point) {
8966 printed = printf("%s[0x%x]", name, value);
8967 if (table == NULL) {
8968 printed += printf(" ");
8969 *cur_column += printed;
8973 while (printed_mask != 0xFF) {
8976 for (entry = 0; entry < num_entries; entry++) {
8977 if (((value & table[entry].mask)
8978 != table[entry].value)
8979 || ((printed_mask & table[entry].mask)
8980 == table[entry].mask))
8983 printed += printf("%s%s",
8984 printed_mask == 0 ? ":(" : "|",
8986 printed_mask |= table[entry].mask;
8990 if (entry >= num_entries)
8993 if (printed_mask != 0)
8994 printed += printf(") ");
8996 printed += printf(" ");
8997 *cur_column += printed;
9002 ahd_dump_card_state(struct ahd_softc *ahd)
9005 ahd_mode_state saved_modes;
9009 u_int saved_scb_index;
9013 if (ahd_is_paused(ahd)) {
9019 saved_modes = ahd_save_modes(ahd);
9020 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9021 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
9022 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
9024 ahd_inw(ahd, CURADDR),
9025 ahd_build_mode_state(ahd, ahd->saved_src_mode,
9026 ahd->saved_dst_mode));
9028 printf("Card was paused\n");
9030 if (ahd_check_cmdcmpltqueues(ahd))
9031 printf("Completions are pending\n");
9034 * Mode independent registers.
9037 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
9038 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
9039 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
9040 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
9041 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
9042 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
9043 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
9044 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
9045 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
9046 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
9047 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
9048 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
9049 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
9050 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
9051 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
9052 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
9053 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
9054 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
9055 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
9056 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
9058 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
9059 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
9061 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
9062 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
9063 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
9064 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
9065 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
9066 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
9067 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
9068 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
9069 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
9070 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
9071 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
9072 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
9074 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
9075 "CURRSCB 0x%x NEXTSCB 0x%x\n",
9076 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
9077 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
9078 ahd_inw(ahd, NEXTSCB));
9081 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
9082 CAM_LUN_WILDCARD, SCB_LIST_NULL,
9083 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
9084 saved_scb_index = ahd_get_scbptr(ahd);
9085 printf("Pending list:");
9087 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9088 if (i++ > AHD_SCB_MAX)
9090 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
9091 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
9092 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9093 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
9095 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
9098 printf("\nTotal %d\n", i);
9100 printf("Kernel Free SCB lists: ");
9102 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
9103 struct scb *list_scb;
9105 printf("\n COLIDX[%d]: ", AHD_GET_SCB_COL_IDX(ahd, scb));
9108 printf("%d ", SCB_GET_TAG(list_scb));
9109 list_scb = LIST_NEXT(list_scb, collision_links);
9110 } while (list_scb && i++ < AHD_SCB_MAX);
9113 printf("\n Any Device: ");
9114 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
9115 if (i++ > AHD_SCB_MAX)
9117 printf("%d ", SCB_GET_TAG(scb));
9121 printf("Sequencer Complete DMA-inprog list: ");
9122 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
9124 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9125 ahd_set_scbptr(ahd, scb_index);
9126 printf("%d ", scb_index);
9127 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9131 printf("Sequencer Complete list: ");
9132 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
9134 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9135 ahd_set_scbptr(ahd, scb_index);
9136 printf("%d ", scb_index);
9137 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9142 printf("Sequencer DMA-Up and Complete list: ");
9143 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9145 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9146 ahd_set_scbptr(ahd, scb_index);
9147 printf("%d ", scb_index);
9148 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9151 printf("Sequencer On QFreeze and Complete list: ");
9152 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9154 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9155 ahd_set_scbptr(ahd, scb_index);
9156 printf("%d ", scb_index);
9157 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9160 ahd_set_scbptr(ahd, saved_scb_index);
9161 dffstat = ahd_inb(ahd, DFFSTAT);
9162 for (i = 0; i < 2; i++) {
9164 struct scb *fifo_scb;
9168 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9169 fifo_scbptr = ahd_get_scbptr(ahd);
9170 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9172 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9173 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9175 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9176 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9177 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9178 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9179 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9181 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9182 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9183 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9184 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9189 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9190 ahd_inl(ahd, SHADDR+4),
9191 ahd_inl(ahd, SHADDR),
9192 (ahd_inb(ahd, SHCNT)
9193 | (ahd_inb(ahd, SHCNT + 1) << 8)
9194 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9199 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9200 ahd_inl(ahd, HADDR+4),
9201 ahd_inl(ahd, HADDR),
9203 | (ahd_inb(ahd, HCNT + 1) << 8)
9204 | (ahd_inb(ahd, HCNT + 2) << 16)));
9205 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9207 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9208 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9209 if (fifo_scb != NULL)
9210 ahd_dump_sglist(fifo_scb);
9215 for (i = 0; i < 20; i++)
9216 printf("0x%x ", ahd_inb(ahd, LQIN + i));
9218 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9219 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9220 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9221 ahd_inb(ahd, OPTIONMODE));
9222 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9223 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9224 ahd_inb(ahd, MAXCMDCNT));
9225 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9226 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9227 ahd_inb(ahd, SAVED_LUN));
9228 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9230 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9232 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9234 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9235 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9236 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9237 ahd_inw(ahd, DINDEX));
9238 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9239 ahd_name(ahd), ahd_get_scbptr(ahd),
9240 ahd_inw_scbram(ahd, SCB_NEXT),
9241 ahd_inw_scbram(ahd, SCB_NEXT2));
9242 printf("CDB %x %x %x %x %x %x\n",
9243 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9244 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9245 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9246 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9247 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9248 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
9250 for (i = 0; i < ahd->stack_size; i++) {
9251 ahd->saved_stack[i] =
9252 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9253 printf(" 0x%x", ahd->saved_stack[i]);
9255 for (i = ahd->stack_size-1; i >= 0; i--) {
9256 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9257 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9259 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9260 ahd_platform_dump_card_state(ahd);
9261 ahd_restore_modes(ahd, saved_modes);
9267 ahd_dump_scbs(struct ahd_softc *ahd)
9269 ahd_mode_state saved_modes;
9270 u_int saved_scb_index;
9273 saved_modes = ahd_save_modes(ahd);
9274 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9275 saved_scb_index = ahd_get_scbptr(ahd);
9276 for (i = 0; i < AHD_SCB_MAX; i++) {
9277 ahd_set_scbptr(ahd, i);
9279 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9280 ahd_inb_scbram(ahd, SCB_CONTROL),
9281 ahd_inb_scbram(ahd, SCB_SCSIID),
9282 ahd_inw_scbram(ahd, SCB_NEXT),
9283 ahd_inw_scbram(ahd, SCB_NEXT2),
9284 ahd_inl_scbram(ahd, SCB_SGPTR),
9285 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9288 ahd_set_scbptr(ahd, saved_scb_index);
9289 ahd_restore_modes(ahd, saved_modes);
9293 /*************************** Timeout Handling *********************************/
9295 ahd_timeout(struct scb *scb)
9297 struct ahd_softc *ahd;
9299 ahd = scb->ahd_softc;
9300 if ((scb->flags & SCB_ACTIVE) != 0) {
9301 if ((scb->flags & SCB_TIMEDOUT) == 0) {
9302 LIST_INSERT_HEAD(&ahd->timedout_scbs, scb,
9304 scb->flags |= SCB_TIMEDOUT;
9306 ahd_wakeup_recovery_thread(ahd);
9311 * ahd_recover_commands determines if any of the commands that have currently
9312 * timedout are the root cause for this timeout. Innocent commands are given
9313 * a new timeout while we wait for the command executing on the bus to timeout.
9314 * This routine is invoked from a thread context so we are allowed to sleep.
9315 * Our lock is not held on entry.
9318 ahd_recover_commands(struct ahd_softc *ahd)
9321 struct scb *active_scb;
9324 u_int active_scbptr;
9328 * Pause the controller and manually flush any
9329 * commands that have just completed but that our
9330 * interrupt handler has yet to see.
9332 was_paused = ahd_is_paused(ahd);
9334 printf("%s: Recovery Initiated - Card was %spaused\n", ahd_name(ahd),
9335 was_paused ? "" : "not ");
9336 AHD_CORRECTABLE_ERROR(ahd);
9337 ahd_dump_card_state(ahd);
9339 ahd_pause_and_flushwork(ahd);
9341 if (LIST_EMPTY(&ahd->timedout_scbs) != 0) {
9343 * The timedout commands have already
9344 * completed. This typically means
9345 * that either the timeout value was on
9346 * the hairy edge of what the device
9347 * requires or - more likely - interrupts
9348 * are not happening.
9350 printf("%s: Timedout SCBs already complete. "
9351 "Interrupts may not be functioning.\n", ahd_name(ahd));
9357 * Determine identity of SCB acting on the bus.
9358 * This test only catches non-packetized transactions.
9359 * Due to the fleeting nature of packetized operations,
9360 * we can't easily determine that a packetized operation
9363 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9364 last_phase = ahd_inb(ahd, LASTPHASE);
9365 active_scbptr = ahd_get_scbptr(ahd);
9367 if (last_phase != P_BUSFREE
9368 || (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) == 0)
9369 active_scb = ahd_lookup_scb(ahd, active_scbptr);
9371 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9376 target = SCB_GET_TARGET(ahd, scb);
9377 channel = SCB_GET_CHANNEL(ahd, scb);
9378 lun = SCB_GET_LUN(scb);
9380 ahd_print_path(ahd, scb);
9381 printf("SCB %d - timed out\n", SCB_GET_TAG(scb));
9383 if (scb->flags & (SCB_DEVICE_RESET|SCB_ABORT)) {
9385 * Been down this road before.
9386 * Do a full bus reset.
9388 aic_set_transaction_status(scb, CAM_CMD_TIMEOUT);
9390 found = ahd_reset_channel(ahd, channel,
9391 /*Initiate Reset*/TRUE);
9392 printf("%s: Issued Channel %c Bus Reset. "
9393 "%d SCBs aborted\n", ahd_name(ahd), channel,
9399 * Remove the command from the timedout list in
9400 * preparation for requeing it.
9402 LIST_REMOVE(scb, timedout_links);
9403 scb->flags &= ~SCB_TIMEDOUT;
9405 if (active_scb != NULL) {
9407 if (active_scb != scb) {
9410 * If the active SCB is not us, assume that
9411 * the active SCB has a longer timeout than
9412 * the timedout SCB, and wait for the active
9413 * SCB to timeout. As a safeguard, only
9414 * allow this deferral to continue if some
9415 * untimed-out command is outstanding.
9417 if (ahd_other_scb_timeout(ahd, scb,
9424 * We're active on the bus, so assert ATN
9425 * and hope that the target responds.
9427 ahd_set_recoveryscb(ahd, active_scb);
9428 active_scb->flags |= SCB_RECOVERY_SCB|SCB_DEVICE_RESET;
9429 ahd_outb(ahd, MSG_OUT, HOST_MSG);
9430 ahd_outb(ahd, SCSISIGO, last_phase|ATNO);
9431 ahd_print_path(ahd, active_scb);
9432 printf("BDR message in message buffer\n");
9433 aic_scb_timer_reset(scb, 2 * 1000);
9435 } else if (last_phase != P_BUSFREE
9436 && ahd_inb(ahd, SCSIPHASE) == 0) {
9438 * SCB is not identified, there
9439 * is no pending REQ, and the sequencer
9440 * has not seen a busfree. Looks like
9441 * a stuck connection waiting to
9442 * go busfree. Reset the bus.
9444 printf("%s: Connection stuck awaiting busfree or "
9445 "Identify Msg.\n", ahd_name(ahd));
9447 } else if (ahd_search_qinfifo(ahd, target, channel, lun,
9449 ROLE_INITIATOR, /*status*/0,
9450 SEARCH_COUNT) > 0) {
9453 * We haven't even gone out on the bus
9454 * yet, so the timeout must be due to
9455 * some other command. Reset the timer
9458 if (ahd_other_scb_timeout(ahd, scb, NULL) == 0)
9462 * This SCB is for a disconnected transaction
9463 * and we haven't found a better candidate on
9464 * the bus to explain this timeout.
9466 ahd_set_recoveryscb(ahd, scb);
9469 * Actually re-queue this SCB in an attempt
9470 * to select the device before it reconnects.
9471 * In either case (selection or reselection),
9472 * we will now issue a target reset to the
9475 scb->flags |= SCB_DEVICE_RESET;
9476 scb->hscb->cdb_len = 0;
9477 scb->hscb->task_attribute = 0;
9478 scb->hscb->task_management = SIU_TASKMGMT_ABORT_TASK;
9480 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
9481 if ((scb->flags & SCB_PACKETIZED) != 0) {
9483 * Mark the SCB has having an outstanding
9484 * task management function. Should the command
9485 * complete normally before the task management
9486 * function can be sent, the host will be
9487 * notified to abort our requeued SCB.
9489 ahd_outb(ahd, SCB_TASK_MANAGEMENT,
9490 scb->hscb->task_management);
9493 * If non-packetized, set the MK_MESSAGE control
9494 * bit indicating that we desire to send a
9495 * message. We also set the disconnected flag
9496 * since there is no guarantee that our SCB
9497 * control byte matches the version on the
9498 * card. We don't want the sequencer to abort
9499 * the command thinking an unsolicited
9500 * reselection occurred.
9502 scb->hscb->control |= MK_MESSAGE|DISCONNECTED;
9505 * The sequencer will never re-reference the
9506 * in-core SCB. To make sure we are notified
9507 * during reslection, set the MK_MESSAGE flag in
9508 * the card's copy of the SCB.
9510 ahd_outb(ahd, SCB_CONTROL,
9511 ahd_inb(ahd, SCB_CONTROL)|MK_MESSAGE);
9515 * Clear out any entries in the QINFIFO first
9516 * so we are the next SCB for this target
9519 ahd_search_qinfifo(ahd, target, channel, lun,
9520 SCB_LIST_NULL, ROLE_INITIATOR,
9521 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
9522 ahd_qinfifo_requeue_tail(ahd, scb);
9523 ahd_set_scbptr(ahd, active_scbptr);
9524 ahd_print_path(ahd, scb);
9525 printf("Queuing a BDR SCB\n");
9526 aic_scb_timer_reset(scb, 2 * 1000);
9532 * Any remaining SCBs were not the "culprit", so remove
9533 * them from the timeout list. The timer for these commands
9534 * will be reset once the recovery SCB completes.
9536 while ((scb = LIST_FIRST(&ahd->timedout_scbs)) != NULL) {
9538 LIST_REMOVE(scb, timedout_links);
9539 scb->flags &= ~SCB_TIMEDOUT;
9546 * Re-schedule a timeout for the passed in SCB if we determine that some
9547 * other SCB is in the process of recovery or an SCB with a longer
9548 * timeout is still pending. Limit our search to just "other_scb"
9549 * if it is non-NULL.
9552 ahd_other_scb_timeout(struct ahd_softc *ahd, struct scb *scb,
9553 struct scb *other_scb)
9558 ahd_print_path(ahd, scb);
9559 printf("Other SCB Timeout%s",
9560 (scb->flags & SCB_OTHERTCL_TIMEOUT) != 0
9561 ? " again\n" : "\n");
9563 AHD_UNCORRECTABLE_ERROR(ahd);
9564 newtimeout = aic_get_timeout(scb);
9565 scb->flags |= SCB_OTHERTCL_TIMEOUT;
9567 if (other_scb != NULL) {
9568 if ((other_scb->flags
9569 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9570 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9572 newtimeout = MAX(aic_get_timeout(other_scb),
9576 LIST_FOREACH(other_scb, &ahd->pending_scbs, pending_links) {
9577 if ((other_scb->flags
9578 & (SCB_OTHERTCL_TIMEOUT|SCB_TIMEDOUT)) == 0
9579 || (other_scb->flags & SCB_RECOVERY_SCB) != 0) {
9581 newtimeout = MAX(aic_get_timeout(other_scb),
9588 aic_scb_timer_reset(scb, newtimeout);
9590 ahd_print_path(ahd, scb);
9591 printf("No other SCB worth waiting for...\n");
9594 return (found != 0);
9597 /**************************** Flexport Logic **********************************/
9599 * Read count 16bit words from 16bit word address start_addr from the
9600 * SEEPROM attached to the controller, into buf, using the controller's
9601 * SEEPROM reading state machine. Optionally treat the data as a byte
9602 * stream in terms of byte order.
9605 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9606 u_int start_addr, u_int count, int bytestream)
9613 * If we never make it through the loop even once,
9614 * we were passed invalid arguments.
9617 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9618 end_addr = start_addr + count;
9619 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9621 ahd_outb(ahd, SEEADR, cur_addr);
9622 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9624 error = ahd_wait_seeprom(ahd);
9627 if (bytestream != 0) {
9628 uint8_t *bytestream_ptr;
9630 bytestream_ptr = (uint8_t *)buf;
9631 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9632 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9635 * ahd_inw() already handles machine byte order.
9637 *buf = ahd_inw(ahd, SEEDAT);
9645 * Write count 16bit words from buf, into SEEPROM attache to the
9646 * controller starting at 16bit word address start_addr, using the
9647 * controller's SEEPROM writing state machine.
9650 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9651 u_int start_addr, u_int count)
9658 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9661 /* Place the chip into write-enable mode */
9662 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9663 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9664 error = ahd_wait_seeprom(ahd);
9669 * Write the data. If we don't get through the loop at
9670 * least once, the arguments were invalid.
9673 end_addr = start_addr + count;
9674 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9675 ahd_outw(ahd, SEEDAT, *buf++);
9676 ahd_outb(ahd, SEEADR, cur_addr);
9677 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9679 retval = ahd_wait_seeprom(ahd);
9687 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9688 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9689 error = ahd_wait_seeprom(ahd);
9696 * Wait ~100us for the serial eeprom to satisfy our request.
9699 ahd_wait_seeprom(struct ahd_softc *ahd)
9704 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9713 * Validate the two checksums in the per_channel
9714 * vital product data struct.
9717 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9724 vpdarray = (uint8_t *)vpd;
9725 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9727 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9728 checksum = checksum + vpdarray[i];
9730 || (-checksum & 0xFF) != vpd->vpd_checksum)
9734 maxaddr = offsetof(struct vpd_config, checksum);
9735 for (i = offsetof(struct vpd_config, default_target_flags);
9737 checksum = checksum + vpdarray[i];
9739 || (-checksum & 0xFF) != vpd->checksum)
9745 ahd_verify_cksum(struct seeprom_config *sc)
9752 maxaddr = (sizeof(*sc)/2) - 1;
9754 scarray = (uint16_t *)sc;
9756 for (i = 0; i < maxaddr; i++)
9757 checksum = checksum + scarray[i];
9759 || (checksum & 0xFFFF) != sc->checksum) {
9767 ahd_acquire_seeprom(struct ahd_softc *ahd)
9770 * We should be able to determine the SEEPROM type
9771 * from the flexport logic, but unfortunately not
9772 * all implementations have this logic and there is
9773 * no programatic method for determining if the logic
9781 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9783 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9790 ahd_release_seeprom(struct ahd_softc *ahd)
9792 /* Currently a no-op */
9796 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9800 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9802 panic("ahd_write_flexport: address out of range");
9803 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9804 error = ahd_wait_flexport(ahd);
9807 ahd_outb(ahd, BRDDAT, value);
9808 ahd_flush_device_writes(ahd);
9809 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9810 ahd_flush_device_writes(ahd);
9811 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9812 ahd_flush_device_writes(ahd);
9813 ahd_outb(ahd, BRDCTL, 0);
9814 ahd_flush_device_writes(ahd);
9819 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9823 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9825 panic("ahd_read_flexport: address out of range");
9826 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9827 error = ahd_wait_flexport(ahd);
9830 *value = ahd_inb(ahd, BRDDAT);
9831 ahd_outb(ahd, BRDCTL, 0);
9832 ahd_flush_device_writes(ahd);
9837 * Wait at most 2 seconds for flexport arbitration to succeed.
9840 ahd_wait_flexport(struct ahd_softc *ahd)
9844 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9845 cnt = 1000000 * 2 / 5;
9846 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9854 /************************* Target Mode ****************************************/
9855 #ifdef AHD_TARGET_MODE
9857 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9858 struct ahd_tmode_tstate **tstate,
9859 struct ahd_tmode_lstate **lstate,
9860 int notfound_failure)
9863 if ((ahd->features & AHD_TARGETMODE) == 0)
9864 return (CAM_REQ_INVALID);
9867 * Handle the 'black hole' device that sucks up
9868 * requests to unattached luns on enabled targets.
9870 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9871 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9873 *lstate = ahd->black_hole;
9877 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9878 if (ccb->ccb_h.target_id > max_id)
9879 return (CAM_TID_INVALID);
9881 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9882 return (CAM_LUN_INVALID);
9884 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9886 if (*tstate != NULL)
9888 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9891 if (notfound_failure != 0 && *lstate == NULL)
9892 return (CAM_PATH_INVALID);
9894 return (CAM_REQ_CMP);
9898 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9901 struct ahd_tmode_tstate *tstate;
9902 struct ahd_tmode_lstate *lstate;
9903 struct ccb_en_lun *cel;
9911 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9912 /*notfound_failure*/FALSE);
9914 if (status != CAM_REQ_CMP) {
9915 ccb->ccb_h.status = status;
9919 if ((ahd->features & AHD_MULTIROLE) != 0) {
9922 our_id = ahd->our_id;
9923 if (ccb->ccb_h.target_id != our_id
9924 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9925 if ((ahd->features & AHD_MULTI_TID) != 0
9926 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9928 * Only allow additional targets if
9929 * the initiator role is disabled.
9930 * The hardware cannot handle a re-select-in
9931 * on the initiator id during a re-select-out
9932 * on a different target id.
9934 status = CAM_TID_INVALID;
9935 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9936 || ahd->enabled_luns > 0) {
9938 * Only allow our target id to change
9939 * if the initiator role is not configured
9940 * and there are no enabled luns which
9941 * are attached to the currently registered
9944 status = CAM_TID_INVALID;
9949 if (status != CAM_REQ_CMP) {
9950 ccb->ccb_h.status = status;
9955 * We now have an id that is valid.
9956 * If we aren't in target mode, switch modes.
9958 if ((ahd->flags & AHD_TARGETROLE) == 0
9959 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9960 printf("Configuring Target Mode\n");
9961 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9962 ccb->ccb_h.status = CAM_BUSY;
9965 ahd->flags |= AHD_TARGETROLE;
9966 if ((ahd->features & AHD_MULTIROLE) == 0)
9967 ahd->flags &= ~AHD_INITIATORROLE;
9973 target = ccb->ccb_h.target_id;
9974 lun = ccb->ccb_h.target_lun;
9975 channel = SIM_CHANNEL(ahd, sim);
9976 target_mask = 0x01 << target;
9980 if (cel->enable != 0) {
9983 /* Are we already enabled?? */
9984 if (lstate != NULL) {
9985 xpt_print_path(ccb->ccb_h.path);
9986 printf("Lun already enabled\n");
9987 AHD_CORRECTABLE_ERROR(ahd);
9988 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9992 if (cel->grp6_len != 0
9993 || cel->grp7_len != 0) {
9995 * Don't (yet?) support vendor
9996 * specific commands.
9998 ccb->ccb_h.status = CAM_REQ_INVALID;
9999 printf("Non-zero Group Codes\n");
10004 * Seems to be okay.
10005 * Setup our data structures.
10007 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
10008 tstate = ahd_alloc_tstate(ahd, target, channel);
10009 if (tstate == NULL) {
10010 xpt_print_path(ccb->ccb_h.path);
10011 printf("Couldn't allocate tstate\n");
10012 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
10016 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
10017 if (lstate == NULL) {
10018 xpt_print_path(ccb->ccb_h.path);
10019 printf("Couldn't allocate lstate\n");
10020 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
10023 memset(lstate, 0, sizeof(*lstate));
10024 status = xpt_create_path(&lstate->path, /*periph*/NULL,
10025 xpt_path_path_id(ccb->ccb_h.path),
10026 xpt_path_target_id(ccb->ccb_h.path),
10027 xpt_path_lun_id(ccb->ccb_h.path));
10028 if (status != CAM_REQ_CMP) {
10029 free(lstate, M_DEVBUF);
10030 xpt_print_path(ccb->ccb_h.path);
10031 printf("Couldn't allocate path\n");
10032 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
10035 SLIST_INIT(&lstate->accept_tios);
10036 SLIST_INIT(&lstate->immed_notifies);
10038 if (target != CAM_TARGET_WILDCARD) {
10039 tstate->enabled_luns[lun] = lstate;
10040 ahd->enabled_luns++;
10042 if ((ahd->features & AHD_MULTI_TID) != 0) {
10045 targid_mask = ahd_inw(ahd, TARGID);
10046 targid_mask |= target_mask;
10047 ahd_outw(ahd, TARGID, targid_mask);
10048 ahd_update_scsiid(ahd, targid_mask);
10053 channel = SIM_CHANNEL(ahd, sim);
10054 our_id = SIM_SCSI_ID(ahd, sim);
10057 * This can only happen if selections
10060 if (target != our_id) {
10065 sblkctl = ahd_inb(ahd, SBLKCTL);
10066 cur_channel = (sblkctl & SELBUSB)
10068 if ((ahd->features & AHD_TWIN) == 0)
10070 swap = cur_channel != channel;
10071 ahd->our_id = target;
10074 ahd_outb(ahd, SBLKCTL,
10075 sblkctl ^ SELBUSB);
10077 ahd_outb(ahd, SCSIID, target);
10080 ahd_outb(ahd, SBLKCTL, sblkctl);
10084 ahd->black_hole = lstate;
10085 /* Allow select-in operations */
10086 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
10087 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10088 scsiseq1 |= ENSELI;
10089 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10090 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10091 scsiseq1 |= ENSELI;
10092 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10095 ccb->ccb_h.status = CAM_REQ_CMP;
10096 xpt_print_path(ccb->ccb_h.path);
10097 printf("Lun now enabled for target mode\n");
10102 if (lstate == NULL) {
10103 ccb->ccb_h.status = CAM_LUN_INVALID;
10107 ccb->ccb_h.status = CAM_REQ_CMP;
10108 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
10109 struct ccb_hdr *ccbh;
10111 ccbh = &scb->io_ctx->ccb_h;
10112 if (ccbh->func_code == XPT_CONT_TARGET_IO
10113 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
10114 printf("CTIO pending\n");
10115 ccb->ccb_h.status = CAM_REQ_INVALID;
10120 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
10121 printf("ATIOs pending\n");
10122 ccb->ccb_h.status = CAM_REQ_INVALID;
10125 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
10126 printf("INOTs pending\n");
10127 ccb->ccb_h.status = CAM_REQ_INVALID;
10130 if (ccb->ccb_h.status != CAM_REQ_CMP) {
10134 xpt_print_path(ccb->ccb_h.path);
10135 printf("Target mode disabled\n");
10136 xpt_free_path(lstate->path);
10137 free(lstate, M_DEVBUF);
10140 /* Can we clean up the target too? */
10141 if (target != CAM_TARGET_WILDCARD) {
10142 tstate->enabled_luns[lun] = NULL;
10143 ahd->enabled_luns--;
10144 for (empty = 1, i = 0; i < 8; i++)
10145 if (tstate->enabled_luns[i] != NULL) {
10151 ahd_free_tstate(ahd, target, channel,
10153 if (ahd->features & AHD_MULTI_TID) {
10156 targid_mask = ahd_inw(ahd, TARGID);
10157 targid_mask &= ~target_mask;
10158 ahd_outw(ahd, TARGID, targid_mask);
10159 ahd_update_scsiid(ahd, targid_mask);
10164 ahd->black_hole = NULL;
10167 * We can't allow selections without
10168 * our black hole device.
10172 if (ahd->enabled_luns == 0) {
10173 /* Disallow select-in */
10176 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
10177 scsiseq1 &= ~ENSELI;
10178 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
10179 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
10180 scsiseq1 &= ~ENSELI;
10181 ahd_outb(ahd, SCSISEQ1, scsiseq1);
10183 if ((ahd->features & AHD_MULTIROLE) == 0) {
10184 printf("Configuring Initiator Mode\n");
10185 ahd->flags &= ~AHD_TARGETROLE;
10186 ahd->flags |= AHD_INITIATORROLE;
10191 * Unpaused. The extra unpause
10192 * that follows is harmless.
10202 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
10208 if ((ahd->features & AHD_MULTI_TID) == 0)
10209 panic("ahd_update_scsiid called on non-multitid unit\n");
10212 * Since we will rely on the TARGID mask
10213 * for selection enables, ensure that OID
10214 * in SCSIID is not set to some other ID
10215 * that we don't want to allow selections on.
10217 if ((ahd->features & AHD_ULTRA2) != 0)
10218 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
10220 scsiid = ahd_inb(ahd, SCSIID);
10221 scsiid_mask = 0x1 << (scsiid & OID);
10222 if ((targid_mask & scsiid_mask) == 0) {
10225 /* ffs counts from 1 */
10226 our_id = ffs(targid_mask);
10228 our_id = ahd->our_id;
10234 if ((ahd->features & AHD_ULTRA2) != 0)
10235 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
10237 ahd_outb(ahd, SCSIID, scsiid);
10242 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
10244 struct target_cmd *cmd;
10246 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
10247 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
10250 * Only advance through the queue if we
10251 * have the resources to process the command.
10253 if (ahd_handle_target_cmd(ahd, cmd) != 0)
10256 cmd->cmd_valid = 0;
10257 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
10258 ahd->shared_data_dmamap,
10259 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
10260 sizeof(struct target_cmd),
10261 BUS_DMASYNC_PREREAD);
10262 ahd->tqinfifonext++;
10265 * Lazily update our position in the target mode incoming
10266 * command queue as seen by the sequencer.
10268 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
10271 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
10272 hs_mailbox &= ~HOST_TQINPOS;
10273 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
10274 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
10280 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
10282 struct ahd_tmode_tstate *tstate;
10283 struct ahd_tmode_lstate *lstate;
10284 struct ccb_accept_tio *atio;
10290 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
10291 target = SCSIID_OUR_ID(cmd->scsiid);
10292 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
10295 tstate = ahd->enabled_targets[target];
10297 if (tstate != NULL)
10298 lstate = tstate->enabled_luns[lun];
10301 * Commands for disabled luns go to the black hole driver.
10303 if (lstate == NULL)
10304 lstate = ahd->black_hole;
10306 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
10307 if (atio == NULL) {
10308 ahd->flags |= AHD_TQINFIFO_BLOCKED;
10310 * Wait for more ATIOs from the peripheral driver for this lun.
10314 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
10316 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10317 printf("Incoming command from %d for %d:%d%s\n",
10318 initiator, target, lun,
10319 lstate == ahd->black_hole ? "(Black Holed)" : "");
10321 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
10323 if (lstate == ahd->black_hole) {
10324 /* Fill in the wildcards */
10325 atio->ccb_h.target_id = target;
10326 atio->ccb_h.target_lun = lun;
10330 * Package it up and send it off to
10331 * whomever has this lun enabled.
10333 atio->sense_len = 0;
10334 atio->init_id = initiator;
10335 if (byte[0] != 0xFF) {
10336 /* Tag was included */
10337 atio->tag_action = *byte++;
10338 atio->tag_id = *byte++;
10339 atio->ccb_h.flags |= CAM_TAG_ACTION_VALID;
10341 atio->ccb_h.flags &= ~CAM_TAG_ACTION_VALID;
10345 /* Okay. Now determine the cdb size based on the command code */
10346 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
10352 atio->cdb_len = 10;
10355 atio->cdb_len = 16;
10358 atio->cdb_len = 12;
10362 /* Only copy the opcode. */
10364 printf("Reserved or VU command code type encountered\n");
10368 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
10370 atio->ccb_h.status |= CAM_CDB_RECVD;
10372 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
10374 * We weren't allowed to disconnect.
10375 * We're hanging on the bus until a
10376 * continue target I/O comes in response
10377 * to this accept tio.
10380 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
10381 printf("Received Immediate Command %d:%d:%d - %p\n",
10382 initiator, target, lun, ahd->pending_device);
10384 ahd->pending_device = lstate;
10385 ahd_freeze_ccb((union ccb *)atio);
10386 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
10388 xpt_done((union ccb*)atio);