2 * Core definitions and data structures shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#61 $
48 /* Register Definitions */
49 #include "aic79xx_reg.h"
51 /************************* Forward Declarations *******************************/
52 struct ahd_platform_data;
53 struct scb_platform_data;
55 /****************************** Useful Macros *********************************/
57 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
61 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
71 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
73 #define ALL_CHANNELS '\0'
74 #define ALL_TARGETS_MASK 0xFFFF
75 #define INITIATOR_WILDCARD (~0)
76 #define SCB_LIST_NULL 0xFF00
77 #define SCB_LIST_NULL_LE (ahd_htole16(SCB_LIST_NULL))
78 #define QOUTFIFO_ENTRY_VALID 0x8000
79 #define QOUTFIFO_ENTRY_VALID_LE (ahd_htole16(0x8000))
80 #define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
82 #define SCSIID_TARGET(ahd, scsiid) \
83 (((scsiid) & TID) >> TID_SHIFT)
84 #define SCSIID_OUR_ID(scsiid) \
86 #define SCSIID_CHANNEL(ahd, scsiid) ('A')
87 #define SCB_IS_SCSIBUS_B(ahd, scb) (0)
88 #define SCB_GET_OUR_ID(scb) \
89 SCSIID_OUR_ID((scb)->hscb->scsiid)
90 #define SCB_GET_TARGET(ahd, scb) \
91 SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
92 #define SCB_GET_CHANNEL(ahd, scb) \
93 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
94 #define SCB_GET_LUN(scb) \
96 #define SCB_GET_TARGET_OFFSET(ahd, scb) \
97 SCB_GET_TARGET(ahd, scb)
98 #define SCB_GET_TARGET_MASK(ahd, scb) \
99 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
101 * TCLs have the following format: TTTTLLLLLLLL
103 #define TCL_TARGET_OFFSET(tcl) \
104 ((((tcl) >> 4) & TID) >> 4)
105 #define TCL_LUN(tcl) \
106 (tcl & (AHD_NUM_LUNS - 1))
107 #define BUILD_TCL(scsiid, lun) \
108 ((lun) | (((scsiid) & TID) << 4))
109 #define BUILD_TCL_RAW(target, channel, lun) \
110 ((lun) | ((target) << 8))
112 #define SCB_GET_TAG(scb) \
113 ahd_le16toh(scb->hscb->tag)
115 #ifndef AHD_TARGET_MODE
116 #undef AHD_TMODE_ENABLE
117 #define AHD_TMODE_ENABLE 0
120 #define AHD_BUILD_COL_IDX(target, lun) \
121 (((lun) << 4) | target)
123 #define AHD_GET_SCB_COL_IDX(ahd, scb) \
124 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
126 #define AHD_SET_SCB_COL_IDX(scb, col_idx) \
128 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \
129 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \
132 #define AHD_COPY_SCB_COL_IDX(dst, src) \
134 dst->hscb->scsiid = src->hscb->scsiid; \
135 dst->hscb->lun = src->hscb->lun; \
138 #define AHD_NEVER_COL_IDX 0xFFFF
140 /**************************** Driver Constants ********************************/
142 * The maximum number of supported targets.
144 #define AHD_NUM_TARGETS 16
147 * The maximum number of supported luns.
148 * The identify message only supports 64 luns in non-packetized transfers.
149 * You can have 2^64 luns when information unit transfers are enabled,
150 * but until we see a need to support that many, we support 256.
152 #define AHD_NUM_LUNS_NONPKT 64
153 #define AHD_NUM_LUNS 256
156 * The maximum transfer per S/G segment.
158 #define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
161 * The maximum amount of SCB storage in hardware on a controller.
162 * This value represents an upper bound. Due to software design,
163 * we may not be able to use this number.
165 #define AHD_SCB_MAX 512
168 * The maximum number of concurrent transactions supported per driver instance.
169 * Sequencer Control Blocks (SCBs) store per-transaction information.
171 #define AHD_MAX_QUEUE AHD_SCB_MAX
174 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2
175 * in size and accomodate as many transactions as can be queued concurrently.
177 #define AHD_QIN_SIZE AHD_MAX_QUEUE
178 #define AHD_QOUT_SIZE AHD_MAX_QUEUE
180 #define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
182 * The maximum amount of SCB storage we allocate in host memory.
184 #define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
187 * Ring Buffer of incoming target commands.
188 * We allocate 256 to simplify the logic in the sequencer
189 * by using the natural wrap point of an 8bit counter.
191 #define AHD_TMODE_CMDS 256
193 /* Reset line assertion time in us */
194 #define AHD_BUSRESET_DELAY 25
196 /******************* Chip Characteristics/Operating Settings *****************/
199 * The chip order is from least sophisticated to most sophisticated.
203 AHD_CHIPID_MASK = 0x00FF,
204 AHD_AIC7901 = 0x0001,
205 AHD_AIC7902 = 0x0002,
206 AHD_AIC7901A = 0x0003,
207 AHD_PCI = 0x0100, /* Bus type PCI */
208 AHD_PCIX = 0x0200, /* Bus type PCIX */
209 AHD_BUS_MASK = 0x0F00
213 * Features available in each chip type.
216 AHD_FENONE = 0x00000,
217 AHD_WIDE = 0x00001, /* Wide Channel */
218 AHD_MULTI_FUNC = 0x00100, /* Multi-Function Twin Channel Device */
219 AHD_TARGETMODE = 0x01000, /* Has tested target mode support */
220 AHD_MULTIROLE = 0x02000, /* Space for two roles at a time */
221 AHD_REMOVABLE = 0x00000, /* Hot-Swap supported - None so far*/
222 AHD_AIC7901_FE = AHD_FENONE,
223 AHD_AIC7902_FE = AHD_MULTI_FUNC
227 * Bugs in the silicon that we work around in software.
230 AHD_BUGNONE = 0x0000,
231 AHD_SENT_SCB_UPDATE_BUG = 0x0001,
232 AHD_ABORT_LQI_BUG = 0x0002,
233 AHD_PKT_BITBUCKET_BUG = 0x0004,
234 AHD_LONG_SETIMO_BUG = 0x0008,
235 AHD_NLQICRC_DELAYED_BUG = 0x0010,
236 AHD_SCSIRST_BUG = 0x0020,
237 AHD_PCIX_CHIPRST_BUG = 0x0040,
238 AHD_PCIX_MMAPIO_BUG = 0x0080,
239 /* Bug workarounds that can be disabled on non-PCIX busses. */
240 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG
241 | AHD_PCIX_MMAPIO_BUG,
242 AHD_LQO_ATNO_BUG = 0x0100,
243 AHD_AUTOFLUSH_BUG = 0x0200,
244 AHD_CLRLQO_AUTOCLR_BUG = 0x0400,
245 AHD_PKTIZED_STATUS_BUG = 0x0800,
246 AHD_PKT_LUN_BUG = 0x1000,
247 AHD_MDFF_WSCBPTR_BUG = 0x2000,
248 AHD_REG_SLOW_SETTLE_BUG = 0x4000,
249 AHD_SET_MODE_BUG = 0x8000,
250 AHD_BUSFREEREV_BUG = 0x10000
254 * Configuration specific settings.
255 * The driver determines these settings by probing the
256 * chip/controller's configuration.
260 AHD_PRIMARY_CHANNEL = 0x00003,/*
261 * The channel that should
264 AHD_USEDEFAULTS = 0x00004,/*
265 * For cards without an seeprom
266 * or a BIOS to initialize the chip's
267 * SRAM, we use the default target
270 AHD_SEQUENCER_DEBUG = 0x00008,
271 AHD_RESET_BUS_A = 0x00010,
272 AHD_EXTENDED_TRANS_A = 0x00020,
273 AHD_TERM_ENB_A = 0x00040,
274 AHD_SPCHK_ENB_A = 0x00080,
275 AHD_STPWLEVEL_A = 0x00100,
276 AHD_INITIATORROLE = 0x00200,/*
277 * Allow initiator operations on
280 AHD_TARGETROLE = 0x00400,/*
281 * Allow target operations on this
284 AHD_RESOURCE_SHORTAGE = 0x00800,
285 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */
286 AHD_INT50_SPEEDFLEX = 0x02000,/*
287 * Internal 50pin connector
288 * sits behind an aic3860
290 AHD_BIOS_ENABLED = 0x04000,
291 AHD_ALL_INTERRUPTS = 0x08000,
292 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */
293 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */
294 AHD_CURRENT_SENSING = 0x40000,
295 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */
296 AHD_CPQ_BOARD = 0x100000,
297 AHD_RESET_POLL_ACTIVE = 0x200000
300 /************************* Hardware SCB Definition ***************************/
303 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
304 * consists of a "hardware SCB" mirroring the fields availible on the card
305 * and additional information the kernel stores for each transaction.
307 * To minimize space utilization, a portion of the hardware scb stores
308 * different data during different portions of a SCSI transaction.
309 * As initialized by the host driver for the initiator role, this area
310 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
311 * the cdb has been presented to the target, this area serves to store
312 * residual transfer information and the SCSI status byte.
313 * For the target role, the contents of this area do not change, but
314 * still serve a different purpose than for the initiator role. See
315 * struct target_data for details.
319 * Status information embedded in the shared poriton of
320 * an SCB after passing the cdb to the target. The kernel
321 * driver will only read this data for transactions that
322 * complete abnormally.
324 struct initiator_status {
325 uint32_t residual_datacnt; /* Residual in the current S/G seg */
326 uint32_t residual_sgptr; /* The next S/G for this transfer */
327 uint8_t scsi_status; /* Standard SCSI status byte */
330 struct target_status {
331 uint32_t residual_datacnt; /* Residual in the current S/G seg */
332 uint32_t residual_sgptr; /* The next S/G for this transfer */
333 uint8_t scsi_status; /* SCSI status to give to initiator */
334 uint8_t target_phases; /* Bitmap of phases to execute */
335 uint8_t data_phase; /* Data-In or Data-Out */
336 uint8_t initiator_tag; /* Initiator's transaction tag */
340 * Initiator mode SCB shared data area.
341 * If the embedded CDB is 12 bytes or less, we embed
342 * the sense buffer address in the SCB. This allows
343 * us to retrieve sense information without interupting
344 * the host in packetized mode.
346 typedef uint32_t sense_addr_t;
347 #define MAX_CDB_LEN 16
348 #define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
349 union initiator_data {
351 uint8_t cdb[MAX_CDB_LEN];
353 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
354 sense_addr_t sense_addr;
359 * Target mode version of the shared data SCB segment.
363 uint8_t scsi_status; /* SCSI status to give to initiator */
364 uint8_t target_phases; /* Bitmap of phases to execute */
365 uint8_t data_phase; /* Data-In or Data-Out */
366 uint8_t initiator_tag; /* Initiator's transaction tag */
369 struct hardware_scb {
371 union initiator_data idata;
372 struct target_data tdata;
373 struct initiator_status istatus;
374 struct target_status tstatus;
377 * A word about residuals.
378 * The scb is presented to the sequencer with the dataptr and datacnt
379 * fields initialized to the contents of the first S/G element to
380 * transfer. The sgptr field is initialized to the bus address for
381 * the S/G element that follows the first in the in core S/G array
382 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
383 * S/G entry for this transfer (single S/G element transfer with the
384 * first elements address and length preloaded in the dataptr/datacnt
385 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
386 * The SG_FULL_RESID flag ensures that the residual will be correctly
387 * noted even if no data transfers occur. Once the data phase is entered,
388 * the residual sgptr and datacnt are loaded from the sgptr and the
389 * datacnt fields. After each S/G element's dataptr and length are
390 * loaded into the hardware, the residual sgptr is advanced. After
391 * each S/G element is expired, its datacnt field is checked to see
392 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
393 * residual sg ptr and the transfer is considered complete. If the
394 * sequencer determines that there is a residual in the tranfer, or
395 * there is non-zero status, it will set the SG_STATUS_VALID flag in
396 * sgptr and dma the scb back into host memory. To sumarize:
399 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
400 * or residual_sgptr does not have SG_LIST_NULL set.
402 * o We are transfering the last segment if residual_datacnt has
403 * the SG_LAST_SEG flag set.
406 * o A residual can only have occurred if a completed scb has the
407 * SG_STATUS_VALID flag set. Inspection of the SCSI status field,
408 * the residual_datacnt, and the residual_sgptr field will tell
411 * o residual_sgptr and sgptr refer to the "next" sg entry
412 * and so may point beyond the last valid sg entry for the
415 #define SG_PTR_MASK 0xFFFFFFF8
417 /*18*/ uint8_t cdb_len;
418 /*19*/ uint8_t task_management;
419 /*20*/ uint32_t next_hscb_busaddr;
420 /*24*/ uint64_t dataptr;
421 /*32*/ uint32_t datacnt; /* Byte 3 is spare. */
422 /*36*/ uint32_t sgptr;
423 /*40*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */
424 /*41*/ uint8_t scsiid; /*
426 * Our Id (bits 0-3) Their ID (bits 4-7)
429 /*43*/ uint8_t task_attribute;
430 /*44*/ uint32_t hscb_busaddr;
431 /******* Long lun field only downloaded for full 8 byte lun support *******/
432 /*48*/ uint8_t pkt_long_lun[8];
433 /******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
434 /*56*/ uint8_t spare[8];
437 /************************ Kernel SCB Definitions ******************************/
439 * Some fields of the SCB are OS dependent. Here we collect the
440 * definitions for elements that all OS platforms need to include
441 * in there SCB definition.
445 * Definition of a scatter/gather element as transfered to the controller.
446 * The aic7xxx chips only support a 24bit length. We use the top byte of
447 * the length to store additional address bits and a flag to indicate
448 * that a given segment terminates the transfer. This gives us an
449 * addressable range of 512GB on machines with 64bit PCI or with chips
450 * that can support dual address cycles on 32bit PCI busses.
455 #define AHD_DMA_LAST_SEG 0x80000000
456 #define AHD_SG_HIGH_ADDR_MASK 0x7F000000
457 #define AHD_SG_LEN_MASK 0x00FFFFFF
460 struct ahd_dma64_seg {
470 SLIST_ENTRY(map_node) links;
474 * The current state of this SCB.
477 SCB_FLAG_NONE = 0x00000,
478 SCB_TRANSMISSION_ERROR = 0x00001,/*
479 * We detected a parity or CRC
480 * error that has effected the
481 * payload of the command. This
482 * flag is checked when normal
483 * status is returned to catch
484 * the case of a target not
485 * responding to our attempt
486 * to report the error.
488 SCB_OTHERTCL_TIMEOUT = 0x00002,/*
489 * Another device was active
490 * during the first timeout for
491 * this SCB so we gave ourselves
492 * an additional timeout period
493 * in case it was hogging the
496 SCB_DEVICE_RESET = 0x00004,
498 SCB_CDB32_PTR = 0x00010,
499 SCB_RECOVERY_SCB = 0x00020,
500 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */
501 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */
503 SCB_ACTIVE = 0x00400,
504 SCB_TARGET_IMMEDIATE = 0x00800,
505 SCB_PACKETIZED = 0x01000,
506 SCB_EXPECT_PPR_BUSFREE = 0x02000,
507 SCB_PKT_SENSE = 0x04000,
508 SCB_CMDPHASE_ABORT = 0x08000,
509 SCB_ON_COL_LIST = 0x10000
513 struct hardware_scb *hscb;
515 SLIST_ENTRY(scb) sle;
517 TAILQ_ENTRY(scb) tqe;
520 SLIST_ENTRY(scb) sle;
522 TAILQ_ENTRY(scb) tqe;
524 #define pending_links links2.le
525 #define collision_links links2.le
528 struct ahd_softc *ahd_softc;
533 struct scb_platform_data *platform_data;
534 struct map_node *hscb_map;
535 struct map_node *sg_map;
536 struct map_node *sense_map;
539 bus_addr_t sg_list_busaddr;
540 bus_addr_t sense_busaddr;
541 u_int sg_count;/* How full ahd_dma_seg is */
544 TAILQ_HEAD(scb_tailq, scb);
545 LIST_HEAD(scb_list, scb);
549 * TAILQ of lists of free SCBs grouped by device
552 struct scb_tailq free_scbs;
555 * Per-device lists of SCBs whose tag ID would collide
556 * with an already active tag on the device.
558 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
561 * SCBs that will not collide with any active device.
563 struct scb_list any_dev_free_scb_list;
566 * Mapping from tag to SCB.
568 struct scb *scbindex[AHD_SCB_MAX];
571 * "Bus" addresses of our data structures.
573 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
574 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
575 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */
576 SLIST_HEAD(, map_node) hscb_maps;
577 SLIST_HEAD(, map_node) sg_maps;
578 SLIST_HEAD(, map_node) sense_maps;
579 int scbs_left; /* unallocated scbs in head map_node */
580 int sgs_left; /* unallocated sgs in head map_node */
581 int sense_left; /* unallocated sense in head map_node */
583 uint16_t maxhscbs; /* Number of SCBs on the card */
584 uint8_t init_level; /*
585 * How far we've initialized
590 /************************ Target Mode Definitions *****************************/
593 * Connection desciptor for select-in requests in target mode.
596 uint8_t scsiid; /* Our ID and the initiator's ID */
597 uint8_t identify; /* Identify message */
598 uint8_t bytes[22]; /*
599 * Bytes contains any additional message
600 * bytes terminated by 0xFF. The remainder
601 * is the cdb to execute.
603 uint8_t cmd_valid; /*
604 * When a command is complete, the firmware
605 * will set cmd_valid to all bits set.
606 * After the host has seen the command,
607 * the bits are cleared. This allows us
608 * to just peek at host memory to determine
609 * if more work is complete. cmd_valid is on
610 * an 8 byte boundary to simplify setting
611 * it on aic7880 hardware which only has
612 * limited direct access to the DMA FIFO.
618 * Number of events we can buffer up if we run out
619 * of immediate notify ccbs.
621 #define AHD_TMODE_EVENT_BUFFER_SIZE 8
622 struct ahd_tmode_event {
623 uint8_t initiator_id;
624 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
625 #define EVENT_TYPE_BUS_RESET 0xFF
630 * Per enabled lun target mode state.
631 * As this state is directly influenced by the host OS'es target mode
632 * environment, we let the OS module define it. Forward declare the
633 * structure here so we can store arrays of them, etc. in OS neutral
636 #ifdef AHD_TARGET_MODE
637 struct ahd_tmode_lstate {
638 struct cam_path *path;
639 struct ccb_hdr_slist accept_tios;
640 struct ccb_hdr_slist immed_notifies;
641 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
646 struct ahd_tmode_lstate;
649 /******************** Transfer Negotiation Datastructures *********************/
650 #define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */
651 #define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
652 #define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */
653 #define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */
654 #define AHD_PERIOD_ASYNC 0xFF
655 #define AHD_PERIOD_10MHz 0x19
658 * Transfer Negotiation Information.
660 struct ahd_transinfo {
661 uint8_t protocol_version; /* SCSI Revision level */
662 uint8_t transport_version; /* SPI Revision level */
663 uint8_t width; /* Bus width */
664 uint8_t period; /* Sync rate factor */
665 uint8_t offset; /* Sync offset */
666 uint8_t ppr_options; /* Parallel Protocol Request options */
670 * Per-initiator current, goal and user transfer negotiation information. */
671 struct ahd_initiator_tinfo {
672 struct ahd_transinfo curr;
673 struct ahd_transinfo goal;
674 struct ahd_transinfo user;
678 * Per enabled target ID state.
679 * Pointers to lun target state as well as sync/wide negotiation information
680 * for each initiator<->target mapping. For the initiator role we pretend
681 * that we are the target and the targets are the initiators since the
682 * negotiation is the same regardless of role.
684 struct ahd_tmode_tstate {
685 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS];
686 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS];
689 * Per initiator state bitmasks.
691 uint16_t auto_negotiate;/* Auto Negotiation Required */
692 uint16_t discenable; /* Disconnection allowed */
693 uint16_t tagenable; /* Tagged Queuing allowed */
697 * Points of interest along the negotiated transfer scale.
699 #define AHD_SYNCRATE_MAX 0x8
700 #define AHD_SYNCRATE_160 0x8
701 #define AHD_SYNCRATE_PACED 0x8
702 #define AHD_SYNCRATE_DT 0x9
703 #define AHD_SYNCRATE_ULTRA2 0xa
704 #define AHD_SYNCRATE_ULTRA 0xc
705 #define AHD_SYNCRATE_FAST 0x19
706 #define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST
707 #define AHD_SYNCRATE_SYNC 0x32
708 #define AHD_SYNCRATE_MIN 0x60
709 #define AHD_SYNCRATE_ASYNC 0xFF
712 * In RevA, the synctable uses a 120MHz rate for the period
713 * factor 8 and 160MHz for the period factor 7. The 120MHz
714 * rate never made it into the official SCSI spec, so we must
715 * compensate when setting the negotiation table for Rev A
718 #define AHD_SYNCRATE_REVA_120 0x8
719 #define AHD_SYNCRATE_REVA_160 0x7
721 /***************************** Lookup Tables **********************************/
723 * Phase -> name and message out response
724 * to parity errors in each phase table.
726 struct ahd_phase_table_entry {
728 uint8_t mesg_out; /* Message response to parity errors */
732 /************************** Serial EEPROM Format ******************************/
734 struct seeprom_config {
736 * Per SCSI ID Configuration Flags
738 uint16_t device_flags[16]; /* words 0-15 */
739 #define CFXFER 0x003F /* synchronous transfer rate */
740 #define CFXFER_ASYNC 0x3F
741 #define CFQAS 0x0040 /* Negotiate QAS */
742 #define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */
743 #define CFSTART 0x0100 /* send start unit SCSI command */
744 #define CFINCBIOS 0x0200 /* include in BIOS scan */
745 #define CFDISC 0x0400 /* enable disconnection */
746 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
747 #define CFWIDEB 0x1000 /* wide bus device */
748 #define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */
753 uint16_t bios_control; /* word 16 */
754 #define CFSUPREM 0x0001 /* support all removeable drives */
755 #define CFSUPREMB 0x0002 /* support removeable boot drives */
756 #define CFBIOSSTATE 0x000C /* BIOS Action State */
757 #define CFBS_DISABLED 0x00
758 #define CFBS_ENABLED 0x04
759 #define CFBS_DISABLED_SCAN 0x08
760 #define CFENABLEDV 0x0010 /* Perform Domain Validation */
761 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
762 #define CFSPARITY 0x0040 /* SCSI parity */
763 #define CFEXTEND 0x0080 /* extended translation enabled */
764 #define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */
765 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
766 #define CFMSG_VERBOSE 0x0000
767 #define CFMSG_SILENT 0x0200
768 #define CFMSG_DIAG 0x0400
769 #define CFRESETB 0x0800 /* reset SCSI bus at boot */
773 * Host Adapter Control Bits
775 uint16_t adapter_control; /* word 17 */
776 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
777 #define CFSTERM 0x0002 /* SCSI low byte termination */
778 #define CFWSTERM 0x0004 /* SCSI high byte termination */
779 #define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/
780 #define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */
781 #define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */
782 #define CFSTPWLEVEL 0x0040 /* Termination level control */
783 #define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */
784 #define CFTERM_MENU 0x0100 /* BIOS displays termination menu */
785 #define CFCLUSTERENB 0x8000 /* Cluster Enable */
788 * Bus Release Time, Host Adapter ID
790 uint16_t brtime_id; /* word 18 */
791 #define CFSCSIID 0x000f /* host adapter SCSI ID */
793 #define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */
798 uint16_t max_targets; /* word 19 */
799 #define CFMAXTARG 0x00ff /* maximum targets */
800 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
801 #define CFBOOTID 0xf000 /* Target to boot from */
802 uint16_t res_1[10]; /* words 20-29 */
803 uint16_t signature; /* BIOS Signature */
804 #define CFSIGNATURE 0x400
805 uint16_t checksum; /* word 31 */
808 /****************************** Flexport Logic ********************************/
809 #define FLXADDR_TERMCTL 0x0
810 #define FLX_TERMCTL_ENSECHIGH 0x8
811 #define FLX_TERMCTL_ENSECLOW 0x4
812 #define FLX_TERMCTL_ENPRIHIGH 0x2
813 #define FLX_TERMCTL_ENPRILOW 0x1
814 #define FLXADDR_ROMSTAT_CURSENSECTL 0x1
815 #define FLX_ROMSTAT_SEECFG 0xF0
816 #define FLX_ROMSTAT_EECFG 0x0F
817 #define FLX_ROMSTAT_SEE_93C66 0x00
818 #define FLX_ROMSTAT_SEE_NONE 0xF0
819 #define FLX_ROMSTAT_EE_512x8 0x0
820 #define FLX_ROMSTAT_EE_1MBx8 0x1
821 #define FLX_ROMSTAT_EE_2MBx8 0x2
822 #define FLX_ROMSTAT_EE_4MBx8 0x3
823 #define FLX_ROMSTAT_EE_16MBx8 0x4
824 #define CURSENSE_ENB 0x1
825 #define FLXADDR_FLEXSTAT 0x2
826 #define FLX_FSTAT_BUSY 0x1
827 #define FLXADDR_CURRENT_STAT 0x4
828 #define FLX_CSTAT_SEC_HIGH 0xC0
829 #define FLX_CSTAT_SEC_LOW 0x30
830 #define FLX_CSTAT_PRI_HIGH 0x0C
831 #define FLX_CSTAT_PRI_LOW 0x03
832 #define FLX_CSTAT_MASK 0x03
833 #define FLX_CSTAT_SHIFT 2
834 #define FLX_CSTAT_OKAY 0x0
835 #define FLX_CSTAT_OVER 0x1
836 #define FLX_CSTAT_UNDER 0x2
837 #define FLX_CSTAT_INVALID 0x3
839 int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
840 u_int start_addr, u_int count);
842 int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
843 u_int start_addr, u_int count);
844 int ahd_wait_seeprom(struct ahd_softc *ahd);
845 int ahd_verify_cksum(struct seeprom_config *sc);
846 int ahd_acquire_seeprom(struct ahd_softc *ahd);
847 void ahd_release_seeprom(struct ahd_softc *ahd);
849 /**************************** Message Buffer *********************************/
851 MSG_FLAG_NONE = 0x00,
852 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01,
853 MSG_FLAG_IU_REQ_CHANGED = 0x02,
854 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04,
855 MSG_FLAG_PACKETIZED = 0x08
859 MSG_TYPE_NONE = 0x00,
860 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
861 MSG_TYPE_INITIATOR_MSGIN = 0x02,
862 MSG_TYPE_TARGET_MSGOUT = 0x03,
863 MSG_TYPE_TARGET_MSGIN = 0x04
872 /*********************** Software Configuration Structure *********************/
873 struct ahd_suspend_channel_state {
883 struct ahd_suspend_state {
884 struct ahd_suspend_channel_state channel[2];
891 /* Host and sequencer SCB counts */
893 uint8_t *scratch_ram;
897 typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
908 #define AHD_MK_MSK(x) (0x01 << (x))
909 #define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0)
910 #define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1)
911 #define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN)
912 #define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI)
913 #define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG)
914 #define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN)
915 #define AHD_MODE_ANY_MSK (~0)
917 typedef uint8_t ahd_mode_state;
919 typedef void ahd_callback_t (void *);
922 bus_space_tag_t tags[2];
923 bus_space_handle_t bshs[2];
925 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
927 struct scb_data scb_data;
929 struct hardware_scb *next_queued_hscb;
932 * SCBs that have been sent to the controller
934 LIST_HEAD(, scb) pending_scbs;
937 * Current register window mode information.
943 * Saved register window mode information
944 * used for restore on next unpause.
946 ahd_mode saved_dst_mode;
947 ahd_mode saved_src_mode;
950 * Platform specific data.
952 struct ahd_platform_data *platform_data;
955 * Platform specific device information.
957 ahd_dev_softc_t dev_softc;
960 * Bus specific device information.
962 ahd_bus_intr_t bus_intr;
965 * Target mode related state kept on a per enabled lun basis.
966 * Targets that are not enabled will have null entries.
967 * As an initiator, we keep one target entry for our initiator
968 * ID to store our sync/wide transfer settings.
970 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS];
973 * The black hole device responsible for handling requests for
974 * disabled luns on enabled targets.
976 struct ahd_tmode_lstate *black_hole;
979 * Device instance currently on the bus awaiting a continue TIO
980 * for a command that was not given the disconnect priveledge.
982 struct ahd_tmode_lstate *pending_device;
985 * Timer handles for timer driven callbacks.
987 ahd_timer_t reset_timer;
990 * Card characteristics
993 ahd_feature features;
996 struct seeprom_config *seep_config;
998 /* Values to store in the SEQCTL register for pause and unpause */
1002 /* Command Queues */
1003 uint16_t qoutfifonext;
1004 uint16_t qoutfifonext_valid_tag;
1005 uint16_t qinfifonext;
1006 uint16_t qinfifo[AHD_SCB_MAX];
1009 /* Critical Section Data */
1010 struct cs *critical_sections;
1011 u_int num_critical_sections;
1013 /* Buffer for handling packetized bitbucket. */
1014 uint8_t *overrun_buf;
1016 /* Links for chaining softcs */
1017 TAILQ_ENTRY(ahd_softc) links;
1019 /* Channel Names ('A', 'B', etc.) */
1022 /* Initiator Bus ID */
1026 * PCI error detection.
1028 int unsolicited_ints;
1031 * Target incoming command FIFO.
1033 struct target_cmd *targetcmds;
1034 uint8_t tqinfifonext;
1037 * Incoming and outgoing message handling.
1039 uint8_t send_msg_perror;
1040 ahd_msg_flags msg_flags;
1041 ahd_msg_type msg_type;
1042 uint8_t msgout_buf[12];/* Message we are sending */
1043 uint8_t msgin_buf[12];/* Message we are receiving */
1044 u_int msgout_len; /* Length of message to send */
1045 u_int msgout_index; /* Current index in msgout */
1046 u_int msgin_index; /* Current index in msgin */
1049 * Mapping information for data structures shared
1050 * between the sequencer and kernel.
1052 bus_dma_tag_t parent_dmat;
1053 bus_dma_tag_t shared_data_dmat;
1054 bus_dmamap_t shared_data_dmamap;
1055 bus_addr_t shared_data_busaddr;
1057 /* Information saved through suspend/resume cycles */
1058 struct ahd_suspend_state suspend_state;
1060 /* Number of enabled target mode device on this card */
1063 /* Initialization level of this data structure */
1066 /* PCI cacheline size. */
1067 u_int pci_cachesize;
1069 /* Per-Unit descriptive information */
1070 const char *description;
1071 const char *bus_description;
1075 /* Selection Timer settings */
1078 uint16_t user_discenable;/* Disconnection allowed */
1079 uint16_t user_tagenable;/* Tagged Queuing allowed */
1082 TAILQ_HEAD(ahd_softc_tailq, ahd_softc);
1083 extern struct ahd_softc_tailq ahd_tailq;
1085 /************************ Active Device Information ***************************/
1092 struct ahd_devinfo {
1095 uint16_t target_mask;
1100 * Only guaranteed to be correct if not
1101 * in the busfree state.
1105 /****************************** PCI Structures ********************************/
1106 #define AHD_PCI_IOADDR0 PCIR_MAPS /* I/O BAR*/
1107 #define AHD_PCI_MEMADDR (PCIR_MAPS + 4) /* Memory BAR */
1108 #define AHD_PCI_IOADDR1 (PCIR_MAPS + 12)/* Second I/O BAR */
1110 typedef int (ahd_device_setup_t)(struct ahd_softc *);
1112 struct ahd_pci_identity {
1116 ahd_device_setup_t *setup;
1118 extern struct ahd_pci_identity ahd_pci_ident_table [];
1119 extern const u_int ahd_num_pci_devs;
1121 /***************************** VL/EISA Declarations ***************************/
1122 struct aic7770_identity {
1126 ahd_device_setup_t *setup;
1128 extern struct aic7770_identity aic7770_ident_table [];
1129 extern const int ahd_num_aic7770_devs;
1131 #define AHD_EISA_SLOT_OFFSET 0xc00
1132 #define AHD_EISA_IOSIZE 0x100
1134 /*************************** Function Declarations ****************************/
1135 /******************************************************************************/
1136 u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl);
1137 void ahd_busy_tcl(struct ahd_softc *ahd,
1138 u_int tcl, u_int busyid);
1139 static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl);
1140 static __inline void
1141 ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl)
1143 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL);
1146 /***************************** PCI Front End *********************************/
1147 struct ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1148 int ahd_pci_config(struct ahd_softc *,
1149 struct ahd_pci_identity *);
1151 /*************************** EISA/VL Front End ********************************/
1152 struct aic7770_identity *aic7770_find_device(uint32_t);
1153 int aic7770_config(struct ahd_softc *ahd,
1154 struct aic7770_identity *);
1156 /************************** SCB and SCB queue management **********************/
1157 int ahd_probe_scbs(struct ahd_softc *);
1158 void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1160 int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb,
1161 int target, char channel, int lun,
1162 u_int tag, role_t role);
1164 /****************************** Initialization ********************************/
1165 struct ahd_softc *ahd_alloc(void *platform_arg, char *name);
1166 int ahd_softc_init(struct ahd_softc *);
1167 void ahd_controller_info(struct ahd_softc *ahd, char *buf);
1168 int ahd_init(struct ahd_softc *ahd);
1169 int ahd_default_config(struct ahd_softc *ahd);
1170 int ahd_parse_cfgdata(struct ahd_softc *ahd,
1171 struct seeprom_config *sc);
1172 void ahd_intr_enable(struct ahd_softc *ahd, int enable);
1173 void ahd_pause_and_flushwork(struct ahd_softc *ahd);
1174 int ahd_suspend(struct ahd_softc *ahd);
1175 int ahd_resume(struct ahd_softc *ahd);
1176 void ahd_softc_insert(struct ahd_softc *);
1177 struct ahd_softc *ahd_find_softc(struct ahd_softc *ahd);
1178 void ahd_set_unit(struct ahd_softc *, int);
1179 void ahd_set_name(struct ahd_softc *, char *);
1180 struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1181 void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1182 void ahd_alloc_scbs(struct ahd_softc *ahd);
1183 void ahd_free(struct ahd_softc *ahd);
1184 int ahd_reset(struct ahd_softc *ahd);
1185 void ahd_shutdown(void *arg);
1186 int ahd_write_flexport(struct ahd_softc *ahd,
1187 u_int addr, u_int value);
1188 int ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1190 int ahd_wait_flexport(struct ahd_softc *ahd);
1192 /*************************** Interrupt Services *******************************/
1193 void ahd_pci_intr(struct ahd_softc *ahd);
1194 void ahd_clear_intstat(struct ahd_softc *ahd);
1195 void ahd_run_qoutfifo(struct ahd_softc *ahd);
1196 #ifdef AHD_TARGET_MODE
1197 void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused);
1199 void ahd_handle_hwerrint(struct ahd_softc *ahd);
1200 void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat);
1201 void ahd_handle_scsiint(struct ahd_softc *ahd,
1203 void ahd_clear_critical_section(struct ahd_softc *ahd);
1205 /***************************** Error Recovery *********************************/
1211 } ahd_search_action;
1212 int ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1213 char channel, int lun, u_int tag,
1214 role_t role, uint32_t status,
1215 ahd_search_action action);
1216 int ahd_search_disc_list(struct ahd_softc *ahd, int target,
1217 char channel, int lun, u_int tag,
1218 int stop_on_first, int remove,
1220 void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb);
1221 int ahd_reset_channel(struct ahd_softc *ahd, char channel,
1222 int initiate_reset);
1223 int ahd_abort_scbs(struct ahd_softc *ahd, int target,
1224 char channel, int lun, u_int tag,
1225 role_t role, uint32_t status);
1226 void ahd_restart(struct ahd_softc *ahd);
1227 void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo);
1228 void ahd_handle_scb_status(struct ahd_softc *ahd,
1230 void ahd_handle_scsi_status(struct ahd_softc *ahd,
1232 void ahd_calc_residual(struct ahd_softc *ahd,
1234 /*************************** Utility Functions ********************************/
1235 struct ahd_phase_table_entry*
1236 ahd_lookup_phase_entry(int phase);
1237 void ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1238 u_int our_id, u_int target,
1239 u_int lun, char channel,
1241 /************************** Transfer Negotiation ******************************/
1242 void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1243 u_int *ppr_options, u_int maxsync);
1244 void ahd_validate_offset(struct ahd_softc *ahd,
1245 struct ahd_initiator_tinfo *tinfo,
1246 u_int period, u_int *offset,
1247 int wide, role_t role);
1248 void ahd_validate_width(struct ahd_softc *ahd,
1249 struct ahd_initiator_tinfo *tinfo,
1252 int ahd_update_neg_request(struct ahd_softc*,
1253 struct ahd_devinfo*,
1254 struct ahd_tmode_tstate*,
1255 struct ahd_initiator_tinfo*,
1257 void ahd_set_width(struct ahd_softc *ahd,
1258 struct ahd_devinfo *devinfo,
1259 u_int width, u_int type, int paused);
1260 void ahd_set_syncrate(struct ahd_softc *ahd,
1261 struct ahd_devinfo *devinfo,
1262 u_int period, u_int offset,
1264 u_int type, int paused);
1271 void ahd_set_tags(struct ahd_softc *ahd,
1272 struct ahd_devinfo *devinfo,
1275 /**************************** Target Mode *************************************/
1276 #ifdef AHD_TARGET_MODE
1277 void ahd_send_lstate_events(struct ahd_softc *,
1278 struct ahd_tmode_lstate *);
1279 void ahd_handle_en_lun(struct ahd_softc *ahd,
1280 struct cam_sim *sim, union ccb *ccb);
1281 cam_status ahd_find_tmode_devs(struct ahd_softc *ahd,
1282 struct cam_sim *sim, union ccb *ccb,
1283 struct ahd_tmode_tstate **tstate,
1284 struct ahd_tmode_lstate **lstate,
1285 int notfound_failure);
1286 #ifndef AHD_TMODE_ENABLE
1287 #define AHD_TMODE_ENABLE 0
1290 /******************************* Debug ***************************************/
1292 extern uint32_t ahd_debug;
1293 #define AHD_SHOW_MISC 0x0001
1294 #define AHD_SHOW_SENSE 0x0002
1295 #define AHD_DUMP_SEEPROM 0x0004
1296 #define AHD_SHOW_TERMCTL 0x0008
1297 #define AHD_SHOW_MEMORY 0x0010
1298 #define AHD_SHOW_MESSAGES 0x0020
1299 #define AHD_SHOW_MODEPTR 0x0040
1300 #define AHD_SHOW_SELTO 0x0080
1301 #define AHD_SHOW_FIFOS 0x0100
1302 #define AHD_SHOW_QFULL 0x0200
1303 #define AHD_SHOW_QUEUE 0x0400
1304 #define AHD_SHOW_TQIN 0x0800
1305 #define AHD_SHOW_SG 0x1000
1306 #define AHD_DEBUG_SEQUENCER 0x2000
1308 void ahd_print_scb(struct scb *scb);
1309 void ahd_dump_sglist(struct scb *scb);
1310 void ahd_dump_all_cards_state(void);
1311 void ahd_dump_card_state(struct ahd_softc *ahd);
1312 int ahd_print_register(ahd_reg_parse_entry_t *table,
1319 void ahd_dump_scbs(struct ahd_softc *ahd);
1320 #endif /* _AIC79XX_H_ */